SiC semiconductor device

Abstract

This SiC semiconductor device is provided with: a SiC layer of a first conductivity type, which includes a main surface and has an axial channel in the stacking direction; a trench formed in the main surface and defining a lower region between the trench and the bottom of the SiC layer; and a pillar region of a second conductivity type, which is formed in the lower region in the SiC layer, and which extends along the axial channel.

Description

Technical Field

[0001] This application claims priority from Patent Application No. 2022-212612 filed with the Japan Patent Office on December 28, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a SiC semiconductor device. Background Art

[0002] Patent Document 1 (US 2015 / 0028351 A1) discloses an electronic device having an impurity region introduced into a silicon carbide layer by a channel implantation method.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent Application Publication No. 2015 / 0028351 Summary of the Invention

[0006] The present disclosure provides a novel SiC semiconductor device.

[0007] The present disclosure provides a SiC semiconductor device, comprising: a first-conductivity-type SiC layer including a main surface and having an axial channel in a stacking direction; a groove formed on the main surface and defining a lower region between the main surface and the bottom of the SiC layer; and a second-conductivity-type column region formed in the SiC layer in the lower region and extending along the axial channel.

[0008] The above and other objects, features and effects will become more apparent from the detailed description given with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG1 is a top view of a SiC semiconductor device showing a specific embodiment.

[0010] Figure 2 It is along Figure 1 A cross-sectional view along line II-II is shown.

[0011] Figure 3 It is a top view showing an example of chip layout.

[0012] Figure 4 It is a perspective view showing an example of chip layout.

[0013] Figure 5 It is a plan view showing the active region and the trench structure of the first embodiment.

[0014] Figure 6 It is a cross-sectional perspective view showing the active region and the trench structure of the first embodiment.

[0015] Figure 7 It is a cross-sectional perspective view showing the active region and the trench structure of the first embodiment.

[0016] Figure 8 It is an enlarged cross-sectional view showing the trench structure of the first embodiment.

[0017] Figure 9 It is an enlarged cross-sectional view showing the trench structure of the first embodiment.

[0018] Figure 10 This is a graph showing an example of the n-type concentration gradient in the high-concentration region.

[0019] Figure 11 This is a graph showing a comparative example of the n-type concentration gradient in the high-concentration region.

[0020] Figure 12 This is a graph showing an example of the p-type concentration gradient in the pillar region.

[0021] Figure 13 It is a perspective view showing the structure of the outer peripheral area.

[0022] Figure 14 It is a cross-sectional view showing a main part of the outer peripheral area.

[0023] Figure 15 It is a cross-sectional view showing a main part of the outer peripheral area.

[0024] Figure 16 This is a schematic diagram showing a wafer used in manufacturing a SiC semiconductor device.

[0025] Figure 17 This is a flowchart showing an example of a method for manufacturing a SiC semiconductor device.

[0026] Figure 18A It is a cross-sectional perspective view showing an example of a method for manufacturing a SiC semiconductor device.

[0027] Figure 18B Yes Figure 18A A sectional perspective view of the subsequent steps.

[0028] Figure 18C Yes Figure 18B A sectional perspective view of the subsequent steps.

[0029] Figure 18D Yes Figure 18C A sectional perspective view of the subsequent steps.

[0030] Figure 18E Yes Figure 18D A sectional perspective view of the subsequent steps.

[0031] Figure 18F Yes Figure 18E A sectional perspective view of the subsequent steps.

[0032] Figure 18G Yes Figure 18F A sectional perspective view of the subsequent steps.

[0033] Figure 18H Yes Figure 18G A sectional perspective view of the subsequent steps.

[0034] Figure 18I Yes Figure 18H A sectional perspective view of the subsequent steps.

[0035] Figure 18J Yes Figure 18I A sectional perspective view of the subsequent steps.

[0036] Figure 18K Yes Figure 18J A sectional perspective view of the subsequent steps.

[0037] Figure 18L Yes Figure 18K A sectional perspective view of the subsequent steps.

[0038] Figure 18M Yes Figure 18L A sectional perspective view of the subsequent steps.

[0039] Figure 18N Yes Figure 18M A sectional perspective view of the subsequent steps.

[0040] Figure 18O Yes Figure 18N A sectional perspective view of the subsequent steps.

[0041] Figure 19A This is a schematic diagram for explaining the crystal orientation measurement process.

[0042] Figure 19B This is a schematic diagram for explaining the crystal orientation measurement process.

[0043] Figure 20A This is a schematic diagram for explaining the ion implantation process.

[0044] Figure 20B This is a schematic diagram for explaining the ion implantation process.

[0045] Figure 21 It is a cross-sectional perspective view showing a groove structure according to a second embodiment.

[0046] Figure 22 It is a cross-sectional perspective view showing a groove structure according to a third embodiment.

[0047] Figure 23 It is a cross-sectional perspective view showing a groove structure according to a fourth embodiment.

[0048] Figure 24 It is a cross-sectional perspective view showing a SiC semiconductor device according to a first modification.

[0049] Figure 25 It is a cross-sectional perspective view showing a SiC semiconductor device according to a second modification. DETAILED DESCRIPTION

[0050] The following describes specific embodiments in detail with reference to the accompanying drawings. The drawings are schematic and not strictly illustrative, and relative positions, scales, ratios, angles, and the like may not necessarily be consistent. Corresponding structures between the drawings are denoted by the same reference numerals, and duplicate descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions before the omission or simplification apply.

[0051] When the term "substantially" is used in this specification, this term includes not only values (forms) equal to the values (forms) of the comparison object, but also numerical errors (form errors) within a range of ±10% based on the values (forms) of the comparison object. In the following description, terms such as "first," "second," and "third" are used. However, these are symbols given to the names of various structures to clarify the order of description and are not intended to limit the names of various structures.

[0052] In the following description, "p-type" or "n-type" is used to indicate the conductivity type of the semiconductor (impurity), but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "P-type" is a conductivity type derived from trivalent elements, and "n-type" is a conductivity type derived from pentavalent elements. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth, unless otherwise specified.

[0053] Figure 1 1 is a plan view of a SiC semiconductor device 1 showing a specific embodiment. Figure 2 It is along Figure 1 A cross-sectional view along line II-II is shown. Figure 3 1 is a plan view showing an example of the layout of the chip 2 . Figure 4 It is a perspective view showing an example of the layout of the chip 2 .

[0054] Figure 5 It is a plan view showing the trench structure 25 according to the first embodiment together with the active region 8 . Figure 6 It is a cross-sectional perspective view showing the trench structure 25 according to the first embodiment together with the active region 8 . Figure 7 It is a cross-sectional perspective view showing the trench structure 25 according to the first embodiment together with the active region 8 . Figure 8 It is an enlarged cross-sectional view showing the trench structure 25 according to the first embodiment. Figure 9 It is an enlarged cross-sectional view showing the trench structure 25 according to the first embodiment.

[0055] Reference Figures 1 to 9 , SiC semiconductor device 1 includes a chip 2 comprising a SiC single crystal. Chip 2 may also be referred to as a "SiC chip" or a "semiconductor chip". In this embodiment, chip 2 is composed of a hexagonal SiC single crystal and is formed into a rectangular parallelepiped shape. Hexagonal SiC single crystals have various polytypes including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example of chip 2 being composed of a 4H-SiC single crystal is shown, but chip 2 may also be composed of other polytypes.

[0056] The chip 2 has a first principal surface 3 on one side, a second principal surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first principal surface 3 and the second principal surface 4. The first principal surface 3 and the second principal surface 4 are formed into a quadrilateral when viewed from above (hereinafter referred to as "top view") as viewed from the vertical direction Z. The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first principal surface 3 (second principal surface 4). The first principal surface 3 and the second principal surface 4 can also be formed into a square or a rectangle when viewed from above.

[0057] The first principal surface 3 and the second principal surface 4 are preferably formed by the c-plane of SiC single crystal. In this case, the first principal surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second principal surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0058] In the circumferential direction of the chip 2 (at Figure 1 In the embodiment shown in FIG. 3 , the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first principal surface 3 and face each other in a second direction Y that intersects (specifically, is orthogonal to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face each other in the first direction X.

[0059] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0060] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Furthermore, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction also extends along the first principal surface 3.

[0061] Reference Figure 4 The chip 2 (first principal surface 3 and second principal surface 4) has an off angle θo, tilted at a predetermined angle in a predetermined off direction Do relative to the c-plane of the SiC single crystal. Specifically, the c-axis ((0001) axis) of the SiC single crystal is tilted from the vertical axis toward the off direction Do by the amount of the off angle θo. Furthermore, the c-plane of the SiC single crystal is tilted relative to the horizontal plane by the amount of the off angle θo.

[0062] The off direction Do is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off angle θo may be greater than 0° and less than 10°. The off angle θo may have a value within any range of greater than 0° and less than 1°, greater than 1° and less than 2.5°, greater than 2.5° and less than 5°, greater than 5° and less than 7.5°, and greater than 7.5° and less than 10°.

[0063] The off angle θo is preferably 5° or less. The off angle θo is particularly preferably 2° or more and 4.5° or less. The off angle θo is typically set within the range of 4°±0.1°. Of course, this specification does not exclude an off angle θo of 0° (i.e., an embodiment in which the first principal surface 3 is the front surface relative to the c-plane).

[0064] Chip 2 includes an n-type base layer 6 composed of SiC single crystal. Base layer 6 may also be referred to as a "base SiC layer," "base region," or the like. Base layer 6 extends horizontally in a layered manner, forming a portion of second principal surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, base layer 6 is formed from a substrate made of SiC single crystal (i.e., a SiC substrate). Base layer 6 has the aforementioned off direction Do and off angle θo.

[0065] The base layer 6 has a first-axis channel C1 along the stacking direction. The first-axis channel C1 is a region (channel) where the interatomic distance (atomic spacing) of the SiC single crystal constituting the base layer 6 is relatively wide, and is surrounded by atomic rows constituting the crystal axis extending in the stacking direction (crystal growth direction).

[0066] That is, the first-axis channel C1 is an area in which the atomic columns are sparse and extend in the stacking direction, and the atomic columns (interatomic distance / atomic density) in the horizontal direction are sparse when viewed from above. The first-axis channel C1 is preferably an area surrounded by atomic columns along the low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values of "a1", "a2", "a3" and "c" are all less than 2 (preferably less than 1) with respect to the Miller index (a1, a2, a3, c) (hereinafter, the same in this specification).

[0067] In this method, the first-axis channel C1 is formed by a region surrounded by atomic rows oriented along the c-axis ((0001) axis) of the SiC single crystal. Specifically, the first-axis channel C1 extends along the c-axis, with the aforementioned off-direction Do and off-angle θo. In other words, the first-axis channel C1 is tilted from the vertical axis toward the off-direction Do by the off-angle θo.

[0068] The base layer 6 may also have a 1×10 18 cm -3 Above and 1×10 21 cm -3 The following n-type impurity concentration is taken as the peak value. The base layer 6 preferably has a substantially constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted using a single pentavalent element. The n-type impurity concentration of the base layer 6 is particularly preferably adjusted using a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted using nitrogen.

[0069] The base layer 6 has a first thickness T1. The first thickness T1 may be greater than or equal to 5 μm and less than or equal to 300 μm. The first thickness T1 may have a value within any range of greater than or equal to 5 μm and less than or equal to 50 μm, greater than or equal to 50 μm and less than or equal to 100 μm, greater than or equal to 100 μm and less than or equal to 150 μm, greater than or equal to 150 μm and less than or equal to 200 μm, greater than or equal to 200 μm and less than or equal to 250 μm, and greater than or equal to 250 μm and less than or equal to 300 μm. The first thickness T1 is preferably greater than or equal to 50 μm and less than or equal to 250 μm.

[0070] Chip 2 includes a semiconductor layer 7 made of single-crystal SiC stacked on a base layer 6. Semiconductor layer 7 may also be referred to as a "SiC layer," a "semiconductor region," or the like. Semiconductor layer 7 extends horizontally in a layered manner, forming portions of first principal surface 3 and first to fourth side surfaces 5A to 5D. Semiconductor layer 7 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) that has been crystallized and grown starting from base layer 6.

[0071] Semiconductor layer 7 has a lower end and an upper end. The lower end of semiconductor layer 7 is the starting point of crystal growth, and the upper end of semiconductor layer 7 is the end point of crystal growth. The lower end of semiconductor layer 7 is also the bottom of semiconductor layer 7. Since semiconductor layer 7 continuously crystallizes and grows from base layer 6, the lower end of semiconductor layer 7 coincides with the upper end of base layer 6.

[0072] The boundary between the underlying layer 6 and the semiconductor layer 7 is not necessarily visually recognizable and can be evaluated and / or determined indirectly based on other structures and elements. The semiconductor layer 7 has an offset direction Do and an offset angle θo that are substantially consistent with those of the underlying layer 6 .

[0073] The semiconductor layer 7 has a second-axis channel C2 along the stacking direction. The second-axis channel C2 is a region (channel) with a relatively wide interatomic distance (atomic spacing) in the SiC single crystal constituting the semiconductor layer 7 and is surrounded by atomic rows along the crystal axis extending in the stacking direction (crystal growth direction).

[0074] That is, the second-axis channel C2 is a region where the atomic rows are sparse, extending in the stacking direction, and the atomic rows (interatomic distance / atomic density) in the horizontal direction are sparse when viewed from above. The second-axis channel C2 is preferably a region surrounded by atomic rows along the low-index crystal axis.

[0075] In this method, the secondary-axis channel C2 is formed by a region surrounded by atomic rows oriented along the c-axis of the SiC single crystal. Specifically, the secondary-axis channel C2 extends along the c-axis, has an off-direction Do, and an off-angle θo. In other words, the secondary-axis channel C2 is tilted from the vertical axis toward the off-direction Do by an off-angle θo.

[0076] The n-type impurity concentration of the semiconductor layer 7 is preferably lower than that of the base layer 6. The semiconductor layer 7 may also have a 1×10 15 cm -3 Above and 1×10 18 cm -3 The n-type impurity concentration below is taken as the peak value. The n-type impurity concentration of the semiconductor layer 7 may also be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the semiconductor layer 7 may also have a concentration gradient that gradually increases and / or decreases toward the stacking direction (crystal growth direction).

[0077] In this embodiment, the n-type impurity concentration of semiconductor layer 7 is adjusted by nitrogen. Alternatively, semiconductor layer 7 may have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of semiconductor layer 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. Semiconductor layer 7 preferably includes a pentavalent element other than phosphorus.

[0078] The n-type impurity concentration of semiconductor layer 7 is preferably adjusted by at least nitrogen. When semiconductor layer 7 includes two or more pentavalent elements, semiconductor layer 7 preferably includes nitrogen and a pentavalent element other than nitrogen. In this case, semiconductor layer 7 preferably includes one or both of arsenic and antimony as the pentavalent element other than phosphorus and nitrogen.

[0079] The semiconductor layer 7 has a second thickness T2 that is smaller than the first thickness T1. The second thickness T2 may be greater than or equal to 1 μm and less than or equal to 10 μm. The second thickness T2 may have a value within any range of greater than or equal to 1 μm and less than 2 μm, greater than or equal to 2 μm and less than 4 μm, greater than or equal to 4 μm and less than 6 μm, greater than or equal to 6 μm and less than 8 μm, and greater than or equal to 8 μm and less than 10 μm. The second thickness T2 is preferably greater than or equal to 2 μm and less than or equal to 8 μm.

[0080] SiC semiconductor device 1 includes an active region 8 defined within chip 2. Active region 8 is defined within chip 2, spaced apart from the periphery of chip 2 (first to fourth side surfaces 5A to 5D) when viewed from above. Active region 8 is configured in a polygonal shape (in this embodiment, a quadrilateral shape) having four sides parallel to the periphery of chip 2 when viewed from above. The planar area of active region 8 is preferably not less than 50% and not more than 90% of the planar area of first principal surface 3.

[0081] SiC semiconductor device 1 includes a peripheral region 9 provided outside active region 8 in chip 2. Peripheral region 9 is provided in a region between the periphery of chip 2 and active region 8 in a plan view. Peripheral region 9 extends in a band along active region 8 in a plan view and is provided in a polygonal ring shape (a quadrilateral ring shape in this embodiment) surrounding active region 8.

[0082] SiC semiconductor device 1 includes an active surface 10 (active surface), an outer surface 11 (outer surface), and first to fourth connecting surfaces 12A to 12D (connecting surfaces) formed on first main surface 3. Active surface 10, outer surface 11, and first to fourth connecting surfaces 12A to 12D define an active terrace 13 on first main surface 3.

[0083] The active surface 10 may also be referred to as the "first surface," the outer peripheral surface 11 as the "second surface," the first to fourth connecting surfaces 12A to 12D as the "connection surface," and the active terrace 13 as the "terrace surface." The active surface 10, the outer peripheral surface 11, and the first to fourth connecting surfaces 12A to 12D (i.e., the active terrace 13) may be considered components of the chip 2 (first main surface 3).

[0084] The active surface 10 is formed in the active region 8. Specifically, the active surface 10 is formed spaced inward from the periphery of the first principal surface 3 (the first to fourth side surfaces 5A to 5D). The active surface 10 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 10 is formed by a c-plane (Si plane). In this embodiment, the active surface 10 is formed into a quadrilateral having four sides parallel to the first to fourth side surfaces 5A to 5D when viewed from above.

[0085] The outer peripheral surface 11 is formed in the outer peripheral region 9. That is, the outer peripheral surface 11 is formed outside the active surface 10. The outer peripheral surface 11 is recessed relative to the active surface 10 in the thickness direction of the chip 2 (on the side of the second main surface 4). Specifically, in this embodiment, the outer peripheral surface 11 is recessed to a depth less than the thickness of the semiconductor layer 7 to expose the semiconductor layer 7. In other words, the outer peripheral surface 11 is opposed to the base layer 6 through a portion of the semiconductor layer 7, thereby exposing the semiconductor layer 7.

[0086] The outer peripheral surface 11 extends in a band-like shape along the active surface 10 in a plan view, forming an annular shape (specifically, a four-sided annular shape) surrounding the active surface 10. The outer peripheral surface 11 has a flat surface extending in the first direction X and the second direction Y, and is formed approximately parallel to the active surface 10. In this embodiment, the outer peripheral surface 11 is formed by a c-plane (Si plane). The outer peripheral surface 11 is continuous with the first to fourth side surfaces 5A to 5D.

[0087] The outer peripheral surface 11 has an outer peripheral depth DO. The outer peripheral depth DO may be 0.1 μm to 2 μm. The outer peripheral depth DO may have a value within any range of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, and 1.5 μm to 2 μm. The outer peripheral depth DO is preferably 0.1 μm to 1.5 μm.

[0088] The first to fourth connecting surfaces 12A to 12D extend along the vertical direction Z and connect the active surface 10 and the outer peripheral surface 11. The first connecting surface 12A is located on the first side surface 5A side, the second connecting surface 12B is located on the second side surface 5B side, the third connecting surface 12C is located on the third side surface 5C side, and the fourth connecting surface 12D is located on the fourth side surface 5D side. The first connecting surface 12A and the third connecting surface 12C extend in the first direction X and face each other in the second direction Y. The second connecting surface 12B and the fourth connecting surface 12D extend in the second direction Y and face each other in the first direction X.

[0089] The first to fourth connecting surfaces 12A to 12D can extend approximately perpendicularly between the active surface 10 and the outer peripheral surface 11, defining quadrangular prism-shaped active terraces 13. Alternatively, the first to fourth connecting surfaces 12A to 12D can be formed so as to slope downwardly from the active surface 10 toward the outer peripheral surface 11, defining quadrangular pyramid-shaped active terraces 13. In this manner, the active terraces 13 are defined as protrusions on the first main surface 3 by the semiconductor layer 7. The active terraces 13 are formed only in the semiconductor layer 7 and not in the base layer 6.

[0090] Reference Figure 6 as well as Figure 7 SiC semiconductor device 1 includes an n-type high-concentration region 15 formed in at least the portion of semiconductor layer 7 located in active region 8. High-concentration region 15 has an n-type impurity concentration higher than the n-type impurity concentration of semiconductor layer 7. In this embodiment, high-concentration region 15 extends from active region 8 to peripheral region 9. In other words, high-concentration region 15 extends from the portion of semiconductor layer 7 located in active region 8 to the portion of semiconductor layer 7 located in peripheral region 9. High-concentration region 15 is exposed from outer peripheral surface 11.

[0091] Furthermore, the high-concentration region 15 extends from the peripheral region 9 toward the first to fourth side surfaces 5A to 5D, and is exposed from the first to fourth side surfaces 5A to 5D. Of course, the high-concentration region 15 may also be formed within the semiconductor layer 7 at intervals inward from the first to fourth side surfaces 5A to 5D. In this case, the peripheral edge of the high-concentration region 15 may be located within the active region 8 or within the peripheral region 9.

[0092] The high-concentration region 15 has an upper end portion located on the upper end side of the semiconductor layer 7 and a lower end portion located on the lower end side of the semiconductor layer 7. In this embodiment, the upper end portion of the high-concentration region 15 is located in a region on the upper end side of the semiconductor layer 7 relative to the middle portion of the thickness range of the semiconductor layer 7, and the lower end portion of the high-concentration region 15 is located in a region on the lower end side of the semiconductor layer 7 relative to the middle portion of the thickness range of the semiconductor layer 7.

[0093] Although not specifically shown in the figure, the upper end of the high-concentration region 15 may be exposed from the first main surface 3. Of course, the upper end of the high-concentration region 15 may be formed spaced apart from the upper end of the semiconductor layer 7 (i.e., the semiconductor layer 7) toward the lower end, and opposed to the first main surface 3 via a portion (the upper end) of the semiconductor layer 7. Such a structure is determined by analyzing the n-type impurity concentration (concentration gradient) of the high-concentration region 15.

[0094] The distance between the first main surface 3 and the upper end of the high-concentration region 15 may be 0 μm or more and 1 μm or less. The distance between the first main surface 3 and the upper end of the high-concentration region 15 may have a value within any range of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0095] The lower end of high-concentration region 15 is formed spaced apart from the lower end of semiconductor layer 7 (i.e., base layer 6) toward the upper end, and faces base layer 6 across a portion (lower end) of semiconductor layer 7. The distance between the lower end of semiconductor layer 7 and the lower end of high-concentration region 15 may be greater than 0 μm and less than 5 μm. The distance between the lower end of semiconductor layer 7 and the lower end of high-concentration region 15 may have a value falling within any of the following ranges: greater than 0 μm and less than 1 μm, greater than 1 μm and less than 2 μm, greater than 2 μm and less than 3 μm, greater than 3 μm and less than 4 μm, and greater than 4 μm and less than 5 μm.

[0096] The high-concentration region 15 has a thickness less than the second thickness T2 of the semiconductor layer 7. The thickness of the high-concentration region 15 can be greater than or equal to 1 μm and less than or equal to 10 μm. The thickness of the high-concentration region 15 can have a value belonging to any range of greater than or equal to 1 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, and greater than or equal to 8 μm and less than or equal to 10 μm. The thickness of the high-concentration region 15 is preferably greater than or equal to 2 μm and less than or equal to 8 μm. Of course, the lower end of the high-concentration region 15 can also be located within the base layer 6, crossing the boundary between the base layer 6 and the semiconductor layer 7.

[0097] The high-concentration region 15 is composed of a p-type channel region extending along the second-axis channel C2 in the semiconductor layer 7 when viewed in cross section. In other words, the high-concentration region 15 is composed of an impurity region introduced parallel or substantially parallel to a region surrounded by atomic rows along the low-index crystal axis (the second-axis channel C2) in the semiconductor layer 7, and extends obliquely with respect to the first main surface 3.

[0098] Therefore, the high-concentration region 15 has an offset direction Do and an offset angle θo that are substantially consistent with the offset direction Do and the offset angle θo of the second axial channel C2. In other words, the high-concentration region 15 is tilted from the vertical axis toward the offset direction Do by the amount of the offset angle θo. The high-concentration region 15 is composed of a single impurity region having a thickness (depth) that extends across the middle portion of the semiconductor layer 7 along the second axial channel C2.

[0099] The high concentration region 15 may also have a 1×10 15 cm -3 Above and 1×10 18cm -3 The following n-type impurity concentration is taken as the peak value. The n-type impurity concentration of the high-concentration region 15 is preferably adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the high-concentration region 15 can also be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0100] High-concentration region 15 preferably includes a pentavalent element other than nitrogen and phosphorus. The n-type impurity concentration in high-concentration region 15 is preferably adjusted with at least one of arsenic, antimony, and bismuth. For ease of availability, the n-type impurity concentration in high-concentration region 15 is preferably adjusted with arsenic or antimony.

[0101] Hereinafter, the n-type concentration gradient of the high-concentration region 15 will be described in detail. Figure 10 Graph (simulation) showing an example of the n-type concentration gradient in the high-concentration region 15 . Figure 11 is a graph (simulation) showing a comparative example of the n-type concentration gradient in the high-concentration region 15. Figure 10 and Figure 11 In FIG. 1 , the vertical axis represents the n-type impurity concentration of the high-concentration region 15 , and the horizontal axis represents the depth of the channel C2 along the second axis with the first main surface 3 as a reference (zero point).

[0102] exist Figure 10 as well as Figure 11 In the middle, there are 1×10 15 cm -3 The region with the above n-type impurity concentration is defined as a high-concentration region 15 and is illustrated as a graph. The numerical values for impurity concentration, thickness, etc. shown below are provided for illustrative purposes only to illustrate the basic structure of high-concentration region 15 based on a concentration gradient and are not intended to uniquely define the structure of high-concentration region 15. The impurity concentration, thickness, etc. are adjusted to various values depending on the pentavalent element implantation conditions (dose, implantation temperature, implantation energy, etc.).

[0103] Figure 10 This is a graph when the high-concentration region 15 is formed by a channel implantation method. Figure 10 The figure shows the concentration gradient of the high-concentration region 15 when a predetermined pentavalent element (arsenic in this case) is introduced into the semiconductor layer 7 parallel or substantially parallel to the second-axis channel C2 with an implantation energy of 500 KeV to 800 KeV.

[0104] The dose of pentavalent elements is 1×10 13 cm -2 The thickness of the semiconductor layer 7 is about 5 μm. Figure 10 In FIG. 1 , the dotted line indicates the concentration gradient when the high-concentration region 15 is formed by implantation energy of 1500 KeV or more and 2500 KeV or less.

[0105] on the other hand, Figure 11 This is a graph when the high-concentration region 15 is formed by the random implantation method. Figure 11 The figure shows the concentration gradient of the high-concentration region 15 when a predetermined pentavalent element (arsenic in this case) is introduced into the semiconductor layer 7 in random directions with an implantation energy of 500 KeV to 800 KeV.

[0106] The random direction is a direction that is not parallel (substantially parallel) to the second axis channel C2 (for example, the vertical direction Z). The dose of the pentavalent element is 1×10 13 cm -2 The thickness of the semiconductor layer 7 is about 5 μm. Figure 11 In FIG. 1 , the dotted line indicates the concentration gradient when the high-concentration region 15 is formed by implantation energy of 1500 KeV or more and 2500 KeV or less.

[0107] Reference Figure 10 The high-concentration region 15 has a thickness of not less than 2.1 μm and not more than 2.4 μm, and has an upper end away from the first main surface 3 toward the lower end of the semiconductor layer 7, and a lower end away from the lower end toward the upper end of the semiconductor layer 7. The high-concentration region 15 has a concentration gradient that gradually decreases from the upper end toward the lower end.

[0108] Specifically, the n-type impurity concentration in high-concentration region 15 has a concentration gradient from the upper end side toward the lower end side, including a first gradually increasing portion 16, a first peak portion 17, a first slow portion 18, and a first gradually decreasing portion 19. First gradually increasing portion 16 is the portion forming the upper end of high-concentration region 15, and the n-type impurity concentration gradually increases at a relatively steep rate from the upper end side toward the lower end side to reach first peak portion 17.

[0109] First peak portion 17 is a portion having a first peak value P1 (maximum value) of the n-type impurity concentration. It is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the n-type impurity concentration changes from increasing (increasing trend) to decreasing (decreasing trend).

[0110] First slow portion 18 is formed in a region below first peak portion 17, where the impurity concentration gradually decreases at a relatively slow rate. Specifically, first slow portion 18 maintains a constant n-type impurity concentration within a certain depth range and forms the bulk of high-concentration region 15. The n-type impurity concentration in first slow portion 18 decreases gradually within a concentration range lower than that of first peak portion 17.

[0111] The first slow portion 18 is defined by a portion having a concentration reduction rate of 50% or less within a thickness range of at least 0.5 μm. Figure 10In the example, the first slow portion 18 has a thickness of 0.8 μm or more and 1.1 μm or less, and has a concentration reduction rate of 50% or less within this thickness range.

[0112] The first slow portion 18 occupies at least one-quarter of the thickness of the high-concentration region 15. Specifically, the first slow portion 18 occupies at least one-third of the thickness of the high-concentration region 15. The first slow portion 18 typically occupies less than one-half of the thickness of the high-concentration region 15. Of course, the first slow portion 18 may also occupy at least one-half of the thickness of the high-concentration region 15.

[0113] First tapering portion 19 forms the lower end of high-concentration region 15. First tapering portion 19 has a concentration reduction rate greater than that in first slow portion 18, and is a portion where the n-type impurity concentration gradually decreases from first slow portion 18 toward the lower end. The concentration reduction rate per unit thickness of first tapering portion 19 is greater than that of first slow portion 18.

[0114] In the case of the channel implantation method, the thickness (depth) of the high-concentration region 15 increases as the implantation energy increases. The depth position of the upper end of the high-concentration region 15 relative to the first main surface 3 increases as the implantation energy increases. The thickness of the first gradually increasing portion 16, the thickness of the first peak portion 17, the thickness of the first slow portion 18, and the thickness of the first gradually decreasing portion 19 increase as the implantation energy increases. On the other hand, the first peak value P1 of the high-concentration region 15 decreases as the implantation energy increases. This is because as the implantation energy increases, the pentavalent element is introduced into the deeper region, and the n-type impurity concentration in the deeper region increases.

[0115] In contrast, the depth of the upper end of high-concentration region 15 relative to first major surface 3 decreases as the implantation energy decreases. The thicknesses of first gradually increasing portion 16, first peak portion 17, first slow portion 18, and first gradually decreasing portion 19 decrease as the implantation energy decreases. Meanwhile, first peak P1 of high-concentration region 15 increases as the implantation energy decreases. This is because the pentavalent element is trapped in a shallow region as the implantation energy decreases.

[0116] On the other hand, refer to Figure 11In the case of the random implantation method, the high-concentration region 15 has a first gradually increasing portion 16, a first peak portion 17 (first peak P1), and a first gradually decreasing portion 19 within a range of 0.5 μm. On the other hand, there is no first slow portion 18 with a thickness greater than 0.5 μm. Furthermore, in the case of the random implantation method, the depth position of the first peak portion 17 (first peak P1) relative to the first principal surface 3 increases with increasing implantation energy, but the thickness of the high-concentration region 15 is less than 2 μm. In other words, even with increasing implantation energy, the thickness does not change significantly.

[0117] From this, it can be seen that SiC single crystal has the physical property that impurities are difficult to diffuse, but in the case of the random injection method, for a semiconductor layer 7 with a relatively large second thickness T2 (for example, greater than 1 μm), it is difficult to form a high-concentration region 15 with a relatively large thickness (for example, a thickness of greater than 1 μm and less than 5 μm) composed of a single region.

[0118] Reference Figures 6 to 9 The SiC semiconductor device 1 includes a p-type body region 20 formed on the surface portion of the first main surface 3 (active surface 10). In this embodiment, the body region 20 is formed in a layer extending along the active surface 10. The body region 20 can also be formed over the entire area of the active surface 10, exposed from the first to fourth connecting surfaces 12A to 12D. The body region 20 is formed at intervals from the lower end of the semiconductor layer 7 toward the active surface 10. The body region 20 is preferably formed at intervals from a depth position of the outer peripheral surface 11 toward the active surface 10, and exposed from the active surface 10.

[0119] The body region 20 is composed of a random region introduced into the surface portion of the semiconductor layer 7 by a random implantation method into the semiconductor layer 7. Therefore, unlike the high-concentration region 15, the body region 20 does not have a slow portion such as the first slow portion 18. The body region 20 has a thickness smaller than that of the high-concentration region 15 in the direction along the second axial channel C2.

[0120] The main body region 20 may also have a 1×10 15 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentration is taken as the peak value. The p-type impurity concentration of the body region 20 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 20 may be at least one of boron, aluminum, gallium, and indium.

[0121] The SiC semiconductor device 1 includes a plurality of trench electrode-type trench structures 25 formed on the first main surface 3 (active surface 10) in the active region 8. The trench structures 25 may also be referred to as "gate structures," "trench gate structures," or the like. A gate potential, serving as a control potential, is applied to the plurality of trench structures 25. The plurality of trench structures 25 controls the inversion and non-inversion of the channel (current path) within the body region 20 in response to the gate potential.

[0122] A plurality of trench structures 25 are arranged in the active region 8 at intervals from the periphery of the active surface 10 (the first to fourth connecting surfaces 12A to 12D) toward the inside. In this embodiment, the plurality of trench structures 25 are arranged at intervals in the first direction X and are each formed into a strip extending in the second direction Y.

[0123] That is, the plurality of trench structures 25 are arranged at intervals in the m-axis direction and extend in the a-axis direction. Furthermore, in this embodiment, the plurality of trench structures 25 are arranged in a stripe pattern extending in the a-axis direction (second direction Y). The extending direction of the plurality of trench structures 25 coincides with the offset direction Do of the semiconductor layer 7.

[0124] The plurality of trench structures 25 are formed at intervals from the lower end of the semiconductor layer 7 (base layer 6) toward the first main surface 3 (active surface 10), and are opposed to the base layer 6 via a portion of the semiconductor layer 7. The plurality of trench structures 25 define a lower region 7a in the area between the bottom walls of the plurality of trench structures 25 and the lower end of the semiconductor layer 7 (base layer 6).

[0125] In this embodiment, a plurality of trench structures 25 are formed at intervals from the bottom of the high-concentration region 15 toward the first main surface 3 (active surface 10), and face a portion (lower end) of the semiconductor layer 7 across a portion (lower end) of the high-concentration region 15. In other words, the lower region 7a is formed by a portion (lower end) of the semiconductor layer 7 and a portion (lower end) of the high-concentration region 15.

[0126] The plurality of trench structures 25 are preferably formed spaced apart from the middle of the thickness range of the high concentration region 15 toward the active surface 10. Of course, the plurality of trench structures 25 may be formed at a depth that crosses the middle of the thickness range of the high concentration region 15.

[0127] Each trench structure 25 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z. The trench width WT is preferably smaller than the second thickness T2 of the semiconductor layer 7. The trench width WT is preferably smaller than the thickness of the high-concentration region 15. The trench width WT can be greater than or equal to 0.1 μm and less than or equal to 5 μm.

[0128] The groove width WT may have a value belonging to any range of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0129] The trench depth DT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench depth DT is preferably less than the thickness of the high-concentration region 15. In particular, the trench depth DT is preferably substantially equal to the outer peripheral depth DO described above. Of course, the trench depth DT may be greater than or less than the outer peripheral depth DO.

[0130] The trench depth DT is preferably greater than the trench width WT. That is, the plurality of trench structures 25 preferably each have an aspect ratio DT / WT, extending in a vertically long columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The trench depth DT can be greater than or equal to 0.1 μm and less than or equal to 5 μm.

[0131] The trench depth DT may have a value within any range of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, and 4 μm to 5 μm. The trench depth DT is preferably 0.1 μm to 1.5 μm.

[0132] The plurality of trench structures 25 are arranged at intervals of a trench pitch PT in the first direction X. The trench pitch PT is preferably smaller than the second thickness T2 of the semiconductor layer 7. The trench pitch PT is preferably smaller than the thickness of the high-concentration region 15. The trench pitch PT is preferably smaller than the trench depth DT. The trench pitch PT can be greater than or equal to 0.1 μm and less than or equal to 5 μm.

[0133] The trench pitch PT may have a value within any range of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The trench pitch PT is preferably 0.5 μm to 1.5 μm.

[0134] Each trench structure 25 includes a trench 26, an insulating film 27, and an embedded electrode 28. The trench 26 is formed in the active surface 10 and defines the walls (side walls and bottom wall) of the trench structure 25. The bottom wall of the trench 26 preferably has a flat extending portion.

[0135] It is particularly preferred that the flat portion of the bottom wall extend substantially parallel to the first major surface 3. Specifically, the bottom wall of the trench 26 preferably has an off angle θo, tilted at a predetermined angle in a predetermined off direction Do relative to the c-plane. In other words, the bottom wall of the trench 26 preferably has a flat portion extending along the off direction Do. Of course, the bottom wall may also be curved in an arc shape toward the lower end of the semiconductor layer 7.

[0136] Insulating film 27 covers the wall surfaces of trench 26. Insulating film 27 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, insulating film 27 has a single-layer structure composed of a silicon oxide film. Insulating film 27 is particularly preferably composed of a silicon oxide film composed of the oxide of chip 2.

[0137] The buried electrode 28 is buried in the trench 26 and faces the channel through the insulating film 27. In this embodiment, the buried electrode 28 faces the high concentration region 15 and the body region 20 through the insulating film 27. The buried electrode 28 may include p-type or n-type conductive polysilicon.

[0138] SiC semiconductor device 1 includes a plurality of p-type pillar regions 30 formed at intervals in the horizontal direction within semiconductor layer 7. Specifically, the plurality of pillar regions 30 are formed in lower region 7a within semiconductor layer 7. That is, the plurality of pillar regions 30 are formed within the thickness range between the lower end of semiconductor layer 7 and the bottom walls of the plurality of trench structures 25.

[0139] The plurality of pillar regions 30 are arranged in the lower region 7a at intervals in the first direction X and are each formed into a stripe shape extending in the second direction Y. Specifically, the plurality of pillar regions 30 are arranged in the m-axis direction at intervals and extend in the a-axis direction of the SiC single crystal. The plurality of pillar regions 30 are formed into a stripe shape extending in the a-axis direction (second direction Y), and the extension direction of the plurality of pillar regions 30 coincides with the off direction Do of the semiconductor layer 7.

[0140] The plurality of pillar regions 30 overlap with the plurality of trench structures 25 in the stacking direction. Specifically, the plurality of pillar regions 30 overlap with the plurality of trench structures 25 in a one-to-one correspondence in the stacking direction. The plurality of pillar regions 30 are formed in the active region 8 at intervals inward from the periphery of the active surface 10 (the first to fourth connecting surfaces 12A to 12D).

[0141] In the second direction Y, both ends of the plurality of pillar regions 30 may be located inward of the active region 8 relative to both ends of the plurality of trench structures 25. In the second direction Y, both ends of the plurality of pillar regions 30 may be located on the peripheral side of the active region 8 relative to both ends of the plurality of trench structures 25.

[0142] The plurality of pillar regions 30 have upper ends located on the bottom wall side of the trench structure 25, and lower ends located on the lower end side of the semiconductor layer 7. In this embodiment, the upper ends of the plurality of pillar regions 30 are located in the region on the bottom wall side of the trench structure 25 relative to the middle portion of the thickness range of the lower region 7a, and the lower ends of the plurality of pillar regions 30 are located in the region on the lower end side of the semiconductor layer 7 relative to the middle portion of the thickness range of the lower region 7a.

[0143] The upper ends of the plurality of pillar regions 30 are formed at intervals on the lower end side of the semiconductor layer 7 at a depth position relative to the outer peripheral surface 11. The upper ends of the plurality of pillar regions 30 are formed at intervals from the bottom walls of the plurality of trench structures 25 toward the lower end side of the semiconductor layer 7, and are opposed to the plurality of trench structures 25 via a portion of the semiconductor layer 7.

[0144] Specifically, the upper ends of the plurality of pillar regions 30 face the plurality of trench structures 25 across a portion of the high-concentration region 15. That is, the upper ends of the plurality of pillar regions 30 are electrically connected to the relatively high-concentration region 15. Of course, the upper ends of the plurality of pillar regions 30 may also be connected to the bottom walls of the plurality of trench structures 25.

[0145] The intermediate distance between the bottom walls of the plurality of trench structures 25 and the upper ends of the plurality of pillar regions 30 may also be 0 μm or more and 1 μm or less. The intermediate distance may have a value falling within any range of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0146] The lower ends of the plurality of pillar regions 30 extend across the bottom of the high-concentration region 15 and into the semiconductor layer 7. Specifically, the plurality of pillar regions 30 include portions located between the bottom of the high-concentration region 15 and the bottom walls of the plurality of trench structures 25, and portions located between the lower end of the semiconductor layer 7 and the bottom of the high-concentration region 15. The lower ends of the plurality of pillar regions 30 are electrically connected to the semiconductor layer 7 having a lower concentration.

[0147] The cross-sectional area of the portion of the plurality of pillar regions 30 located within the high-concentration region 15 is preferably larger than the cross-sectional area of the portion of the plurality of pillar regions 30 located within the semiconductor layer 7. Of course, the cross-sectional area of the portion of the plurality of pillar regions 30 located within the high-concentration region 15 may also be smaller than the cross-sectional area of the portion of the plurality of pillar regions 30 located within the semiconductor layer 7.

[0148] In this embodiment, the lower ends of the plurality of pillar regions 30 are formed at intervals from the lower end of the semiconductor layer 7 toward the bottom side of the high-concentration region 15, and face the base layer 6 via a portion of the semiconductor layer 7. Of course, the lower ends of the plurality of pillar regions 30 may also be located within the base layer 6, crossing the boundary between the semiconductor layer 7 and the base layer 6. If the lower end of the high-concentration region 15 is located within the base layer 6, the lower ends of the plurality of pillar regions 30 may also cross the bottom of the high-concentration region 15 within the base layer 6.

[0149] The lower end distance between the lower end of the semiconductor layer 7 and the lower end portions of the plurality of pillar regions 30 may be 0 μm to 2 μm inclusive. The lower end distance may have a value within any range of 0 μm to 0.5 μm inclusive, 0.5 μm to 1 μm inclusive, 1 μm to 1.5 μm inclusive, and 1.5 μm to 2 μm inclusive.

[0150] Of course, when a relatively thick high-concentration region 15 is formed, the lower ends of the plurality of pillar regions 30 may be formed spaced apart from the bottom of the high-concentration region 15 toward the bottom wall of the trench structure 25. In other words, the plurality of pillar regions 30 may be electrically connected to the high-concentration region 15 at both the upper and lower ends.

[0151] The plurality of pillar regions 30 are formed by channel regions extending along the second-axis channel C2 when viewed in cross section. Specifically, the pillar regions 30 are impurity regions introduced into the semiconductor layer 7 parallel or substantially parallel to the region surrounded by atomic rows along the low-index crystal axis (the second-axis channel C2), and extend obliquely relative to the first principal surface 3.

[0152] Therefore, the plurality of pillar regions 30 have an offset direction Do and an offset angle θo that are substantially consistent with the offset direction Do and the offset angle θo of the second axial channel C2. In other words, the plurality of pillar regions 30 are tilted from the vertical axis toward the offset direction Do by the offset angle θo. The plurality of pillar regions 30 are composed of a single region having a thickness (depth) extending across the middle of the lower region 7a along the second axial channel C2.

[0153] The plurality of pillar regions 30 may also have 1×10 15 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentration is taken as the peak value. The p-type impurity concentration (peak value) of the pillar region 30 may be higher than the p-type impurity concentration (peak value) of the body region 20. The p-type impurity concentration (peak value) of the pillar region 30 may also be lower than the p-type impurity concentration (peak value) of the body region 20.

[0154] The p-type impurity concentration in pillar region 30 is preferably adjusted by at least one trivalent element. It is particularly preferred that the p-type impurity concentration in pillar region 30 be adjusted by a trivalent element heavier than carbon. Specifically, pillar region 30 preferably includes a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration in pillar region 30 is adjusted by aluminum.

[0155] Each of the plurality of pillar regions 30 has a pillar width WC in the arrangement direction. The pillar width WC may be substantially equal to the trench width WT. The pillar width WC may be greater than the trench width WT. The pillar width WC may be less than the trench width WT. The pillar width WC may be less than the trench depth DT. The pillar width WC may be greater than the trench depth DT. The pillar width WC is preferably less than the second thickness T2 of the semiconductor layer 7. The pillar width WC is preferably less than the thickness of the high-concentration region 15.

[0156] The column width WC may be greater than or equal to 0.1 μm and less than or equal to 5 μm. The column width WC may have a value falling within any range of greater than or equal to 0.1 μm and less than or equal to 0.25 μm, greater than or equal to 0.25 μm and less than or equal to 0.5 μm, greater than or equal to 0.5 μm and less than or equal to 0.75 μm, greater than or equal to 0.75 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, greater than or equal to 1.5 μm and less than or equal to 2 μm, greater than or equal to 2.5 μm and less than or equal to 2.5 μm, greater than or equal to 3 μm, greater than or equal to 3.5 μm, greater than or equal to 3.5 μm and less than or equal to 4 μm, greater than or equal to 4.5 μm, and greater than or equal to 4.5 μm.

[0157] Each of the plurality of pillar regions 30 has a pillar thickness TC (region depth). Preferably, the pillar thickness TC is less than the second thickness T2 of the semiconductor layer 7. Preferably, the pillar thickness TC is less than the thickness of the high-concentration region 15. The pillar thickness TC is particularly preferably greater than the trench depth DT. The pillar thickness TC is preferably greater than the trench width WT. Particularly preferably, the pillar thickness TC is greater than the trench depth DT. Of course, the pillar thickness TC may also be less than the trench depth DT.

[0158] The pillar thickness TC may be greater than or equal to 1 and less than or equal to 5 times the trench depth DT. The ratio TC / DT of the pillar thickness TC to the trench depth DT may be greater than or equal to 1 and less than or equal to 1.5, greater than or equal to 1.5 and less than or equal to 2, greater than or equal to 2 and less than or equal to 2.5, greater than or equal to 2.5 and less than or equal to 3, greater than or equal to 3 and less than or equal to 3.5, greater than or equal to 3.5 and less than or equal to 4, greater than or equal to 4 and less than or equal to 4.5, and greater than or equal to 4.5 and less than or equal to 5.

[0159] The pillar thickness TC is preferably greater than the pillar width WC. That is, each of the plurality of pillar regions 24 preferably has an aspect ratio TC / WC, extending in a vertically elongated columnar shape along the second-axis channel C2. The aspect ratio TC / WC is the ratio of the pillar thickness TC to the pillar width WC. The pillar thickness TC is preferably 1 μm or more and 5 μm or less.

[0160] The column thickness TC can have a value belonging to any range of 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0161] The plurality of pillar regions 30 are formed at intervals of a pillar pitch PC in the arrangement direction. The pillar pitch PC may be substantially equal to the trench pitch PT. The pillar pitch PC may be greater than the trench pitch PT. The pillar pitch PC may also be smaller than the trench pitch PT.

[0162] The column pitch PC is preferably smaller than the column thickness TC. The column pitch PC is preferably smaller than the trench depth DT. The column pitch PC is preferably smaller than the second thickness T2 of the semiconductor layer 7. The column pitch PC is preferably smaller than the thickness of the high concentration region 15. The column pitch PC can be 0.1 μm or more and 5 μm or less.

[0163] The pillar pitch PC may have a value within any range of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. Preferably, the pillar pitch PC is 0.5 μm to 1.5 μm.

[0164] Hereinafter, the p-type concentration gradient of the pillar region 30 will be described in detail. Figure 12 is a graph showing an example of the p-type concentration gradient in the pillar region 30. Figure 12 In FIG. 1 , the vertical axis represents the p-type impurity concentration of the pillar region 30 , and the horizontal axis represents the depth of the channel C2 along the second axis with the bottom wall of the trench structure 25 as a reference (zero point).

[0165] exist Figure 12 In the middle, there are 1×10 15 cm -3 The region with the above p-type impurity concentration is defined as pillar region 30 and is illustrated as a graph. The numerical values for impurity concentration, thickness, etc. shown below are provided as examples to illustrate the basic structure of pillar region 30 based on concentration gradients and are not intended to uniquely define the structure of pillar region 30. The impurity concentration, thickness, etc. are adjusted to various values depending on the implantation conditions (dose, implantation temperature, implantation energy, etc.) of the trivalent element.

[0166] Figure 12 This is a graph showing a case where the pillar region 30 is formed by a channel implantation method. Figure 12 1 and 2 show the concentration gradient of the pillar region 30 when a predetermined trivalent element (aluminum in this case) is introduced into the lower region 7 a parallel or substantially parallel to the second-axis channel C2 with an implantation energy of 500 KeV to 800 KeV.

[0167] The dose of trivalent elements is 1×10 13 cm -2 The trench depth DT is about 1 μm, and the thickness of the lower region 7a is about 4 μm. Figure 12 In FIG. 1 , the dotted line indicates the concentration gradient when the pillar region 30 is formed by implantation energy of 1500 KeV or more and 2500 KeV or less.

[0168] Reference Figure 12The pillar region 30 has a thickness of 2.5 μm to 2.8 μm, an upper end away from the bottom wall of the trench structure 25 toward the lower end of the semiconductor layer 7 , and a lower end away from the lower end of the semiconductor layer 7 toward the upper end.

[0169] The p-type impurity concentration of pillar region 30 has a concentration gradient from the upper end toward the lower end, including a second gradually increasing portion 31, a second peak portion 32, a second slow portion 33, and a second gradually decreasing portion 34. Second gradually increasing portion 31 forms the upper end of pillar region 30, and the p-type impurity concentration gradually increases at a relatively steep rate from the upper end toward the lower end to reach second peak portion 32. In this embodiment, second gradually increasing portion 31 is located within high-concentration region 15 and is electrically connected to high-concentration region 15.

[0170] Second peak portion 32 is a portion having a second peak value P2 (maximum value) of the p-type impurity concentration. Second peak portion 32 is also a convex main concentration transition portion, including a series of concentration changes (inflection points) where the p-type impurity concentration transitions from increasing (increasing trend) to decreasing (decreasing trend). Second peak portion 32 is electrically connected to high-concentration region 15. In this embodiment, second peak P2 is located lower than first peak P1 of high-concentration region 15 in semiconductor layer 7.

[0171] Second slow portion 33 is formed in a region below second peak portion 32, where the impurity concentration gradually decreases at a relatively slow rate. Specifically, second slow portion 33 maintains a constant p-type impurity concentration within a certain depth range and forms the main body of pillar region 30. The p-type impurity concentration in second slow portion 33 decreases gradually within a concentration range lower than that of second peak portion 32.

[0172] The second slow portion 33 is defined by a portion having a concentration reduction rate of 50% or less within a thickness range of at least 0.5 μm. Figure 12 In the example shown, second slow portion 33 has a thickness of 1 μm to 1.3 μm, with a concentration reduction rate of 50% or less within this thickness range. Second slow portion 33 is located in high-concentration region 15 and electrically connected to high-concentration region 15. Second slow portion 33 may also have a portion located within a thickness range between the lower end of semiconductor layer 7 and the lower end of high-concentration region 15, and electrically connected to semiconductor layer 7.

[0173] The second slow portion 33 occupies at least 1 / 4 of the thickness of the pillar region 30. Specifically, the second slow portion 33 occupies at least 1 / 3 of the pillar region 30. Typically, the second slow portion 33 occupies at least 1 / 2 of the pillar region 30. Of course, the second slow portion 33 may also occupy at least 1 / 2 of the pillar region 30.

[0174] Second tapering portion 34 forms the lower end of pillar region 30. Second tapering portion 34 has a concentration reduction rate greater than that in second slow portion 33, and is the portion where the p-type impurity concentration gradually decreases from second slow portion 33 toward the lower end. The concentration reduction rate per unit thickness of second tapering portion 34 is greater than that of second slow portion 33. Second tapering portion 34 is located within the thickness range between the lower end of semiconductor layer 7 and the lower end of high-concentration region 15 and is electrically connected to semiconductor layer 7.

[0175] In the case of the channel implantation method, the thickness (depth) of the pillar region 30 increases as the implantation energy increases. The depth position of the upper end of the pillar region 30 relative to the bottom wall of the trench structure 25 increases as the implantation energy increases. The thickness of the second gradually increasing portion 31, the thickness of the second peak portion 32, the thickness of the second slow portion 33, and the thickness of the second gradually decreasing portion 34 increase as the implantation energy increases. On the other hand, the second peak value P2 of the pillar region 30 decreases as the implantation energy increases. This is because as the implantation energy increases, the trivalent element is introduced into the deeper region, and the p-type impurity concentration in the deeper region increases.

[0176] In contrast, the depth of the upper end of the pillar region 30 relative to the bottom wall of the trench structure 25 decreases as the implantation energy decreases. The thicknesses of the second gradually increasing portion 31, the second peak portion 32, the second slow portion 33, and the second gradually decreasing portion 34 decrease as the implantation energy decreases. Meanwhile, the second peak value P2 of the pillar region 30 increases as the implantation energy decreases. This is because the incorporation of trivalent elements is hindered in shallower regions as the implantation energy decreases.

[0177] In the case of the pillar regions 30, since trivalent elements are introduced into the semiconductor layer 7 instead of pentavalent elements, even if the same process conditions as those for the high-concentration regions 15 are applied, it is necessary to be aware that the concentration distribution and thickness (depth) of the pillar regions 30 differ from those of the high-concentration regions 15. Therefore, in order to achieve appropriate charge balance, it is preferable to set separate process conditions for the pillar regions 30 and the high-concentration regions 15.

[0178] SiC semiconductor device 1 includes multiple n-type drift regions 35 formed in semiconductor layer 7. Each of the multiple drift regions 35 is composed of a region in semiconductor layer 7 that is partitioned by multiple pillar regions 30. In other words, the multiple drift regions 35 are arranged in the semiconductor layer 7 at intervals in the first direction X (m-axis direction) and are each partitioned into strips extending in the second direction Y (a-axis direction).

[0179] In this manner, the plurality of drift regions 35 are formed by a portion of the semiconductor layer 7 and a portion of the high concentration region 15. The portion of the plurality of drift regions 35 including the high concentration region 15 is constituted by an n-type channel region extending along the second-axis channel C2.

[0180] The plurality of drift regions 35 form a plurality of charge-balanced pn junctions together with the plurality of pillar regions 30. This charge-balanced state means that, for the plurality of adjacent pillar regions 30, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the plurality of drift regions 35.

[0181] In this embodiment, the multiple n-type drift regions 35 (semiconductor layer 7) whose concentrations are adjusted by the high concentration region 15 form a charge balance with the multiple p-type pillar regions 30 whose concentrations are adjusted. The multiple drift regions 35 form a superjunction structure with the multiple pillar regions 30 in the lower region 7a.

[0182] SiC semiconductor device 1 includes a plurality of p-type intermediate regions 36 located within semiconductor layer 7, each located between the bottom walls of the plurality of trench structures 25 and the plurality of pillar regions 30. In this embodiment, the plurality of intermediate regions 36 are located between the bottom wall of one trench structure 25 and the upper end of one pillar region 30.

[0183] A plurality of intermediate regions 36 are formed immediately below the corresponding trench structures 25, spaced apart along the extending direction (second direction Y) of the corresponding trench structures 25. In the extending direction of the trench structures 25, the plurality of intermediate regions 36 may be arranged at intervals greater than the trench width WT (pillar width WC). The intervals between the plurality of intermediate regions 36 may also be greater than the trench pitch PT (pillar pitch PC). Of course, the intervals between the plurality of intermediate regions 36 may also be less than the trench pitch PT (pillar pitch PC).

[0184] Regarding the groove structures 25 on one side and the other side, multiple intermediate regions 36 on one side directly below the groove structure 25 on one side are formed at intervals from multiple intermediate regions 36 on the other side directly below the groove structure 25 on the other side in the arrangement direction (first direction X) of the multiple groove structures 25.

[0185] The plurality of intermediate regions 36 on one side are opposed to the plurality of intermediate regions 36 on the other side in a one-to-one correspondence in the arrangement direction (first direction X) across a portion of the semiconductor layer 7 (a portion of the high-concentration region 15). Of course, the plurality of intermediate regions 36 on one side may also be opposed to the region between the plurality of intermediate regions 36 on the other side in a one-to-one correspondence in the arrangement direction.

[0186] The plurality of intermediate regions 36 are respectively connected to the bottom wall of the trench structure 25 and the upper end of the pillar region 30. The plurality of intermediate regions 36 also have portions extending from the area directly below the trench structure 25 to both sides of the trench structure 25 and along the sidewalls of the trench structure 25.

[0187] The plurality of intermediate regions 36 are electrically connected to the body region 20 at the surface portion of the first main surface 3 (active surface 10). In other words, the plurality of intermediate regions 36 electrically connect the plurality of pillar regions 30 to the body region 20. This prevents the plurality of pillar regions 30 from being electrically floating.

[0188] The plurality of intermediate regions 36 may also extend in the vertical direction Z within the main body region 20 along the sidewalls of the groove structures 25, and be exposed from the first main surface 3. In this case, the plurality of intermediate regions 36 may also have portions extending in the horizontal direction on the surface portion of the first main surface 3. Adjacent intermediate regions 36 in the arrangement direction of the plurality of groove structures 25 (first direction X) are formed at intervals on the surface portion of the first main surface 3. Of course, adjacent intermediate regions 36 may also be connected to each other on the surface portion of the first main surface 3.

[0189] The plurality of intermediate regions 36 moderate the electric field relative to the trench structure 25. The plurality of intermediate regions 36 do not necessarily need to form charge balance together with the plurality of drift regions 35. Of course, the plurality of intermediate regions 36 may also form a plurality of pn junctions with charge balance together with the plurality of drift regions 35.

[0190] The plurality of intermediate regions 36 are composed of random regions introduced into the surface portion of the plurality of drift regions 35 by a random implantation method into the semiconductor layer 7. Specifically, the plurality of intermediate regions 36 have a thickness along the second-axis channel C2 that is less than the thickness of the plurality of pillar regions 30. Furthermore, the plurality of intermediate regions 36 do not include the second slow portion 33 having a thickness of 0.5 μm or greater in both directions along the second-axis channel C2.

[0191] The plurality of intermediate regions 36 may also have 1×10 15 cm -3 Above and 1×10 18 cm -3 The p-type impurity concentration below is the peak value. The plurality of intermediate regions 36 may also have a concentration of 1×10 18 cm -3 Above and 1×10 21 cm -3 The following p-type impurity concentration is taken as the peak value. The intermediate region 36 may have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 20. The p-type impurity concentration (peak value) of the intermediate region 36 may also be lower than the p-type impurity concentration (peak value) of the body region 20.

[0192] The p-type impurity concentration (peak value) of the intermediate region 36 may be higher than the p-type impurity concentration (peak value) of the pillar region 30 . The p-type impurity concentration (peak value) of the intermediate region 36 may be lower than the p-type impurity concentration (peak value) of the pillar region 30 .

[0193] The p-type impurity concentration in the intermediate region 36 is preferably adjusted by at least one trivalent element. The trivalent element in the intermediate region 36 may be the same as or different from the trivalent element in the pillar region 30. The trivalent element in the intermediate region 36 may be at least one of boron, aluminum, gallium, and indium.

[0194] The SiC semiconductor device 1 includes a plurality of source regions 37 formed on both sides of the plurality of trench structures 25 in the surface portion of the first main surface 3 (active surface 10). The plurality of source regions 37 are formed in the surface portion of the body region 20. The plurality of source regions 37 have a higher n-type impurity concentration (peak value) than the semiconductor layer 7. The n-type impurity concentration of the plurality of source regions 37 is higher than the n-type impurity concentration of the high-concentration region 15. The plurality of source regions 37 may also have a 1×10 18 cm -3 Above and 1×10 21 cm -3 The following n-type impurity concentrations are taken as peak values.

[0195] The multiple source regions 37 extend in a strip-like pattern in the direction in which the corresponding trench structures 25 extend when viewed from above. The multiple source regions 37 are spaced apart from each other from the bottom of the body region 20 toward the active surface 10, and face the drift region 35 (semiconductor layer 7 / high-concentration region 15) directly below them across a portion of the body region 20 in the stacking direction. Together with the multiple drift regions 35 directly below them, the multiple source regions 37 define a channel (current path) extending along the wall of the corresponding trench structure 25. The multiple source regions 37 may also face the multiple intermediate regions 36 in the horizontal direction.

[0196] SiC semiconductor device 1 includes a plurality of contact regions 38 formed in a surface portion of first main surface 3 (active surface 10 ) in a region between a plurality of trench structures 25 . Contact regions 38 are formed in a surface portion of body region 20 .

[0197] The plurality of contact regions 38 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 20. The p-type impurity concentration (peak value) of the plurality of contact regions 38 is higher than the p-type impurity concentration (peak value) of the plurality of pillar regions 30. The p-type impurity concentration (peak value) of the plurality of contact regions 38 is higher than the p-type impurity concentration (peak value) of the plurality of intermediate regions 36. The plurality of contact regions 38 may also have a 1×10 18 cm -3 Above and 1×1021 cm -3 The following p-type impurity concentrations are taken as peak values.

[0198] Multiple contact regions 38 are located between adjacent source regions 37 and extend in a stripe shape in the direction in which the trench structures 25 extend. The multiple contact regions 38 are formed at intervals from the bottom of the body region 20 toward the active surface 10. In the stacking direction, the multiple contact regions 38 face the drift region 35 (semiconductor layer 7 / high-concentration region 15) directly below them, across a portion of the body region 20. The multiple contact regions 38 may also face the multiple intermediate regions 36 in the horizontal direction.

[0199] The structure on the outer peripheral region 9 side is shown below. Figure 13 It is a perspective view showing the structure of the outer peripheral area 9. Figure 14 It is a cross-sectional view showing a main part of the outer peripheral area 9. Figure 15 It is a cross-sectional view showing a main part of the outer peripheral area 9.

[0200] SiC semiconductor device 1 includes a p-type well region 39 formed in the surface portion of outer peripheral surface 11. Well region 39 is formed at intervals from the periphery of outer peripheral surface 11 (first to fourth side surfaces 5A to 5D) toward active surface 10 in a plan view, extending in a strip shape along active surface 10. In this embodiment, well region 39 is formed in a ring shape (specifically, a four-sided ring shape) surrounding active surface 10 in a plan view.

[0201] The well region 39 extends from the surface of the outer peripheral surface 11 toward the first to fourth connection surfaces 12A to 12D and along the surface of the first to fourth connection surfaces 12A to 12D. The well region 39 is electrically connected to the body region 20 at the surface of the active surface 10 .

[0202] Well region 39 is formed at intervals from the lower end of semiconductor layer 7 toward outer peripheral surface 11, and is opposed to base layer 6 via a portion of semiconductor layer 7. Specifically, well region 39 is formed at intervals from the bottom of high-concentration region 15 toward outer peripheral surface 11, and is located closer to the bottom of high-concentration region 15 than the bottom wall of trench structure 25. Well region 39 forms a pn junction with semiconductor layer 7 (high-concentration region 15).

[0203] The well region 39 is composed of a random region introduced into the surface portion of the semiconductor layer 7 by a random implantation method. The well region 39 has a thickness along the second-axis channel C2 that is smaller than the thickness of the high-concentration region 15. In addition, the thickness of the well region 39 is smaller than the thickness of the pillar region 30.

[0204] The well region 39 is different from the pillar region 30 and does not have a slow portion having a thickness of 0.5 μm or more. The well region 39 may also have a thickness of 1×10 15cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentrations are peak values: The well region 39 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 38 .

[0205] The p-type impurity concentration of well region 39 may be higher than the p-type impurity concentration of body region 20. Of course, the p-type impurity concentration of well region 39 may also be lower than that of body region 20. The p-type impurity concentration of well region 39 may also be substantially equal to the p-type impurity concentration of intermediate region 36. Of course, the p-type impurity concentration of well region 39 may be higher or lower than that of intermediate region 36.

[0206] The p-type impurity concentration of the well region 39 is preferably adjusted by at least one trivalent element. The trivalent element of the well region 39 may be the same as or different from the trivalent element of the pillar region 30. The trivalent element of the well region 39 may be at least one of boron, aluminum, gallium, and indium.

[0207] SiC semiconductor device 1 includes at least one (preferably two or more and twenty or less) p-type field region 40 formed in the surface portion of outer peripheral surface 11 (first main surface 3) in peripheral region 9. The number of field regions 40 is typically four or more and eight or less. Field regions 40 are electrically floating and mitigate the electric field within chip 2 at the periphery of first main surface 3. The number, width, depth, and p-type impurity concentration of field regions 40 are arbitrary and can take various values depending on the electric field to be mitigated.

[0208] In this embodiment, multiple field regions 40 are arranged at intervals from the periphery of active surface 10 (first to fourth connection surfaces 12A to 12D) and the periphery of chip 2 (first to fourth side surfaces 5A to 5D). Specifically, multiple field regions 40 are arranged at intervals from well region 39 toward the periphery of outer peripheral surface 11.

[0209] The plurality of field regions 40 are formed in a strip shape extending along the active region 8 in a plan view. The plurality of field regions 40 each have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. In this embodiment, the plurality of field regions 40 are formed in a ring shape (specifically, a four-sided ring shape) surrounding the active region 8 (i.e., the plurality of pillar regions 30) in a plan view.

[0210] The plurality of field regions 40 are formed in the semiconductor layer 7 at intervals from the lower end of the semiconductor layer 7 toward the outer peripheral surface 11, forming a pn junction with the semiconductor layer 7. The plurality of field regions 40 preferably have a bottom portion located toward the outer peripheral surface 11 relative to the middle of the thickness range of the semiconductor layer 7. The plurality of field regions 40 are preferably formed at intervals from the bottom of the high-concentration region 15 toward the outer peripheral surface 11, forming a pn junction with the high-concentration region 15.

[0211] In this embodiment, the plurality of field regions 40 are formed so as to be spaced apart from the plurality of pillar regions 30 on the peripheral side of the chip 2. Therefore, the plurality of field regions 40 do not face the plurality of pillar regions 30 in the stacking direction. The plurality of field regions 40 are located closer to the bottom side of the semiconductor layer 7 (high concentration region 15) than the bottom wall of the trench structure 25.

[0212] The bottoms of the plurality of field regions 40 may be located closer to the bottom of the semiconductor layer 7 (high-concentration region 15) than the depth of the upper ends of the plurality of pillar regions 30. Of course, the bottoms of the plurality of field regions 40 may also be located closer to the bottom wall of the trench structure 25 than the depth of the upper ends of the plurality of pillar regions 30.

[0213] The plurality of field regions 40 are composed of random regions introduced into the surface portion of the semiconductor layer 7 by a random implantation method. The plurality of field regions 40 have a thickness along the second-axis channel C2 that is smaller than the thickness of the high-concentration region 15. Furthermore, the thickness of the plurality of field regions 40 is smaller than the thickness of the pillar region 30.

[0214] The plurality of field regions 40 are different from the pillar regions 30 and the like and do not have a slow portion having a thickness of 0.5 μm or more. The plurality of field regions 40 may also have a thickness of 1×10 15 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentration is taken as the peak value. The p-type impurity concentration of the field region 40 may be substantially equal to the p-type impurity concentration of the body region 20. The p-type impurity concentration of the plurality of field regions 40 may be higher than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the plurality of field regions 40 may be lower than the p-type impurity concentration of the body region 20.

[0215] The p-type impurity concentration of the plurality of field regions 40 is preferably adjusted by at least one trivalent element. The trivalent element of the field regions 40 may be the same as or different from the trivalent element of the pillar regions 30. The trivalent element of the field regions 40 may be at least one of boron, aluminum, gallium, and indium.

[0216] The plurality of field regions 40 preferably have a width different from the column width WC of the pillar region 30. That is, the electric field mitigation effect provided by the plurality of field regions 40 is preferably adjusted separately from the plurality of pillar regions 30. The width of the plurality of field regions 40 is particularly preferably greater than the column width WC. Of course, the width of the plurality of field regions 40 may also be less than the column width WC. Furthermore, the width of the pillar region 30 may also be approximately equal to the column width WC.

[0217] The plurality of field regions 40 are preferably formed at a pitch different from the column pitch PC of the column regions 30. The pitch between the plurality of field regions 40 is particularly preferably greater than the column pitch PC. The pitch between the plurality of field regions 40 may be less than the column pitch PC. Alternatively, the pitch between the plurality of field regions 40 may be substantially equal to the column pitch PC.

[0218] SiC semiconductor device 1 includes an interlayer insulating film 41 covering first main surface 3. Interlayer insulating film 41 may also be referred to as an "insulating film," "interlayer film," or "intermediate insulating film." In this embodiment, interlayer insulating film 41 has a stacked structure including a first insulating film 42 and a second insulating film 43. First insulating film 42 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. First insulating film 42 preferably includes a silicon oxide film formed from the oxide of chip 2 (semiconductor layer 7).

[0219] The first insulating film 42 selectively covers the first main surface 3 in the active region 8 and the peripheral region 9. Specifically, the first insulating film 42 selectively covers the active surface 10, the peripheral surface 11, and the first to fourth connection surfaces 12A to 12D. The first insulating film 42 is connected to the insulating film 27 on the active surface 10, exposing the embedded electrode 28.

[0220] The first insulating film 42 covers the well region 39 and the plurality of field regions 40 on the outer peripheral surface 11. In this embodiment, the first insulating film 42 is connected to the first to fourth side surfaces 5A to 5D. Of course, the first insulating film 42 can also be formed spaced inward from the periphery of the outer peripheral surface 11, so that the semiconductor layer 7 is exposed from the periphery of the outer peripheral surface 11. The first insulating film 42 covers the body region 20 and the well region 39 on the first to fourth connecting surfaces 12A to 12D.

[0221] The second insulating film 43 is stacked on the first insulating film 42. The second insulating film 43 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 41 preferably includes a silicon oxide film. The second insulating film 43 covers the first main surface 3 in the active region 8 and the peripheral region 9 via the first insulating film 42. Specifically, the second insulating film 43 selectively covers the active surface 10, the peripheral surface 11, and the first to fourth connecting surfaces 12A to 12D via the first insulating film 42.

[0222] The second insulating film 43 covers the plurality of trench structures 25 (buried electrodes 28) in the active region 8. In the peripheral region 9, the second insulating film 43 covers the well region 39 and the plurality of field regions 40 via the first insulating film 42. In this embodiment, the second insulating film 43 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the second insulating film 43 can also be formed at intervals inward from the periphery of the peripheral surface 11, so that the periphery of the first principal surface 3 is exposed together with the first insulating film 42.

[0223] SiC semiconductor device 1 includes a plurality of contact openings 44 formed in interlayer insulating film 41. The plurality of contact openings 44 include a plurality of contact openings 44 (not shown) that expose the plurality of trench structures 25 (buried electrodes 28) and a plurality of contact openings 44 that expose the plurality of source regions 37. The plurality of contact openings 44 for source regions 37 are formed in regions between adjacent plurality of trench structures 25, exposing the plurality of source regions 37 and the plurality of contact regions 38.

[0224] SiC semiconductor device 1 includes a sidewall structure 45 disposed within interlayer insulating film 41 so as to cover at least one of first to fourth connecting surfaces 12A to 12D. Sidewall structure 45 is disposed on first insulating film 42 and covered by second insulating film 43. Sidewall structure 45 mitigates the step formed between active surface 10 and outer peripheral surface 11.

[0225] Sidewall structure 45 is formed in a strip shape extending along at least one of first to fourth connecting surfaces 12A to 12D. In this embodiment, sidewall structure 45 is formed in an annular shape (specifically, a four-sided annular shape) extending along first to fourth connecting surfaces 12A to 12D so as to surround active surface 10 when viewed from above.

[0226] The sidewall structure 45 may also include a portion extending in a film-like manner along the outer peripheral surface 11 and a portion extending in a film-like manner along the first to fourth connecting surfaces 12A to 12D. In this embodiment, the sidewall structure 45 is formed at intervals from the innermost field region 40 toward the active surface 10, and faces the well region 39 in the horizontal direction and the stacking direction via the first insulating film 42. The sidewall structure 45 may also face the body region 20 via the first insulating film 42.

[0227] Reference Figure 1 SiC semiconductor device 1 includes a gate pad 50 disposed on interlayer insulating film 41. Gate pad 50 is an electrode to which a gate potential is externally applied. Gate pad 50 may also be referred to as a "gate pad electrode," "first pad electrode," or the like. Gate pad 50 may also have a stacked structure including a Ti-based metal film and an Al-based metal film stacked sequentially from the interlayer insulating film 41 side.

[0228] In this embodiment, gate pad 50 is disposed on the portion of interlayer insulating film 41 that covers active region 8. Specifically, gate pad 50 is disposed on active surface 10 at a distance from peripheral surface 11 when viewed from above. Gate pad 50 is disposed in a region near the center of one side of active surface 10 (in this embodiment, second connection surface 12B) when viewed from above.

[0229] Of course, gate pad 50 can also be arranged in a region along the center of any of first to fourth connecting surfaces 12A to 12D. Of course, gate pad 50 can also be arranged at any corner of active surface 10 when viewed from above. Alternatively, gate pad 50 can be arranged in the center of active surface 10 when viewed from above. In this embodiment, gate pad 50 is formed into a quadrilateral shape when viewed from above.

[0230] SiC semiconductor device 1 includes at least one (or in this embodiment, multiple) gate wiring 51 extending from gate pad 50 to interlayer insulating film 41. Gate wiring 51 may also be referred to as "wiring," "wiring electrode," or the like. In this embodiment, multiple gate wirings 51 are arranged on active surface 10 at intervals from outer peripheral surface 11 when viewed from above.

[0231] The plurality of gate wirings 51 may have a stacked structure including a Ti-based metal film and an Al-based metal film stacked in this order from the side of the interlayer insulating film 41. In this embodiment, the plurality of gate wirings 51 include a first gate wiring 51A and a second gate wiring 51B.

[0232] The first gate wiring 51A extends from the gate pad 50 toward the first connection surface 12A and extends linearly along the periphery of the active surface 10 so as to intersect (specifically, orthogonally intersect) a portion (specifically, one end) of the plurality of trench structures 25. The first gate wiring 51A penetrates the interlayer insulating film 41 via a plurality of contact openings 44 and is electrically connected to one end of the plurality of trench structures 25.

[0233] The second gate wiring 51B extends from the gate pad 50 toward the third connection surface 12C and extends linearly along the periphery of the active surface 10, intersecting (specifically, orthogonally) with a portion (specifically, the other end portions) of the plurality of trench structures 25. The second gate wiring 51B penetrates the interlayer insulating film 41 via a plurality of contact openings 44 and is electrically connected to the other end portions of the plurality of trench structures 25.

[0234] SiC semiconductor device 1 includes a source pad 52 disposed on interlayer insulating film 41, spaced apart from gate pad 50 and gate wiring 51. Source pad 52 is an electrode to which a source potential is externally applied. Source pad 52 may also be referred to as a "source pad electrode," "second pad electrode," or the like. Source pad 52 may have a stacked structure including a Ti-based metal film and an Al-based metal film stacked sequentially from the interlayer insulating film 41 side.

[0235] In this embodiment, source pad 52 is disposed on active surface 10 at a distance from outer peripheral surface 11 in a plan view. In this embodiment, source pad 52 is formed in a polygonal shape having a recessed portion along gate pad 50 in a plan view. Of course, source pad 52 may also be formed in a quadrilateral shape in a plan view.

[0236] Source pad 52 penetrates interlayer insulating film 41 via contact openings 44 and is electrically connected to body region 20 , source regions 37 , and contact regions 38 . That is, source pad 52 is electrically connected to pillar regions 30 via body region 20 .

[0237] SiC semiconductor device 1 includes a drain pad 53 covering second main surface 4. Drain pad 53 is an electrode to which a drain potential is externally applied. Drain pad 53 may also be referred to as a "drain pad electrode," "third pad electrode," or the like. Drain pad 53 forms an ohmic contact with base layer 6 exposed from second main surface 4.

[0238] That is, the drain pad 53 is electrically connected to the plurality of drift regions 35 via the base layer 6. The drain pad 53 may also cover the entire area of the second main surface 4 in a manner continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 53 may also cover the second main surface 4 at intervals inward from the periphery of the chip 2 so that the periphery of the chip 2 is exposed.

[0239] The breakdown voltage that can be applied between source pad 52 and drain pad 53 (between first main surface 3 and second main surface 4) can be 500 V or more and 3000 V or less. The breakdown voltage can have a value falling within any range of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0240] Figure 16This is a schematic diagram showing a wafer 60 used in the manufacture of SiC semiconductor device 1. Wafer 60 is the base material of base layer 6 and is composed of SiC single crystal. Wafer 60 is formed in a flat disk shape. Of course, wafer 60 can also be formed in a flat rectangular parallelepiped shape. Wafer 60 has a first wafer main surface 61 on one side, a second wafer main surface 62 on the other side, and a wafer side surface 63 connecting the first wafer main surface 61 and the second wafer main surface 62.

[0241] The first wafer main surface 61 corresponds to the upper end of the base layer 6, and the second wafer main surface 62 corresponds to the lower end of the base layer 6. The first wafer main surface 61 and the second wafer main surface 62 are formed by the c-plane of the SiC single crystal. The first wafer main surface 61 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 62 is formed by the carbon surface of the SiC single crystal. The wafer 60 (the first wafer main surface 61 and the second wafer main surface 62) has the aforementioned off direction Do and off angle θo.

[0242] Wafer 60 has a mark 64 on wafer side 63 indicating the crystal orientation of the SiC single crystal. Mark 64 may include either or both an orientation flat and an orientation notch. The orientation flat is formed by a notch that appears linear when viewed from above. The orientation notch is formed by a notch that is cut into a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 61 when viewed from above.

[0243] The mark 64 may also include either or both of a first orientation flat extending along the m-axis direction and a second orientation flat extending along the a-axis direction. The mark 64 may also include either or both of an orientation notch recessed toward the m-axis direction and an orientation notch recessed toward the a-axis direction. Figure 14 , an orientation plane extending along the m-axis direction (first direction X) in a plan view is shown.

[0244] For example, a plurality of device regions 65 and a plurality of planned cutting lines 66 are defined on the wafer 60 by alignment marks or the like. Each device region 65 corresponds to the SiC semiconductor device 1. The plurality of device regions 65 are each defined in a quadrilateral shape in plan view.

[0245] In this method, multiple device regions 65 are arranged in a matrix along the first direction X and the second direction Y when viewed from above. The multiple device regions 65 are spaced inward from the periphery of the first wafer main surface 61 when viewed from above. Multiple planned cutting lines 66 are arranged in a grid pattern extending along the first direction X and the second direction Y to divide the multiple device regions 65.

[0246] Figure 17 1 is a flowchart showing an example of a method for manufacturing the SiC semiconductor device 1 . Figures 18A to 18O It is a cross-sectional perspective view showing an example of a method for manufacturing the SiC semiconductor device 1 . Figures 19A and 19B This is a schematic diagram for explaining the crystal orientation measurement process. Figures 20A and 20B This is a schematic diagram for explaining the ion implantation process. Figures 18A to 18O A cross-sectional perspective view showing a portion of the active region 8 of one device region 65 .

[0247] First, refer to Figure 18A , implement the aforementioned preparation process of the wafer 60 ( Figure 17 Next, the semiconductor layer 7 is formed ( Figure 17 The semiconductor layer 7 is formed by epitaxial growth with the first wafer main surface 61 (wafer 60) as a starting point.

[0248] Next, a step of measuring the crystal orientation of the semiconductor layer 7 is performed ( Figure 17 The crystal orientation of the semiconductor layer 7 includes a step of measuring the off angle θo of the semiconductor layer 7. That is, the step includes a step of measuring the crystal orientation of the second-axis channel C2 of the semiconductor layer 7.

[0249] Wafer 60 is cut from an ingot (SiC ingot) as a crystal block, but there is a risk of errors in the off angle θo due to process errors. If the off angle θo of wafer 60 is distorted, the off angle θo of semiconductor layer 7 will also be distorted, which will hinder the channel implantation process. Therefore, it is preferable to obtain data (information) on the off angle θo before the channel implantation process and perform the channel implantation process based on this data (information) on the off angle θo.

[0250] Reference Figure 19A In this step, the crystal orientation of the semiconductor layer 7 is measured by X-ray diffraction (so-called ω-2θ measurement method) using an X-ray diffraction device 67. The X-ray diffraction device 67 may also be called an "XRD (X-ray Diffraction) device."

[0251] The X-ray diffraction device 67 includes an irradiation unit 68 and a detection unit 69, and performs a rocking curve measurement method. The irradiation unit 68 irradiates the upper end of the semiconductor layer 7 (the first wafer main surface 61 of the wafer 60) with incident X-rays L1 having a predetermined incident angle ω. The incident angle ω is defined by the angle between the incident X-rays L1 and the upper end of the semiconductor layer 7 (the first wafer main surface 61 of the wafer 60).

[0252] Detection unit 69 is positioned at a diffraction angle 2θ (θ is the Bragg angle) relative to the position where incident X-ray L1 irradiates wafer 60, and detects diffracted X-ray L2. Diffraction angle 2θ is the angle between the incident direction of incident X-ray L1 and the diffraction direction of diffracted X-ray L2.

[0253] In the rocking curve measurement method, while the diffraction angle 2θ is fixed, the incident angle ω is varied within a small angular range to measure a rocking curve representing the intensity of the diffracted X-ray L2 (the intensity distribution of the diffracted X-ray L2). The rocking curve has the intensity of the diffracted X-ray L2 on the vertical axis and the incident angle ω on the horizontal axis. The incident angle ω is determined at the angular position where the intensity of the diffracted X-ray L2 reaches its peak.

[0254] In this step, the rocking curve measurement method is performed only on one location (e.g., the center) of the upper end (the first wafer main surface 61 of the wafer 60) of the semiconductor layer 7. If in-plane variation of the off angle θo is assumed, the rocking curve measurement method may also be performed on multiple locations (e.g., the center and the peripheral portion) of the upper end (the first wafer main surface 61 of the wafer 60) of the semiconductor layer 7.

[0255] exist Figure 19B , the measurement positions when the rocking curve measurement method is performed on multiple positions (here, 5 positions) of the upper end of the semiconductor layer 7 are shown. The off angle θo of the semiconductor layer 7 is set to about 4°. Figure 19B In FIG, the first to fifth measurement points Po1 to Po5 are shown.

[0256] The first measurement point Po1 is set at the center of the semiconductor layer 7. The second measurement point Po2 is set at the peripheral edge of the semiconductor layer 7 at a distance from the first measurement point Po1 to one side in the second direction Y (the side opposite to the mark 64). The third measurement point Po3 is set at the peripheral edge of the semiconductor layer 7 at a distance from the first measurement point Po1 to one side in the first direction X (the right side with respect to the mark 64).

[0257] The fourth measurement point Po4 is set at a distance from the first measurement point Po1 toward the other side in the second direction Y (toward the mark 64) at the peripheral portion of the semiconductor layer 7. The fifth measurement point Po5 is set at a distance from the first measurement point Po1 toward the other side in the first direction X (to the left of the mark 64) at the peripheral portion of the semiconductor layer 7.

[0258] The measurement results of the incident angle ω, diffraction angle 2θ, and deviation angle θo at the first to fifth measurement points Po1 to Po5 are shown in Table 1 below. The deviation angle θo was calculated using the formula "ω - (2θ × 1 / 2)" using the incident angle ω and the diffraction angle 2θ.

[0259] Table 1

[0260] Table 1

[0261]

[0262] As shown in Table 1, the average value of the off angle θo at the first to fifth measurement points Po1 to Po5 is 4.036°, and the standard deviation of these off angles θo is 0.009° (±0.01°). This shows that the in-plane variation of the off angle θo generated at the upper end of the semiconductor layer 7 (the first wafer main surface 61 of the wafer 60) is extremely small and does not hinder the channel implantation process.

[0263] Therefore, it is understood that there is no problem with at least one measurement location relative to the upper end of the semiconductor layer 7 (the first wafer main surface 61). For example, the measurement location may be any one or more (or all) of the first to fifth measurement points Po1 to Po5. For example, the measurement location may be only the first measurement point Po1. By reducing the number of measurement locations (the number of measurements), manufacturing man-hours (manufacturing costs) can be reduced.

[0264] Of course, the off angle θo can also be measured at multiple locations on the upper end of the semiconductor layer 7 (first wafer main surface 61), and the implantation angle can be set according to the in-plane deviation of the off angle θo during the channel implantation process. In this case, the manufacturing man-hours (manufacturing costs) increase, but the in-plane deviation of the pillar regions 30 formed in the semiconductor layer 7 can be appropriately suppressed.

[0265] The off angle θo of the semiconductor layer 7 is substantially identical to the off angle θo of the wafer 60. Therefore, the crystal orientation measurement step may be performed on the wafer 60 before the formation step of the semiconductor layer 7. However, for the sake of accuracy, the crystal orientation measurement step is preferably performed on the semiconductor layer 7.

[0266] Next, refer to Figure 18C , implement the formation process of the high concentration region 15 ( Figure 17 The step of forming the high-concentration region 15 includes a channel implantation step of a pentavalent element (n-type impurity) into the semiconductor layer 7. In this step, the pentavalent element is implanted throughout the entire semiconductor layer 7. The semiconductor layer 7 (wafer 60) has an off angle θo, tilted at a predetermined angle in a predetermined off direction Do relative to the first wafer main surface 61. The channel implantation step is performed based on data (information) regarding the off angle θo.

[0267] Reference Figure 20A In the random implantation method, a pentavalent element is introduced into the semiconductor layer 7 with a predetermined implantation energy in a direction intersecting the second axis channel C2 (offset angle θo) (also refer to Figure 11 For example, in the random implantation method, the pentavalent element is implanted along the vertical direction Z perpendicular to the upper end of the semiconductor layer 7 (the first wafer main surface 61 ).

[0268] In the random implantation method, the pentavalent element is introduced along a direction where the atomic rows are denser when viewed from above. Therefore, the pentavalent element collides with the atomic rows at a relatively shallow depth. Consequently, the introduction of the pentavalent element into a relatively deep position within the semiconductor layer 7 is hindered by the atomic rows. As a result, a high-concentration region 15 is formed that lacks the first slow portion 18.

[0269] On the other hand, refer to Figure 20B In the channel implantation method, the pentavalent element is implanted into the semiconductor layer 7 at a predetermined implantation energy along the second axis channel C2 (in this method, the c-axis of the SiC single crystal). Figure 10 In this case, either or both of the injection angle of the pentavalent element relative to the semiconductor layer 7 and the tilt angle of the semiconductor layer 7 relative to the injection angle of the pentavalent element are adjusted.

[0270] For example, the wafer 60 may be supported horizontally, and the pentavalent element may be introduced into the semiconductor layer 7 along the second-axis channel C2. Alternatively, the wafer 60 may be supported in a state tilted at an offset angle θo relative to the horizontal, and the pentavalent element may be introduced into the semiconductor layer 7 along the second-axis channel C2. By any combination of the implantation energy and implantation temperature of the pentavalent element, a high-concentration region 15 having a predetermined thickness is formed at a predetermined depth.

[0271] The implantation energy of the pentavalent element may be 100 KeV to 2000 KeV. The implantation energy may have a value falling within any range of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0272] The implantation temperature of the pentavalent element can be adjusted within a range of 0° C. to 1500° C. The implantation temperature can have a value falling within any range of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0273] The injection angle of the pentavalent element is preferably set within a range of (0°) ±2° with respect to the axis along the second-axis channel C2 (in this embodiment, the c-axis of the SiC single crystal). The injection angle of the pentavalent element is particularly preferably set within a range of (0°) ±1° with respect to the axis along the second-axis channel C2 (in this embodiment, the c-axis of the SiC single crystal).

[0274] In the case of the channel implantation method, the pentavalent element is introduced along the second-axis channel C2, where the atomic array is relatively sparse when viewed from above. The pentavalent element propagates within the second-axis channel C2 through repeated small-angle scattering due to the channeling effect, reaching a relatively deep position in the semiconductor layer 7. In other words, in the case of the channel implantation method, the probability of the pentavalent element colliding with the atomic array of the SiC single crystal is reduced. The pentavalent element is preferably arsenic or antimony.

[0275] After the pentavalent element implantation step, annealing can be performed to electrically activate the pentavalent element and simultaneously repair lattice defects generated in the semiconductor layer 7. The annealing temperature of the semiconductor layer 7 can be 500°C or higher and 2000°C or lower.

[0276] Next, refer to Figure 18D , implement the formation process of the main body region 20 ( Figure 17 The step of forming the main region 20 includes randomly implanting a trivalent element (p-type impurity) into the surface portion of the semiconductor layer 7. In this step, the trivalent element is introduced into the entire area of the semiconductor layer 7. For example, in the random implantation method, the trivalent element is implanted along a vertical direction Z perpendicular to the upper end of the semiconductor layer 7 (the first wafer main surface 61). As a result, the main region 20 is formed over the entire surface portion of the semiconductor layer 7.

[0277] Next, refer to Figure 18E , implement the formation process of multiple source regions 37 ( Figure 17 The plurality of source regions 37 are formed by introducing pentavalent elements into the surface portion of the semiconductor layer 7 by random implantation through a mask (not shown) having a predetermined layout.

[0278] In addition, a step of forming a plurality of contact regions 38 is performed ( Figure 17 The plurality of contact regions 38 are formed by randomly implanting a trivalent element into the surface portion of the semiconductor layer 7 through a mask (not shown) having a predetermined layout. The step of forming the contact regions 38 may be performed before the step of forming the source regions 37.

[0279] Next, refer to Figure 18F , a step of forming a first mask 71 having a predetermined pattern is performed ( Figure 17The first mask 71 is preferably an inorganic mask (hard mask). The first mask 71 is disposed on the upper end of the semiconductor layer 7 and has a plurality of first openings 71a that expose regions where the plurality of trenches 26 are to be formed.

[0280] The plurality of first openings 71a are formed at intervals in the first direction X and are each divided into strips extending in the second direction Y. In other words, the plurality of first openings 71a extend along the deviation direction Do when viewed from above. Furthermore, the first mask 71 includes first openings 71a (not shown) that expose the area where the outer peripheral surface 11 is to be formed. The first openings 71a for the outer peripheral surface 11 are formed in a grid pattern along the plurality of planned cutting lines 66.

[0281] Next, a plurality of trenches 26 are formed ( Figure 17 In step S9), in the process of forming the trench 26, unnecessary portions of the semiconductor layer 7 are removed by etching through the first mask 71. The etching method may be either wet etching or dry etching, or both.

[0282] The etching method is preferably RIE (Reactive Ion Etching). This forms a plurality of trenches 26 at the upper end of semiconductor layer 7. Furthermore, active surface 10, peripheral surface 11, and first to fourth connecting surfaces 12A to 12D are formed at the upper end of semiconductor layer 7. After forming the plurality of trenches 26, first mask 71 is removed.

[0283] Next, refer to Figure 18G , a step of forming a second mask 72 having a predetermined pattern is performed ( Figure 17 The second mask 72 is preferably an organic mask (resist mask). The second mask 72 is disposed on the upper end of the semiconductor layer 7 and has a plurality of second openings 72a that expose the plurality of trenches 26 in a one-to-one correspondence. The plurality of second openings 72a are formed at intervals in the first direction X and are each divided into strips extending in the second direction Y. In other words, the plurality of second openings 72a extend along the deviation direction Do when viewed from above.

[0284] Next, a step of forming a plurality of pillar regions 30 is performed ( Figure 17 The formation process of the plurality of pillar regions 30 includes a channel implantation process of a trivalent element (n-type impurity) into the semiconductor layer 7. The trivalent element is introduced into the lower region 7a of the semiconductor layer 7 through the bottom walls of the plurality of trenches 26 from the plurality of second openings 72a of the second mask 72. The channel implantation process is performed based on the data (information) of the aforementioned off angle θo.

[0285] In the channel implantation method, the implantation angle of the trivalent element relative to the semiconductor layer 7 is controlled, and the trivalent element is introduced into the semiconductor layer 7 at a predetermined implantation energy along the second-axis channel C2 (in this embodiment, the c-axis of the SiC single crystal). In this case, either or both of the implantation angle of the trivalent element relative to the semiconductor layer 7 and the tilt angle of the semiconductor layer 7 relative to the implantation angle of the trivalent element are adjusted.

[0286] For example, the wafer 60 may be supported horizontally, and the trivalent element may be introduced into the semiconductor layer 7 along the second-axis channel C2. Alternatively, the wafer 60 may be supported tilted at an offset angle θo relative to the horizontal, and the trivalent element may be introduced into the semiconductor layer 7 along the second-axis channel C2. By adjusting any combination of the implantation energy of the trivalent element and the implantation temperature of the trivalent element (the temperature of the wafer 60), a plurality of column regions 30 having a predetermined thickness are formed at predetermined depths.

[0287] The implantation energy of the trivalent element may be 100 KeV to 2000 KeV. The implantation energy may have a value falling within any range of 100 KeV to 250 KeV, 250 KeV to 500 KeV, 500 KeV to 750 KeV, 750 KeV to 1000 KeV, 1000 KeV to 1250 KeV, 1250 KeV to 1500 KeV, 1500 KeV to 1750 KeV, and 1750 KeV to 2000 KeV.

[0288] The implantation energy of the pillar region 30 may be substantially equal to or different from the implantation energy of the high-concentration region 15. The implantation energy of the pillar region 30 may be greater than or less than the implantation energy of the high-concentration region 15.

[0289] The implantation temperature of the trivalent element can be adjusted within a range of 0° C. to 1500° C. The implantation temperature may have a value falling within any one of the ranges of 0° C. to 25° C., 25° C. to 50° C., 50° C. to 100° C., 100° C. to 250° C., 250° C. to 500° C., 500° C. to 750° C., 750° C. to 1000° C., 1000° C. to 1250° C., and 1250° C. to 1500° C.

[0290] The injection temperature of the pillar region 30 may be substantially equal to or different from the injection temperature of the high concentration region 15. The injection temperature of the pillar region 30 may be higher than or lower than the injection temperature of the high concentration region 15.

[0291] The injection angle of the trivalent element is preferably set within a range of ±2° relative to the axis along the second-axis channel C2 (in this embodiment, the c-axis of the SiC single crystal) (0°). The injection angle of the trivalent element is particularly preferably set within a range of ±1° relative to the axis along the second-axis channel C2 (in this embodiment, the c-axis of the SiC single crystal) (0°).

[0292] In the case of the channel implantation method, the trivalent element is introduced along the second-axis channel C2, where the atomic array is relatively sparse when viewed from above. The trivalent element propagates within the second-axis channel C2 while repeatedly performing small-angle scattering due to the channeling effect, reaching a relatively deep position in the semiconductor layer 7. In other words, in the case of the channel implantation method, the probability of the trivalent element colliding with the atomic array of the SiC single crystal is reduced.

[0293] In this case, a trivalent element heavier than carbon is preferably introduced into the semiconductor layer 7. Specifically, the trivalent element is preferably a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the trivalent element is aluminum.

[0294] The plurality of second openings 72 a have an extension direction extending along the off direction Do, and the injection angle of the trivalent element is inclined toward the off direction Do. Therefore, the trivalent element is introduced into the semiconductor layer 7 substantially perpendicularly to the bottom wall of the trench 26 through the plurality of second openings 72 a in a cross-sectional view perpendicular to the extension direction.

[0295] This prevents the plurality of pillar regions 30 from being formed in an inclined position within the semiconductor layer 7. Furthermore, the walls of the plurality of second openings 72 a are prevented from blocking the incident path of the trivalent element. This reduces process variations in the plurality of pillar regions 30 caused by blocking by the walls of the plurality of second openings 72 a. Consequently, the accuracy of charge balancing is improved.

[0296] After the trivalent element implantation step, annealing can be performed to electrically activate the trivalent element and simultaneously repair lattice defects and the like generated in the semiconductor layer 7. The annealing temperature for the semiconductor layer 7 can be between 500°C and 2000°C. This allows the formation of a superjunction structure while simultaneously forming the plurality of pillar regions 30 and the plurality of drift regions 35.

[0297] The annealing method for the pillar region 30 may also serve as the annealing method for the high-concentration region 15. In this case, the annealing method for the high-concentration region 15 before the step of forming the pillar region 30 may be omitted. Figure 18HAfter the process of forming the plurality of pillar regions 30 , the second mask 72 is removed.

[0298] Next, refer to Figure 18I , a step of forming a third mask 73 having a predetermined pattern is performed ( Figure 17 The third mask 73 is preferably an organic mask (resist mask). The third mask 73 is disposed on the upper end of the semiconductor layer 7 and has a plurality of third openings 73a that selectively expose the plurality of trenches 26. The plurality of third openings 73a are spaced apart in the first direction X and the second direction Y to expose a portion of each of the plurality of trenches 26.

[0299] Next, a plurality of intermediate regions 36 are formed ( Figure 17 The step of forming the plurality of intermediate regions 36 includes introducing a trivalent element into the semiconductor layer 7 at a predetermined implantation energy in a direction intersecting the second-axis channel C2 (offset angle θo) using a random implantation method through the third mask 73. The trivalent element is introduced into the semiconductor layer 7 (high-concentration region 15) through the walls (sidewalls and bottom walls) of the plurality of trenches 26 from the plurality of third openings 73a. The trivalent element may be introduced into the semiconductor layer 7 once or multiple times.

[0300] When the trivalent element is introduced multiple times, the trivalent element can be introduced into different depth positions of the semiconductor layer 7 in multiple stages with multiple implantation energies. The trivalent element can also be introduced into the semiconductor layer 7 (high concentration region 15) through the walls (side walls and bottom walls) of the multiple trenches 26 by an inclined ion implantation method. Figure 18J After the formation process of the plurality of intermediate regions 36 , the third mask 73 is removed.

[0301] The process of forming the plurality of intermediate regions 36 can also serve as the process of forming the well region 39. The well region 39 is formed by introducing a trivalent element into the semiconductor layer 7 (high-concentration region 15) through the plurality of third openings 73a via the outer peripheral surface 11 and the first to fourth connecting surfaces 12A to 12D. Of course, the well region 39 can also be formed by introducing the trivalent element into the surface layer portion of the semiconductor layer 7 by a random implantation method using a mask different from the third mask 73.

[0302] Although not specifically shown in the figure, a step of forming the plurality of field regions 40 is performed before or after the step of forming the well region 39. The plurality of field regions 40 are formed by introducing a trivalent element into the surface portion of the semiconductor layer 7 by a random implantation method through a mask (not shown) having a predetermined layout.

[0303] Next, refer to Figure 18K , the insulating film 27 is formed ( Figure 17The insulating film 27 formation step also serves as the first insulating film 42 formation step. The insulating film 27 can also be formed by either or both of CVD (Chemical Vapor Deposition) and oxidation. The insulating film 27 and the first insulating film 42 are typically formed by thermal oxidation. The insulating film 27 is formed in a film-like manner on the walls of the plurality of trenches 26, and the first insulating film 42 is formed in a film-like manner in the region outside the plurality of trenches 26 at the upper end of the semiconductor layer 7.

[0304] Next, refer to Figure 18L , the process of forming the buried electrode 28 is implemented ( Figure 17 This step includes forming a base electrode film 74 on the insulating film 27. In this method, the base electrode film 74 comprises conductive polysilicon. The base electrode film 74 backfills the plurality of trenches 26 and covers the upper end of the semiconductor layer 7. The base electrode film 74 can also be formed by CVD.

[0305] Next, refer to Figure 18M The unnecessary portion of the embedded electrode 28 is removed by etching. The unnecessary portion of the embedded electrode 28 is removed until the insulating film 27 is exposed. The etching method can be either wet etching or dry etching, or both. Thus, multiple embedded electrodes 28 are embedded in each of the multiple trenches 26, forming multiple trench structures 25.

[0306] Next, refer to Figure 18N , the interlayer insulating film 41 (second insulating film 43) is formed ( Figure 17 The interlayer insulating film 41 may also be formed by CVD. In the interlayer insulating film 41, a plurality of contact openings 44 having a predetermined layout are formed by etching through a mask (not shown) having a predetermined layout.

[0307] Next, refer to Figure 18O , implement the formation process of the gate pad 50, the gate wiring 51 and the source pad 52 ( Figure 17 The gate pad 50, the gate wiring 51, and the source pad 52 are formed by depositing a metal film on the interlayer insulating film 41 by sputtering and then etching through a mask (not shown) having a predetermined layout to form a predetermined layout.

[0308] Next, the drain pad 53 is formed ( Figure 17 The drain pad 53 is formed by depositing a metal film on the second wafer main surface 62 by sputtering. Then, the wafer 60 is cut along a plurality of cutting lines 66 ( Figure 17Through the above steps, a plurality of SiC semiconductor devices 1 are manufactured from one wafer 60 .

[0309] Other examples of the trench structure 25 are described below. Figure 21 2 is a perspective view showing a cross-section of the trench structure 25 according to the second embodiment. Figure 21 The plurality of trench structures 25 of the second embodiment each have a structure that contributes to narrowing the pitch. The plurality of trench structures 25 of the second embodiment are particularly effective in achieving narrowing the pitch of the plurality of pillar regions 30 .

[0310] Each of the plurality of trench structures 25 includes a trench 26, an insulating film 27, an embedded electrode 28, and an embedded insulator 80. The trenches 26 have the same configuration as in the first embodiment. In this embodiment, the insulating film 27 is formed at intervals from the first principal surface 3 (active surface 10) toward the bottom wall of the trench 26, with the surface portion of the first principal surface 3 (active surface 10) exposed at the open end of the trench 26. The upper end of the insulating film 27 is preferably located on the first principal surface 3 side relative to the middle of the depth range of the trench 26.

[0311] In this embodiment, the embedded electrode 28 is embedded in the trench 26 at intervals from the first principal surface 3 (active surface 10) toward the bottom wall of the trench 26, and defines an open groove at the open end of the trench 26 that is recessed toward the bottom wall of the trench 26. The embedded electrode 28 exposes the surface portion of the first principal surface 3 (active surface 10) and the upper end portion of the insulating film 27 at the open end of the trench 26. The upper end portion of the embedded electrode 28 is preferably located on the first principal surface 3 side relative to the middle of the depth range of the trench 26.

[0312] The embedded insulator 80 is embedded in the trench 26 (open recess) so as to expose the first principal surface 3 (active surface 10), and the trench 26 is covered with the insulating film 27 and the embedded electrode 28. The embedded insulator 80 is embedded in the trench 26 at intervals from the first principal surface 3 (active surface 10) toward the embedded electrode 28, and the surface layer of the first principal surface 3 (active surface 10) is exposed at the open end of the trench 26.

[0313] The upper end of the buried insulator 80 is preferably located on the first main surface 3 side relative to the middle of the depth range of the trench 26. The buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The buried insulator 80 preferably includes a silicon oxide film.

[0314] In this embodiment, the plurality of source regions 37 are formed in regions between adjacent trench structures 25 in the surface portion of the first main surface 3 (active surface 10). The plurality of source regions 37 are arranged at intervals along the plurality of trench structures 25 so as to connect to the plurality of trench structures 25 located on both sides.

[0315] Specifically, the plurality of source regions 37 arranged along one sidewall of the trench structure 25 are arranged along the other sidewall of the trench structure 25, facing the plurality of source regions 37 on the other side in a one-to-one correspondence. That is, the plurality of source regions 37 are arranged in a matrix when viewed from above.

[0316] Of course, the multiple source regions 37 on one side may be arranged in a one-to-one correspondence with the regions between the multiple source regions 37 on the other side. That is, the multiple source regions 37 may be arranged in a staggered pattern in a plan view. The multiple source regions 37 have portions exposed from the sidewalls of the trench 26 at the open end of the trench 26, and are opposed to the embedded electrode 28 and the embedded insulator 80 via the insulating film 27.

[0317] In this embodiment, the plurality of contact regions 38 are formed in the region between adjacent groove structures 25 in the surface portion of the first main surface 3 (active surface 10). The plurality of contact regions 38 are arranged at intervals along the plurality of groove structures 25 so as to connect to the plurality of groove structures 25 located on both sides.

[0318] Specifically, the plurality of contact regions 38 are arranged alternately with the plurality of source regions 37 along the plurality of trench structures 25. More specifically, the plurality of contact regions 38 arranged along the sidewall of one side of the trench structure 25 are arranged along the sidewall of the other side of the trench structure 25, and are opposed to the plurality of contact regions 38 on the other side in a one-to-one correspondence. Furthermore, the plurality of source regions 37 are arranged in a matrix when viewed from above.

[0319] Of course, the multiple contact regions 38 on one side may be arranged in a one-to-one correspondence with the region between the multiple source regions 37 on the other side (i.e., the multiple source regions 37). In other words, the multiple contact regions 38 may be arranged in a staggered pattern when viewed from above. The multiple contact regions 38 have portions exposed from the sidewalls of the trench 26 at the open end of the trench 26, and are opposed to the embedded electrode 28 and the embedded insulator 80 via the insulating film 27.

[0320] Although not specifically shown, the interlayer insulating film 41 has a stacked structure including a first insulating film 42 and a second insulating film 43. As in the first embodiment, the first insulating film 42 selectively covers the active surface 10, the outer peripheral surface 11, and the first to fourth connection surfaces 12A to 12D.

[0321] In this embodiment, the first insulating film 42 covers the periphery of the active surface 10, exposing the plurality of trench structures 25 within the active surface 10. Specifically, the first insulating film 42 connects to the insulating film 27 at both ends of the plurality of trench structures 25, exposing the embedded electrodes 28. Furthermore, the first insulating film 42 covers the outer peripheral surface 11 and the first to fourth connecting surfaces 12A to 12D in the same manner as in the first embodiment.

[0322] As in the first embodiment, the second insulating film 43 selectively covers the active surface 10, the outer peripheral surface 11, and the first to fourth connection surfaces 12A to 12D via the first insulating film 42. In this embodiment, the second insulating film 43 covers the periphery of the active surface 10, exposing the plurality of trench structures 25 within the active surface 10. Specifically, the second insulating film 43 extends from above the first principal surface 3 (active surface 10) at both ends of the plurality of trench structures 25 into the trenches 26, connecting to the buried insulator 80 within the trenches 26.

[0323] In this manner, the interlayer insulating film 41 includes a plurality of contact openings 44 (not shown) that expose both ends of the plurality of trench structures 25 (buried electrodes 28), and a single contact opening 44 that exposes the interiors of the plurality of trench structures 25 (buried insulators 80), the plurality of source regions 37, and the plurality of contact regions 38.

[0324] The gate pad 50, the plurality of gate wirings 51, and the drain pad 53 are similar to those of the first embodiment. The source pad 52 extends from above the interlayer insulating film 41 into a single contact opening 44, and covers the interiors of the plurality of trench structures 25 (buried insulator 80), the plurality of source regions 37, and the plurality of contact regions 38 within the single contact opening 44.

[0325] Source pad 52 is electrically insulated from multiple trench structures 25 (buried electrodes 28) by buried insulator 80 and is electrically connected to multiple source regions 37 and multiple contact regions 38 on first main surface 3 (active surface 10). In this embodiment, source pad 52 is also electrically connected to the exposed portions of multiple intermediate regions 36 on first main surface 3.

[0326] Source pad 52 has a buried portion buried in trench 26. The buried portion of source pad 52 faces buried electrode 28 via buried insulator 80 in trench 26 and is electrically connected to source regions 37 and contact regions 38 at the open end of trench 26.

[0327] Figure 22 : is a cross-sectional perspective view showing a trench structure 25 according to a third embodiment. Figure 22The plurality of trench structures 25 of the third embodiment example each have a structure obtained by deforming the plurality of trench structures 25 of the second embodiment example.

[0328] Each of the trench structures 25 includes a trench 26, an insulating film 27, a buried electrode 28, and a buried insulator 80. The trench 26 has the same configuration as that of the first embodiment. In this embodiment, the insulating film 27 includes an upper insulating film 81 and a lower insulating film 82.

[0329] The upper insulating film 81 is formed as the channel control insulating film 27 and covers the wall surface of the trench 26 on the opening side relative to the bottom of the body region 20. The upper insulating film 81 has a portion that crosses the boundary between the semiconductor layer 7 (high-concentration region 15) and the body region 20 and covers the semiconductor layer 7 (high-concentration region 15). In this case, the coverage area of the upper insulating film 81 with respect to the body region 20 is preferably larger than the coverage area of the upper insulating film 81 with respect to the drift region 35.

[0330] The upper insulating film 81 may also include a silicon oxide film. The upper insulating film 81 preferably includes a silicon oxide film composed of the oxide of the chip 2. The upper insulating film 81 may also have a thickness of 1 nm to 100 nm. The thickness of the upper insulating film 81 may have a value within any range of 1 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, and 75 nm to 100 nm.

[0331] The lower insulating film 82 covers the bottom wall of the trench 26 relative to the bottom of the body region 20. The lower insulating film 82 covers the semiconductor layer 7 (high concentration region 15). The coverage area of the drift region 35 by the lower insulating film 82 is larger than the coverage area of the body region 20 by the upper insulating film 81.

[0332] The lower insulating film 82 may also include a silicon oxide film. The lower insulating film 82 may include a silicon oxide film composed of the oxide of the chip 2 or may include a silicon oxide film formed by CVD. The lower insulating film 82 has a thickness greater than that of the upper insulating film 81. The thickness of the lower insulating film 82 is preferably not less than 10 times and not more than 50 times the thickness of the upper insulating film 81.

[0333] The lower insulating film 82 may have a thickness of 100 nm to 500 nm. The thickness of the lower insulating film 82 may have a value within any range of 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0334] In this embodiment, the embedded electrode 28 has a multi-electrode structure (a dual-electrode structure) including an upper electrode 83, a lower electrode 84, and an intermediate insulating film 85. The upper electrode 83 is embedded on the opening side of the trench 26 via the insulating film 27. Specifically, the upper electrode 83 is embedded on the opening side of the trench 26 via the upper insulating film 81, and faces the body region 20 via the upper insulating film 81.

[0335] The area of the upper electrode 83 facing the body region 20 is larger than the area of the upper electrode 83 facing the drift region 35. In this embodiment, the upper electrode 83 is embedded in the trench 26 at intervals from the first main surface 3 (active surface 10) toward the bottom wall side of the trench 26, and defines an open groove at the open end of the trench 26 that is recessed toward the bottom wall of the trench 26. The upper electrode 83 exposes the surface portion of the first main surface 3 (active surface 10) and the upper end portion of the upper insulating film 81 at the open end of the trench 26.

[0336] A gate potential serving as a control potential is applied to the upper electrode 83. In response to the gate potential, the upper electrode 83 controls inversion and non-inversion of the channel (current path) in the body region 20. The upper electrode 83 may also include p-type or n-type conductive polysilicon.

[0337] The lower electrode 84 is embedded in the bottom wall of the trench 26 via the insulating film 27. Specifically, the lower electrode 84 is embedded in the bottom wall of the trench 26 via the lower insulating film 82, and faces the drift region 35 via the lower insulating film 82. In other words, the lower electrode 84 is embedded in the bottom wall of the trench 26 relative to the bottom of the body region 20. Although not specifically illustrated, the lower electrode 84 is led out to the opening of the trench 26 at a portion of the trench 26 (in this embodiment, both ends).

[0338] The area of the lower electrode 84 facing the drift region 35 is larger than the area of the upper electrode 83 facing the body region 20. The lower electrode 84 extends in a wall-like manner along the depth direction of the trench 26. The lower electrode 84 has an upper end portion that protrudes from the lower insulating film 82 toward the upper electrode 83 and is bonded to the lower end portion of the upper electrode 83. The upper end portion of the lower electrode 84 is horizontally opposed to the upper insulating film 81 (body region 20) across the lower end portion of the upper electrode 83.

[0339] Alternatively, a gate potential or a source potential may be applied to the lower electrode 84. When a gate potential is applied to the lower electrode 84, the lower electrode 84 has the same potential as the upper electrode 83. Therefore, the voltage drop between the upper electrode 83 and the lower electrode 84 is suppressed. This suppresses electric field concentration on the trench structure 25.

[0340] On the other hand, when a source potential is applied to the lower electrode 84, the lower electrode 84 can function as a field electrode. Consequently, the parasitic capacitance between the lower electrode 84 (field electrode) and the drift region 35 is reduced. This suppresses a decrease in switching speed due to the parasitic capacitance. The lower electrode 84 can be made of p-type or n-type conductive polysilicon.

[0341] Intermediate insulating film 85 is interposed between upper electrode 83 and lower electrode 84, electrically insulating upper electrode 83 from lower electrode 84 within trench 26. Intermediate insulating film 85 is connected to upper insulating film 81 and lower insulating film 82. Intermediate insulating film 85 is thinner than lower insulating film 82. The thickness of intermediate insulating film 85 is preferably greater than that of upper insulating film 81. Intermediate insulating film 85 may also include a silicon oxide film. Intermediate insulating film 85 preferably includes a silicon oxide film formed from the oxide of lower electrode 84.

[0342] The embedded insulator 80 is embedded in the trench 26 (opening groove) so as to expose the first principal surface 3 (active surface 10), and the groove is covered with an upper insulating film 81 and an upper electrode 83. The embedded insulator 80 is embedded in the trench 26 at a distance from the first principal surface 3 (active surface 10) toward the upper electrode 83, and the surface layer of the first principal surface 3 (active surface 10) is exposed at the open end of the trench 26.

[0343] In this embodiment, the plurality of source regions 37 have portions exposed from the sidewalls of the trench 26 at the open end of the trench 26, and face the upper electrode 83 and the buried insulator 80 via the upper insulating film 81. In this embodiment, the plurality of contact regions 38 have portions exposed from the sidewalls of the trench 26 at the open end of the trench 26, and face the upper electrode 83 and the buried insulator 80 via the upper insulating film 81.

[0344] In this embodiment, the plurality of gate wirings 51 penetrate the interlayer insulating film 41 via the plurality of contact openings 44 and are electrically connected to the plurality of upper electrodes 83. When a gate potential is applied to the lower electrodes 84, the plurality of gate wirings 51 penetrate the interlayer insulating film 41 via the plurality of contact openings 44 and are electrically connected to the plurality of upper electrodes 83 and the plurality of lower electrodes 84.

[0345] When a source potential is applied to lower electrodes 84, source pad 52 is electrically connected to the plurality of lower electrodes 84. In this case, SiC semiconductor device 1 may also include a source wiring extending from source pad 52 to interlayer insulating film 41. In this case, the source wiring is formed as a line extending along the periphery of active surface 10 in a region outside the plurality of gate wirings 51, intersecting (specifically, orthogonal to) a portion (one or both ends) of the plurality of trench structures 25. The source wiring penetrates interlayer insulating film 41 via a plurality of contact openings 44 and is electrically connected to the plurality of lower electrodes 84.

[0346] Figure 23 This is a cross-sectional perspective view of a trench structure 25 according to a fourth embodiment. In the first embodiment, the plurality of trench structures 25 are arranged at intervals in the first direction X (m-axis direction) and are each formed into a strip extending in the second direction Y (a-axis direction). However, the plurality of trench structures 25 may each be formed into a strip extending in the first direction X (m-axis direction) and arranged at intervals in the second direction Y (a-axis direction).

[0347] Based on the layout of the multiple trench structures 25, the multiple pillar regions 30 are formed into strips extending in the first direction X (m-axis direction) and are spaced apart in the second direction Y (a-axis direction). In this case, the extension direction of the multiple pillar regions 30 intersects (specifically, is perpendicular to) the off direction Do of the SiC single crystal. Therefore, when viewed in cross-section from the m-plane of the SiC single crystal, the multiple pillar regions 30 are tilted from the vertical axis toward the off direction Do by approximately an off angle θo. Therefore, in order to ensure accurate charge balance, it is preferable that the multiple pillar regions 30 extend along the off direction Do.

[0348] Of course, the arrangement direction of the plurality of trench structures 25 may be a direction other than the a-axis and the m-axis, and the extension direction of the plurality of trench structures 25 may be a direction other than the a-axis and the m-axis. In other words, the plurality of trench structures 25 may extend in a direction intersecting both the a-axis and the m-axis. In this case, the arrangement direction of the plurality of pillar regions 30 is a direction other than the a-axis and the m-axis, and the extension direction of the plurality of pillar regions 30 is a direction other than the a-axis and the m-axis. In other words, the plurality of pillar regions 30 extend in a direction intersecting both the a-axis and the m-axis.

[0349] The following describes modified examples of the SiC semiconductor device 1. The structures of the modified examples are applicable to the first to fourth embodiments described above. Figure 24 This is a cross-sectional perspective view of a SiC semiconductor device 1 according to a first modification. In the above embodiment, SiC semiconductor device 1 includes high-concentration region 15. In contrast, SiC semiconductor device 1 according to a second modification does not include high-concentration region 15. In this case, multiple trench structures 25, multiple pillar regions 30, multiple drift regions 35, and the like are formed within semiconductor layer 7.

[0350] Figure 25 This is a cross-sectional perspective view of a second modified SiC semiconductor device 1. The second modified SiC semiconductor device 1 further includes an n-type buffer layer 86 made of single-crystal SiC stacked on the base layer 6. The buffer layer 86 is also a component of the chip 2. The buffer layer 86 may also be referred to as a "buffer SiC layer," a "buffer region," or the like.

[0351] Buffer layer 86 extends horizontally in a layered manner, forming the middle portion of chip 2 and a portion of first to fourth side surfaces 5A to 5D. Buffer layer 86 is composed of an epitaxial layer (ie, a SiC epitaxial layer) crystal-grown starting from base layer 6 .

[0352] The buffer layer 86 has a lower end and an upper end. The lower end of the buffer layer 86 is the starting point of crystal growth, and the upper end of the buffer layer 86 is the end point of crystal growth. The buffer layer 86 continuously crystallizes and grows from the base layer 6, so the lower end of the buffer layer 86 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the buffer layer 86 is not necessarily visually discernible and can be indirectly evaluated and / or determined based on other structures and factors. The buffer layer 86 has a deviation direction Do and deviation angle θo that are substantially consistent with those of the base layer 6.

[0353] The buffer layer 86 has a third-axis channel C3 along the stacking direction. The third-axis channel C3 is a region (channel) where the interatomic distance (atomic spacing) of the SiC single crystal constituting the buffer layer 86 is relatively wide, and is surrounded by atomic rows along the crystal axis extending in the stacking direction (crystal growth direction).

[0354] Specifically, the third-axis channel C3 is a region where the atomic rows are sparse, extending in the stacking direction, and the atomic rows (interatomic distance / atomic density) in the horizontal direction are sparse when viewed from above. The third-axis channel C3 is preferably a region surrounded by atomic rows along the low-index crystal axis.

[0355] In this method, the third-axis channel C3 is formed by a region surrounded by atomic rows along the c-axis of the SiC single crystal. Specifically, the third-axis channel C3 extends along the c-axis, has an off direction Do, and an off angle θo. In other words, the third-axis channel C3 is tilted from the vertical axis toward the off direction Do by the off angle θo.

[0356] The n-type impurity concentration of the buffer layer 86 is preferably lower than that of the base layer 6. The buffer layer 86 may also have a 1×10 15 cm -3 Above and 1×10 18 cm -3 The following n-type impurity concentration is taken as the peak value. The n-type impurity concentration of the buffer layer 86 may also be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the buffer layer 86 may also have a concentration gradient that gradually increases and / or decreases toward the stacking direction (crystal growth direction).

[0357] The buffer layer 86 has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the buffer layer 86 can also be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The buffer layer 86 preferably includes a pentavalent element other than phosphorus.

[0358] The n-type impurity concentration of buffer layer 86 is preferably adjusted by at least nitrogen. When buffer layer 86 includes two or more pentavalent elements, buffer layer 86 preferably includes nitrogen and a pentavalent element other than nitrogen. In this case, buffer layer 86 preferably includes either or both of arsenic and antimony as the pentavalent element other than phosphorus and nitrogen.

[0359] The buffer layer 86 has a third thickness T3. The third thickness T3 is preferably less than the first thickness T1 of the base layer 6. The third thickness T3 is preferably 1 μm or greater. The third thickness T3 is preferably 5 μm or less. The third thickness T3 may have a value within any range of 1 μm or greater and 1.5 μm or less, 1.5 μm or greater and 2 μm or less, 2 μm or greater and 2.5 μm or less, 2.5 μm or greater and 3 μm or less, 3 μm or greater and 3.5 μm or less, 3.5 μm or greater and 4 μm or less, 4 μm or greater and 4.5 μm or less, and 4.5 μm or greater and 5 μm or less.

[0360] Semiconductor layer 7 is stacked on buffer layer 86. Semiconductor layer 7 is composed of an epitaxial layer (i.e., a SiC epitaxial layer) that has been crystallized and grown starting from buffer layer 86. Therefore, semiconductor layer 7 has an offset direction Do and an offset angle θo that are substantially consistent with those of buffer layer 86. Furthermore, the second-axis channel C2 and the third-axis channel C3 are substantially consistent.

[0361] The second thickness T2 of the semiconductor layer 7 is preferably greater than the third thickness T3. Of course, the second thickness T2 may also be less than the third thickness T3. In addition, the second thickness T2 may also be substantially equal to the third thickness T3.

[0362] The above-described method can also be implemented in other ways. For example, in the above-described method, the base layer 6, semiconductor layer 7, and buffer layer 86 are each composed of SiC single crystal. However, at least one or all of the base layer 6, semiconductor layer 7, and buffer layer 86 may also be composed of a single crystal of a wide-bandgap semiconductor other than SiC single crystal.

[0363] Wide-bandgap semiconductors are semiconductors with a bandgap larger than that of silicon. Examples of wide-bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga2O3). The base layer 6, semiconductor layer 7, and buffer layer 86 may be composed of the same type of single crystal or different types of single crystals.

[0364] The above-described channel implantation process (the process of implanting impurities into regions with sparse atomic rows) can also be applied to single crystals forming cubic crystals. Therefore, the wide-bandgap semiconductor single crystal can be either cubic or hexagonal. When a cubic single crystal is used for at least one or all of the base layer 6, semiconductor layer 7, and buffer layer 86, these axial channels are formed by regions surrounded by atomic rows along the low-index crystal axes of the cubic crystal.

[0365] The low-index crystal axis of the cubic crystal is a crystal axis for which the absolute values of "h", "k", and "l" are all less than 2 (preferably less than 1) with respect to the Miller indices (h, k, l). Of course, at least one or all of the base layer 6, the semiconductor layer 7, and the buffer layer 86 may also include single crystal silicon.

[0366] In the above embodiment, an n-type base layer 6 is shown. However, a p-type base layer 6 may also be used. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of a MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure. The p-type base layer 6 may also be a p-type region containing a trivalent element introduced into the surface portion of the second main surface 4 of the chip 2 by ion implantation.

[0367] The following describes examples of features extracted from this specification and the accompanying drawings. Below, alphanumeric characters in parentheses indicate corresponding components in the aforementioned embodiments, but are not intended to limit the scope of each clause to the aforementioned embodiments. The term "semiconductor device" in the following clauses can be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," and the like, as needed.

[0368] [A1] A semiconductor device 1 comprises: a semiconductor layer 7 of a first conductive type (n-type), which includes a main surface 3 and has an axial channel C2 in the stacking direction; a groove 26 formed on the main surface 3 and dividing a lower side region 7a between the main surface 3 and the bottom of the semiconductor layer 7; and a column region 30 of a second conductive type (p-type), which is formed in the lower side region 7a within the semiconductor layer 7 and extends along the axial channel C2.

[0369] [A2] The semiconductor device 1 according to A1, wherein the pillar region 30 traverses a middle portion of the thickness range of the lower region 7 a along the axial channel C2 .

[0370] [A3] The semiconductor device 1 according to A1 or A2, wherein the pillar region 30 has a thickness TC in the thickness direction Z of the semiconductor layer 7 that is greater than a depth DT of the trench 26 .

[0371] [A4] The semiconductor device 1 according to any one of A1 to A3, wherein the pillar region 30 has an aspect ratio TC / WC extending in a vertically long columnar shape along the axial channel C2.

[0372] [A5] The semiconductor device 1 according to any one of A1 to A4, wherein the pillar region 30 is composed of a single impurity region.

[0373] [A6] The semiconductor device 1 according to any one of A1 to A5, wherein the column region 30 has an upper end portion on the trench 26 side and a lower end portion on the bottom side of the semiconductor layer 7, and has a concentration gradient that gradually decreases from the upper end portion toward the lower end portion.

[0374] [A7] The semiconductor device 1 according to A6, wherein the concentration gradient includes: a peak P2 on the upper end side; and a slow portion 33 whose impurity concentration gradually decreases in the region on the lower end side at a rate slower than that of the peak P2.

[0375] [A8] The semiconductor device 1 according to A7, wherein the slow portion 33 occupies a thickness range of 1 / 4 or more of the pillar region 30 .

[0376] [A9] The semiconductor device 1 according to any one of A1 to A8, wherein the trench 26 extends in a stripe shape in a plan view, and the pillar region 30 extends in a stripe shape along the trench 26 in a plan view.

[0377] [A10] The semiconductor device 1 according to A9, wherein the trench 26 extends along the a-axis direction of the semiconductor layer 7 in a plan view.

[0378] [A11] A semiconductor device 1 according to any one of A1 to A10, wherein the semiconductor layer 7 has a deviation angle θo inclined toward the deviation direction Do with respect to the vertical axis Z, and the axial channel has the deviation angle θo inclined toward the deviation direction Do with respect to the vertical axis Z.

[0379] [A12] The semiconductor device 1 according to A11, wherein the off direction Do is the a-axis direction of the semiconductor layer 7 .

[0380] [A13] The semiconductor device 1 according to A11 or A12, wherein the off angle θo is 10° or less.

[0381] [A14] The semiconductor device 1 according to any one of A1 to A13, wherein the pillar region 30 is formed on the bottom side of the semiconductor layer 7 at a distance from the trench 26 .

[0382] [A15] The semiconductor device 1 according to A14 further includes an intermediate region 36 of the second conductivity type (p-type), which is formed in the semiconductor layer 7 in a region between the trench 26 and the pillar region 30.

[0383] [A16] The semiconductor device 1 according to A15 further includes a main body region 20 of a second conductive type (p-type) formed on the surface portion of the main surface 3, the groove 26 passes through the main body region 20, and the intermediate region 36 is electrically connected to the main body region 20 and the column region 30.

[0384] [A17] The semiconductor device 1 according to A16 further includes a first conductivity type (n-type) source region 37 formed on the side of the trench 26 in the surface portion of the body region 20 .

[0385] [A18] The semiconductor device 1 according to A16 or A17 further includes a contact region 38 of a second conductive type (p-type), which has an impurity concentration higher than the impurity concentration of the main region and is formed on the side of the groove 26 in the surface portion of the main region.

[0386] [A19] The semiconductor device 1 according to any one of A1 to A18 further includes a high-concentration region 15 of the first conductive type (n-type), which has an impurity concentration higher than the impurity concentration of the semiconductor layer 7 and is formed on the surface portion of the main surface 3, and the groove 26 is formed on the side of the main surface 3 at a distance from the bottom of the high-concentration region 15.

[0387] [A20] The semiconductor device 1 according to A19, wherein the pillar region 30 traverses a bottom portion of the high-concentration region 15 .

[0388] [A21] The semiconductor device 1 according to any one of A1 to A20, wherein the semiconductor layer 7 is a SiC layer 7 including a SiC single crystal.

[0389] The above detailed descriptions of specific embodiments are merely specific examples to illustrate the technical content. Various technical concepts extracted from this specification are not limited to the order of description, the order of embodiment examples, and the order of modification examples within the specification, and can be appropriately combined.

[0390] Explanation of symbols

[0391] 1—SiC semiconductor device; 3—first main surface; 7—semiconductor layer; 7a—lower side region; 15—high concentration region; 20—main region; 26—groove; 30—pillar region; 33—second slow portion; 36—intermediate region; 37—source region; 38—contact region; C2—second axis channel; D—deviation direction; θ—deviation angle; DT—trench depth; TC—pillar thickness; P2—peak value; Z—vertical direction.

Claims

1. A SiC semiconductor device, characterized in that: include: a first conductivity type SiC layer including a main surface and having an axial channel in a stacking direction; a groove formed in the main surface and defining a lower region between the main surface and the bottom of the SiC layer; as well as A second conductivity type pillar region is formed in the lower region within the SiC layer and extends along the axial channel.

2. The SiC semiconductor device according to claim 1, wherein The pillar region traverses a middle portion of the thickness range of the lower region along the axial channel.

3. The SiC semiconductor device according to claim 1 or 2, wherein: The pillar region has a thickness greater than a depth of the trench in a thickness direction of the SiC layer.

4. The SiC semiconductor device according to any one of claims 1 to 3, wherein: The pillar region has an aspect ratio extending in a longitudinal column shape along the shaft channel.

5. The SiC semiconductor device according to any one of claims 1 to 4, wherein The pillar region is composed of a single impurity region.

6. The SiC semiconductor device according to any one of claims 1 to 5, wherein: The pillar region has an upper end portion on the trench side and a lower end portion on the bottom side of the SiC layer, and has a concentration gradient that gradually decreases from the upper end portion toward the lower end portion.

7. The SiC semiconductor device according to claim 6, wherein The concentration gradient includes a peak on the upper end side and a slow portion in which the impurity concentration gradually decreases at a rate slower than that of the peak in a region on the lower end side.

8. The SiC semiconductor device according to claim 7, wherein The slow portion occupies more than 1 / 4 of the thickness of the column region.

9. The SiC semiconductor device according to any one of claims 1 to 8, wherein The groove extends in a strip shape when viewed from above. The column region extends in a strip shape along the groove in a top view.

10. The SiC semiconductor device according to claim 9, wherein The trench extends along the a-axis direction of the SiC single crystal in a plan view.

11. The SiC semiconductor device according to any one of claims 1 to 10, wherein: The SiC layer has an off angle inclined toward an off direction with respect to the vertical axis. The axial groove has the offset angle inclined toward the offset direction with respect to the vertical axis.

12. The SiC semiconductor device according to claim 11, wherein The deviation direction is the a-axis direction of the SiC single crystal.

13. The SiC semiconductor device according to claim 11 or 12, wherein: The deviation angle is less than 10°.

14. The SiC semiconductor device according to any one of claims 1 to 13, wherein: The pillar region is formed on the bottom side of the SiC layer at a distance from the trench.

15. The SiC semiconductor device according to claim 14, wherein The invention further includes an intermediate region of the second conductivity type formed in the SiC layer in a region between the trench and the pillar region.

16. The SiC semiconductor device according to claim 15, wherein It also includes a second conductive type body region, the second conductive type body region is formed on the surface portion of the main surface, The groove runs through the main body area, The middle region is electrically connected to the body region and the pillar region.

17. The SiC semiconductor device according to claim 16, wherein The present invention further includes a source region of the first conductivity type, wherein the source region of the first conductivity type is formed on a side of the trench in a surface portion of the body region.

18. The SiC semiconductor device according to claim 16 or 17, wherein: A contact region of the second conductivity type is further included. The contact region of the second conductivity type has an impurity concentration higher than that of the body region and is formed on a side of the trench in a surface portion of the body region.

19. The SiC semiconductor device according to any one of claims 1 to 18, wherein It also includes a first conductivity type high concentration region having an impurity concentration higher than that of the SiC layer and formed on the surface portion of the main surface, and the trench is formed on the main surface side at a distance from the bottom of the high concentration region.

20. The SiC semiconductor device according to claim 19, wherein The pillar region traverses the bottom of the high-concentration region.

Images