BGA chip packaging test method

Abstract

The invention relates to the field of chip packaging testing, in particular to a BGA chip packaging testing method. The method comprises the following steps: carrying out full-flow thermal imaging scanning on a BGA chip packaging process, carrying out space temperature gradient diffusion distribution analysis, and constructing a temperature diffusion distribution map of each region; according to the probe array, acoustic scanning is carried out on the BGA chip solder ball contact surface, abnormal frequency detection is carried out, and abnormal acoustic nodes are marked; performing transient temperature mutation detection and potential packaging defect positioning analysis on the temperature diffusion distribution map based on abnormal acoustic nodes, and extracting a potential packaging defect area; and carrying out multi-threshold micro-vibration excitation on the potential packaging defect area, carrying out comprehensive evaluation on the reliability of the defect area structure, and generating a reliability evaluation report of the solder ball contact surface structure. According to the invention, accurate packaging test failure prediction is realized, packaging process parameters are optimized, and chip packaging quality and stability are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging and testing, and in particular to a BGA chip packaging and testing method. Background Art

[0002] With the continuous advancement of semiconductor processing and microelectronics packaging technology, BGA (Ball Grid Array) packaging, as a high-density, high-performance chip packaging format, has been widely used in computer processors, memory chips, communication chips, and various embedded systems. BGA packaging achieves electrical connection to the PCB by placing a large number of solder balls on the bottom of the chip. With significant advantages such as small size, a large number of pins, good heat dissipation, and excellent electrical performance, it has become one of the mainstream packaging methods for modern high-performance integrated circuits.

[0003] However, the structural complexity of BGA packaging also presents numerous challenges in terms of packaging quality and reliability. Because the solder ball array is distributed on the bottom of the chip, conventional visual inspection methods cannot directly observe the solder joint quality. Defects such as solder ball voids, cold solder joints, cracks, and delamination during the packaging process can not only seriously affect the chip's connection reliability, but can also cause thermal fatigue failure, electrical performance degradation, and even malfunction of the entire electronic system during long-term operation. In applications with extremely high reliability requirements, such as automotive electronics, industrial control, and aerospace, BGA packaging defects have become a key hidden danger that restricts the stable operation of the system.

[0004] Currently, BGA chip packaging quality inspection primarily relies on non-destructive testing methods such as X-ray imaging, acoustic scanning (such as C-SAM), and thermal imaging. While these methods can identify packaging defects to a certain extent, they often suffer from limited resolution, restricted detection range, and incomplete identification of defect types. Furthermore, traditional inspection methods, which primarily rely on static testing, struggle to adapt to the complex defect evolution caused by the coupling of multiple physical fields (thermal, acoustic, and mechanical) during actual chip operation. Furthermore, there is a lack of systematic linkage between inspection methods and reliability assessment and failure prediction, making it difficult to establish a complete closed-loop packaging and testing system. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention proposes a BGA chip packaging and testing method to solve at least one of the above technical problems.

[0006] To achieve the above object, the present invention provides a BGA chip packaging test method, comprising the following steps: Step S1: Perform thermal imaging scanning of the entire BGA chip packaging process, perform spatial temperature gradient diffusion distribution analysis, and construct a temperature diffusion distribution map for each area; Step S2: acoustically scanning the contact surface of the BGA chip solder balls according to the probe array, performing abnormal frequency detection, and marking abnormal acoustic nodes; Step S3: performing transient temperature mutation detection and potential packaging defect location analysis on the temperature diffusion distribution map based on abnormal acoustic nodes to extract potential packaging defect areas; Step S4: performing multi-threshold micro-vibration excitation on the potential package defect area, and performing a comprehensive structural reliability assessment of the defect area to generate a solder ball contact surface structural reliability assessment report; Step S5: performing risk path deduction and failure time prediction based on the solder ball contact surface structure reliability assessment report to generate a solder ball failure prediction time point; Step S6: Perform comprehensive defect diagnosis based on the predicted time point of solder ball failure, then perform intelligent optimization of packaging process parameters to build an intelligent packaging test optimization model.

[0007] This invention acquires full-process thermal characteristic data by fully monitoring the temperature behavior of different regions during the BGA chip packaging process. Spatial temperature gradients and diffusion distribution maps help reveal potential thermal anomalies, such as localized overheating and uneven heat conduction. This provides a high-resolution thermal behavior baseline for subsequent defect correlation analysis, improving the accuracy and efficiency of problem location. Non-destructive acoustic scanning using a probe array accurately detects minute structural defects (such as voids, cracks, and delamination) on the solder ball contact surface. Identifying abnormal frequency signatures allows for rapid screening of suspected defect areas, significantly improving detection efficiency. Abnormal acoustic nodes serve as spatial anchor points for subsequent analysis, enhancing the synergy of multi-physics field analysis. Combining thermal imaging and acoustic anomaly data improves the sensitivity of potential defect identification through transient temperature shock detection. Thermal-acoustic coupling analysis accurately locates packaging defects (such as cold solder joints and poorly placed packaging spots with concentrated thermal stress) in a spatially precise manner. The extracted defect areas lay the foundation for subsequent structural assessment and reliability analysis, reducing the risk of misdiagnosis. Multi-threshold micro-vibration excitation simulates the effects of mechanical loads in real-world environments, improving the consistency of test results with actual failure behavior. Evaluate the structural integrity of defective areas under vibration and detect hidden risks that may develop due to fatigue and stress concentration. Output structural reliability reports to provide a quantitative basis for risk prediction and product improvement. Combined with multi-physics field data such as heat, sound, and vibration, simulate the potential failure path of solder balls through reliability models. Failure time prediction leaves a sufficient time window for early deployment of maintenance plans and optimized design. Improve the initiative and accuracy of product life management and assist in the establishment of a "predictive maintenance" mechanism. Use AI and big data models to reversely deduce the defect occurrence mechanism and realize intelligent packaging defect identification. Optimize packaging process parameters (such as heating rate, reflow temperature, pressure distribution, etc.) based on failure prediction results to achieve closed-loop process optimization. Building an intelligent packaging test optimization model can improve the overall process yield, reduce costs, and enhance process stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a schematic flow chart of the steps of a BGA chip packaging test method of the present invention; Figure 2 Detailed implementation flow chart of step S1; Figure 3 Detailed implementation flow chart of step S2; Figure 4 Schematic diagram of the detailed implementation steps of step S3. DETAILED DESCRIPTION

[0009] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0010] This application provides a BGA chip packaging and testing method. The execution entities of the BGA chip packaging and testing method include, but are not limited to, the following: mechanical equipment, data processing platforms, cloud server nodes, network upload devices, etc. equipped with the system, which can be regarded as general computing nodes of this application. The data processing platform includes, but is not limited to, at least one of an audio and image management system, an information management system, and a cloud data management system.

[0011] See also Figures 1 to 4 The present invention provides a BGA chip packaging and testing method, which includes the following steps: Step S1: Perform thermal imaging scanning of the entire BGA chip packaging process, perform spatial temperature gradient diffusion distribution analysis, and construct a temperature diffusion distribution map for each area; Step S2: acoustically scanning the contact surface of the BGA chip solder balls according to the probe array, performing abnormal frequency detection, and marking abnormal acoustic nodes; Step S3: performing transient temperature mutation detection and potential packaging defect location analysis on the temperature diffusion distribution map based on abnormal acoustic nodes to extract potential packaging defect areas; Step S4: performing multi-threshold micro-vibration excitation on the potential package defect area, and performing a comprehensive structural reliability assessment of the defect area to generate a solder ball contact surface structural reliability assessment report; Step S5: performing risk path deduction and failure time prediction based on the solder ball contact surface structure reliability assessment report to generate a solder ball failure prediction time point; Step S6: Perform comprehensive defect diagnosis based on the predicted time point of solder ball failure, then perform intelligent optimization of packaging process parameters to build an intelligent packaging test optimization model.

[0012] In the embodiment of the present invention, see Figure 1 , is a schematic flow chart of the steps of a BGA chip packaging and testing method of the present invention. In this example, the steps of the BGA chip packaging and testing method include: Step S1: Perform thermal imaging scanning of the entire BGA chip packaging process, perform spatial temperature gradient diffusion distribution analysis, and construct a temperature diffusion distribution map for each area; In this embodiment, BGA chips and materials required for packaging, such as solder paste and substrates, are prepared. A thermal imaging scanning system is set up, including a high-resolution thermal imager, a data acquisition system, and a control system. Ensure that the focus, viewing angle, and position of the thermal imager can cover the entire BGA chip packaging area. Calibrate the thermal imager to ensure the accuracy of temperature measurements. Use a blackbody radiation source for calibration, and the calibration range covers the temperature range that may occur during the packaging process, such as 25°C to 250°C. Divide the BGA chip packaging process into several key stages, such as: Solder paste coating stage: Apply solder paste on the substrate.

[0013] Chip placement stage: Place the BGA chip onto the substrate.

[0014] Reflow soldering stage: The mounted BGA chip is reflow soldered.

[0015] Cooling stage: After reflow soldering is completed, the BGA chip is cooled.

[0016] Post-processing stage: The packaged BGA chips are cleaned, inspected and other post-processed. At each key stage, the thermal imager is started to scan and record the temperature data. During the reflow soldering stage, scan once every 1 second and continue scanning the entire reflow soldering process. Ensure that the scanning frequency and resolution of the thermal imager can capture rapid changes in temperature. The resolution of the thermal imager is 640x480 pixels, and the scanning frequency is 30 frames per second. Record the thermal imaging data at each stage, including the temperature value and timestamp of each pixel. Pre-process the thermal imaging data, including noise removal, temperature drift correction and image enhancement. Use image processing techniques such as median filtering or Gaussian filtering to remove noise from the thermal imaging data. Use a temperature correction algorithm to correct temperature errors caused by changes in ambient temperature or drift of the thermal imager itself.

[0017] The purpose of spatial temperature gradient diffusion distribution analysis is to analyze the temperature distribution and gradient changes of BGA chips during the packaging process based on thermal imaging data, thereby understanding the heat transfer and diffusion patterns. Numerical methods, such as the finite difference method or the finite element method, are used to calculate temperature gradients and thermal diffusivity. Based on the thermal imaging data, the temperature gradient is calculated at each location on the BGA chip surface. The temperature gradient represents the rate of temperature change over space and can be calculated using the finite difference method. The temperature gradients in the X and Y directions are calculated. The magnitude and direction of the temperature gradient are calculated to understand the direction and intensity of heat transfer. The thermal diffusivity of the BGA chip is calculated based on the thermal imaging data and material properties. The thermal diffusivity indicates the material's ability to transfer heat. The thermal conductivity, density, and specific heat capacity of each BGA chip component (such as the chip, solder, and substrate) are obtained from material handbooks or experimental data. Based on the temperature gradients and thermal diffusivity, a temperature diffusion distribution map of the BGA chip at each key stage is constructed. The temperature gradients and thermal diffusivity are visualized, for example, using color maps or contour plots to represent the temperature distribution and gradient changes. Analyze the temperature diffusion distribution map to understand the heat transfer and diffusion patterns, such as hotspot locations, heat diffusion paths, and temperature change rates. Record the temperature diffusion distribution map for each area to provide a basis for subsequent analysis and optimization.

[0018] Step S2: acoustically scanning the contact surface of the BGA chip solder balls according to the probe array, performing abnormal frequency detection, and marking abnormal acoustic nodes; In this embodiment, an acoustic scanning system is set up, including a probe array, ultrasonic transmitting and receiving circuits, a data acquisition system, and a control system. Appropriate ultrasonic frequency and scanning parameters are selected. The choice of ultrasonic frequency depends on the size of the solder ball and the size of the defect. Generally speaking, the higher the frequency, the higher the resolution, but the weaker the penetration ability. Assume that the selected ultrasonic frequency is 50 MHz. Calibrate the acoustic scanning system to ensure the accuracy of the scanning results. Use a standard test block for calibration to calibrate the position and sensitivity of the probe array. Place the BGA chip on the acoustic scanning platform and adjust the position of the probe array so that it can cover all the solder ball contact surfaces. Start the acoustic scanning system and scan each solder ball in turn. The probe array transmits ultrasonic waves and receives the sound waves reflected back from the solder ball contact surface. Record the acoustic scanning data of each solder ball, including the amplitude, phase, and time delay of the sound wave. Use image processing technology to convert the acoustic scanning data into an acoustic image. The acoustic image shows the internal structure of the solder ball contact surface, and the presence of defects can be intuitively observed. C-scan is a commonly used acoustic scanning image that displays the acoustic reflection intensity of the solder ball at a specific depth. Acoustic scan data is preprocessed, including noise removal, signal attenuation correction, and image enhancement. Digital signal processing techniques, such as bandpass filtering or wavelet transform, are used to remove noise from the acoustic scan data. Signal attenuation correction algorithms are used to correct for signal attenuation caused by ultrasonic waves propagating through the material. Image enhancement techniques, such as contrast enhancement or histogram equalization, are used to improve the clarity of the acoustic image. Abnormal frequency detection aims to analyze the frequency components in the acoustic scan data and identify abnormal frequencies associated with defects. Different defect types may induce different frequency responses. Using Fourier transform or wavelet transform, the acoustic scan data is converted from the time domain to the frequency domain and the frequency components are analyzed. A Fourier transform is performed on the acoustic scan data for each solder ball to calculate its spectrum. The Fourier transform decomposes the acoustic scan data into components with different frequencies, revealing the frequency response of the solder ball. The spectrum is analyzed to identify abnormal frequencies associated with defects. Voids may enhance low-frequency components, while cracks may enhance high-frequency components. A frequency threshold is set to determine the presence of abnormal frequencies based on the amplitude and frequency of the spectrum. If the amplitude of a frequency exceeds the set threshold, it is considered an abnormal frequency. Abnormal acoustic nodes, i.e., solder balls with abnormal frequencies, are marked. The location and frequency of these abnormal acoustic nodes are recorded to provide a basis for subsequent analysis and diagnosis. If a solder ball has a significant frequency peak at 5 MHz and this frequency peak exceeds the set threshold, it is marked as an abnormal acoustic node. Step S3: performing transient temperature mutation detection and potential packaging defect location analysis on the temperature diffusion distribution map based on abnormal acoustic nodes to extract potential packaging defect areas; In this embodiment, the position coordinates of the abnormal acoustic node are mapped to the temperature diffusion distribution map. The coordinates (x, y) of the abnormal acoustic node are mapped to the corresponding pixel position in the temperature diffusion distribution map. The temperature time series data of the abnormal acoustic node in the temperature diffusion distribution map is extracted. This data records the temperature changes over time near the abnormal acoustic node during the packaging process. The temperature change rate is calculated, for example, using a difference method to calculate the temperature difference between adjacent time points. A sliding average or other smoothing technique is used to remove noise from the temperature change rate. A temperature mutation threshold is set, for example, based on the mean and standard deviation of the temperature change rate. The temperature mutation threshold is assumed to be the mean of the temperature change rate plus two standard deviations. Transient thermal mutation points are marked, that is, time points at which the temperature change rate exceeds the threshold. These mutation points may indicate packaging defects or thermal stress concentrations. The time and temperature values of each transient thermal mutation point are recorded to provide a basis for subsequent potential packaging defect location analysis. If an abnormal acoustic node experiences a temperature mutation at 0.5 seconds and the temperature change rate exceeds the set threshold, the point is marked as a transient thermal mutation point. Mark the locations of abnormal acoustic nodes and transient thermal mutation points on the temperature diffusion distribution map. Mark abnormal acoustic nodes with red circles and transient thermal mutation points with blue squares. Identify potential packaging defect areas based on the distribution of abnormal acoustic nodes and transient thermal mutation points. If multiple abnormal acoustic nodes and transient thermal mutation points are clustered together, it is assumed that a packaging defect exists in that area. Determine the type of potential packaging defect by combining the acoustic scan results and the temperature diffusion distribution map. If an abnormal acoustic node indicates the presence of a void and the temperature diffusion distribution map shows thermal stress concentration in that area, it can be determined that a void defect and thermal stress concentration exist in that area. Assess the severity of the potential packaging defect based on the frequency of the abnormal acoustic node and the temperature change rate of the transient thermal mutation point. If the frequency of the abnormal acoustic node is high and the temperature change rate of the transient thermal mutation point is large, the defect is considered to be more severe. Extract the potential packaging defect areas and record their location, type, and severity. Generate a report on potential packaging defect areas to provide a basis for subsequent analysis and optimization. If a region has void defects and thermal stress concentrations, and the defects are severe, the region is marked as a potential package defect area, and its location, type, and severity are recorded.

[0019] Step S4: performing multi-threshold micro-vibration excitation on the potential package defect area, and performing a comprehensive structural reliability assessment of the defect area to generate a solder ball contact surface structural reliability assessment report; In this embodiment, a micro-vibration excitation system is provided, including a vibration exciter, a signal generator, and a control system. Ensure that the exciter can precisely control the vibration frequency and amplitude. Select an appropriate vibration frequency range, such as from 1 kHz to 10 kHz, and set multiple vibration amplitude thresholds, such as 0.1 g, 0.5 g, and 1 g (g represents the acceleration due to gravity). Use a laser Doppler vibrometer or accelerometer to measure the vibration response of the solder ball contact surface. These sensors should have sufficient sensitivity and bandwidth to capture minute vibration signals. Multi-threshold micro-vibration excitation is performed on potential packaging defect areas, sequentially applying vibrations of varying frequencies and amplitudes. First, apply 1 kHz and 0.1 g vibration, then 5 kHz and 0.5 g vibration, and finally 10 kHz and 1 g vibration. Under each vibration excitation, measure the vibration response of the solder ball contact surface. Record the vibration amplitude, frequency, and phase for each solder ball contact surface. Analyze the vibration response data to identify vibration characteristics associated with defects. Voids may cause a shift in the resonant frequency, while cracks may cause an increase in the vibration amplitude. A time-series analysis of the vibration response parameters of the solder ball contact surfaces is performed, and the cross-correlation function between different solder ball contact surfaces is calculated. Assume that the cross-correlation function shows a clear correlation between the vibration responses of solder balls A and B, with the vibration response of solder ball A preceding that of solder ball B. Based on the cross-correlation function results, a vibration response correlation diagram is constructed. This diagram shows the relationship between the vibration responses of different solder ball contact surfaces, as well as the direction and intensity of vibration transmission. The micro-vibration input path of the potential defect is extracted, namely, the vibration transmission path from the vibration excitation source to the defect area. The vibration input path is assumed to be: excitation source -> solder ball A -> solder ball B -> defect area. The vibration amplitude and phase of each solder ball contact surface are vector-decomposed to obtain the X, Y, and Z components of the vibration vector. Finite element analysis software is used to construct a structural model of the BGA chip and simulate the stress distribution under multi-threshold micro-vibration excitation. The model should include the geometric dimensions and material properties of the chip, solder balls, substrate, and packaging materials. Experimentally measured vibration response data are used as boundary conditions for the finite element analysis. The finite element analysis results are analyzed to determine the stress concentration in the defect area. Calculate the maximum stress, strain, and stress intensity factor of the defect area. Predict the failure probability and remaining life of the solder ball based on the finite element analysis results and the material fatigue life curve. Use Miner's cumulative damage theory to calculate the fatigue life of the solder ball at different stress levels. Verify the finite element analysis results and reliability assessment results with experimental data. Conduct accelerated life tests to measure the actual failure time of the solder ball and compare it with the predicted failure time. Evaluate the structural strength and reliability of the defect area based on finite element analysis and experimental data. Calculate the failure probability and remaining life of the defect area. Generate a solder ball contact surface structural reliability assessment report, including the following: Location and type of defective area.

[0020] Vibration response data under multi-threshold micro-vibration excitation.

[0021] Finite element analysis results, including stress distribution, strain distribution, and stress intensity factor.

[0022] Failure probability and remaining life prediction of solder balls.

[0023] Structural strength and reliability assessment of defective areas. This report provides a basis for quality assessment and reliability assurance of BGA chips.

[0024] Step S5: performing risk path deduction and failure time prediction based on the solder ball contact surface structure reliability assessment report to generate a solder ball failure prediction time point; In this embodiment, a suitable failure model is selected based on the material properties and working conditions of the solder ball. Common failure models include: Miner cumulative damage theory: This theory assumes that the fatigue damage of the solder ball is cumulative, and when the cumulative damage reaches a certain level, the solder ball will fail. Coffin-Manson model: This model describes the relationship between the fatigue life of the solder ball and the plastic strain amplitude. Darveaux model: This model takes into account the creep and fatigue damage of the solder ball and is suitable for high-temperature working conditions. Using Monte Carlo simulation, the working condition parameters of the solder ball, such as temperature, vibration and impact, are randomly generated. These parameters should conform to the distribution law of actual working conditions. Based on the stress distribution data in the reliability assessment report of the solder ball contact surface structure, the stress level under each working condition is calculated. Based on the selected failure model, the fatigue life under each working condition is calculated. The fatigue damage of the solder ball is accumulated, and when the cumulative damage reaches 1, the solder ball is considered to have failed. Repeat the above steps multiple times, for example 1000 times, to obtain the failure time distribution of the solder ball. Analyze the results of the Monte Carlo simulation to determine the failure path of the solder ball. The failure path refers to the failure process of the solder ball under different working conditions. Solder balls may first creep under high temperature and then fatigue fracture under vibration. Record the failure modes of the solder balls, such as fatigue fracture, creep fracture, or corrosion. Extract solder ball failure time data from the risk path deduction results. Preprocess the failure time data, including removing outliers and smoothing the data. Select an appropriate life prediction model, such as the Weibull distribution or exponential distribution. The Weibull distribution is suitable for describing systems with increasing or decreasing failure probabilities, while the exponential distribution is suitable for describing systems with constant failure probabilities. Using maximum likelihood estimation or least squares estimation, calculate the mean time to failure (MTTF) and reliability function of the solder balls based on the parameters of the Weibull distribution. Generate a predicted solder ball failure time point. For example, if the mean time to failure of a solder ball is predicted to be 10,000 hours, the time at which the reliability reaches 90% is 5,000 hours. Record the predicted solder ball failure time points to provide a basis for reliability assessment and maintenance of BGA chips.

[0025] Step S6: Perform comprehensive defect diagnosis based on the predicted time point of solder ball failure, then perform intelligent optimization of packaging process parameters to build an intelligent packaging test optimization model.

[0026] In this embodiment, defect diagnosis is performed using an expert system or machine learning algorithm. The expert system diagnoses defects based on predefined rules and a knowledge base. If the predicted time to solder ball failure is less than 1000 hours and there are obvious void defects, the defect is diagnosed as a critical defect. The machine learning algorithm uses training data to train a machine learning model for defect diagnosis. Common machine learning algorithms include support vector machines (SVMs), decision trees, and neural networks. The output defect diagnosis results include defect type, location, and severity assessment. The goal of intelligent optimization of packaging process parameters is to optimize packaging process parameters based on the comprehensive defect diagnosis results to improve the reliability and performance of BGA chips. Optimization algorithms, such as genetic algorithms or particle swarm optimization, are used to find the optimal packaging process parameters. Based on the comprehensive defect diagnosis results, the packaging process parameters to be optimized and the optimization objectives are determined. For example, soldering temperature can be optimized to reduce void defects, reflow profiles can be optimized to reduce thermal stress, and packaging materials can be optimized to improve structural strength. Optimization objectives are set, such as minimizing the number of defects, maximizing chip reliability, and minimizing production costs. A relationship model between packaging process parameters and chip reliability is constructed. The model can be built using finite element analysis, experimental data, or machine learning algorithms. Use finite element analysis to simulate the stress distribution under different packaging process parameters and calculate the failure probability of the solder balls. Use optimization algorithms, such as genetic algorithms or particle swarm algorithms, to find the optimal packaging process parameters. Set the parameters of the optimization algorithm, such as population size, number of iterations, and crossover mutation probability. Run the optimization algorithm to obtain the optimal packaging process parameters. Use experimental data or simulation data to verify the impact of the optimized packaging process parameters on chip reliability and performance. If the verification results meet the requirements, the optimized packaging process parameters will be applied to actual production. The purpose of the intelligent packaging test optimization model is to integrate comprehensive defect diagnosis and intelligent optimization of packaging process parameters into a system to realize the intelligence of BGA chip packaging test.

[0027] In this embodiment, refer to Figure 2 , is a flowchart of the detailed implementation steps of step S1. In this embodiment, the detailed implementation steps of step S1 include: Conduct thermal imaging scans of the entire BGA chip packaging process and collect thermal images of the BGA chip packaging; Perform real-time temperature distribution analysis on BGA chip package thermal imaging to obtain the sequential package temperature distribution field; Divide the temperature distribution field of the timing package into isothermal gradient regions and extract multiple temperature gradient regions; Conducting deep mining of inter-regional heat diffusion in the temperature gradient region to obtain inter-regional temperature diffusion heat flow waveforms; Based on the temperature diffusion heat flow waveform between regions, the spatial temperature gradient diffusion distribution analysis is performed to construct the temperature diffusion distribution map of each region.

[0028] In this embodiment, the goal of full-process thermal imaging scanning is to capture the temperature distribution of the chip surface in real time throughout the BGA chip packaging process, providing a data foundation for subsequent temperature analysis. A high-resolution infrared thermal imager is used for non-contact temperature measurement, recording thermal imaging data at each time point. Prepare a high-resolution infrared thermal imager, ensuring its measurement accuracy and response speed meet the requirements. Select a thermal imager with a resolution of 640x480 pixels and a temperature measurement accuracy of ±2°C or ±2%. Mount the thermal imager above the BGA chip packaging equipment to ensure coverage of the entire chip packaging area. Adjust the thermal imager's focus and angle to ensure a clear view of the chip surface. Set the thermal imager parameters, including measurement range, emissivity, and ambient temperature. Emissivity is the ability of an object's surface to radiate heat and needs to be adjusted based on the BGA chip material. The emissivity of solder balls is approximately 0.04-0.06, and that of PCB boards is approximately 0.85-0.95. During the BGA chip packaging process, collect thermal imaging data of the chip surface in real time. Set the data acquisition frequency, for example, to 10 frames per second. Save the captured thermal imaging data as an image file (such as TIFF or JPEG format) or a video file (such as AVI format). Record the thermal imaging data at each time point and create a timestamp index to facilitate subsequent temperature analysis. The goal of real-time temperature distribution analysis is to convert the captured thermal imaging data into temperature data and generate a temperature distribution map on the chip surface, providing a data foundation for subsequent temperature gradient analysis. Image processing and temperature calibration techniques are used to convert the pixel values of the thermal image to temperature values and perform temperature calibration to improve measurement accuracy. BGA chip package thermal imaging data is read and the thermal image is extracted frame by frame. Each thermal image frame is pre-processed, such as image noise reduction and image enhancement, to improve the accuracy of temperature analysis. The pixel values of the thermal image are converted to temperature values using the thermal imager's temperature calibration curve. The temperature calibration curve is provided by the thermal imager manufacturer and is used to convert pixel values into temperature values. The converted temperature data is then temperature-calibrated to eliminate measurement errors. Temperature calibration can be achieved by comparing with a standard thermometer. The temperature data is mapped to the chip surface to generate a temperature distribution map on the chip surface. The temperature distribution graph can use color coding to indicate high and low temperatures, for example, red for high temperatures and blue for low temperatures. The temperature distribution graph for each time point is recorded and indexed with timestamps to generate a time-series packaged temperature distribution field. The time-series packaged temperature distribution field data is read and the temperature distribution graph is extracted frame by frame. Image segmentation is performed on each frame of the temperature distribution graph, grouping pixels with similar temperatures into the same region. Image segmentation can use methods such as threshold segmentation, region growing, or cluster analysis. Cluster analysis is performed on the segmented regions, merging regions with similar temperature gradients into the same region. Cluster analysis can use methods such as K-means clustering or hierarchical clustering.Extract multiple temperature gradient regions and record the boundaries and temperature range of each region. Based on the boundaries and temperature ranges of the temperature gradient regions, establish a thermodynamic model to describe the heat transfer process between the different regions. The thermodynamic model can consider factors such as heat conduction, heat convection, and heat radiation. Use numerical calculation methods, such as the finite element method or the finite difference method, to solve the thermodynamic model and calculate the intensity and direction of heat flux between the different regions. Plot the changes in heat flux intensity and direction over time as a waveform graph to generate an inter-regional temperature diffusion heat flux waveform. Read the inter-regional temperature diffusion heat flux waveform data and analyze the heat inflow and outflow in each region. Calculate the temperature gradient and heat flux density for each region to describe the temperature diffusion in each region. Use visualization techniques to display the temperature gradient and heat flux density in the form of a graph. Color coding can be used to indicate the magnitude of the temperature gradient, and arrows can be used to indicate the direction of heat flow. Perform statistical analysis on the temperature diffusion distribution graph to calculate the average temperature gradient and average heat flux density for each region, providing a data foundation for subsequent thermal design optimization.

[0029] In this embodiment, refer to Figure 3 , is a flowchart of the detailed implementation steps of step S2. In this embodiment, the detailed implementation steps of step S2 include: Perform acoustic scanning on the contact surface of the BGA chip solder balls according to the probe array to obtain the acoustic reflection signal flow on the solder ball surface; Adaptive frequency domain optimization is performed on the acoustic reflection signal flow on the solder ball surface to construct an adaptive gain acoustic signal flow; Define equal-time windows, perform multi-window decomposition on the adaptive gain acoustic signal stream, and extract the acoustic signal streams of multiple windows; Calculate the acoustic wave frequency of each window on the acoustic signal streams of multiple windows to obtain the acoustic wave frequency parameters of each window; Frequency distribution analysis is performed based on the acoustic wave frequency parameters, abnormal frequency detection is performed, and abnormal acoustic nodes are marked.

[0030] In this example, a BGA chip is prepared, ensuring its surface is clean, and placed on an acoustic scanning platform. The acoustic scanner parameters are set, such as the scanning frequency, scanning speed, and probe array arrangement. Assume the scanning frequency is set to 50 MHz, the scanning speed is 1 mm / s, and the probe spacing is 50 microns. The acoustic scanner is activated, and the probe array scans along the solder ball contact surface of the BGA chip, emitting high-frequency acoustic waves and receiving reflected acoustic wave signals. The acoustic reflection signals received by each probe are recorded to form an acoustic reflection signal stream. Assuming a BGA chip with 1,000 solder balls is scanned, with 100 sampling points per solder ball, a total of 100,000 acoustic reflection signals are recorded. The acoustic reflection signal stream is stored and subjected to preliminary data preprocessing, such as noise removal and signal strength correction, to provide a foundation for subsequent adaptive frequency domain optimization. Spectral analysis is performed on the acoustic reflection signal stream, for example, using a fast Fourier transform (FFT) to convert the time domain signal into a frequency domain signal. Assume that the spectral analysis shows that the signal's primary frequency components are concentrated between 20 MHz and 30 MHz. Design an adaptive filter. Dynamically adjust the filter parameters based on the results of spectrum analysis to enhance the signal of the primary frequency component and suppress noise at other frequencies. Use the least mean square error (LMS) algorithm to adjust the filter coefficients. Apply the adaptive filter to the acoustic reflection signal stream to generate an adaptive gain acoustic signal stream. Assume that after filtering, the signal-to-noise ratio of the signal improves by 10 dB, indicating that the effective signal has been enhanced. Record the adaptive gain acoustic signal stream and visualize it to evaluate the optimization effect. Set the window size to be equal, for example, 10 milliseconds, with a 50% overlap between windows. Split the adaptive gain acoustic signal stream into multiple windows. Assuming there are 100,000 samples in total and each window contains 500 samples, a total of 200 windows are obtained. Record the start and end times of each window to provide a time reference for subsequent acoustic wave frequency calculations. Store the acoustic signal stream for each window and number it for window-by-window analysis. Perform a short-time Fourier transform on the acoustic signal stream in each window to generate a spectrogram for each window. Assume that the spectrum shows that the main frequency components of each window are concentrated between 20 MHz and 30 MHz. Calculate the frequency parameters of each window, such as peak frequency, average frequency, and frequency bandwidth. Assume that the peak frequency of a window is 25 MHz, the average frequency is 24 MHz, and the frequency bandwidth is 2 MHz. Record the acoustic wave frequency parameters of each window and perform statistical analysis to provide a data basis for subsequent frequency distribution analysis. Perform statistical analysis on the acoustic wave frequency parameters of all windows and calculate the mean and standard deviation of the frequency distribution. Assume that the mean of the frequency distribution is 25 MHz and the standard deviation is 1 MHz. Use the Z-score method to detect abnormal frequencies, setting the threshold to 3. Calculate the Z-score for the frequency value of each window.When the absolute value of the Z-score is greater than 3, it is marked as an abnormal frequency. Abnormal acoustic nodes are marked and their locations and frequencies are recorded for subsequent analysis and verification. Assume that five abnormal acoustic nodes are detected, with frequencies of 21 MHz, 22 MHz, 28 MHz, 29 MHz, and 30 MHz. An abnormal frequency detection report is generated, including the locations, frequencies, and Z-scores of the abnormal nodes, providing a basis for BGA chip quality assessment.

[0031] In this embodiment, the specific steps of performing adaptive frequency domain optimization on the solder ball surface acoustic reflection signal flow and constructing the adaptive gain acoustic signal flow are as follows: Perform short-time Fourier transform on the acoustic reflection signal flow on the solder ball surface to obtain a time-frequency domain distribution diagram; Identifying the time dimension energy distribution and the frequency dimension energy distribution of the time-frequency domain distribution graph; Detect energy dispersion areas based on energy distribution in time dimension and energy distribution in frequency dimension, and mark weak and strong frequency bands; Adaptive frequency domain optimization is performed on weak and strong frequency bands to construct adaptive gain acoustic signal flow; The adaptive frequency domain optimization specifically includes: performing signal gain processing on weak frequency bands; and performing signal attenuation processing on strong frequency bands.

[0032] In this embodiment, the acoustic reflection signal stream of the solder ball surface is prepared to ensure that the data has been preprocessed, such as removing noise and correcting the signal intensity. Select a suitable window function, such as a Hanning window or a Hamming window, to reduce spectral leakage. Assume that the Hanning window is selected as the window function. Set the window size and step size, for example, the window size is 1 millisecond and the step size is 0.5 milliseconds. This means that each window covers 1 millisecond of signal and there is a 50% overlap between adjacent windows. Apply short-time Fourier transform to divide the signal into multiple windows, and perform Fourier transform on each window to obtain the spectrum of each window. Combine the spectra of all windows to form a time-frequency domain distribution diagram.

[0033] Assume that the horizontal axis of the time-frequency domain distribution graph represents time, the vertical axis represents frequency, and the color represents energy intensity. The time-frequency domain distribution graph is stored and visualized for subsequent analysis. Analyze the time-frequency domain distribution graph and calculate the summed energy at each time point to obtain a time-dimensional energy distribution curve. Assume that the time-dimensional energy distribution curve shows high energy within a certain time period, indicating that the signal strength is high within that time period. Calculate the summed energy at each frequency point to obtain a frequency-dimensional energy distribution curve. Assume that the frequency-dimensional energy distribution curve shows high energy within certain frequency ranges, indicating that the signal components within those frequency ranges are strong. Record the energy distribution curves in both the time and frequency dimensions and visualize them for subsequent detection of energy dispersion areas. Set an energy threshold, for example, based on the mean and standard deviation of the energy distribution curve. Assume that the energy threshold is the mean minus one standard deviation. Mark weak frequency bands, i.e., frequency ranges with energy below the threshold. Assume that on the frequency-dimensional energy distribution curve, the energy between 20 MHz and 22 MHz is below the threshold, then mark this frequency range as a weak frequency band. Mark strong frequency bands, i.e., frequency ranges with energy above the threshold. Assume that the energy between 28 MHz and 30 MHz on the frequency-dimensional energy distribution curve is above the threshold. Mark this frequency range as a strong band. Record the locations and energy intensities of weak and strong bands to provide a basis for subsequent adaptive frequency-domain optimization. Design adaptive filters, such as using a bandpass filter to enhance the signal in weak bands and a bandstop filter to attenuate the signal in strong bands. Assume that the center frequency of the bandpass filter is 21 MHz and the bandwidth is 2 MHz; the center frequency of the bandstop filter is 29 MHz and the bandwidth is 2 MHz.

[0034] Perform signal gain processing on the weak frequency band. This involves applying a bandpass filter to the signal in the weak frequency band to enhance the signal strength within this frequency range. Assume that after the gain processing, the energy in the weak frequency band increases by 5 dB. Perform signal attenuation processing on the strong frequency band. This involves applying a bandstop filter to the signal in the strong frequency band to reduce the signal strength within this frequency range. Assume that after the attenuation processing, the energy in the strong frequency band decreases by 5 dB. Apply the adaptive filter to the entire time-frequency domain distribution graph to obtain the adaptive gain acoustic signal flow. Record the adaptive gain acoustic signal flow and visualize it to evaluate the optimization effect. Design adaptive filters, such as using a bandpass filter to enhance the signal in the weak frequency band and a bandstop filter to attenuate the signal in the strong frequency band. Assume that the bandpass filter has a center frequency of 21 MHz and a bandwidth of 2 MHz; the bandstop filter has a center frequency of 29 MHz and a bandwidth of 2 MHz. Perform signal gain processing on the weak frequency band. This involves applying a bandpass filter to the signal in the weak frequency band to enhance the signal strength within this frequency range. Assume that after the gain processing, the energy in the weak frequency band increases by 5 dB. Perform signal attenuation on the strong frequency band. This involves applying a band-stop filter to the signal in the strong frequency band, reducing the signal strength within this frequency range. Assume that after attenuation, the energy in the strong frequency band is reduced by 5 dB. Apply the adaptive filter to the entire time-frequency domain distribution graph to obtain the adaptive gain acoustic signal flow. Record the adaptive gain acoustic signal flow and visualize it to evaluate the optimization effect.

[0035] In this embodiment, refer to Figure 4 , is a flowchart of the detailed implementation steps of step S3. In this embodiment, the detailed implementation steps of step S3 include: performing spatial positioning of abnormal nodes on the temperature diffusion distribution map based on abnormal acoustic nodes, and marking the spatial position of the abnormal nodes in the thermal distribution map; Performing transient temperature mutation detection on the spatial position and marking the transient thermal mutation point; Calculating the transient thermal mutation temperature peak value and the temperature gradient diffusion rate of the transient thermal mutation point; Calculate the duration of transient thermal anomaly at the transient thermal mutation point to obtain the duration of thermal anomaly; According to the duration of thermal anomaly, the transient mutation temperature peak and temperature gradient diffusion rate are mined to mine the mutation point temperature time series fluctuation, and the thermal anomaly time-varying curve of the mutation point is constructed; Based on the time-varying curve of thermal anomaly at the mutation point, potential packaging defect positioning analysis is performed to extract the potential packaging defect area.

[0036] In this example, abnormal acoustic node data is prepared, including the location coordinates (X, Y coordinates) and abnormal frequency value of each abnormal node. Assume that five abnormal nodes are detected through acoustic scanning, with coordinates at (10, 20), (30, 40), (50, 60), (70, 80), and (90, 100). A temperature diffusion distribution map of the BGA chip is prepared. This map displays the surface temperature distribution of the chip and includes the temperature value at each location. Assume that the resolution of the temperature diffusion distribution map is 100x100, with each pixel corresponding to a temperature value. The location coordinates of the abnormal acoustic node are mapped to the temperature diffusion distribution map. The coordinate (10, 20) is mapped to the pixel position (10, 20) of the temperature diffusion distribution map. The spatial location of the abnormal node in the temperature diffusion distribution map is marked, for example, by marking the location of the abnormal node with a red circle on the temperature diffusion distribution map. The spatial location and corresponding temperature value of each abnormal node in the thermal distribution map are recorded to provide a basis for subsequent transient temperature change detection. Collect temperature time series data at the spatial location of the abnormal node, for example, record the temperature value every 1 millisecond.

[0037] Suppose that at an abnormal node, temperature data is recorded for one second, totaling 1000 temperature values. Calculate the temperature change rate, for example, using a differencing method to calculate the temperature difference between adjacent time points. Set a temperature jump threshold, for example, based on the mean and standard deviation of the temperature change rate. Assume the temperature jump threshold is the mean plus two standard deviations. Mark transient thermal jump points, which are time points where the temperature change rate exceeds the threshold. Suppose that three transient thermal jump points are detected at an abnormal node, with durations of 0.2 seconds, 0.5 seconds, and 0.8 seconds, respectively. Record the time and temperature of each transient thermal jump point to provide a basis for subsequent calculation of the transient thermal jump peak and temperature gradient diffusion rate. Calculate the transient thermal jump peak, which is the highest temperature value near the transient thermal jump point. Assume that the duration of a transient thermal jump point is 0.2 seconds, and the highest temperature value near it is 85°C. Calculate the temperature gradient diffusion rate, which is the rate of temperature change over space. Calculate the temperature change rate within a 1 mm radius around the transient thermal jump point.

[0038] Record the transient thermal anomaly peak temperature and temperature gradient diffusion rate for each transient thermal mutation point to provide a basis for subsequent calculation of the transient thermal anomaly duration. Set a temperature recovery threshold, for example, based on the mean and standard deviation of the normal temperature. Assume the temperature recovery threshold is the mean of the normal temperature plus one standard deviation. Calculate the transient thermal anomaly duration, which is the time from the transient thermal mutation point to the temperature returning below the threshold. Assume the duration at a transient thermal mutation point is 0.2 seconds, and the temperature returns below the threshold at 0.5 seconds, then the transient thermal anomaly duration is 0.3 seconds. Record the thermal anomaly duration for each transient thermal mutation point to provide a basis for subsequent mining of temperature time series fluctuations at the mutation point. Perform a wavelet transform on the temperature time series data for each transient thermal mutation point to extract frequency components at different scales. Assume that the wavelet transform shows a 10 Hz oscillation in the temperature time series data at a transient thermal mutation point. Based on the duration of the thermal anomaly, analyze the temporal changes of the temperature peak value and temperature gradient diffusion rate.

[0039] Calculate the mean and standard deviation of the temperature peak and temperature gradient diffusion rate during the duration of the thermal anomaly. Construct a time-varying curve of the thermal anomaly at the mutation point, visualizing the temperature peak, temperature gradient diffusion rate, and duration of the thermal anomaly to analyze thermal behavior. Record the thermal anomaly time-varying curve for each transient thermal mutation point to provide a basis for subsequent analysis of potential packaging defects. Analyze the characteristics of the thermal anomaly time-varying curve at the mutation point, such as the temperature peak, temperature gradient diffusion rate, and duration of the thermal anomaly. If certain curves show high temperature peaks, rapid temperature gradient diffusion rates, and long duration of the thermal anomaly, they may indicate serious packaging defects. Combined with the acoustic scanning results, analyze the location and frequency of abnormal acoustic nodes. If the location of certain abnormal acoustic nodes coincides with the location of serious defects indicated by the time-varying curve of the thermal anomaly at the mutation point, it can be determined that a packaging defect exists in that area. Mark potential packaging defect areas on the BGA chip's temperature diffusion distribution map, for example, by marking the defective area in red. Generate a packaging defect location analysis report that includes the location of the defect area, defect type, and severity assessment, providing a basis for BGA chip quality assessment.

[0040] In this embodiment, step S4 includes the following steps: Perform multi-threshold micro-vibration excitation on the potential package defect area and extract the vibration response parameters of the solder ball contact surface in the potential defect area; Identify the vibration response correlation sequence based on the solder ball contact surface vibration response parameters to extract the micro-vibration input path of the potential defect; Calculate the vibration vector of the micro-vibration input path of the potential defect to obtain the vibration vector information of the solder ball contact surface; Calculate the vibration excitation amplitude and phase according to the vibration vector information of the solder ball contact surface; A comprehensive structural reliability assessment of the defective area is performed based on the vibration excitation amplitude and phase, and a structural reliability assessment report of the solder ball contact surface is generated.

[0041] In this embodiment, a micro-vibration excitation system is provided, including a vibration exciter, a signal generator, and a control system. A suitable vibration frequency range is selected, for example, from 1 kHz to 10 kHz, and multiple vibration amplitude thresholds are set, for example, 0.1g, 0.5g, and 1g (g is the acceleration of gravity). Multi-threshold micro-vibration excitation is performed on the potential packaging defect area, and vibrations of different frequencies and amplitudes are applied in sequence. First, a vibration of 1 kHz and 0.1g is applied, then a vibration of 5 kHz and 0.5g is applied, and finally a vibration of 10 kHz and 1g is applied. A laser Doppler vibrometer or an accelerometer is used to measure the vibration response of the solder ball contact surface. The vibration amplitude, frequency, and phase of each solder ball contact surface are recorded. The vibration response parameters of the solder ball contact surface are stored to provide a basis for the subsequent identification of the vibration response correlation sequence. The vibration response parameters of the solder ball contact surface are subjected to time series analysis, and the cross-correlation function between different solder ball contact surfaces is calculated. Assume that the cross-correlation function shows that there is a clear correlation between the vibration response of solder ball A and the vibration response of solder ball B, and that the vibration response of solder ball A precedes that of solder ball B. Based on the results of the cross-correlation function, a vibration response correlation diagram is constructed. This diagram shows the vibration response relationship between different solder ball contact surfaces, as well as the direction and intensity of vibration transmission. Extract the micro-vibration input path of the potential defect, that is, the vibration transmission path from the vibration excitation source to the defect area. Assume that the vibration input path is: excitation source -> solder ball A -> solder ball B -> defect area. Record the micro-vibration input path of the potential defect to provide a basis for subsequent vibration vector calculation. Perform vector decomposition on the vibration amplitude and phase of each solder ball contact surface to obtain the X, Y, and Z components of the vibration vector. Assuming that the vibration amplitude of solder ball A is 0.5g and the phase is 30 degrees, its vibration vector is: The vibration vector of each solder ball contact surface along the micro-vibration input path is calculated and visualized to understand the transfer and distribution of vibration energy. The vibration vector information of the solder ball contact surface is stored to provide a basis for subsequent vibration excitation amplitude and phase calculations. The purpose of calculating the vibration excitation amplitude and phase is to determine the optimal vibration excitation parameters based on the vibration vector information of the solder ball contact surface to more effectively stimulate the vibration response of the defect area. An optimization algorithm, such as a genetic algorithm or a particle swarm algorithm, is used to find the optimal vibration excitation amplitude and phase. The optimization goal is set, such as maximizing the vibration response of the defect area while minimizing the vibration response of other areas. The genetic algorithm or particle swarm algorithm is used to find the optimal vibration excitation amplitude and phase. Assume that after optimization, the optimal vibration excitation amplitude is 0.8g and the phase is 45 degrees. The optimal vibration excitation amplitude and phase are recorded to provide a basis for the subsequent comprehensive structural reliability assessment of the defect area. The comprehensive structural reliability assessment aims to evaluate the structural strength and reliability of the defect area based on the vibration excitation amplitude and phase, thereby determining the severity of the package defect. This comprehensive assessment is performed by combining finite element analysis and experimental data. Use finite element analysis software to build a structural model of the BGA chip and simulate the stress distribution under optimal vibration excitation. Assume that the finite element analysis shows high stress concentration in the defect area, which may lead to structural failure. Combined with experimental data, analyze the vibration response and structural deformation of the defect area. Assume that the experimental data shows that under optimal vibration excitation, the vibration amplitude in the defect area is large and significant structural deformation occurs. Based on the finite element analysis and experimental data, evaluate the structural strength and reliability of the defect area. Calculate the failure probability and remaining life of the defect area. Generate a structural reliability assessment report for the solder ball contact surface, including the location of the defect area, defect type, structural strength, reliability assessment, and remaining life prediction, providing a basis for quality assessment of BGA chips.

[0042] In this embodiment, step S5 includes the following steps: Obtain the historical work log of the BGA chip; identify the chip working environment thermal cycle and mechanical error parameters based on the historical work log of the BGA chip; Conduct multi-parameter coupling mining on the reliability assessment report of the solder ball contact surface structure and construct a multi-parameter coupling model of the solder ball contact surface; Based on the chip working environment thermal cycle and mechanical error parameters, a risk path deduction is performed on the multi-parameter coupling model of the solder ball contact surface to generate a solder ball failure action trajectory; The failure time of the solder ball failure action trajectory is predicted to generate the predicted time point of solder ball failure.

[0043] In this example, historical operating logs of a BGA chip are collected. These logs may contain information such as chip temperature, voltage, current, operating time, vibration, and shock. Assume that a log file containing 10,000 records is collected. The log data is preprocessed, including data cleaning, data conversion, and data integration. Duplicate records are removed, missing values are processed, and timestamps are converted to date format. Thermal cycle parameters of the chip's operating environment are identified, such as temperature range, temperature gradient, thermal cycle period, and number of thermal cycles. Assume that the chip's temperature range is -40°C to 85°C, the temperature gradient is 5°C / min, the thermal cycle period is 24 hours, and the number of thermal cycles is 500. Mechanical error parameters of the chip's operating environment are identified, such as vibration frequency, vibration amplitude, shock intensity, and number of shocks. Assume that the chip's vibration frequency is 100 Hz, the vibration amplitude is 0.1g, the shock intensity is 10g, and the number of shocks is 100. Recording the chip's operating environment thermal cycle and mechanical error parameters provides a foundation for the subsequent construction of a multi-parameter coupled model of the solder ball contact surface. The goal of building a multi-parameter coupling model is to correlate various parameters in the solder ball contact surface structural reliability assessment report, such as stress, strain, and failure probability, with chip operating environment parameters, thereby establishing a comprehensive reliability model. This multi-parameter coupling model is constructed using machine learning algorithms, such as neural networks or support vector machines. A structural reliability assessment report for the solder ball contact surface is prepared, containing information such as the solder ball's geometry, material properties, stress distribution, strain distribution, and failure probability. An appropriate machine learning algorithm, such as a neural network, is selected to construct the multi-parameter coupling model. The neural network inputs are chip operating environment thermal cycling and mechanical error parameters, and the output is the solder ball's failure probability. The neural network is trained using historical data, such as a training dataset containing 1,000 solder balls, where each ball's data includes chip operating environment parameters and the ball's failure probability. The neural network's performance is evaluated, for example, by calculating its accuracy, recall, and F1 value. Assuming a 90% accuracy rate, this indicates that the model can accurately predict solder ball failure probability. The multi-parameter coupling model for the solder ball contact surface is documented to provide a foundation for subsequent risk path deduction. Set simulation parameters, such as simulation time, time step, and number of simulations. Assume a simulation time of 1000 hours, a time step of 1 hour, and 1000 simulations. Use Monte Carlo simulation to randomly generate chip operating environment thermal cycle and mechanical error parameters. These parameters are input into a multi-parameter coupled model of the solder ball contact surface to calculate the solder ball failure probability. Based on the failure probability, determine whether the solder ball has failed.

[0044] If the failure probability of the solder ball exceeds the set threshold, the solder ball is considered to have failed. Record the failure time and failure mode of the solder ball, for example, the failure time of the solder ball is 500 hours, and the failure mode is fatigue fracture. Analyze the failure path of the solder ball, such as the failure process of the solder ball under high temperature and high vibration conditions. Generate a solder ball failure trajectory and visualize the failure time and failure mode of the solder ball to understand the failure process of the solder ball. The purpose of failure time prediction is to predict the failure time point of the solder ball based on the solder ball failure trajectory, thereby providing a basis for the reliability assessment of the BGA chip. Use a service life prediction model, such as the Weibull distribution or exponential distribution, to predict failure time. Analyze the solder ball failure trajectory and extract failure time data. Assume that the failure time data of 100 solder balls are extracted from the solder ball failure trajectory. Select a suitable life prediction model, such as the Weibull distribution, to fit the failure time data. The probability density function of the Weibull distribution is: , where t is time, β is the shape parameter, and η is the scale parameter. Use maximum likelihood estimation or least squares estimation to estimate the parameters 𝛽 and η of the Weibull distribution. Based on the parameters of the Weibull distribution, calculate the mean time to failure (MTTF) and reliability function of the solder balls. Generate predicted solder ball failure times. For example, if the mean time to failure of a solder ball is predicted to be 10,000 hours, the time at which reliability reaches 90% is 5,000 hours. Record the predicted solder ball failure times to provide a basis for reliability assessment and maintenance of BGA chips.

[0045] In this embodiment, step S6 includes the following steps: Predict the failure probability of future working cycles based on the solder ball failure trajectory and generate a failure probability density curve; Based on the solder ball failure prediction time point and failure probability density curve, the solder joint failure risk rating is performed to obtain the package solder joint failure risk level; Perform comprehensive defect diagnosis based on the package solder joint failure risk level and generate the final defect diagnosis results; Based on the final defect diagnosis results, the packaging process parameters are intelligently optimized and an intelligent packaging test optimization model is constructed.

[0046] In this embodiment, solder ball failure trajectory data is prepared, including the failure time, failure mode, and working environment parameters of the solder balls. An appropriate statistical model, such as exponential distribution, Weibull distribution, or lognormal distribution, is selected to fit the failure time data. The parameters 𝛽 and η of the Weibull distribution are estimated using maximum likelihood estimation or least squares method. Based on the parameters of the Weibull distribution, the failure probability of the solder balls in the future working cycle is calculated. The failure probability of the solder balls in the next 1000 hours is calculated. A failure probability density curve is generated to visualize the change in failure probability over time to understand the failure risk of the solder balls. The failure probability density curve is recorded to provide a basis for subsequent solder joint failure risk rating. The purpose of solder joint failure risk rating is to evaluate the solder joint failure risk of BGA chips based on the predicted solder ball failure time point and the failure probability density curve, thereby determining which solder joints require special attention. Risk rating standards are set to classify solder joint failure risks into different levels. Risk rating standards are set, for example, to classify solder joint failure risks into four levels: low risk, medium risk, high risk, and extremely high risk.

[0047] Low risk: The predicted failure time is greater than 10,000 hours and the failure probability is less than 1%.

[0048] Medium risk: The predicted failure time is between 5,000 and 10,000 hours, and the failure probability is between 1% and 5%.

[0049] High risk: The predicted failure time is between 1000 and 5000 hours, and the failure probability is between 5% and 10%.

[0050] Very high risk: The predicted failure time is less than 1000 hours and the failure probability is greater than 10%. A risk rating is assigned to each solder joint based on the predicted failure time and the failure probability density curve.

[0051] If a solder joint has a predicted failure time of 2000 hours and a failure probability of 8%, it is considered high-risk. Recording the failure risk level of each solder joint provides a basis for subsequent comprehensive defect diagnosis. The goal of comprehensive defect diagnosis is to determine the defect type and location within the BGA chip based on the package solder joint failure risk level, combined with previous acoustic scanning, thermal analysis, and vibration analysis results. Comprehensive defect diagnosis is performed using an expert system or decision tree algorithm. This expert system or decision tree algorithm is constructed, taking the package solder joint failure risk level, acoustic scanning results, thermal analysis results, and vibration analysis results as inputs and outputting the defect type and location. The expert system or decision tree algorithm is trained based on historical data and expert experience. Comprehensive defect diagnosis is performed on the BGA chip, determining the defect type and location based on the package solder joint failure risk level and other analysis results. If a solder joint is considered high-risk and the acoustic scan indicates a void, it can be diagnosed as having a void defect. The final defect diagnosis results, including defect type, location, and severity assessment, are generated, providing a basis for subsequent intelligent optimization of packaging process parameters. Identify the packaging process parameters that need to be optimized, such as soldering temperature, soldering time, soldering pressure, and reflow temperature profile. Set optimization goals, such as minimizing the number of defects, maximizing chip reliability, and minimizing production costs. Build an intelligent packaging test optimization model that uses the packaging process parameters as input and the number of defects, chip reliability, and production cost as output. Use a genetic algorithm or particle swarm algorithm to find the optimal packaging process parameters. After optimization, the optimal soldering temperature is 250°C, the soldering time is 10 seconds, the soldering pressure is 1 MPa, and the reflow temperature profile is A. Verify the optimized packaging process parameters, such as using experimental data or simulation data, and evaluate their impact on chip reliability and performance. Record the optimized packaging process parameters and apply them in actual production to improve the quality and reliability of BGA chips.

[0052] The present invention is therefore intended to be illustrative and non-restrictive in all respects, with the scope of the invention being defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the application documents are intended to be embraced therein.

[0053] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A BGA chip packaging test method, characterized in that: The following steps are involved: Step S1: Perform thermal imaging scanning of the entire BGA chip packaging process, perform spatial temperature gradient diffusion distribution analysis, and construct a temperature diffusion distribution map for each area; Step S2: acoustically scanning the contact surface of the BGA chip solder balls according to the probe array, performing abnormal frequency detection, and marking abnormal acoustic nodes; Step S3: performing transient temperature mutation detection and potential packaging defect location analysis on the temperature diffusion distribution map based on abnormal acoustic nodes to extract potential packaging defect areas; Step S4: performing multi-threshold micro-vibration excitation on the potential package defect area, and performing a comprehensive structural reliability assessment of the defect area to generate a solder ball contact surface structural reliability assessment report; Step S5: performing risk path deduction and failure time prediction based on the solder ball contact surface structure reliability assessment report to generate a solder ball failure prediction time point; Step S6: Perform comprehensive defect diagnosis based on the predicted time point of solder ball failure, then perform intelligent optimization of packaging process parameters to build an intelligent packaging test optimization model.

2. The BGA chip packaging and testing method according to claim 1, wherein: The specific steps of step S1 are: Conduct thermal imaging scans of the entire BGA chip packaging process and collect thermal images of the BGA chip packaging; Perform real-time temperature distribution analysis on BGA chip package thermal imaging to obtain the sequential package temperature distribution field; Divide the temperature distribution field of the timing package into isothermal gradient regions and extract multiple temperature gradient regions; Conducting deep mining of inter-regional heat diffusion in the temperature gradient region to obtain inter-regional temperature diffusion heat flow waveforms; Based on the temperature diffusion heat flow waveform between regions, the spatial temperature gradient diffusion distribution analysis is performed to construct the temperature diffusion distribution map of each region.

3. The BGA chip packaging and testing method according to claim 1, wherein: The specific steps of step S2 are: Perform acoustic scanning on the contact surface of the BGA chip solder balls according to the probe array to obtain the acoustic reflection signal flow on the solder ball surface; Adaptive frequency domain optimization is performed on the acoustic reflection signal flow on the solder ball surface to construct an adaptive gain acoustic signal flow; Define equal-time windows, perform multi-window decomposition on the adaptive gain acoustic signal stream, and extract the acoustic signal streams of multiple windows; Calculate the acoustic wave frequency of each window on the acoustic signal streams of multiple windows to obtain the acoustic wave frequency parameters of each window; Frequency distribution analysis is performed based on the acoustic wave frequency parameters, abnormal frequency detection is performed, and abnormal acoustic nodes are marked.

4. The BGA chip packaging and testing method according to claim 3, wherein: The specific steps of adaptively optimizing the acoustic reflection signal flow on the solder ball surface in the frequency domain and constructing the adaptive gain acoustic signal flow are as follows: Perform short-time Fourier transform on the acoustic reflection signal flow on the solder ball surface to obtain a time-frequency domain distribution diagram; Identifying the time dimension energy distribution and the frequency dimension energy distribution of the time-frequency domain distribution graph; Detect energy dispersion areas based on energy distribution in time dimension and energy distribution in frequency dimension, and mark weak and strong frequency bands; Adaptive frequency domain optimization is performed on weak and strong frequency bands to construct adaptive gain acoustic signal flow; The adaptive frequency domain optimization specifically includes: performing signal gain processing on weak frequency bands; and performing signal attenuation processing on strong frequency bands.

5. The BGA chip packaging and testing method according to claim 1, wherein: The specific steps of step S3 are: performing spatial positioning of abnormal nodes on the temperature diffusion distribution map based on abnormal acoustic nodes, and marking the spatial position of the abnormal nodes in the thermal distribution map; Performing transient temperature mutation detection on the spatial position and marking the transient thermal mutation point; Calculating the transient thermal mutation temperature peak value and the temperature gradient diffusion rate of the transient thermal mutation point; Calculate the duration of transient thermal anomaly at the transient thermal mutation point to obtain the duration of thermal anomaly; According to the duration of thermal anomaly, the transient mutation temperature peak and temperature gradient diffusion rate are mined to mine the mutation point temperature time series fluctuation, and the thermal anomaly time-varying curve of the mutation point is constructed; Based on the time-varying curve of thermal anomaly at the mutation point, potential packaging defect positioning analysis is performed to extract the potential packaging defect area.

6. The BGA chip packaging and testing method according to claim 1, wherein: The specific steps of step S4 are: Perform multi-threshold micro-vibration excitation on the potential package defect area and extract the vibration response parameters of the solder ball contact surface in the potential defect area; Identify the vibration response correlation sequence based on the solder ball contact surface vibration response parameters to extract the micro-vibration input path of the potential defect; Calculate the vibration vector of the micro-vibration input path of the potential defect to obtain the vibration vector information of the solder ball contact surface; Calculate the vibration excitation amplitude and phase according to the vibration vector information of the solder ball contact surface; A comprehensive structural reliability assessment of the defective area is performed based on the vibration excitation amplitude and phase, and a structural reliability assessment report of the solder ball contact surface is generated.

7. The BGA chip packaging and testing method according to claim 1, wherein: The specific steps of step S5 are: Obtain the historical work log of the BGA chip; identify the chip working environment thermal cycle and mechanical error parameters based on the historical work log of the BGA chip; Conduct multi-parameter coupling mining on the reliability assessment report of the solder ball contact surface structure and construct a multi-parameter coupling model of the solder ball contact surface; Based on the chip working environment thermal cycle and mechanical error parameters, a risk path deduction is performed on the multi-parameter coupling model of the solder ball contact surface to generate a solder ball failure action trajectory; The failure time of the solder ball failure action trajectory is predicted to generate the predicted time point of solder ball failure.

8. The BGA chip packaging and testing method according to claim 1, wherein: The specific steps of step S6 are: Predict the failure probability of future working cycles based on the solder ball failure trajectory and generate a failure probability density curve; Based on the solder ball failure prediction time point and failure probability density curve, the solder joint failure risk rating is performed to obtain the package solder joint failure risk level; Perform comprehensive defect diagnosis based on the package solder joint failure risk level and generate the final defect diagnosis results; Based on the final defect diagnosis results, the packaging process parameters are intelligently optimized and an intelligent packaging test optimization model is constructed.

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