Test board with universal mother board matched with special daughter board and design method thereof

Abstract

The invention discloses a test board with a universal mother board matched with a special daughter board and a design method of the test board, the flexibility and reusability of a test system are remarkably improved, the mother board is integrated with a classification resource interface and a universal peripheral circuit, and standardized access and balanced distribution of test equipment resources are achieved; the special daughter board quickly obtains mother board resources through the modularized connector daughter head, and customizes a peripheral circuit according to the characteristics of a tested chip, so that the problem of repeated development of hardware in a traditional scheme is solved; through combination of a connector type selection database and an algorithm resource allocation model, signal type grouping isolation and power supply load dynamic balance are ensured, and crosstalk and temperature rise problems are effectively inhibited. In addition, due to the design that expansion interfaces are reserved on the mother board and the daughter boards are unified in mechanical size, the follow-up upgrading and maintaining cost is further reduced, the development period of the test board can be shortened, meanwhile, the integrity index of test signals is improved, and remarkable technical and economic benefits are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip detection, and in particular to a test board of a universal motherboard matched with a dedicated daughterboard and a design method thereof. Background Art

[0002] When testing chips with test equipment, a printed circuit board (PCB) is typically required. This board must be connected to the test equipment via a fixed interface, allowing for the passage of fixed pins on the test equipment. Furthermore, to meet customer testing requirements, the necessary peripheral circuitry for resource utilization on the test equipment must be configured. Consequently, the board is typically larger and has thicker layers.

[0003] Before delivery to customers, the test board usually needs to be debugged, during which various problems may arise. If it is a circuit design problem, the test PCB board needs to be redesigned and produced, which will increase the project cost. In order to reduce costs and reduce design risks, this application proposes a solution for designing a test board using a universal motherboard with a dedicated daughterboard. Summary of the Invention

[0004] The purpose of the present invention is to provide a test board for a universal motherboard and a dedicated daughterboard and a design method thereof, so as to solve the problems existing in the above-mentioned prior art.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] The present invention provides a test board for a universal motherboard and a dedicated daughterboard, comprising:

[0007] A motherboard, wherein a test equipment connector interface, a power resource connector female head, a digital signal resource connector female head, and an analog signal resource connector female head are provided on the motherboard; a motherboard peripheral circuit is printed on the motherboard; the test equipment connector interface, the power resource connector female head, the digital signal resource connector female head, and the analog signal resource connector female head are all connected to the motherboard peripheral circuit;

[0008] A daughterboard is provided with a test chip mounting seat, a power resource connector sub-head, a digital signal resource connector sub-head and an analog signal resource connector sub-head; the daughterboard is printed with a daughterboard peripheral circuit; the test chip mounting seat, the power resource connector sub-head, the digital signal resource connector sub-head and the analog signal resource connector sub-head are all connected to the daughterboard peripheral circuit; the analog signal resource connector sub-head cooperates with the power resource connector female head, the digital signal resource connector sub-head cooperates with the digital signal resource connector female head, and the analog signal resource connector sub-head cooperates with the analog signal resource connector female head.

[0009] The present invention also provides a method for designing a test board for a universal motherboard and a dedicated daughterboard, comprising the following steps:

[0010] S1. Collect existing test board information to build a database and collect customer test requirement information through standardized customer requirement templates;

[0011] S2. Based on customer test requirements and database data, use the Python algorithm model to allocate resources and generate a motherboard design framework;

[0012] S3. Design the motherboard schematic and PCB layout using Cadence software based on the motherboard design framework.

[0013] S4. Select connectors and perform mechanical reliability verification;

[0014] S5. Design the daughterboard schematic and PCB layout using Cadence software based on the motherboard and connectors.

[0015] S6. Simulate and verify the motherboard and daughterboard, and output the final design file;

[0016] S7. Put the motherboard and daughterboard into production according to the final design documents.

[0017] Preferably, in step S1, the existing test board information includes the size, number of layers, material, connector type, signal type, and Pogo Pin specifications, HSD connector model, and power interface protocol of the existing test board.

[0018] Preferably, the database includes a connector library, a test equipment resource library and a peripheral circuit module library, wherein the connector library stores female head model data, female head model data, pin definition data, current carrying capacity data, voltage carrying capacity data, and frequency carrying capacity data; the test equipment resource library stores power supply parameter data, digital signal protocol data, and analog signal bandwidth data; the peripheral circuit module library stores power supply filter circuit data, signal conditioning circuit data, and impedance matching circuit data; the customer demand standardization template includes a test equipment resource list, a chip test requirement list, and a physical constraint condition list, wherein the test equipment resource list includes the number of power supplies, power supply accuracy, number of digital channels, digital channel rate, analog signal type, and analog signal bandwidth; the chip test requirement list includes power supply voltage, power supply current, signal timing requirements, and test point distribution map; the physical constraint condition list includes the test machine interface position and board installation space restrictions.

[0019] Preferably, step S2 specifically includes:

[0020] S21. Evenly distribute the power to multiple female connectors based on the customer's total power requirements;

[0021] S22. Grouped by signal type and assigned to different female connectors;

[0022] S23. Generate connector layout suggestions;

[0023] S24. Output the JSON configuration file of the motherboard design framework.

[0024] Preferably, in step S24, the JSON configuration file includes: the number of connector female heads, the number and type of connector female heads, a list of peripheral circuit modules, and PCB stacking recommendations.

[0025] Preferably, step S3 specifically includes:

[0026] S31. Place the standardized female connector symbol in Cadence software.

[0027] S32. Integrate the necessary peripheral circuit modules, including the power inlet including a TVS diode and a π-type filter circuit, the digital signal including a termination resistor network and ESD protection device, and the analog signal including a low-noise LDO regulator and RC filter device;

[0028] S33. The female connector is fixedly arranged according to the device interface position;

[0029] S34. Segment the power layer based on the independent copper area of each power supply;

[0030] S35. Routing high-speed signals based on impedance control;

[0031] S36. Reserve test points.

[0032] Preferably, step S4 specifically includes:

[0033] S41. Select a corresponding sub-head for each female head;

[0034] S42. Check the insertion tolerance using the 3D model.

[0035] Preferably, step S5 specifically includes:

[0036] S51. Map resources from the motherboard to the daughterboard in Cadence software;

[0037] S52 introduces the power signal through the sub-head connector;

[0038] S53. Design peripheral circuits according to chip requirements, including an adjustable LDO voltage regulator and current monitoring circuit for the chip under test, and a digital interface including a level shifter and signal buffer.

[0039] S54. Sub-board layered design;

[0040] S55. Use ground wrapping and length matching methods for high-speed clock routing;

[0041] S56. Use guard ring isolation and independent grounding methods for analog signal area processing.

[0042] Preferably, step S6 specifically includes:

[0043] S61. Perform PDN impedance analysis, eye diagram verification, and crosstalk analysis using Cadence Sigrity.

[0044] S62. Use Cadence Celsius to analyze the temperature rise of power modules;

[0045] S63. Export the STEP model to ANSYS to verify the connector plug-in life and board deformation.

[0046] Compared with the prior art, the present invention has achieved the following beneficial technical effects:

[0047] 1. Reduced costs. Different projects are tested on the same machine, so only daughter boards can be produced for testing, and some motherboards with fixed configurations do not need to be produced again. If problems arise during the debugging of the same project later, only the daughter board can be replaced, and the motherboard and daughterboard can be designed and produced at the same time, which can reduce time costs.

[0048] 2. Reduce design errors. The fixed configuration required by the machine can be designed on the motherboard, reducing the problems of missing designs and design errors during the project design process;

[0049] 3. Improved project efficiency. Some fixed configurations do not need to be redesigned. Only different parts of different projects need to be designed.

[0050] 4. Improved the utilization rate of consumables. The board factory design requires a minimum number of blocks, which are usually not used up in one project. The motherboard is designed to be universal so that idle consumables can be reused. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 A schematic diagram of the motherboard structure in a test board comprising a universal motherboard and a dedicated daughterboard provided by the present invention;

[0053] Figure 2A schematic diagram of the daughterboard structure of a test board comprising a universal motherboard and a dedicated daughterboard provided by the present invention;

[0054] In the figure: 1: motherboard, 11: test equipment connector interface, 12: power resource connector female head, 13: digital signal resource connector female head, 14: analog signal resource connector female head; 2: daughter board, 21: test chip mounting base, 22: power resource connector sub-head, 23: digital signal resource connector sub-head, 24: analog signal resource connector sub-head. DETAILED DESCRIPTION

[0055] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0056] The purpose of the present invention is to provide a test board for a universal motherboard and a dedicated daughterboard and a design method thereof, so as to solve the problems existing in the prior art.

[0057] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0058] Example 1:

[0059] This embodiment provides a test board that combines a universal motherboard with a dedicated daughterboard, such as Figure 1 and Figure 2 Shown, including:

[0060] A motherboard 1 is provided with a test equipment connector interface 11, a power resource connector female head 12, a digital signal resource connector female head 13, and an analog signal resource connector female head 14. Motherboard peripheral circuits are printed on the motherboard 1. The test equipment connector interface 11, the power resource connector female head 12, the digital signal resource connector female head 13, and the analog signal resource connector female head 14 are all connected to the motherboard peripheral circuits.

[0061] The daughter board 2 is provided with a test chip mounting seat 21, a power resource connector sub-head 22, a digital signal resource connector sub-head 23 and an analog signal resource connector sub-head 24. The daughter board 2 is printed with a daughter board peripheral circuit. The test chip mounting seat 21, the power resource connector sub-head 22, the digital signal resource connector sub-head 23 and the analog signal resource connector sub-head 24 are all connected to the daughter board peripheral circuit. The analog signal resource connector sub-head 22 cooperates with the power resource connector female head 12, the digital signal resource connector sub-head 23 cooperates with the digital signal resource connector female head 13, and the analog signal resource connector sub-head 24 cooperates with the analog signal resource connector female head 14.

[0062] The test board provided in this embodiment, which combines a universal motherboard with a dedicated daughterboard, significantly enhances the flexibility and reusability of the test system through a layered architecture of "standardized motherboard + customized daughterboard." Specifically, the motherboard integrates classified resource interfaces (power supply, digital signal, analog signal female connectors) and universal peripheral circuits, enabling standardized access and balanced distribution of test equipment resources. The dedicated daughterboard quickly accesses motherboard resources through modular connector sub-headers and customizes peripheral circuits based on the characteristics of the chip being tested, eliminating the problem of duplicate hardware development in traditional solutions.

[0063] This embodiment also provides a method for designing a test board for a universal motherboard and a dedicated daughterboard, comprising the following steps:

[0064] S1. Collect existing test board information to build a database and collect customer test requirement information through standardized customer requirement templates;

[0065] The existing test board information includes the size, number of layers, material, connector type, signal type, Pogo Pin specifications of common test equipment resource interfaces, HSD connector model, and power interface protocol of the existing test board;

[0066] The database includes a connector library, a test equipment resource library, and a peripheral circuit module library. The connector library stores female connector model data, sub-connector model data, pin definition data, current carrying capacity data, voltage carrying capacity data, and frequency carrying capacity data; the test equipment resource library stores power supply parameter data, digital signal protocol data, and analog signal bandwidth data; the peripheral circuit module library stores power supply filter circuit data, signal conditioning circuit data, and impedance matching circuit data; the customer demand standardization template includes a test equipment resource list, a chip test requirement list, and a physical constraint list. The test equipment resource list includes the number of power supplies, power supply accuracy, number of digital channels, digital channel rate, analog signal type, and analog signal bandwidth; the chip test requirement list includes power supply voltage, power supply current, signal timing requirements, and test point distribution diagram; the physical constraint list includes the test machine interface location and board installation space restrictions;

[0067] S2. Based on customer test requirements and database data, use the Python algorithm model to allocate resources and generate a motherboard design framework. This includes:

[0068] S21. Based on the customer's total power requirements, evenly distribute power to multiple female connectors to avoid single-point overload.

[0069] S22. Group signals by type and assign them to different female connectors to reduce crosstalk;

[0070] S23. Generate connector layout suggestions, such as placing power connectors close to the board edge and high-speed signal connectors in a centralized location.

[0071] S24. Output the JSON configuration file of the motherboard design framework; the JSON configuration file includes: the number of female connectors, the number and type of female connectors, a list of peripheral circuit modules, and PCB stackup recommendations;

[0072] S3. Design the motherboard schematic and PCB layout using Cadence software based on the motherboard design framework. This includes:

[0073] S31. Place the standardized female connector symbol in the Cadence software, matching the footprint model in the database.

[0074] S32. Integrate the necessary peripheral circuit modules, including the power inlet including a TVS diode and a π-type filter circuit, the digital signal including a termination resistor network and ESD protection device, and the analog signal including a low-noise LDO regulator and RC filter device;

[0075] S33. The female connectors are arranged according to the device interface location. For example, the three female connectors on the left correspond to the test machine slots.

[0076] S34. Segment the power layer based on the independent copper area of each power supply, for example, setting a 20-mil spacing isolation zone;

[0077] S35. Routing high-speed signals according to impedance control, such as single-ended 50Ω, differential 100Ω, and length matching ±50mil;

[0078] S36. Reserve test points, at least two test pads for each power network, and add via stubs for key signal lines;

[0079] S4. Select connectors and perform mechanical reliability verification, including:

[0080] S41. Select a corresponding sub-head for each female head;

[0081] S42. Use the 3D model to check the mating tolerance. In Cadence 3D Canvas, confirm that the connector alignment deviation is <0.2mm and the board parallelism is <0.5°.

[0082] S5. Design the daughterboard schematics and PCB layout using Cadence software based on the motherboard and connectors. This includes:

[0083] S51. Map resources from the motherboard to the daughterboard in Cadence software;

[0084] S52. Introduce the power signal through the sub-head connector and add decoupling capacitors of 100nF + 10μF per power pin;

[0085] S53. Design peripheral circuits according to chip requirements, including an adjustable LDO voltage regulator and current monitoring circuit for the chip under test, and a digital interface including a level shifter and signal buffer.

[0086] S54. Sub-board layered design;

[0087] S55. Use ground wrapping and length matching methods for high-speed clock routing;

[0088] S56. Use guard ring isolation and independent grounding methods for analog signal area processing;

[0089] S6. Simulate and verify the motherboard and daughterboard, and output the final design files; specifically, including:

[0090] S61. Perform PDN impedance analysis, eye diagram verification, and crosstalk analysis using Cadence Sigrity.

[0091] S62. Use Cadence Celsius to analyze the temperature rise of power modules;

[0092] S63. Export the STEP model to ANSYS to verify the connector plug life and board deformation;

[0093] S7. Put the motherboard and daughterboard into production according to the final design documents.

[0094] In this embodiment, the selection of the motherboard connector interface must meet the requirements of the test equipment resources. Consider the temperature resistance of the connector, the frequency, current, and voltage that the connector can pass; the placement of the motherboard connector, and the placement of several connectors in a position that does not affect the fixed connection port of the test equipment resources; the distribution of resources on the motherboard connector, how much power resources are placed on the connector, how many pins are needed for the power resources to evenly distribute the current, the power resources must be designed with Force and Sense signals, and GND and DGS signals are also required for the power signals; digital signal resources require digital ground signals to be arranged around each signal as a spacing, and how many signals need to be placed on each connector. For the circuit from the fixed connector of the test equipment to the motherboard connector to the chip, equal length design must be considered in advance for time parameter testing; impedance control must be considered in advance for high-frequency signal testing; and anti-interference design must be considered in advance for analog signal testing.

[0095] This embodiment provides a design method for a test board that combines a universal motherboard with a dedicated daughterboard. By combining a connector selection database with an algorithmic resource allocation model, this method ensures signal type grouping and isolation, and dynamic power load balancing, effectively suppressing crosstalk and temperature rise issues. Furthermore, the motherboard's reserved expansion interface and the daughterboard's uniform mechanical dimensions further reduce subsequent upgrade and maintenance costs. This solution can shorten the test board development cycle by over 40%, while improving test signal integrity and eye diagram height by 30%, resulting in significant technical and economic benefits.

[0096] The present invention uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A test board for a universal motherboard with a dedicated daughterboard, featuring: include: A motherboard (1), wherein the motherboard (1) is provided with a test equipment connector interface (11), a power resource connector female head (12), a digital signal resource connector female head (13), and an analog signal resource connector female head (14); a motherboard peripheral circuit is printed on the motherboard (1); the test equipment connector interface (11), the power resource connector female head (12), the digital signal resource connector female head (13), and the analog signal resource connector female head (14) are all connected to the motherboard peripheral circuit; A daughterboard (2) is provided with a test chip mounting seat (21), a power resource connector sub-head (22), a digital signal resource connector sub-head (23) and an analog signal resource connector sub-head (24); a daughterboard peripheral circuit is printed on the daughterboard (2); the test chip mounting seat (21), the power resource connector sub-head (22), the digital signal resource connector sub-head (23) and the analog signal resource connector sub-head (24) are all connected to the daughterboard peripheral circuit; the analog signal resource connector sub-head (22) cooperates with the power resource connector female head (12), the digital signal resource connector sub-head (23) cooperates with the digital signal resource connector female head (13), and the analog signal resource connector sub-head (24) cooperates with the analog signal resource connector female head (14).

2. A design method for a test board that combines a universal motherboard with a dedicated daughterboard, characterized by: The following steps are involved: S1. Collect existing test board information to build a database and collect customer test requirement information through standardized customer requirement templates; S2. Based on customer test requirements and database data, use the Python algorithm model to allocate resources and generate a motherboard design framework; S3. Design the motherboard schematic and PCB layout using Cadence software based on the motherboard design framework. S4. Select connectors and perform mechanical reliability verification; S5. Design the daughterboard schematic and PCB layout using Cadence software based on the motherboard and connectors. S6. Simulate and verify the motherboard and daughterboard, and output the final design file; S7. Put the motherboard and daughterboard into production according to the final design documents.

3. The method for designing a test board for a universal motherboard and a dedicated daughterboard according to claim 2, characterized in that: In step S1, the existing test board information includes the size, number of layers, material, connector type, signal type, and Pogo Pin specifications, HSD connector model, and power interface protocol of the existing test board.

4. The method for designing a test board for a universal motherboard and a dedicated daughterboard according to claim 2, wherein: In step S1, the database includes a connector library, a test equipment resource library, and a peripheral circuit module library. The connector library stores female connector model data, female connector model data, pin definition data, current carrying capacity data, voltage carrying capacity data, and frequency carrying capacity data. The test equipment resource library stores power supply parameter data, digital signal protocol data, and analog signal bandwidth data; the peripheral circuit module library stores power supply filter circuit data, signal conditioning circuit data, and impedance matching circuit data; The standardized template for customer requirements includes a list of test equipment resources, a list of chip test requirements, and a list of physical constraints. The list of test equipment resources includes the number of power supplies, power supply accuracy, number of digital channels, digital channel rate, analog signal type, and analog signal bandwidth; the list of chip test requirements includes supply voltage, supply current, signal timing requirements, and a test point distribution diagram. The physical constraint list includes the test machine interface location and board installation space limitations.

5. The method for designing a test board for a universal motherboard and a dedicated daughterboard according to claim 2, wherein: Step S2 specifically includes: S21. Evenly distribute the power to multiple female connectors based on the customer's total power requirements; S22. Grouped by signal type and assigned to different female connectors; S23. Generate connector layout suggestions; S24. Output the JSON configuration file of the motherboard design framework.

6. The method for designing a test board for a universal motherboard and a dedicated daughterboard according to claim 5, characterized in that: In step S24, the JSON configuration file includes: the number of connector female heads, the number and type of connector female heads, a list of peripheral circuit modules, and PCB stacking recommendations.

7. The method for designing a test board for a universal motherboard and a dedicated daughterboard according to claim 2, wherein: Step S3 specifically includes: S31. Place the standardized female connector symbol in Cadence software. S32. Integrate the necessary peripheral circuit modules, including the power inlet including a TVS diode and a π-type filter circuit, the digital signal including a termination resistor network and ESD protection device, and the analog signal including a low-noise LDO regulator and RC filter device; S33. The female connector is fixedly arranged according to the device interface position; S34. Segment the power layer based on the independent copper area of each power supply; S35. Routing high-speed signals based on impedance control; S36. Reserve test points.

8. The method for designing a test board for a universal motherboard and a dedicated daughterboard according to claim 2, wherein: Step S4 specifically includes: S41. Select a corresponding sub-head for each female head; S42. Check the insertion tolerance using the 3D model.

9. The method for designing a test board for a universal motherboard and a dedicated daughterboard according to claim 2, wherein: Step S5 specifically includes: S51. Map resources from the motherboard to the daughterboard in Cadence software; S52 introduces the power signal through the sub-head connector; S53. Design peripheral circuits according to chip requirements, including an adjustable LDO voltage regulator and current monitoring circuit for the chip under test, and a digital interface including a level shifter and signal buffer. S54. Sub-board layered design; S55. Use ground wrapping and length matching methods for high-speed clock routing; S56. Use guard ring isolation and independent grounding methods for analog signal area processing.

10. The method for designing a test board for a universal motherboard and a dedicated daughterboard according to claim 2, wherein: Step S6 specifically includes: S61. Perform PDN impedance analysis, eye diagram verification, and crosstalk analysis using Cadence Sigrity. S62. Use Cadence Celsius to analyze the temperature rise of power modules; S63. Export the STEP model to ANSYS to verify the connector plug-in life and board deformation.

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