Processor execution method and device, electronic equipment and storage medium

Abstract

The invention provides a processor execution method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a target address space identifier which is obtained by an instruction executed by a processor, querying a preset system register configuration area according to the target address space identifier, and executing the target address space identifier according to the preset system register configuration area, the configuration contents corresponding to the multiple address space identifiers are stored in the system register configuration area, and the corresponding instruction logic is executed according to the target configuration contents. According to the method, the configuration content is stored in the system register configuration area which can be indexed through the target address space identifier, the processor can inquire and determine the target configuration content according to the target address space identifier when needed, an operation system does not need to be modified, and meanwhile operation complexity is reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a processor execution method, device, electronic device, and storage medium. Background Art

[0002] When a thread is running, it may be necessary to perform special settings on the processor, which is usually done by configuring processor-specific system registers.

[0003] In the related art, an instruction for setting a system register is inserted into the software process for scheduling a running thread, thereby achieving the effect of modifying the processor settings.

[0004] However, the above configuration method is not transparent to the operating system, and the operating system may not use the newly added system registers. Therefore, it is necessary to modify the operating system or add a callback function to implement it, which is relatively complicated. Summary of the Invention

[0005] In view of this, an embodiment of the present application provides a processor execution method, device, electronic device and storage medium to store configuration content in a system register configuration area that can be indexed by a target address space identifier. When necessary, the processor can determine the target configuration content based on the target address space identifier query without modifying the operating system, while reducing operational complexity.

[0006] In a first aspect, an embodiment of the present application provides a processor execution method, including:

[0007] Obtaining a target address space identifier, where the target address space identifier is obtained by an instruction executed by a processor;

[0008] According to the target address space identifier, query a preset system register configuration area to obtain target configuration content corresponding to the target address space identifier, wherein the system register configuration area stores: configuration contents corresponding to multiple address space identifiers;

[0009] Execute corresponding instruction logic according to the target configuration content.

[0010] In an optional implementation, the target address space identifier includes: a first address space identifier currently used by the processor;

[0011] The executing corresponding instruction logic according to the target configuration content includes:

[0012] The first configuration content corresponding to the first address space identifier is loaded into the system register corresponding to the processor, and the corresponding instruction logic is executed.

[0013] In an optional implementation, the target address space identifier includes: a second address space identifier not used by the processor;

[0014] The executing corresponding instruction logic according to the target configuration content includes:

[0015] The second configuration content corresponding to the second address space identifier is cached, and the corresponding instruction logic is executed.

[0016] In an optional implementation, obtaining the target address space identifier includes:

[0017] The target address space identifier is obtained from a translation lookaside buffer (TLB) invalidation instruction.

[0018] In an optional implementation, executing corresponding instruction logic according to the target configuration content includes:

[0019] Determining a target processor core set of the processor according to the target configuration content, the target processor core set including: processor cores in the processor other than those that do not have an address mapping relationship corresponding to the target address space identifier;

[0020] The TLB invalidation instruction is sent to each processor core in the target processor core set, so that each processor core clears the address mapping relationship.

[0021] In an optional implementation, the target configuration content includes a configuration bitmap, and the configuration bitmap is used to indicate whether the processor core contains the address mapping relationship;

[0022] The determining, based on the target configuration content, a target processor core set of the processor includes:

[0023] According to the configuration bitmap, processor cores that do not contain the address mapping relationship are excluded to generate the target processor core set.

[0024] In an optional implementation, the target address space identifier includes at least one of a process address space identifier, a virtual machine identifier, a process address space identifier within the virtual machine, and a thread identifier.

[0025] In an optional embodiment, the method further includes:

[0026] Loading the target address space identifier on the new first processor core;

[0027] If the loading is abnormal, modifying the target processor core set according to the first processor core; or

[0028] The target processor set is modified according to the first processor core.

[0029] In an optional embodiment, the method further includes:

[0030] determining a second processor core identified by the target address space;

[0031] Other processor cores are deleted from the target processor core set, where the other processor cores are processing cores in the target processor core set except the second processor core.

[0032] In a second aspect, an embodiment of the present application further provides a processor execution device, including:

[0033] An acquisition module, configured to acquire a target address space identifier, wherein the target address space identifier is acquired by an instruction executed by a processor;

[0034] a query module, configured to query a preset system register configuration area according to the target address space identifier to obtain target configuration content corresponding to the target address space identifier, wherein the system register configuration area stores: configuration content corresponding to a plurality of address space identifiers;

[0035] An execution module is used to execute corresponding instruction logic according to the target configuration content.

[0036] In a third aspect, an embodiment of the present application further provides an electronic device comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory through the bus, and the processor executes the machine-readable instructions to execute any one of the methods described in the first aspect.

[0037] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in any one of the first aspects is executed.

[0038] The present application provides a processor execution method, device, electronic device, and storage medium, wherein the method includes: obtaining a target address space identifier, the target address space identifier being obtained by an instruction executed by the processor, querying a preset system register configuration area based on the target address space identifier, and obtaining a target configuration content corresponding to the target address space identifier, wherein the system register configuration area stores: configuration content corresponding to multiple address space identifiers, and executing corresponding instruction logic based on the target configuration content. The present application stores the configuration content in a system register configuration area that can be indexed by the target address space identifier. When needed, the processor can query and determine the target configuration content based on the target address space identifier, without modifying the operating system, while reducing operational complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 Schematic diagram of the process of the processor execution method provided in the embodiment of the application Figure 1 ;

[0041] Figure 2 Schematic diagram of the process of the processor execution method provided in the embodiment of the application Figure 2 ;

[0042] Figure 3 Schematic diagram of the process of the processor execution method provided in the embodiment of the application Figure 3 ;

[0043] Figure 4 Schematic diagram of the process of the processor execution method provided in the embodiment of the application Figure 4 ;

[0044] Figure 5 Schematic diagram of the process of the processor execution method provided in the embodiment of the application Figure 5 ;

[0045] Figure 6 A schematic diagram of the architecture of a processor execution process provided in an embodiment of the present application;

[0046] Figure 7 A schematic diagram of the structure of a processor execution device provided in an embodiment of the present application;

[0047] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0049] Special processor settings may be required for thread execution. This is typically achieved by inserting instructions for setting system registers into the software process that schedules the thread, thereby modifying the processor settings. The problems with this approach are: 1) Configuring system registers is opaque to the operating system and requires modifying the operating system, as the operating system may not use the newly added system registers. Therefore, implementing the newly added registers requires promotional issues or adding a scheduling callback function. 2) When the processor is running a process, only the system register configuration of the current process can be obtained, not the configuration of another process.

[0050] Based on this, the present application stores the configuration content in a system register configuration area that can be indexed by the target address space identifier. When needed, the processor can query and determine the target configuration content based on the target address space identifier without modifying the operating system, while reducing operational complexity.

[0051] Figure 1 Schematic diagram of the process of the processor execution method provided in the embodiment of the application Figure 1 The execution subject of this embodiment may be a processor in an electronic device, and the processor may be, for example, a central processing unit (CPU) or a microcontroller unit (MCU).

[0052] like Figure 1 As shown, the method may include:

[0053] S101: Obtain a target address space identifier.

[0054] The target address space identifier is obtained by the instruction executed by the processor, wherein the instruction may explicitly or implicitly specify the target address space identifier, wherein explicit specification can be understood as when the processor executes the instruction, the instruction carries the target address space identifier, or the instruction itself declares to use the current address space identifier as the target address space identifier.

[0055] The implicit indication can be understood as the instruction parameter in the instruction executed by the processor being the target register, wherein the target register can be a general register or an address translation register, and the value of the target register includes the target address space identifier, so the target address space identifier can be obtained through the value of the target register.

[0056] In an optional implementation, the target address space identifier may include at least one of a process address space identifier (ASID), a virtual machine identifier, a process address space identifier within the virtual machine, and a thread identifier.

[0057] Among them, the process address space identifier is the address space identifier of the process currently running on the processor, the virtual machine identifier is the identifier of the virtual machine currently running on the processor, the process address space identifier within the virtual machine is the address space identifier of the process within the virtual machine currently running on the processor, and the thread identifier is the identifier of the thread currently running on the processor.

[0058] It is worth noting that the virtual machine identifier and the address space identifier of the process in the virtual machine can be used together as the target address space identifier.

[0059] S102: According to the target address space identifier, query the preset system register configuration area to obtain the target configuration content corresponding to the target address space identifier.

[0060] The system register configuration area stores configuration contents corresponding to multiple address space identifiers.

[0061] According to the target address space identifier, the preset system register configuration area is queried to obtain the target configuration content corresponding to the target address space identifier, wherein the processor content corresponding to each address space identifier is the configuration content of the processor pre-configured for each address space identifier, and the target configuration content is the configuration content of the processor pre-configured for the target address space identifier.

[0062] In some embodiments, there can be multiple ways to store configuration content corresponding to different address space identifiers in the system register configuration area. For example, on an instruction set architecture arm64 machine, the system register configuration area can be defined as containing 512 items, of which the first 256 items describe the configuration content corresponding to the 8-bit process address address space identifier on the physical machine, and the last 256 items describe the configuration content of the virtual machine corresponding to the 8-bit virtual machine identifier (Virtual Machine Identifier, VMID).

[0063] It is worth noting that when the number of bits of the process address space identifier and the virtual machine identifier is small, such as 8 bits, these configuration register contents (configuration contents) can be recorded in a storage area with continuous physical addresses in the system register configuration area; for situations with a large number of address identifiers (such as using 16 bits as address identifiers), you can consider organizing these configuration register contents (configuration contents) in a manner similar to a page table, and store them in multiple discontinuous physical memory blocks, so as to avoid unused address space identifiers occupying physical memory space.

[0064] S103: Execute corresponding instruction logic according to the target configuration content.

[0065] After obtaining the target configuration content from the system register configuration area, the corresponding instruction logic can be executed according to the target configuration content. For example, the target configuration content is loaded into the system register corresponding to the processor for use or cached, so that the target configuration content can be read from the system register or cache later and the instruction logic of the corresponding processor configuration instruction can be executed. The processor configuration instruction is used to configure the processor.

[0066] In this embodiment, by storing the configuration content in a system register configuration area that can be indexed by the target address space identifier, the processor can determine the target configuration content based on the target address space identifier when needed, without modifying the operating system, while reducing operational complexity.

[0067] Figure 2 Schematic diagram of the process of the processor execution method provided in the embodiment of the application Figure 2 ,like Figure 2 As shown, in an optional implementation manner, the target address space identifier includes: a first address space identifier currently used by the processor.

[0068] The above step S103, executing the corresponding instruction logic according to the target configuration content, may include:

[0069] S201: Load a first configuration content corresponding to a first address space identifier into a system register corresponding to a processor, and execute corresponding instruction logic.

[0070] The first address space identifier includes at least one of a process address space identifier, a virtual machine identifier, a process address space identifier within the virtual machine, and a thread identifier.

[0071] If the target address space identifier includes a first address space identifier currently used by the processor, and the target configuration content includes a first configuration content corresponding to the first address space identifier, then the first configuration content is loaded into a system register corresponding to the processor, so that the first configuration content can be subsequently read from the system register to execute instruction logic corresponding to the processor configuration instruction. The target configuration content includes the first configuration content.

[0072] In one possible implementation, the processor provides an interface for registering a continuous physical memory area (system register configuration area). The operating system sequentially records the system register configuration (configuration content) corresponding to each address space identifier in this continuous memory area, and informs the processor through the interface. The processor determines the first configuration content corresponding to the current first address space identifier based on the pre-registered continuous physical memory area and address space identifier, and loads it into the system register corresponding to the processor for use.

[0073] In one possible implementation, the processor provides an interface for registering continuous virtual address areas, and the operating system places this configuration information into the memory corresponding to the virtual address. At this time, if these address identifiers are not allocated for use, the operating system can avoid allocating physical memory pages for the configuration content corresponding to these address identifiers. Due to the use of virtual addresses, when the processor obtains the configuration content, it needs to look up the page table to know the specific physical memory address where the configuration content is stored, which will be slower. Since the configuration content corresponding to the 16-bit address space identifier may not occupy a large space, the memory waste that may be caused by using continuous physical memory to store the configuration content is tolerable.

[0074] In an optional implementation, the target address space identifier includes: a second address space identifier not used by the processor.

[0075] The above step S103, executing the corresponding instruction logic according to the target configuration content, may include:

[0076] S202: Cache the second configuration content corresponding to the second address space identifier and execute the corresponding instruction logic.

[0077] The second address space identifier includes at least one of a process address space identifier, a virtual machine identifier, a process address space identifier within the virtual machine, and a thread identifier.

[0078] If the target address space identifier includes a second address space identifier not used by the current processor, and the target configuration content includes second configuration content corresponding to the second address space identifier, the second configuration content is cached so that the second configuration content can be subsequently read from the cache to execute the instruction logic corresponding to the processor configuration instruction. The target configuration content includes the second configuration content.

[0079] In this embodiment, the target address space identifier may include at least one of a first address space identifier and a second address space identifier, which may be determined according to actual needs and is not particularly limited in this embodiment.

[0080] Figure 3 Schematic diagram of the process of the processor execution method provided in the embodiment of the application Figure 3 ,like Figure 3 As shown, in an optional implementation, the above step S101, obtaining the target address space identifier, may include:

[0081] S301. Obtain a target address space identifier from a Translation Lookaside Buffer (TLB) invalidation instruction.

[0082] Among them, the TLB invalidation instruction is used to invalidate part or all of the address mapping relationship corresponding to the target address space identifier, that is, to clear the address mapping relationship corresponding to the target address space identifier, which is the mapping relationship between the target address space identifier and the physical address.

[0083] When the address mapping relationship of the target address space identifier changes, a TLB invalidation instruction may be obtained, the TLB invalidation instruction carries the target address space identifier, and the target address space identifier is obtained from the TLB invalidation instruction.

[0084] In an optional embodiment, the above step S103, executing the corresponding instruction logic according to the target configuration content, may include:

[0085] S302: Determine a target processor core set of the processor according to the target configuration content.

[0086] The target processor core set includes: processor cores other than the processor cores that do not have the address mapping relationship corresponding to the target address space identifier.

[0087] The processor is a multi-core processor, and the processor cores other than the address mapping relationship corresponding to the target address space identifier include two types of processor cores: one is that the cache has the address mapping relationship and has not been deleted, and the other is that the cache has the address mapping relationship but has been deleted.

[0088] The target configuration content may include a configuration bitmap, which is used to indicate whether the processor core contains an address mapping relationship corresponding to the target address space identifier. According to the configuration bitmap, the processor cores that do not contain the address mapping relationship are excluded to generate a target processor core set.

[0089] That is, according to the configuration bitmap, the processor cores that do not contain the address mapping relationship in the processor are excluded, and the remaining processor cores constitute the target processor core set.

[0090] In this embodiment, if a processor core is not in the target processor set, there is no need to send a TLB invalidation instruction to the processor core. That is, the target processor set is regarded as a broadcast domain for the TLB invalidation instruction, and the processors that are not in the set do not need to receive the TLB invalidation instruction, thereby reducing the TLB global invalidation overhead.

[0091] S303: Send a TLB invalidation instruction to each processor core in the target processor core set, so that each processor core clears the address mapping relationship.

[0092] A TLB invalidation instruction is sent to each processor core in the processor cores, and each processor core clears the address mapping relationship corresponding to the target address space identifier stored in itself based on the TLB invalidation instruction.

[0093] It's worth noting that if a processor core is part of the target set of processor cores, but has the address mapping cached but deleted, that core doesn't need to clear the address mapping. Instead, the core that cached the address mapping will clear it. However, when sending TLB invalidation instructions, both cores will receive them.

[0094] If the target address space identifier includes the first address space identifier, the first configuration content is read from the system register, and a TLB invalidation instruction is sent to each processor core in the target processor core set corresponding to the first configuration content, so that each processor core clears the corresponding address mapping relationship.

[0095] If the target address space identifier includes the second address space identifier, the second configuration content is read from the cache, and a TLB invalidation instruction is sent to each processor core in the target processor core set corresponding to the second configuration content, so that each processor core clears the corresponding address mapping relationship.

[0096] It is understandable that the operating system has a paging mechanism, the essence of which is: when running process A, the address mapping relationship of process B is modified. Therefore, the address mapping relationship corresponding to the process address space identifier of process B can be invalidated through the TLB invalidation instruction. That is to say, if the TLB invalidation instruction includes the second address space identifier, it means that the second configuration content needs to be used to clear the address mapping relationship.

[0097] It is worth noting that the schedulability bitmap is used to represent the set of target processor cores that may cache the address mapping relationship corresponding to the target address space identifier. Since the address mapping relationship corresponding to the target address space will not be cached on the processor core that does not use the target address space, when executing the TLB invalidation instruction, the schedulability bitmap corresponding to the target address space identifier can be used to forward only the TLB invalidation instruction of the address mapping relationship to the processor core that may store the address mapping relationship and wait for its processing to be completed, thereby avoiding waiting for irrelevant processor cores to complete the processing of the TLB invalidation instruction, thereby achieving the effect of improving the execution performance of the TLB invalidation instruction.

[0098] Figure 4 Schematic diagram of the process of the processor execution method provided in the embodiment of the application Figure 4 ,like Figure 4 As shown, in an optional embodiment, the method may further include steps S401-S402, or step S403:

[0099] S401: Load a target address space identifier on a new first processor core.

[0100] S402: If the loading is abnormal, modify the target processor core set according to the first processor core.

[0101] The new first processor core is a processor in the non-target processor core set, for example, a processor core to which a process or thread corresponding to a process address space is migrated.

[0102] The target address space identifier is loaded on the first processor core. If the loading is abnormal, it means that the first processor core is not allowed by the target address space identifier. It can be determined that a thread contained in the process corresponding to the target address space identifier may have migrated to the first processor core that is currently not allowed. Then, the target processor core set can be modified according to the first processor core, that is, the first processor core is added to the target processor core set to realize the automatic update of the TLB invalidation broadcast domain corresponding to the target address space identifier.

[0103] For example, initially, the administrator expects Task A to run on processor cores 0 and 1. The TLB invalidate broadcast domain bitmap defined for Task A's address space identifier is 0x3. During runtime, the TLB invalidate instruction caused by the operating system's modification of Task A's address space will only be sent to processor cores 0 and 1. Later, the operating system attempts to schedule Task A to run on processor core 2. When loading Task A's address space, because processor core 2 is not in the TLB invalidate broadcast domain bitmap, a synchronization exception is triggered. The synchronization exception handling function modifies the TLB invalidate broadcast domain bitmap to 0x7, that is, processor core 2 is added to the TLB invalidate broadcast domain bitmap, and the exception handling ends.

[0104] After the exception handling is completed, the operating system continues to try to load the address space of task A on processor core 2. At this time, because processor core 2 is allowed by bitmap 0x7, it can be executed successfully. Then, the TLB invalidation instruction caused by the operating system's modification of task A's address space will be sent to processor core 0, processor core 1, and processor core 2.

[0105] S403: Modify the target processor set according to the first processor core.

[0106] When it is determined that a new first processor core exists, the target processor set is modified to add the new first processor core to the target processor core set, so that the processor supports loading the target address space identifier on the new first processor core.

[0107] In this embodiment, by tracking migration between process cores, it is determined that a thread contained in the process corresponding to the target address space identifier may have migrated to the first processor core that is currently not allowed, or when a new processor core exists, the target processor core set is modified to achieve automatic update of the TLB invalidation broadcast domain corresponding to the target address space identifier.

[0108] Figure 5 Schematic diagram of the process of the processor execution method provided in the embodiment of the application Figure 5 ,like Figure 5 As shown, in an optional embodiment, the method may further include:

[0109] S501: Determine information of a second processor core identified by using a target address space.

[0110] S502: Delete other processor cores from the target processor core set, where the other processor cores are the processing cores in the target processor core set except the second processor core.

[0111] As Task A drifts across various processor cores, the TLB invalidation broadcast domain may include too many processor cores, resulting in poor multicast performance. To address this issue, we can track which processor cores are currently using the target address space identifier, identify the second processor core using the target address space identifier, and then remove all processor cores from the processor set except the second core to update the target processor core set.

[0112] In this embodiment, by tracking which cores are currently using this address space, unnecessary processor cores can be deleted from the processor set. When executing a TLB invalidation instruction, it is possible to avoid waiting for irrelevant processor cores to complete processing the TLB invalidation instruction, thereby improving the execution performance of the TLB invalidation instruction.

[0113] Based on the above embodiments, Figure 6 A specific processor execution process is described.

[0114] Figure 6 A schematic diagram of the architecture of a processor execution process provided in an embodiment of the present application is shown as follows: Figure 6 As shown, it includes: a processor core and a memory, and the processor core can be any processor core of a multi-core processor.

[0115] The processor core determines the system register configuration area in the memory based on the system register configuration area base address (Base Address), wherein the system register storage area base address refers to the starting address of a system register configuration area in the memory.

[0116] The processor core obtains the first address space identifier currently in use, and queries the system register configuration area in the memory, obtains the first configuration content corresponding to the first address space identifier and loads it into the system register. When the instruction is executed, if the first configuration content needs to be used, the current value of the system register is directly used.

[0117] If the processor core finds that the second configuration content corresponding to the second address space identifier (another address space identifier) needs to be used, it queries the system register configuration area according to the second address space identifier, obtains the second configuration content, and caches it in the processor core for instruction execution.

[0118] Figure 7 This is a structural diagram of a processor execution device provided in an embodiment of the present application, which can be integrated into a processor of an electronic device.

[0119] like Figure 7 As shown, the device may include:

[0120] An acquisition module 601 is configured to acquire a target address space identifier, where the target address space identifier is acquired by an instruction executed by a processor;

[0121] A query module 602 is configured to query a preset system register configuration area according to the target address space identifier to obtain target configuration content corresponding to the target address space identifier, wherein the system register configuration area stores configuration content corresponding to multiple address space identifiers;

[0122] The execution module 603 is used to execute the corresponding instruction logic according to the target configuration content.

[0123] In an optional embodiment, the target address space identifier includes: a first address space identifier currently used by the processor;

[0124] The execution module 603 is specifically configured to:

[0125] The first configuration content corresponding to the first address space identifier is loaded into the system register corresponding to the processor, and the corresponding instruction logic is executed.

[0126] In an optional embodiment, the target address space identifier includes: a second address space identifier not used by the processor;

[0127] The execution module 603 is specifically configured to:

[0128] The second configuration content corresponding to the second address space identifier is cached, and the corresponding instruction logic is executed.

[0129] In an optional implementation, the execution module 603 is specifically configured to:

[0130] Determine a target processor core set of the processor according to the target configuration content, the target processor core set including: processor cores other than the processor cores that do not have an address mapping relationship corresponding to the target address space identifier;

[0131] A TLB invalidation instruction is sent to each processor core in the target processor core set, so that each processor core clears the address mapping relationship.

[0132] In an optional embodiment, the target configuration content includes a configuration bitmap, and the configuration bitmap is used to indicate whether the processor core contains an address mapping relationship;

[0133] The execution module 603 is specifically configured to:

[0134] According to the configuration bitmap, processor cores without address mapping relationships are excluded and a target processor core set is generated.

[0135] In an optional implementation, the target address space identifier includes at least one of a process address space identifier, a virtual machine identifier, a process address space identifier within the virtual machine, and a thread identifier.

[0136] In an optional implementation, the execution module 603 is further configured to:

[0137] Loading the target address space identifier on the new first processor core;

[0138] If the loading is abnormal, modify the target processor core set according to the first processor core; or,

[0139] The target processor set is modified based on the first processor core.

[0140] In an optional implementation, the execution module 603 is further configured to:

[0141] determining a second processor core identified using the target address space;

[0142] The other processor cores are deleted from the target processor core set, where the other processor cores are the processing cores in the target processor core set except the second processor core.

[0143] For descriptions of the processing flow of each module in the device and the interaction flow between each module, reference can be made to the relevant descriptions in the above method embodiment, which will not be described in detail here.

[0144] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, such as Figure 8 As shown, the device may include: a processor 701, a memory 702 and a bus 703. The memory 702 stores machine-readable instructions executable by the processor 701. When the electronic device is running, the processor 701 communicates with the memory 702 through the bus 703, and the processor 701 executes the machine-readable instructions to perform the above method.

[0145] The memory 702 may be implemented by the memory in the above embodiment.

[0146] An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the above method is executed.

[0147] In the embodiment of the present application, the computer program can also execute other machine-readable instructions when run by the processor to execute other methods described in the embodiment. For the specific execution method steps and principles, please refer to the description of the embodiment and will not be repeated here.

[0148] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into a second system, or some features can be ignored or not executed. Second, the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0149] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0150] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0151] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0152] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0153] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed in the present application, or make equivalent replacements for some of the technical features thereof. However, these modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A processor execution method, characterized in that: include: Obtaining a target address space identifier, where the target address space identifier is obtained by an instruction executed by a processor; According to the target address space identifier, query a preset system register configuration area to obtain target configuration content corresponding to the target address space identifier, wherein the system register configuration area stores: configuration contents corresponding to multiple address space identifiers; Execute corresponding instruction logic according to the target configuration content.

2. The method according to claim 1, characterized in that The target address space identifier includes: a first address space identifier currently used by the processor; The executing corresponding instruction logic according to the target configuration content includes: The first configuration content corresponding to the first address space identifier is loaded into the system register corresponding to the processor, and the corresponding instruction logic is executed.

3. The method according to claim 1, characterized in that The target address space identifier includes: a second address space identifier not used by the processor; The executing corresponding instruction logic according to the target configuration content includes: The second configuration content corresponding to the second address space identifier is cached, and the corresponding instruction logic is executed.

4. The method according to claim 1, wherein The obtaining of the target address space identifier includes: The target address space identifier is obtained from a translation lookaside buffer (TLB) invalidation instruction.

5. The method according to claim 4, characterized in that The executing corresponding instruction logic according to the target configuration content includes: Determining a target processor core set of the processor according to the target configuration content, the target processor core set including: processor cores in the processor other than those that do not have an address mapping relationship corresponding to the target address space identifier; The TLB invalidation instruction is sent to each processor core in the target processor core set, so that each processor core clears the address mapping relationship.

6. The method according to claim 5, characterized in that The target configuration content includes a configuration bitmap, and the configuration bitmap is used to indicate whether the processor core contains the address mapping relationship; The determining, based on the target configuration content, a target processor core set of the processor includes: According to the configuration bitmap, processor cores that do not contain the address mapping relationship are excluded to generate the target processor core set.

7. The method according to any one of claims 1 to 6, characterized in that The target address space identifier includes at least one of a process address space identifier, a virtual machine identifier, a process address space identifier within the virtual machine, and a thread identifier.

8. The method according to claim 5, characterized in that The method further comprises: Loading the target address space identifier on the new first processor core; If the loading is abnormal, modifying the target processor core set according to the first processor core; or The target processor set is modified according to the first processor core.

9. The method according to claim 5, characterized in that The method further comprises: determining a second processor core identified by the target address space; Other processor cores are deleted from the target processor core set, where the other processor cores are processing cores in the target processor core set except the second processor core.

10. A processor execution device, characterized in that: include: An acquisition module, configured to acquire a target address space identifier, wherein the target address space identifier is acquired by an instruction executed by a processor; a query module, configured to query a preset system register configuration area according to the target address space identifier to obtain target configuration content corresponding to the target address space identifier, wherein the system register configuration area stores: configuration content corresponding to a plurality of address space identifiers; An execution module is used to execute corresponding instruction logic according to the target configuration content.

11. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and the processor executes the machine-readable instructions to perform the method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 9 is executed.

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