Method, device and equipment for quickly evaluating post-simulation power consumption of large-scale chip

Abstract

The invention relates to the technical field of chip development, and discloses a rapid post-simulation power consumption evaluation method, device and equipment for a large-scale chip, and the method comprises the steps: collecting various types of data of the large-scale chip, and dividing the large-scale chip into a plurality of functional sub-modules and a top-layer module; setting a time point required by post-simulation according to a waveform file FSDB generated by pre-simulation, respectively compiling RTL, netlist files and verification environments of the top-layer module and each functional sub-module to generate database files, reversely marking standard units and inter-unit connection line delay information in a simulation circuit according to an SDF file, and carrying out simulation according to the standard units and the inter-unit connection line delay information. And carrying out parallel simulation by utilizing a preset optimization tool so as to carry out post-simulation power consumption evaluation. Through the unique parallel mapping and simulation architecture, the evaluation time of the post-simulation power consumption of the large-scale integrated circuit is remarkably shortened, the advantages of a power consumption analysis and optimization tool are fully utilized, the power consumption waveform can be quickly and accurately obtained, and the power consumption evaluation speed is increased.

Description

Technical Field

[0001] The present application relates to the field of chip development technology, for example, to a method, device, and equipment for rapid evaluation of power consumption of large-scale chip post-simulation. Background Art

[0002] With the continuous development of integrated circuit technology, the scale and design complexity of chips have increased dramatically, resulting in an increasing length of time required for chip design. In the design process of large-scale integrated circuits, post-simulation power consumption evaluation is a critical factor in ensuring chip performance.

[0003] Traditional post-simulation involves placing the entire gate-level netlist into an EDA environment for simulation. During simulation, a standard delay format file is read in, and the correctness of the post-simulation is determined by applying stimulus and monitoring the netlist's output and internal signals. While this method works well for small and medium-sized circuits, the gate-level netlists of large-scale chips contain a vast number of logic gates, complex interconnect structures, and logic gate delay parameters, resulting in extremely lengthy simulation times.

[0004] In addition, the selection of power consumption simulation scenarios and waveform periods are all constructed by designers, which may lead to human errors or omissions, resulting in inaccurate power consumption assessment.

[0005] Moreover, existing chip power consumption testing technology does not have the ability to automatically select the time points of the power consumption waveform, and must be performed entirely manually. The extracted time point information cannot be reused and needs to be reconfirmed each time, which is very inefficient. When different chip modules are delivered by different teams, the confirmation work is even more time-consuming.

[0006] Although existing power analysis and optimization tools have RTL and netlist mapping and power consumption evaluation functions, their use in large-scale chip post-simulation scenarios cannot effectively solve the problem of long power consumption evaluation time in traditional methods.

[0007] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of this application. Summary of the Invention

[0008] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0009] The method, apparatus, device, and storage medium for rapid evaluation of power consumption of large-scale chip post-simulation provided by the embodiments of the present disclosure solve the problem of excessively long power consumption evaluation time in traditional methods.

[0010] The method for rapidly evaluating power consumption of a large-scale chip post-simulation in the embodiment of the present disclosure includes:

[0011] Collect multiple types of data on large-scale chips and divide them into multiple functional sub-modules and top-level modules based on their functions and physical layout;

[0012] Map and configure each functional submodule and top-level module to ensure that the RTL hierarchy is consistent with the netlist hierarchy;

[0013] According to the waveform file FSDB generated by the pre-simulation, the time point required for the post-simulation is set, and the RTL, netlist files and verification environment of the top-level module and each functional sub-module are compiled to generate database files. According to the SDF file, the standard units and the delay information of the connection between units are back-labeled in the simulation circuit, and the preset power consumption analysis and optimization tools are used for parallel simulation to obtain the waveform files required for the post-simulation power consumption evaluation.

[0014] In some embodiments, the method further comprises:

[0015] Obtaining a generated post-simulation waveform file from a preset power consumption analysis and optimization tool, and collecting standard cell library information, wherein the standard cell library information includes static power consumption parameters and dynamic power consumption related parameters of each standard cell;

[0016] Perform power consumption evaluation on the post-simulation waveform files generated by the preset power consumption analysis and optimization tools.

[0017] In some embodiments, during the power consumption evaluation, the method further includes:

[0018] Collecting power consumption data under different design parameters and working conditions as sample data, wherein the sample data includes information on module power consumption, signal flip rate, voltage change, and temperature fluctuation dimensions;

[0019] The sample data is trained using a preset artificial intelligence model to learn the relationship between chip power consumption and various design parameters and working conditions. Based on the deviation between the actual evaluation results and the model prediction values, the model parameters and structure are continuously adjusted to correct the artificial intelligence model and obtain a power consumption prediction model.

[0020] In some embodiments, the aforementioned collection of multiple types of data from large-scale chips includes:

[0021] Collect RTL code, obtain gate-level netlist, organize SDF files, and organize pre-simulation test cases.

[0022] In some embodiments, each functional submodule has independent functions and logical architecture, and the top-level module is used to coordinate the communication and data interaction between the functional submodules;

[0023] The method further comprises: for each independent functional submodule, extracting a partial netlist corresponding to the functional submodule from the synthesized overall gate-level netlist using a design tool;

[0024] A netlist of a top-level module is extracted from the overall gate-level netlist, wherein the netlist of the top-level module includes connection logic between various functional sub-modules and processing logic of top-level control signals.

[0025] In some embodiments, the mapping configuration of each functional submodule and the top-level module to ensure that the RTL hierarchy is consistent with the netlist hierarchy includes:

[0026] According to the preset mapping rules, mapping configuration operations are performed on each functional submodule and top-level module to ensure that the instance name and module name in the RTL code match the instance name and module name in the corresponding gate-level netlist;

[0027] The mapping rate and signal activity characteristics are monitored in real time. When the mapping rate is lower than the preset threshold, the mapping rules are adjusted to re-match the logic units in the RTL with the units in the netlist.

[0028] In some embodiments, the waveform file FSDB generated by the pre-simulation is used to set the time point required for the post-simulation, and the RTL, netlist files, and verification environment of the top-level module and each functional sub-module are compiled to generate a database file. According to the SDF file, the standard cells and the delay information of the connection between cells are back-labeled in the simulation circuit, and a preset power analysis and optimization tool is used to perform parallel simulation to obtain the waveform file required for the post-simulation power consumption evaluation, including:

[0029] Analyze signal changes based on the FSDB files of each functional submodule and top-level module generated in the pre-simulation phase. Set time points that require attention in the post-simulation phase based on power consumption assessment requirements.

[0030] Compile the RTL files, netlist files, verification environment files, and back-annotated delay information SDF files of the top-level module and each functional sub-module using the preset power analysis and optimization tools;

[0031] According to the corresponding SDF file and the compiled database file, the compiled database file is back-annotated with the delay information of the standard cells and the connection between cells in the simulation tool;

[0032] Using the preset power consumption analysis and optimization tools, extract the waveform range that needs to be dumped for the top-level module and each functional sub-module according to the preset post-simulation time point, and start parallel simulation at the same time;

[0033] The preset power analysis and optimization tool simulates the behavior of the circuit based on the back-annotated delay information and generates the waveform files required for post-simulation power consumption evaluation.

[0034] The large-scale chip post-simulation power consumption rapid evaluation device in the embodiment of the present disclosure includes:

[0035] The collection module is used to collect multiple types of data from large-scale chips and divide the large-scale chips into multiple functional sub-modules and top-level modules based on their functions and physical layout;

[0036] The mapping configuration module is used to map and configure each functional submodule and the top-level module to ensure that the RTL hierarchy is consistent with the netlist hierarchy;

[0037] The simulation module is used to set the time point required for post-simulation based on the waveform file FSDB generated by the pre-simulation, compile the RTL, netlist files and verification environment of the top-level module and each functional sub-module to generate database files, and according to the SDF file, back-label the standard units and the delay information of the connection between units in the simulation circuit, use the preset power consumption analysis and optimization tools to perform parallel simulation, and obtain the waveform files required for post-simulation power consumption evaluation.

[0038] An electronic device provided by an embodiment of the present disclosure includes at least one processor;

[0039] and a memory communicatively coupled to the at least one processor;

[0040] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the above-mentioned large-scale chip post-simulation power consumption rapid evaluation method.

[0041] The storage medium provided by the embodiment of the present disclosure stores program instructions, which, when running, execute the above-mentioned large-scale chip post-simulation power consumption rapid evaluation method.

[0042] The method, apparatus, device, and storage medium for rapid evaluation of large-scale chip post-simulation power consumption provided by the embodiments of the present disclosure can achieve the following technical effects:

[0043] The large-scale chip post-simulation power consumption rapid evaluation method provided by the present disclosure significantly shortens the evaluation time of large-scale integrated circuit post-simulation power consumption through a unique parallel mapping and simulation architecture, fully utilizes the advantages of power consumption analysis and optimization tools, can quickly and accurately obtain power consumption waveforms, and accelerate the speed of power consumption evaluation.

[0044] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,

[0046] Figure 1 This is a flow chart of a method for rapid power consumption evaluation of large-scale chip post-simulation provided by an embodiment of the present disclosure;

[0047] Figure 2 This is a flow chart of another method for rapid power consumption evaluation of large-scale chip post-simulation provided by an embodiment of the present disclosure;

[0048] Figure 3 This is a schematic diagram of the structure of a large-scale chip post-simulation power consumption rapid evaluation device provided by an embodiment of the present disclosure;

[0049] Figure 4 This is a structural diagram of a large-scale chip post-simulation power consumption rapid evaluation device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0051] The terms "first," "second," and the like in the embodiments of the present disclosure are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to facilitate the description of the embodiments of the present disclosure herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0052] Unless otherwise stated, the term "plurality" means two or more.

[0053] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.

[0054] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0055] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0056] In order to solve the above problems, the present disclosure provides a method, apparatus, device and storage medium for rapid evaluation of power consumption of large-scale chip post-simulation.

[0057] The following describes the method, apparatus, device, and storage medium for rapid evaluation of post-simulation power consumption of large-scale chips provided by the embodiments of the present disclosure in conjunction with the accompanying drawings.

[0058] Figure 1 This is a flow chart of a method for rapid evaluation of power consumption of a large-scale chip post-simulation provided by an embodiment of the present disclosure.

[0059] like Figure 1 As shown in FIG, a method for rapidly evaluating power consumption of a large-scale chip after simulation may include:

[0060] S101, collecting multiple types of data of large-scale chips, and dividing the large-scale chips into multiple functional sub-modules and top-level modules based on their functions and physical layout;

[0061] S102, mapping and configuring each functional submodule and the top-level module to ensure that the RTL hierarchy is consistent with the netlist hierarchy;

[0062] S103: Set the time point required for post-simulation according to the waveform file FSDB generated by the pre-simulation, compile the RTL, netlist files and verification environment of the top-level module and each functional sub-module to generate database files, and according to the SDF file, back-label the standard cells and the delay information of the connection between cells in the simulation circuit. Use the preset power consumption analysis and optimization tools to perform parallel simulation to obtain the waveform files required for post-simulation power consumption evaluation.

[0063] In some embodiments, Figure 1 The method may further include:

[0064] Obtaining the generated post-simulation waveform file from a preset power analysis and optimization tool, and collecting standard cell library information, wherein the standard cell library information includes static power consumption parameters and dynamic power consumption related parameters of each standard cell;

[0065] Perform power consumption evaluation on the post-simulation waveform files generated by the preset power consumption analysis and optimization tools.

[0066] In some embodiments, during power consumption evaluation, Figure 1 The method may further include:

[0067] Collect power consumption data under different design parameters and operating conditions as sample data, where the sample data includes information on module power consumption, signal flip rate, voltage change, and temperature fluctuation dimensions;

[0068] The sample data is trained using a preset artificial intelligence model to learn the relationship between chip power consumption and various design parameters and working conditions. Based on the deviation between the actual evaluation results and the model prediction values, the model parameters and structure are continuously adjusted to correct the artificial intelligence model and obtain a power consumption prediction model.

[0069] In some embodiments, collecting multi-category data from large-scale chips may include:

[0070] Collect RTL code, obtain gate-level netlist, organize SDF files, and organize pre-simulation test cases.

[0071] In some embodiments, each functional submodule has independent functions and logical architecture, and the top-level module is used to coordinate the communication and data interaction between the functional submodules;

[0072] The method further includes: for each independent functional submodule, extracting a partial netlist corresponding to the functional submodule from the synthesized overall gate-level netlist using a design tool;

[0073] A top-level module netlist is extracted from the overall gate-level netlist, wherein the top-level module netlist includes connection logic between various functional sub-modules and top-level control signal processing logic.

[0074] In some embodiments, the mapping configuration of each functional submodule and the top-level module to ensure that the RTL hierarchy is consistent with the netlist hierarchy may include:

[0075] According to the preset mapping rules, mapping configuration operations are performed on each functional submodule and top-level module to ensure that the instance name and module name in the RTL code match the instance name and module name in the corresponding gate-level netlist;

[0076] The mapping rate and signal activity characteristics are monitored in real time. When the mapping rate is lower than the preset threshold, the mapping rules are adjusted to re-match the logic units in the RTL with the units in the netlist.

[0077] In some embodiments, the waveform file FSDB generated by the pre-simulation is used to set the time point required for the post-simulation, and the RTL, netlist files, and verification environment of the top-level module and each functional sub-module are compiled to generate a database file. According to the SDF file, the standard cells and the delay information of the connection between cells are back-labeled in the simulation circuit, and a preset power analysis and optimization tool is used to perform parallel simulation to obtain the waveform file required for the post-simulation power consumption evaluation, including:

[0078] Analyze signal changes based on the FSDB files of each functional submodule and top-level module generated in the pre-simulation phase. Set time points that require attention in the post-simulation phase based on power consumption assessment requirements.

[0079] Compile the RTL files, netlist files, verification environment files, and back-annotated delay information SDF files of the top-level module and each functional sub-module using the preset power analysis and optimization tools;

[0080] According to the corresponding SDF file and the compiled database file, the compiled database file is back-annotated with the delay information of the standard cells and the connection between cells in the simulation tool;

[0081] Using the preset power consumption analysis and optimization tools, extract the waveform range that needs to be dumped for the top-level module and each functional sub-module according to the preset post-simulation time point, and start parallel simulation at the same time;

[0082] The preset power analysis and optimization tool simulates the behavior of the circuit based on the back-annotated delay information and generates the waveform files required for post-simulation power consumption evaluation.

[0083] Figure 2 This is a flow chart of another large-scale chip post-simulation power consumption rapid evaluation method provided by the embodiment of the present disclosure, combined with Figure 2 ,right Figure 1 The rapid evaluation method of post-simulation power consumption of medium and large-scale chips is further described.

[0084] It can be seen that the rapid evaluation method of large-scale chip post-simulation power consumption can specifically include multi-dimensional data fusion input, innovative architecture design, adaptive mapping configuration, parallel simulation, power consumption evaluation, and feedback and iteration process.

[0085] In terms of multi-dimensional data fusion input, comprehensive data collection for large-scale chips can be used as a foundation for subsequent power consumption assessment. The RTL code describes the chip's logical functions in detail. The gate-level netlist converts the RTL code into specific logic gate connections, reflecting the chip's underlying circuit structure. The standard delay format (SDF) file records the delay information for each logic gate in the gate-level netlist. Pre-simulation test cases ensure the logical correctness of the chip's functions and provide data for post-simulation power consumption assessment.

[0086] In terms of innovative architecture design, large-scale chips can be divided into multiple functional sub-modules and a top-level module based on their functions and physical layout. Each sub-module has independent functions and logical architecture, and the top-level module is responsible for coordinating communication and data exchange between the sub-modules.

[0087] Obtain the netlists and RTL of the top layer and submodules in a large-scale chip to be post-simulated, wherein the netlists corresponding to the top layer and each submodule are independent and different from each other; for each submodule, perform pre-simulation on the submodule using the simulation parameters corresponding to the submodule to obtain the corresponding simulation results and a fast signal database (FSDB) file, and perform pre-simulation on the top layer using the simulation parameters corresponding to the top layer to obtain the simulation results and FSDB file of the top layer.

[0088] In terms of adaptive mapping configuration, the mapping configuration and instance name and module name matching of each sub-module and top-level module can be performed according to conventional methods to ensure that the RTL hierarchy is consistent with the netlist hierarchy. By adjusting the mapping rules, the logic units in the RTL can be correctly corresponded to the units in the netlist. The PowerReplay tool monitors the mapping rate and signal activity characteristics in real time during the mapping process. When the mapping rate is lower than the set threshold (such as 90%) or the signal activity is abnormal, the mapping mechanism is readjusted until the mapping rate reaches more than 95% to ensure the accuracy and completeness of the mapping. Among them, the PowerReplay tool is the above-mentioned preset power consumption analysis and optimization tool.

[0089] In terms of parallel simulation, the time point required for post-simulation can be set according to the waveform file FSDB generated by the previous simulation, and the RTL, netlist files and verification environment of the top-level module and each sub-module can be compiled to generate database files. According to the SDF file, the standard units and the delay information of the connection between units are back-labeled in the simulation circuit, and the PowerReplay tool is used for simulation to obtain the waveform files required for post-simulation power consumption evaluation.

[0090] For power consumption evaluation, the PowerReplay tool can be used to quickly generate post-simulation waveform files. This tool also collects standard cell library information, including static power consumption parameters (such as leakage current) and dynamic power consumption parameters (such as capacitance load) for each standard cell. The EDA tool PTPX is used to perform power consumption evaluation on the post-simulation waveform files quickly generated by the PowerReplay tool.

[0091] During the power consumption evaluation process, a large amount of power consumption data under different design parameters and operating conditions can be continuously collected as samples. This data includes information on multiple dimensions, such as module power consumption, signal toggle rate, voltage variation, and temperature fluctuation. The collected sample data is stored in a dedicated database, providing rich data support for subsequent model training.

[0092] The AI model is then trained on the sample data to establish a power consumption prediction model. This model learns the complex relationship between chip power consumption and various design parameters and operating conditions. Based on the deviation between the actual evaluation results and the model's predicted values, the model's parameters and structure are continuously adjusted to revise the power consumption model.

[0093] After completing the power consumption assessment, conduct an in-depth analysis of the power consumption distribution and assessment results. Use visualization tools to display the power consumption of each chip module and identify high-power consumption areas and power bottlenecks. For example, analyze which modules have a disproportionately high power consumption share and which signal flips cause significant power consumption.

[0094] In terms of design feedback and iteration, analysis results can be fed back to the chip design stage, providing the design team with targeted optimization suggestions. These suggestions include logic optimization and clock tree adjustments. After the design team modifies the chip design based on the feedback, they conduct another PowerReplay evaluation, forming an iterative optimization process. Through continuous iteration, the chip's power consumption is gradually reduced until the design goals are met.

[0095] To more clearly illustrate the implementation details of the large-scale chip post-simulation power consumption rapid assessment method, the following will be described in conjunction with detailed steps and specific technical means. Through these specific implementations, the significant advantages of the present invention in improving the speed and accuracy of chip power consumption assessment are more intuitively demonstrated.

[0096] 1. Multidimensional data fusion input stage

[0097] Collect RTL code. Extract the complete RTL code from the chip design project's code repository. For a large-scale chip, its RTL code may consist of code files for multiple functional modules. Organize these code files into a specific project directory for subsequent processing.

[0098] Obtain a gate-level netlist. Use chip design tools to synthesize the organized RTL code to generate the corresponding gate-level netlist. Use the Synopsys Design Compiler tool to set the target process library and synthesis constraints (such as area and timing). Run the synthesis command to obtain a gate-level netlist file saved in a standard format.

[0099] Organize the SDF file. The SDF file details the delay information of each logic gate in the gate-level netlist under different operating conditions (such as different voltages and temperatures). Store the SDF file in association with the corresponding gate-level netlist file to facilitate subsequent simulation calls.

[0100] Organize pre-simulation test cases. Collect and organize the test cases used in the pre-simulation phase of the chip. These test cases have already verified the correctness of the chip's logical functions and are typically written in a specific testbench language (such as SystemVerilog). Categorize and organize the test cases, marking those related to different functional modules for targeted use in post-simulation power consumption assessment.

[0101] 2. Innovative architecture design stage

[0102] Module division: Large-scale chips are divided into multiple functional submodules and a top-level module based on their functions and physical layout. Each submodule has independent functions and logical architecture, and the top-level module is responsible for coordinating communication and data exchange between the submodules.

[0103] Independent Submodule Netlist Acquisition: For each independent functional submodule, design tools are used to extract the corresponding partial netlist from the synthesized overall gate-level netlist. For example, for the ALU submodule, by setting specific module boundary conditions, a netlist processing tool is used to extract a netlist file containing only the ALU logic gates and their connections, and save it with a separate file name.

[0104] Top-level netlist acquisition: The netlist of the top-level module is also extracted from the overall gate-level netlist. The netlist mainly contains the connection logic between each sub-module and the processing logic of the top-level control signal.

[0105] Pre-verification simulation preparation: Prepare independent simulation environments and verification cases for the top layer and each sub-module in the large-scale chip. For each sub-module, use the corresponding test case to pre-simulate the sub-module to ensure the correctness of the logical function, and obtain the corresponding simulation results and fast signal database FSDB file.

[0106] 3. Adaptive mapping configuration phase

[0107] Initial mapping configuration: Follow the normal mapping rules to perform mapping configuration on each submodule and top-level module. During the configuration process, ensure that the instance and module names in the RTL code accurately match the instance and module names in the corresponding gate-level netlist. For example, if a module named "alu_module" is defined in the RTL code, the corresponding module name in the gate-level netlist must also be "alu module."

[0108] Mapping Monitoring and Adjustment: During the mapping process, the mapping rate and signal activity characteristics are monitored in real time. For example, if the mapping rate falls below a set threshold of 90%, the mapping mechanism can be re-adjusted to re-match logic cells in the RTL with those in the netlist. During the remapping process, the tool records detailed information about logic cells that failed to map, allowing designers to analyze them later. When the mapping rate reaches above 95%, the mapping operation is considered successful and the mapping configuration is saved.

[0109] 4. Parallel simulation stage

[0110] Post-simulation time point setting: Open the FSDB files for each submodule and top-level module generated during the pre-simulation phase, analyze the signal changes within them, and set time points of interest for post-simulation based on power consumption assessment requirements. For example, for a data processing module, identify time periods where data transfer and computational operations frequently occur in the FSDB file. Mark key time points within these time periods as post-simulation time points.

[0111] Compile and generate database files: Use the Powerreply tool to compile the RTL files, netlist files, verification environment files, and back-annotated delay information SDF files for the top-level module and each submodule. During the compilation process, set the correct compilation options to ensure that the database files can be generated for simulation.

[0112] Back-annotate delay information: Based on the corresponding SDF file and compiled database file, back-annotate the delay information of standard cells and inter-cell connections in the compiled database file in the simulation tool.

[0113] Parallel simulation execution: Using the PowerReplay tool, extract the waveform ranges that require dumping at pre-set post-simulation time points for the top-level module and each submodule, and initiate parallel simulations simultaneously. During simulation, PowerReplay accurately simulates circuit behavior based on back-annotated delay information and generates the waveform files required for post-simulation power consumption evaluation.

[0114] 5. Power consumption evaluation stage

[0115] Waveform file acquisition: After the simulation is complete, quickly generate post-simulation waveform files from the PowerReplay tool's output directory. These waveform files record the signal changes of each module during the simulation, including information such as signal high and low level changes and signal flip-flop timing.

[0116] Standard cell library information collection: Extract static power consumption parameters (such as leakage current consumption) and dynamic power consumption parameters (such as capacitance load) of each standard cell from the standard cell library file. These parameters are organized into a structured data format for subsequent use in power estimation tools.

[0117] Power consumption evaluation: You can use the EDA tool PTPX to perform power consumption evaluation, using the post-simulation waveform file generated by the PowerReplay tool and the collected standard cell library information as input. In PTPX, set the correct power consumption evaluation algorithm and parameters (such as considering different power consumption models and setting the ambient temperature), run the evaluation command, and generate power consumption evaluation reports for each module and the entire chip. The report details the static power consumption, dynamic power consumption, and total power consumption of each module.

[0118] 6. Sample data collection stage

[0119] Collect module power consumption data: During the power consumption evaluation process, extract the power consumption data of each module from the power consumption evaluation report generated by the PTPX tool. For example, record the power consumption values of the ALU module under different operating conditions (such as different input data types and different clock frequencies).

[0120] Collect signal toggle rate data: Analyze the waveform files generated by the PowerReplay tool and count the toggle rates of key signals in each module. For example, for a data transmission module, calculate the number of toggle times per unit time for both the data signal and the control signal.

[0121] Collect voltage variation data: This data is collected from the chip's power management module under different operating conditions. For example, the voltage values of each power domain are recorded when the chip is operating at full load and light load.

[0122] 7. Model training and correction stage

[0123] AI model selection and construction: Select an AI model suitable for power consumption prediction, such as a neural network model, and build a neural network structure consisting of an input layer, multiple hidden layers, and an output layer. The number of nodes in the input layer is determined based on the dimensions of the collected sample data. For example, if data is collected on four dimensions (module power consumption, signal toggle rate, voltage variation, and temperature fluctuation), the number of input layer nodes is set to 4. The number of nodes and layers in the hidden layer is determined through experimental debugging to achieve optimal model performance. The number of nodes in the output layer is set to 1 to output the predicted power consumption value.

[0124] Model training: The preprocessed sample data is divided into a training set and a test set, typically with a ratio of 70%-30% or 80%-20%. The constructed AI model is trained using the training set data. By continuously adjusting the model parameters (such as weights and biases), the error between the model's predicted value and the actual power consumption value in the training set data is minimized. During the training process, an appropriate loss function such as the mean squared error loss function and the optimized stochastic gradient descent algorithm are used for optimization.

[0125] Model Correction: Use the test data to validate the trained model and calculate the deviation between the model's predicted values and the actual power consumption values in the test data. Based on the deviation, adjust the model structure (such as increasing or decreasing the number of hidden layer nodes) or retrain the model until the model's prediction accuracy meets the requirements. Save the corrected model for subsequent power consumption prediction and evaluation.

[0126] 8. Evaluation results analysis phase

[0127] Power consumption distribution visualization: Use professional visualization tools such as Python's Matplotlib library to visualize the data in the power consumption assessment report generated by the PTPX tool.

[0128] Identify high-power consumption areas: By analyzing the visualized power distribution results, identify areas within the chip where excessive power consumption occurs. For example, if a specific functional module within the chip (such as a high-speed data cache module) is found to consume significantly more power than other modules, it is marked as a high-power consumption area.

[0129] Power consumption bottleneck analysis: Further analyze signal activity within high-power consumption areas to identify key signals that contribute to significant power consumption. For example, by analyzing signals in a high-speed data cache module, we found that the frequent toggling of cache data read and write signals was the primary cause of the module's excessive power consumption, identifying this signal as a power consumption bottleneck.

[0130] 9. Design feedback and iteration phase

[0131] Feedback and Recommendation Generation: Based on the conclusions of the evaluation analysis, targeted optimization recommendations are generated for the chip design team. For identified high-power consumption areas (high-speed data cache modules) and power consumption bottlenecks (cache data read and write signals), the design team is advised to adopt a more efficient cache architecture design to reduce the frequency of data read and write operations; or to optimize the signal driver circuit to reduce power consumption during signal flipping.

[0132] Design modification: Based on feedback, the design team modified the chip's RTL code. For example, they modified the RTL code of the high-speed data cache module, optimized the data cache algorithm, and reduced unnecessary data read and write operations.

[0133] Re-evaluation: After completing the design modification, the modified chip design is again evaluated using the proposed large-scale post-simulation power consumption rapid evaluation method. The aforementioned stages, from multi-dimensional data fusion input to evaluation result analysis, are repeated to verify the effectiveness of the design optimization. If the chip power consumption still does not meet the design target, design feedback and iteration are continued until the design requirements are met.

[0134] The large-scale chip post-simulation power consumption rapid evaluation method provided by the present disclosure can significantly shorten the time for the chip to obtain the power consumption waveform by splitting the original overall simulation. This allows the correctness of the timing function to be fully verified before the chip is tape-out, and generates an accurate FSDB file for subsequent process analysis, reducing the margin reserved in the design, thereby reducing chip costs and significantly shortening the power consumption evaluation time.

[0135] Through multi-dimensional data fusion and adaptive mapping strategies, chip power consumption can be accurately assessed in the early stages of RTL design, identifying potential power consumption issues in advance. Designers can optimize chip power consumption early in the design process, avoiding large-scale modifications later in the design process, reducing design costs and time, and improving early assessment capabilities.

[0136] The AI-based power consumption model correction mechanism fully considers the complex relationship between chip power consumption and various factors, enabling more accurate prediction and evaluation of power consumption. By continuously revising the model, the evaluation results are closer to the actual chip power consumption, providing a more reliable basis for design optimization.

[0137] A feedback-driven, iterative optimization process ensures continuous improvement in chip design. Through continuous evaluation and feedback, the design team can specifically address power consumption issues within the chip, effectively reducing power consumption and improving chip performance and competitiveness.

[0138] It can be seen that the large-scale chip post-simulation power consumption rapid evaluation method provided by the present invention significantly shortens the evaluation time of large-scale integrated circuit post-simulation power consumption through a unique parallel mapping and simulation architecture, fully utilizes the advantages of the PowerReply tool, can quickly and accurately obtain power consumption waveforms, and speed up power consumption evaluation.

[0139] and Figure 1 Corresponding to the method for rapid evaluation of power consumption of medium and large-scale chip after simulation, the present disclosure also provides a device for rapid evaluation of power consumption of large-scale chip after simulation, such as Figure 3 As shown, the device may specifically include:

[0140] The collection module 301 is used to collect various types of data of a large-scale chip and divide the large-scale chip into multiple functional sub-modules and a top-level module according to its function and physical layout;

[0141] A mapping configuration module 302 is used to map and configure each functional submodule and the top-level module to ensure that the RTL hierarchy is consistent with the netlist hierarchy;

[0142] The simulation module 303 is used to set the time point required for the post-simulation according to the waveform file FSDB generated by the pre-simulation, compile the RTL, netlist files and verification environment of the top-level module and each functional sub-module to generate a database file, and according to the SDF file, back-label the standard cells and the delay information of the connection between cells in the simulation circuit, use the preset power consumption analysis and optimization tools to perform parallel simulation, and obtain the waveform file required for the post-simulation power consumption evaluation.

[0143] In some embodiments, the large-scale chip post-simulation power consumption rapid evaluation device can also be used to obtain a generated post-simulation waveform file from a preset power consumption analysis and optimization tool, and collect standard cell library information, wherein the standard cell library information includes static power consumption parameters and dynamic power consumption related parameters of each standard cell;

[0144] Perform power consumption evaluation on the post-simulation waveform files generated by the preset power consumption analysis and optimization tools.

[0145] In some embodiments, during power consumption evaluation, the large-scale chip post-simulation power consumption rapid evaluation device may further collect power consumption data under different design parameters and working conditions as sample data, wherein the sample data includes information on module power consumption, signal flip rate, voltage change, and temperature fluctuation dimensions;

[0146] The sample data is trained using a preset artificial intelligence model to learn the relationship between chip power consumption and various design parameters and working conditions. Based on the deviation between the actual evaluation results and the model prediction values, the model parameters and structure are continuously adjusted to correct the artificial intelligence model and obtain a power consumption prediction model.

[0147] In some embodiments, the aforementioned collection of multiple types of data from large-scale chips includes:

[0148] Collect RTL code, obtain gate-level netlist, organize SDF files, and organize pre-simulation test cases.

[0149] In some embodiments, each functional submodule has independent functions and logical architecture, and the top-level module is used to coordinate the communication and data interaction between the functional submodules;

[0150] For each independent functional sub-module, a design tool is used to extract the partial netlist of the corresponding functional sub-module from the synthesized overall gate-level netlist;

[0151] A top-level module netlist is extracted from the overall gate-level netlist, wherein the top-level module netlist includes connection logic between various functional sub-modules and top-level control signal processing logic.

[0152] In some embodiments, the mapping configuration of each functional submodule and the top-level module to ensure that the RTL hierarchy is consistent with the netlist hierarchy includes:

[0153] According to the preset mapping rules, mapping configuration operations are performed on each functional submodule and top-level module to ensure that the instance name and module name in the RTL code match the instance name and module name in the corresponding gate-level netlist;

[0154] The mapping rate and signal activity characteristics are monitored in real time. When the mapping rate is lower than the preset threshold, the mapping rules are adjusted to re-match the logic units in the RTL with the units in the netlist.

[0155] In some embodiments, the waveform file FSDB generated by the pre-simulation is used to set the time point required for the post-simulation, and the RTL, netlist files, and verification environment of the top-level module and each functional sub-module are compiled to generate a database file. According to the SDF file, the standard cells and the delay information of the connection between cells are back-labeled in the simulation circuit, and a preset power analysis and optimization tool is used to perform parallel simulation to obtain the waveform file required for the post-simulation power consumption evaluation, including:

[0156] Analyze signal changes based on the FSDB files of each functional submodule and top-level module generated in the pre-simulation phase. Set time points that require attention in the post-simulation phase based on power consumption assessment requirements.

[0157] Compile the RTL files, netlist files, verification environment files, and back-annotated delay information SDF files of the top-level module and each functional sub-module using the preset power analysis and optimization tools;

[0158] According to the corresponding SDF file and the compiled database file, perform the back-annotation operation on the compiled database file in the simulation tool to determine the delay information of the standard cells and the connection between cells;

[0159] Using the preset power consumption analysis and optimization tools, extract the waveform range that needs to be dumped for the top-level module and each functional sub-module according to the preset post-simulation time point, and start parallel simulation at the same time;

[0160] The preset power analysis and optimization tool simulates the circuit behavior based on the back-annotated delay information and generates the waveform files required for post-simulation power consumption evaluation.

[0161] Combine Figure 4As shown, the embodiment of the present disclosure also provides a large-scale chip post-simulation power consumption rapid evaluation device 400, including a processor 404 and a memory 401. Optionally, the system may also include a communication interface 402 and a bus 403. The processor 404, the communication interface 402, and the memory 401 can communicate with each other through the bus 403. The communication interface 402 can be used for information transmission. The processor 404 can call the logic instructions in the memory 401 to execute the large-scale chip post-simulation power consumption rapid evaluation method of the above embodiment.

[0162] In addition, the logic instructions in the memory 401 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0163] Memory 401, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present disclosure. Processor 404 executes the program instructions / modules stored in memory 401 to perform functional applications and data processing, thereby implementing the large-scale chip post-simulation power consumption rapid evaluation method described in the above-mentioned embodiments.

[0164] The memory 401 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Furthermore, the memory 401 may include high-speed random access memory and non-volatile memory.

[0165] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute a method for rapidly evaluating power consumption of a large-scale chip post-simulation.

[0166] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0167] The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of the embodiments of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program code, or a transient storage medium.

[0168] The above description and accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Unless expressly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replaced with portions and features of other embodiments. As used in the description of the embodiments, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms as well. Similarly, the term "and / or" as used in this application means including any and all possible combinations of one or more of the associated listed items. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. In the absence of further limitations, the phrase "comprising a..." does not preclude the presence of other identical elements in the process, method, or device comprising the elements. In this document, each embodiment may focus on the differences from other embodiments, and similar parts between the embodiments can be referenced to each other. For methods, products, etc. disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referenced to the description of the method section.

[0169] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units can be merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, the functional units in the embodiments of the present disclosure may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0170] The flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the systems, methods and computer program products according to the embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of the code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in an order different from that disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A method for rapid evaluation of power consumption of large-scale chip post-simulation, characterized in that: The method comprises: Collect multiple types of data on large-scale chips and divide them into multiple functional sub-modules and top-level modules based on their functions and physical layout; Map and configure each functional submodule and top-level module to ensure that the RTL hierarchy is consistent with the netlist hierarchy; According to the waveform file FSDB generated by the pre-simulation, the time point required for the post-simulation is set, and the RTL, netlist files and verification environment of the top-level module and each functional sub-module are compiled to generate database files. According to the SDF file, the standard units and the delay information of the connection between units are back-labeled in the simulation circuit, and the preset power consumption analysis and optimization tools are used for parallel simulation to obtain the waveform files required for the post-simulation power consumption evaluation.

2. The method according to claim 1, characterized in that The method further comprises: Obtaining a generated post-simulation waveform file from a preset power consumption analysis and optimization tool, and collecting standard cell library information, wherein the standard cell library information includes static power consumption parameters and dynamic power consumption related parameters of each standard cell; Perform power consumption evaluation on the post-simulation waveform files generated by the preset power consumption analysis and optimization tools.

3. The method according to claim 2, characterized in that During the power consumption evaluation, the method further includes: Collecting power consumption data under different design parameters and working conditions as sample data, wherein the sample data includes information on module power consumption, signal flip rate, voltage change, and temperature fluctuation dimensions; The sample data is trained using a preset artificial intelligence model to learn the relationship between chip power consumption and various design parameters and working conditions. Based on the deviation between the actual evaluation results and the model prediction values, the model parameters and structure are continuously adjusted to correct the artificial intelligence model and obtain a power consumption prediction model.

4. The method according to claim 1, wherein The multi-category data collected from large-scale chips includes: Collect RTL code, obtain gate-level netlist, organize SDF files, and organize pre-simulation test cases.

5. The method according to claim 1, wherein Each functional submodule has independent functions and logical architecture, and the top-level module is used to coordinate the communication and data interaction between the functional submodules; The method further comprises: for each independent functional submodule, extracting a partial netlist corresponding to the functional submodule from the synthesized overall gate-level netlist using a design tool; A netlist of a top-level module is extracted from the overall gate-level netlist, wherein the netlist of the top-level module includes connection logic between various functional sub-modules and processing logic of top-level control signals.

6. The method according to claim 1, characterized in that The mapping configuration of each functional submodule and the top-level module to ensure that the RTL hierarchy is consistent with the netlist hierarchy includes: According to the preset mapping rules, mapping configuration operations are performed on each functional submodule and top-level module to ensure that the instance name and module name in the RTL code match the instance name and module name in the corresponding gate-level netlist; The mapping rate and signal activity characteristics are monitored in real time. When the mapping rate is lower than the preset threshold, the mapping rules are adjusted to re-match the logic units in the RTL with the units in the netlist.

7. The method according to claim 1, characterized in that The waveform file FSDB generated by the pre-simulation is used to set the time point required for the post-simulation, and the RTL, netlist files, and verification environment of the top-level module and each functional sub-module are compiled to generate database files. According to the SDF file, the standard cells and the delay information of the connection between cells are back-labeled in the simulation circuit. The preset power analysis and optimization tools are used for parallel simulation to obtain the waveform files required for the post-simulation power consumption evaluation, including: Analyze signal changes based on the FSDB files of each functional submodule and top-level module generated in the pre-simulation phase. Set time points that require attention in the post-simulation phase based on power consumption assessment requirements. Compile the RTL files, netlist files, verification environment files, and back-annotated delay information SDF files of the top-level module and each functional sub-module using the preset power analysis and optimization tools; According to the corresponding SDF file and the compiled database file, perform the back-annotation operation on the compiled database file in the simulation tool to determine the delay information of the standard cells and the connection between cells; Using the preset power consumption analysis and optimization tools, extract the waveform range that needs to be dumped for the top-level module and each functional sub-module according to the preset post-simulation time point, and start parallel simulation at the same time; The preset power analysis and optimization tool simulates the circuit behavior based on the back-annotated delay information and generates the waveform files required for post-simulation power consumption evaluation.

8. A large-scale chip post-simulation power consumption rapid evaluation device, characterized in that: The device comprises: The collection module is used to collect multiple types of data from large-scale chips and divide the large-scale chips into multiple functional sub-modules and top-level modules based on their functions and physical layout; The mapping configuration module is used to map and configure each functional submodule and the top-level module to ensure that the RTL hierarchy is consistent with the netlist hierarchy; The simulation module is used to set the time point required for post-simulation based on the waveform file FSDB generated by the pre-simulation, compile the RTL, netlist files and verification environment of the top-level module and each functional sub-module to generate database files, and according to the SDF file, back-label the standard units and the delay information of the connection between units in the simulation circuit, use the preset power consumption analysis and optimization tools to perform parallel simulation, and obtain the waveform files required for post-simulation power consumption evaluation.

9. An electronic device, characterized in that: include: at least one processor; and a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 7.

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