SOI silicon wafer preparation method and SOI silicon wafer
By forming a thin silicon nitride mask layer on the back of the SOI silicon wafer as a selective thermal oxidation mask, the problem of insufficient adsorption force between the back of the SOI silicon wafer and the electrostatic suction cup is solved, and the chip manufacturing process is smoothly carried out and damage reduction is achieved.
Patent Information
- Application Number
- CN202410124416.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-29
- Publication Date
- 2025-08-12
AI Technical Summary
In the preparation of existing SOI silicon wafers, the adsorption force between the back and the electrostatic suction cup is insufficient or the static discharge is unclear, resulting in slippers or fragments, affecting the smooth progress of the chip manufacturing process.
A thin layer of silicon nitride mask layer is formed on the back of the SOI silicon wafer as a selective thermal oxidation mask to avoid the formation of a thermal oxidation film layer on the back and front side at the same time, promote charge release, and match the stress of the silicon nitride layer with the stress of the silicon oxide layer to improve the overall flatness.
Effectively avoid slip or debris problems, ensure the smooth progress of the chip manufacturing process, reduce back damage, and improve the flow capacity of SOI silicon wafers in electrostatic suction cup equipment.
Smart Images
Figure CN120473433A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor process technology, and in particular to a method for preparing an SOI silicon wafer and an SOI silicon wafer prepared by the method. Background Art
[0002] SOI can eliminate or reduce the body effect, parasitic effect and small size effect in bulk silicon, and has broad application prospects in the fields of ultra-large-scale integrated circuits, optoelectronics, etc.
[0003] In the hydrogen injection intelligent stripping technology that combines hydrogen ion implantation and bonding, which is commonly used in the preparation of existing SOI materials, an oxide film serving as a buried oxide layer is generally formed on the front side of a single-crystal silicon wafer serving as the substrate silicon layer of the SOI through a thermal oxidation process. However, this method inevitably forms an oxide film on the back side of the single-crystal silicon wafer at the same time. Since the required buried oxide layer is relatively thick (about 2000nm), the oxide film formed on the back side of the single-crystal silicon wafer also has the same thickness. When the SOI silicon wafer is placed on the electrostatic chuck of the semiconductor device, it will cause insufficient adsorption force between the back side of the SOI silicon wafer and the electrostatic chuck or unclean static discharge. In this way, when the SOI silicon wafer is transferred between multiple devices with electrostatic chucks, slippage or fragmentation is likely to occur, which brings many difficulties to chip manufacturing and affects the smooth progress of the process. Summary of the Invention
[0004] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a method for preparing an SOI silicon wafer and an SOI silicon wafer.
[0005] To achieve the above object, the technical solution of the present invention is as follows:
[0006] The present invention provides a method for preparing an SOI silicon wafer, comprising:
[0007] providing a first silicon wafer as a substrate silicon layer;
[0008] forming a cushion layer of a first thickness on the first surface of the first silicon wafer;
[0009] forming a mask layer of a second thickness on the surface of the pad layer;
[0010] Using the mask layer as a mask, forming a first silicon oxide layer on a second surface of the first silicon wafer opposite to the first surface, for forming a buried oxide layer of a third thickness;
[0011] A top silicon layer is formed on a surface of the buried oxide layer facing away from the first silicon wafer.
[0012] Furthermore, a ratio of the first thickness to the second thickness is less than or equal to 0.1; and / or a ratio of the second thickness to the third thickness is less than or equal to 0.05.
[0013] Furthermore, the electrostatic discharge equivalent thickness of the mask layer is less than one tenth of that of the buried oxide layer; and / or the stress of the mask layer is equivalent to the stress of the buried oxide layer.
[0014] Furthermore, the pad layer and the mask layer are formed by a CVD process.
[0015] Furthermore, the pad layer includes a second silicon oxide layer.
[0016] Furthermore, the mask layer includes a silicon nitride layer.
[0017] Furthermore, the first thickness is 2-10 nm, and the second thickness is 100-120 nm.
[0018] Furthermore, the first silicon oxide layer is formed by a thermal oxidation process, and the mask layer serves as a mask during the thermal oxidation process to prevent water vapor from penetrating the mask layer, so that the first silicon oxide layer is formed only on the second surface.
[0019] Furthermore, forming a top silicon layer on a surface of the buried oxide layer facing away from the first silicon wafer specifically includes:
[0020] providing a second silicon wafer;
[0021] forming a third silicon oxide layer on the third surface of the second silicon wafer;
[0022] implanting hydrogen ions into the second silicon wafer from the third surface to form a hydrogen ion implantation layer in the second silicon wafer;
[0023] aligning the third silicon oxide layer with the first silicon oxide layer, bonding the second silicon wafer to the first silicon wafer, and forming the buried oxide layer between the second silicon wafer and the first silicon wafer;
[0024] Through the first heat treatment, the second silicon wafer is peeled off along the hydrogen ion implantation layer, and the top silicon layer formed by the remaining second silicon wafer is formed on the surface of the buried oxide layer away from the first silicon wafer.
[0025] The present invention also provides an SOI silicon wafer, which is prepared by the above-mentioned SOI silicon wafer preparation method.
[0026] As can be seen from the above technical solution, the present invention forms a mask layer on the back side (first surface) of the first silicon wafer serving as the substrate silicon layer as a mask for selective thermal oxidation to avoid the simultaneous formation of a thermal oxide film layer (first silicon oxide layer) on the back side and the front side of the first silicon wafer. This promotes the charge release process when in contact with the electrostatic chuck, thereby enabling the chip manufacturing process to proceed smoothly. Furthermore, by making the thickness of the silicon nitride mask layer, for example, much smaller than the thickness of the thermal oxide film layer (i.e., the buried oxide layer thickness) formed on the back side of a conventional SOI silicon wafer, the obstruction to the release of static charge can be greatly reduced, effectively avoiding the problem of slippage or fragmentation, thereby enabling smooth wafer flow in a device with an electrostatic chuck. Furthermore, by making the stress of the back silicon nitride and the front silicon oxide equivalent, the SOI silicon wafer can have a very high overall flatness. In addition, by utilizing the hard and wear-resistant characteristics of silicon nitride, the back side damage that occurs during chip manufacturing can be greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 The present invention is a flowchart of a method for preparing an SOI silicon wafer according to a preferred embodiment of the present invention.
[0028] Figure 2-Figure 7 A preferred embodiment of the present invention adopts Figure 1 Schematic diagram of the process steps for preparing SOI silicon wafers. DETAILED DESCRIPTION
[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.
[0030] In the hydrogen-implanted smart stripping technology (Smart-Cut) commonly used in the preparation of existing SOI materials, a thick (about 2000nm) thermal oxide film is also formed on the back side of the single-crystal silicon wafer. This can cause insufficient adsorption between the back side of the SOI silicon wafer and the electrostatic chuck or unclean static discharge, which can easily cause the SOI silicon wafer to slip or break during transfer, thereby causing many difficulties in chip manufacturing and affecting the smooth progress of the process. The present invention provides a new SOI silicon wafer preparation method. By forming a mask layer on the back side of the SOI silicon wafer (the first surface of the first silicon wafer) to replace the thermal oxide film formed simultaneously on the back side and front side of the conventional SOI silicon wafer, the mask layer can be formed on the back side of the SOI silicon wafer (the first surface of the first silicon wafer) to promote the charge release process when in contact with the electrostatic chuck, thereby smoothly proceeding with the chip manufacturing process.
[0031] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.
[0032] refer to Figure 1 and Figure 2-Figure 7 The present invention provides a method for preparing an SOI silicon wafer, comprising the following steps:
[0033] Step S1: providing a first silicon wafer 10 as a substrate silicon layer 101 .
[0034] like Figure 2 As shown, a first silicon wafer 10 is first used as a substrate silicon layer 101 of the SOI silicon wafer to be prepared.
[0035] Step S2 : forming a pad layer 11 with a first thickness on the first surface of the first silicon wafer 10 .
[0036] like Figure 3 As shown, a 2-10 nm (first thickness) silicon oxide pad layer 11 is formed on a first surface (shown as the top surface, i.e., the backside of the first silicon wafer 10) of the first silicon wafer 10 by a CVD process. In this embodiment, a 5 nm thickness of silicon oxide is formed on the backside of the first silicon wafer 10 by a CVD process to form a second silicon oxide layer serving as the pad layer 11.
[0037] Step S3 : forming a mask layer 12 of a second thickness on the surface of the pad layer 11 facing away from the first silicon wafer 10 .
[0038] like Figure 3 As shown, a silicon nitride mask layer 12 having a thickness of 100 to 120 nm (second thickness) is formed on the surface of the pad layer 11 facing away from the first silicon wafer 10 (shown as the upper surface of the pad layer 11) by a CVD process. In this embodiment, a 100 nm silicon nitride layer is formed on the surface of the pad layer 11 by a CVD process to serve as the mask layer 12.
[0039] Step S4: Using the mask layer 12 as a mask, a first silicon oxide layer 13 is formed on the second surface of the first silicon wafer 10 opposite to the first surface, to form a buried oxide layer 30 of a third thickness (refer to FIG. Figure 6 ).
[0040] like Figure 4 As shown, a thermal oxidation film layer with a thickness of 1500 to 2300 nm is formed on a second surface of the first silicon wafer 10 opposite to the first surface (shown as the upper surface, i.e., the front surface of the first silicon wafer 10) through a thermal oxidation process, serving as the first silicon oxide layer 13. In this embodiment, a thermal oxidation film layer with a thickness of approximately 2000 nm is formed on the front surface of the first silicon wafer 10 through the thermal oxidation process, which is used to form a buried oxide layer 30 of a third thickness after subsequent bonding.
[0041] During the thermal oxidation process, the silicon nitride mask layer 12 is used as a mask, which can effectively prevent water vapor from penetrating the mask layer 12 and entering the back side of the first silicon wafer 10 to react with the Si of the first silicon wafer 10 to oxidize the first silicon wafer 10. Therefore, the first silicon oxide layer 13 can be formed only on the front side of the first silicon wafer 10.
[0042] Step S5 : forming a top silicon layer on the surface of the buried oxide layer 30 facing away from the first silicon wafer 10 .
[0043] like Figure 5 As shown, a second silicon wafer 20 is used to prepare the top silicon layer 201 of the required SOI silicon wafer (refer to Figure 7 ).
[0044] First, a certain thickness of silicon oxide is formed on the third surface (shown as the top surface; the third surface can be the front or back surface of the second silicon wafer 20) of the second silicon wafer 20 through CVD or thermal oxidation, serving as a third silicon oxide layer 21 for bonding. In this embodiment, the third silicon oxide layer 21 is formed on the front surface of the second silicon wafer 20 through CVD to a thickness of approximately 100 nm.
[0045] Then, hydrogen ions are implanted into the second silicon wafer 20 through the third surface of the second silicon wafer 20 (i.e., through the surface of the third silicon oxide layer 21), forming a hydrogen ion implantation layer 22 at a certain depth within the second silicon wafer 20. The implantation depth depends on the thickness of the single crystal Si thin film layer on the second silicon wafer 20 that needs to be left as the top silicon layer 201.
[0046] like Figure 6As shown, first and second silicon wafers 10, 20 are subjected to surface oxygen plasma activation and hydrophilic treatment. Then, the third silicon oxide layer 21 of the second silicon wafer 20 is aligned with the first silicon oxide layer 13 of the first silicon wafer 10, and the second silicon wafer 20 and the first silicon wafer 10 are bonded. This forms a buried oxide layer 30 comprising the first silicon oxide layer 13 and the third silicon oxide layer 21 between the second silicon wafer 20 and the first silicon wafer 10. The thickness (third thickness) of the buried oxide layer 30 is the sum of the thicknesses of the first silicon oxide layer 13 and the third silicon oxide layer 21, for example, 1600 to 2400 nm.
[0047] like Figure 7 As shown, the first silicon wafer 10 and the second silicon wafer 20 in the bonded state are then subjected to a first heat treatment at a treatment temperature of, for example, 550°C, so that the second silicon wafer 20 is peeled off along the hydrogen ion implantation layer 22, thereby forming a top silicon layer 201 formed by the portion of the second silicon wafer 20 remaining on the surface of the buried oxide layer 30 after peeling on the surface of the buried oxide layer 30 facing away from the first silicon wafer 10.
[0048] Finally, a second heat treatment is further performed to firmly bond the first silicon wafer 10 and the second silicon wafer 20, that is, the top silicon layer 201 is firmly bonded to the first silicon wafer 10. Thus, the SOI silicon wafer of the present invention is prepared.
[0049] In some embodiments, a ratio of the first thickness of the silicon oxide pad layer 11 to the second thickness of the silicon nitride mask layer 12 is less than or equal to 0.1.
[0050] In some embodiments, a ratio of the second thickness of the silicon nitride mask layer 12 to the third thickness of the buried oxide layer 30 is less than or equal to 0.05.
[0051] In some embodiments, the electrostatic discharge equivalent thickness of the silicon nitride mask layer 12 is less than one tenth of that of the buried oxide layer 30 .
[0052] In some embodiments, the stress of silicon nitride mask layer 12 is comparable to that of buried oxide layer 30, offsetting the stress of buried oxide layer 30 and resulting in high overall flatness of the SOI silicon wafer fabricated using the present invention. Furthermore, silicon nitride is hard and wear-resistant, significantly reducing backside damage during chip manufacturing.
[0053] It can be seen that in the SOI silicon wafer prepared by the method of the present invention, the thickness of the silicon nitride layer located on the back side of the SOI silicon wafer is only about 100 nm, which is 1 / 20 of the physical thickness of the silicon oxide (about 2000 nm) originally formed on the back side of the SOI silicon wafer according to the conventional process and 1 / 10 of the electrostatic discharge equivalent thickness (the dielectric constant of silicon nitride is ~8, and the dielectric constant of silicon oxide is ~4). Therefore, the obstacle to the release of static charge is greatly reduced, allowing the SOI silicon wafer prepared by the method of the present invention to be smoothly taped out in equipment equipped with an electrostatic chuck.
[0054] The SOI silicon wafer of the present invention is prepared using the above-mentioned SOI silicon wafer preparation method of the present invention. The prepared SOI silicon wafer structure includes a buried oxide layer 30 (a first silicon oxide layer 13 and a third silicon oxide layer 21) and a top silicon layer 201 (the portion remaining after the second silicon wafer 20 is peeled off) sequentially located on the front surface of the substrate silicon layer 101 (the first silicon wafer 10), and a pad layer 11 (a second silicon oxide layer) and a mask layer 12 (a silicon nitride layer) sequentially located on the back surface of the substrate silicon layer 101. Figure 7 shown.
[0055] In summary, the present invention forms a silicon nitride mask layer 12 on the back of the first silicon wafer 10 as the substrate silicon layer 101 as a mask for selective thermal oxidation to avoid the formation of a thermal oxide film layer on the back and front of the first silicon wafer 10 at the same time. When in contact with the electrostatic chuck, the charge release process can be promoted, thereby allowing the chip manufacturing process to proceed smoothly. Furthermore, by making the thickness of the silicon nitride mask layer 12 much smaller than the thickness of the thermal oxide film layer formed on the back of a conventional SOI silicon wafer (i.e., the thickness of the buried oxide layer 30), the obstruction to the release of static charge can be greatly reduced, effectively avoiding the problem of slip or fragmentation, thereby achieving smooth wafer flow in a device with an electrostatic chuck. Moreover, by making the stress of the back silicon nitride and the front silicon oxide equivalent, the SOI silicon wafer can have a very high overall flatness. In addition, by utilizing the hard and wear-resistant characteristics of silicon nitride, the back damage occurring during chip manufacturing can be greatly reduced.
[0056] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.
Claims
1. A method for preparing an SOI silicon wafer, characterized in that: include: providing a first silicon wafer as a substrate silicon layer; forming a cushion layer of a first thickness on the first surface of the first silicon wafer; forming a mask layer of a second thickness on the surface of the pad layer; Using the mask layer as a mask, forming a first silicon oxide layer on a second surface of the first silicon wafer opposite to the first surface, for forming a buried oxide layer of a third thickness; A top silicon layer is formed on a surface of the buried oxide layer facing away from the first silicon wafer.
2. The method for preparing an SOI silicon wafer according to claim 1, wherein: The ratio of the first thickness to the second thickness is less than or equal to 0.1; and / or the ratio of the second thickness to the third thickness is less than or equal to 0.
05.
3. The method for preparing an SOI silicon wafer according to claim 1, wherein: The electrostatic discharge equivalent thickness of the mask layer is less than one tenth of the buried oxide layer; and / or the stress of the mask layer is equivalent to the stress of the buried oxide layer.
4. The method for preparing an SOI silicon wafer according to claim 1, wherein: The pad layer and the mask layer are formed by a CVD process.
5. The method for preparing an SOI silicon wafer according to claim 1, wherein: The pad layer includes a second silicon oxide layer.
6. The method for preparing an SOI silicon wafer according to claim 1, wherein: The mask layer includes a silicon nitride layer.
7. The method for preparing an SOI silicon wafer according to claim 1, wherein: The first thickness is 2-10 nm, and the second thickness is 100-120 nm.
8. The method for preparing an SOI silicon wafer according to claim 1, wherein: The first silicon oxide layer is formed by a thermal oxidation process, and the mask layer serves as a mask during the thermal oxidation process, so that the first silicon oxide layer is formed only on the second surface.
9. The method for preparing an SOI silicon wafer according to claim 1, wherein: The forming of a top silicon layer on a surface of the buried oxide layer facing away from the first silicon wafer specifically includes: providing a second silicon wafer; forming a third silicon oxide layer on the third surface of the second silicon wafer; implanting hydrogen ions into the second silicon wafer from the third surface to form a hydrogen ion implantation layer in the second silicon wafer; aligning the third silicon oxide layer with the first silicon oxide layer, bonding the second silicon wafer to the first silicon wafer, and forming the buried oxide layer between the second silicon wafer and the first silicon wafer; Through the first heat treatment, the second silicon wafer is peeled off along the hydrogen ion implantation layer, and the top silicon layer formed by the remaining second silicon wafer is formed on the surface of the buried oxide layer away from the first silicon wafer.
10. An SOI silicon wafer, characterized in that: The SOI silicon wafer is prepared by the SOI silicon wafer preparation method according to any one of claims 1 to 9.