Power module and equipment

Abstract

The invention discloses a power module and equipment. The power module comprises a substrate and a plurality of power chips arranged on the substrate, and the plurality of power chips respectively form a rectifier pile circuit, a power factor correction circuit and an inverter circuit; the rectifier pile circuit and the power factor correction circuit are arranged at one end of the substrate, and the inverter circuit is arranged at the other end of the substrate. The inverter circuit in the power module is separated from other circuits, so that the inductance of the power module is lower, and the heat dissipation performance is better.

Description

Technical Field

[0001] The present application relates to the field of electronic power technology, and in particular to a power module and equipment. Background Art

[0002] Existing power modules typically utilize three separate modules: a bridge rectifier module, a PFC module, and an IPM module, electrically connected by peripheral circuitry. This results in a large number of components and a complex layout. This technology leads to significant electromagnetic interference, a large control board area, numerous exposed connection points in the peripheral circuitry, and wide spacing between units, resulting in relatively high overall costs. This severely impacts overall system performance and significantly complicates hardware design. Summary of the Invention

[0003] The embodiment of the present application provides a power module, comprising: a substrate,

[0004] A plurality of power chips are arranged on the substrate, and the plurality of power chips respectively constitute a rectifier stack circuit, a power factor correction circuit and an inverter circuit; the rectifier stack circuit and the power factor correction circuit are arranged at one end of the substrate, and the inverter circuit is arranged at the other end of the substrate.

[0005] Optionally, the rectifier stack circuit and the power factor correction circuit are arranged in parallel.

[0006] Optionally, the inverter circuit includes an upper bridge arm and a lower bridge arm, and the upper bridge arm and the lower bridge arm are arranged in parallel.

[0007] Optionally, the rectifier stack circuit and the power factor correction circuit are parallel to the long side direction of the power module.

[0008] Optionally, the upper bridge arm and the lower bridge arm are parallel to the long side direction of the power module.

[0009] Optionally, the upper bridge arm includes three upper bridge single-phase bridge arms, and the three upper bridge single-phase bridge arms are arranged along the long side direction of the power module.

[0010] Optionally, the lower bridge arm includes three lower bridge single-phase bridge arms, and the three lower bridge single-phase bridge arms are arranged along the long side direction of the power module.

[0011] Optionally, the upper bridge single-phase bridge arm and the lower bridge single-phase bridge arm are electrically connected in a one-to-one correspondence.

[0012] Optionally, the upper bridge single-phase bridge arm and / or the lower bridge single-phase bridge arm include at least one insulated gate bipolar transistor chip and at least one fast recovery diode chip.

[0013] Optionally, the insulated gate bipolar transistor chips of the three upper bridge single-phase bridge arms and / or the three lower bridge single-phase bridge arms are arranged along the long side direction of the power module.

[0014] Optionally, the power module further includes an inverter input terminal and an inverter output terminal, and the inverter input terminal and inverter output terminal are respectively arranged on the two long sides of the power module, the inverter input terminal is arranged close to the upper bridge arm, and the inverter output terminal is arranged close to the lower bridge arm.

[0015] Optionally, the rectifier stack circuit includes a plurality of sub-rectifier stack circuits, and the plurality of sub-rectifier stack circuits are arranged along the long side direction of the power module.

[0016] Optionally, the sub-rectifier stack circuit includes an upper sub-rectifier stack circuit and a lower sub-rectifier stack circuit, and the upper sub-rectifier stack circuit and the lower sub-rectifier stack circuit are arranged parallel to the long side direction of the power module.

[0017] Optionally, each of the sub-rectifier stack circuits includes at least two rectifier diodes, and the upper sub-rectifier stack circuit and / or the lower sub-rectifier stack circuit includes at least one rectifier diode.

[0018] Optionally, the power factor correction circuit includes a plurality of sub-power factor correction circuits, and the plurality of sub-power factor correction circuits are arranged along the long side direction of the power module.

[0019] Optionally, the sub-power factor correction circuit includes two groups of power chip pairs connected in series, and the two groups of power chip pairs are arranged along the long side direction of the power module.

[0020] Optionally, the power chip pair includes at least one insulated gate bipolar transistor chip and at least one fast recovery diode chip, and the insulated gate bipolar transistor chip and the fast recovery diode chip are arranged along the short side direction of the power module.

[0021] Optionally, the power module further includes a heat dissipation substrate and an outer frame, the substrate is arranged on the heat dissipation substrate, the substrate is arranged in the outer frame, and the outer frame is connected to the heat dissipation substrate through a sealant.

[0022] Optionally, the outer frame is filled with insulating glue, and the insulating glue is used to fix the multiple power chips and the connecting wires between the power chips.

[0023] A device comprises a power module as described in any one of the above items.

[0024] In the present application, the power chips of the rectifier stack circuit, power factor correction circuit and inverter circuit in the power module are integrated on the same substrate, and the power chips of the rectifier stack circuit and the power factor correction circuit are arranged at one end of the substrate, while the power chip of the inverter circuit is arranged at the other end of the substrate. The inverter circuit in the power module is separated from other circuits, so that the inductance of the power module is lower and the heat dissipation performance is better.

[0025] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0027] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0028] Figure 1 is a circuit connection diagram of a power module provided in an exemplary embodiment of the present disclosure;

[0029] Figure 2 is a schematic diagram of a chip layout of a power module provided in an exemplary embodiment of the present disclosure;

[0030] Figure 3 A schematic diagram of a chip layout of a power module provided in an exemplary embodiment of the present disclosure Figure 1 .

[0031] Figure 4 A schematic diagram of a chip layout of a power module provided in an exemplary embodiment of the present disclosure Figure 2 .

[0032] Figure 5 Schematic diagram of a cross-sectional structure of a power module provided in an exemplary embodiment of the present disclosure.

[0033] Description of reference numerals:

[0034] 1. Substrate;

[0035] 2. Power chip; 21. Rectifier circuit; 22. Power factor correction circuit; 23. Inverter circuit;

[0036] 231, upper bridge arm; 232, lower bridge arm; 2311, 2312, 2313, upper bridge single-phase bridge arm; 2321, 2322, 2323, lower bridge single-phase bridge arm;

[0037] 211, 212, 213, sub-rectifier stack circuit; 2111, upper sub-rectifier stack circuit; 2112, lower sub-rectifier stack circuit;

[0038] 221, 222, 223, sub-power factor correction circuit; 2211, 2212, power chip pair;

[0039] 3. Heat dissipation substrate; 4. Outer frame; 5. Sealant; 6. Insulation glue; 7. Temperature measuring element; 8. Connecting bonding wires. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0041] In this application, a power module is provided which integrates a rectifier circuit 21, a power factor correction circuit 22 and an inverter circuit 23. The circuit connection relationship can be seen in FIG. Figure 1 After the AC input ports A, B, and C are connected to the AC power, the L1 inductor, L2 inductor, and L3 inductor can be connected to the circuit. T1, T2, T3, T4, T5, and T6 of the power factor correction circuit 22 can all be IGBT chips, D1, D2, D3, D4, D5, and D6 can be fast recovery diodes connected in reverse parallel with the IGBT chip, and the gate of the IGBT chip is connected to the drive circuit at the periphery. D7, D8, D9, D10, D11, and D12 can be fast recovery diodes of the rectifier stack circuit 21, and O can be the neutral point terminal of the power factor correction circuit 22. The first terminal of the C1 capacitor can be connected to the DC1+ terminal and the neutral point terminal of the Vienna PFC bus at the periphery ( Figure 1 Not shown), the second terminal of the C2 capacitor can be connected to the Vienna PFC bus terminal DC1- and the neutral point terminal ( Figure 1(Not shown). DC1+ and DC2+ can be connected peripherally, and DC2- can add corresponding detection circuits in the periphery, and finally connected to DC1-. U1, V1, and W1 are the IGBT chip of the upper bridge arm of the inverter circuit 23 and the fast recovery FRD chip connected in reverse parallel thereto. U2, V2, and W2 are the IGBT chip of the lower bridge arm of the inverter circuit 23 and the fast recovery FRD chip connected in reverse parallel thereto. The gates of these six IGBT chips can be connected to the drive circuit in the periphery. U, V, and W are the output terminals of the three-phase full bridge, connected to the load. The NTC thermistor has separate terminals NTC1 and NTC2, which can be connected in the peripheral circuit.

[0042] When the circuit is operating normally, switch T1 is on. The circuit stores the circuit's electrical energy in the L1 inductor through the L1 inductor, T1 switch, D2 diode, and neutral point. At this point, the energy stored in capacitors C1 and C2 powers the load. When switch T1 is off, the energy stored in the inductor charges capacitor C1 through the circuit formed by the L1 inductor, D7 diode, and C1 capacitor. The principle remains the same when the input voltage is reversed. When the three-phase full-bridge circuit is operating normally, DC1+ is connected to the positive bus after Vienna rectification, and DC2- is connected to the negative bus. The six bridge arms, U1, V1, W1, U2, V2, and W2, are used to convert DC power into controllable AC power. The NTC thermistor has separate lead terminals, and an external current sensing circuit is connected for voltage detection, providing temperature monitoring.

[0043] In a first aspect of the present application, a power module is provided, which may include: a substrate 1 and a plurality of power chips 2 arranged on the substrate, wherein the plurality of power chips respectively constitute a rectifier stack circuit 21, a power factor correction circuit 22 and an inverter circuit 23; the rectifier stack circuit 21 and the power factor correction circuit 22 are arranged at one end of the substrate 1, and the inverter circuit 23 is arranged at the other end of the substrate 1.

[0044] Specifically, see Figure 2 The substrate 1 can be rectangular, and the power chip 2 can be connected to form multiple circuits by connecting bonding wires, etc., wherein the power chip 2 constituting the rectifier stack circuit 21 and the power factor correction circuit 22 can be arranged at one end of the rectangular substrate 1, and the inverter circuit 23 can be arranged at the other end of the rectangular substrate 2.

[0045] In the present application, the power chips of the rectifier stack circuit, power factor correction circuit and inverter circuit in the power module are integrated on the same substrate, and the power chips of the rectifier stack circuit and the power factor correction circuit are arranged at one end of the substrate, while the power chip of the inverter circuit is arranged at the other end of the substrate. The inverter circuit in the power module is separated from other circuits, so that the inductance of the power module is lower and the heat dissipation performance is better.

[0046] As an optional implementation, see Figure 2 , the rectifier stack circuit 21 and the power factor correction circuit 22 are arranged in parallel. Specifically, the rectifier stack circuit 21 and the power factor correction circuit 22 arranged at one end of the substrate 1 can be arranged in parallel. The parallel arrangement can be the power chip constituting the rectifier stack circuit 21 and the power chip constituting the power factor correction circuit 22, and the two groups of power chips are arranged in parallel with each other. As an optional embodiment, see Figure 2 When the substrate 1 is rectangular, the rectifier stack 21 and the power factor correction circuit 22 are parallel to the long side direction X of the power module. By arranging the power chips of the rectifier stack 21 and the power factor correction circuit 22 in parallel, the power module layout can be made more compact, the bonding wires between the chips are more regular, and the welding process is simpler. In addition, such a layout also reduces the inductance of the power module and improves the electrical performance.

[0047] As an optional implementation, see Figure 3 The inverter circuit 23 may include an upper bridge arm 231 and a lower bridge arm 232, wherein the upper bridge arm 231 and the lower bridge arm 132 are arranged in parallel. The upper bridge arm 231 and the lower bridge arm 132 may be arranged in parallel by a power chipset constituting the upper bridge arm 231 and a power chipset constituting the lower bridge arm 132 being arranged in parallel. As an optional embodiment, see Figure 3 The upper bridge arm 231 and the lower bridge arm 232 are parallel to the long side direction X of the power module. Parallel to the long side direction X of the power module can mean that the upper bridge arm 231 and the lower bridge arm 232 are arranged parallel to this direction. In this chip layout, the upper bridge arm chip is placed on one side, and the lower bridge arm chip is placed on the other side, with both arranged in parallel. This adheres to the principle of reducing gate stray current and reduces the inductance of the power module.

[0048] As an optional implementation, see Figure 3, the upper bridge arm 231 may include three upper bridge single-phase bridge arms 2311, 2312, and 2313, and the three upper bridge single-phase bridge arms may be arranged along the long side direction X of the power module. As an optional embodiment, the lower bridge arm 232 may include three lower bridge single-phase bridge arms 2321, 2322, and 2323, and the three lower bridge single-phase bridge arms may be arranged along the long side direction X of the power module. Specifically, the power chip constituting the upper bridge arm 231 may be divided into three upper bridge single-phase bridge arms 2311, 2312, and 2313 according to the electrical connection relationship, wherein the three upper bridge single-phase bridge arms may be arranged in sequence along the long side direction X of the power module. The same power chip constituting the lower bridge arm 232 may be divided into three lower bridge single-phase bridge arms 2321, 2322, and 2323 according to the electrical connection relationship, wherein the three lower bridge single-phase bridge arms may also be arranged in sequence along the long side direction X of the power module.

[0049] As an optional implementation, the upper bridge single-phase bridge arm and the lower bridge single-phase bridge arm are electrically connected in a one-to-one correspondence. Figure 3 The three upper bridge single-phase bridge arms 2311, 2312, and 2313 can be arranged in parallel with the three lower bridge single-phase bridge arms 2321, 2322, and 2323. An upper bridge single-phase bridge arm and a lower bridge single-phase bridge arm are arranged in a one-to-one correspondence and can form an electrical connection.

[0050] As an optional embodiment, the upper bridge single-phase bridge arm and / or the lower bridge single-phase bridge arm include at least one insulated gate bipolar transistor chip and at least one fast recovery diode chip. As an optional embodiment, the three upper bridge single-phase bridge arms and / or the three lower bridge single-phase bridge arms of the insulated gate bipolar transistor chips are arranged along the long side of the power module.

[0051] See also Figure 3 The upper bridge single-phase bridge arm 2311 may include an insulated gate bipolar transistor chip (a power chip with a larger area in 2311) and a fast recovery diode chip (a power chip with a smaller area in 2311), and the lower bridge single-phase bridge arm 2321 may also be configured similarly to the above. Figure 3 Because the three upper bridge single-phase arms of the upper bridge arm 231 can be arranged sequentially along the long side direction X of the power module, the insulated gate bipolar transistor chips of these three upper bridge single-phase arms can also be arranged along the long side direction X of the power module. The chip layout in this solution can facilitate the symmetrical switching of heat sources in rotation, thereby ensuring thermal balance of the module.

[0052] As an optional embodiment, the power module further includes an inverter input terminal and an inverter output terminal, which are respectively arranged on the two long sides of the power module, the inverter input terminal is arranged close to the upper bridge arm, and the inverter output terminal is arranged close to the lower bridge arm. Figure 2 The inverter input terminal of the power module can be DC2+ and the inverter output terminal DC2- (or DC3-, DC4-), and the inverter input terminal and the inverter output terminal can be respectively arranged on the long sides of both sides of the power module, wherein the inverter input terminal DC2+ can be arranged close to the upper bridge arm 231, and the inverter output terminal DC2- (or DC3-, DC4-) can be arranged close to the lower bridge arm 232.

[0053] The following is a comparison of simulation data of the inverter circuit 23 in the laboratory under the existing power module layout and the layout of the present application. From the experimental data, it can be seen that under the power module chip layout of the present application, the parasitic inductance of each phase loop is significantly reduced.

[0054] name Existing power module layout This application layout U-phase loop parasitic inductance (nH) 45.5 36 V-phase loop parasitic inductance (nH) 70.8 34.22 W phase loop parasitic inductance (nH) 62.4 34.28

[0055] As an optional embodiment, the rectifier stack circuit includes sub-rectifier stack circuits, the number of the sub-rectifier stack circuits is at least three, and the at least three sub-rectifier stack circuits are arranged along the long side direction of the power module. Figure 4 The rectifier stack circuit 21 may include sub-rectifier stack circuits 211, 212, and 213, and these three sub-rectifier stack circuits may be arranged in sequence along the long side direction X of the power module.

[0056] As an optional implementation, see Figure 4 The sub-rectifier stack circuit 211 may include an upper sub-rectifier stack circuit 2111 and a lower sub-rectifier stack circuit 2112. The upper sub-rectifier stack circuit 2111 and the lower sub-rectifier stack circuit 2112 are arranged parallel to the short side direction Y of the power module. Figure 4 , that is, the upper sub-rectifier stack circuit 2111 and the lower sub-rectifier stack circuit 2112 are arranged up and down along the Y direction. When there are multiple sub-rectifier stack circuits, the multiple upper sub-rectifier stack circuits 2111 can be arranged along the long side direction X of the power module, and the multiple lower sub-rectifier stack circuits 2112 can be arranged parallel to the upper sub-rectifier stack circuit 2111 and along the long side direction of the power module. As an optional embodiment, each of the sub-rectifier stack circuits includes at least two rectifier diodes, and the upper sub-rectifier stack circuit and / or the lower sub-rectifier stack circuit includes at least one rectifier diode. Specifically, see Figure 4The upper rectifier stack circuit 2111 may include a rectifier diode, and the lower rectifier stack circuit 2112 may also include a rectifier diode. The upper and lower rectifier diodes are electrically connected via bonding wires. The rectifier stack circuits 212 and 213 may also be similar to 211 and have the same or similar layout. The rectifier stack circuit in this application has a small difference in the copper area occupied by the chip layout, which is conducive to balanced chip heat dissipation, thereby facilitating parallel current sharing of the chips.

[0057] The following is a comparison of simulation data of the rectifier stack circuit 21 in the laboratory under the existing power module layout and the layout of the present application. From the experimental data, it can be seen that under the power module chip layout of the present application, the parasitic inductance of each loop is significantly reduced.

[0058] name Existing power module layout This application layout Parasitic inductance of loop A (nH) 36.23 30.26 B loop parasitic inductance (nH) 33.42 30.19 C loop parasitic inductance (nH) 41.32 31.89

[0059] As an optional implementation manner, the power factor correction circuit includes a plurality of sub-power factor correction circuits, and the plurality of sub-power factor correction circuits are arranged along the long side direction of the power module.

[0060] Specifically, see Figure 4 The power chip constituting the power factor correction circuit 22 can be composed of multiple sub-power factor correction circuits 221, 222, and 223. The multiple sub-power factor correction circuits can be arranged in sequence along the long side direction of the power module, so that the power factor correction circuit 22 and the power chip of the rectifier stack circuit 21 are arranged in parallel with each other. As an optional embodiment, see Figure 4 The sub-power factor correction 221 may include two groups of power chip pairs 2211 and 2212 connected in series, and the two groups of power chip pairs may be arranged in sequence along the long side direction X of the power module.

[0061] As an optional embodiment, the power chip pair includes at least one insulated gate bipolar transistor chip and at least one fast recovery diode chip, and the insulated gate bipolar transistor chip and the fast recovery diode chip are arranged along the short side direction of the power module. Figure 4 The power chip pair 2211 may include at least one insulated gate bipolar transistor chip (the chip with the larger area shown in 2211) and at least one fast recovery diode chip (the chip with the smaller area shown in 2211). The insulated gate bipolar transistor chip and the fast recovery diode chip may be arranged vertically along the short side direction Y of the power module. The sub-power factor correction circuits 212 and 213 may also have the same or similar layout as 211. The above layout can reduce the copper plate area occupied and shorten the length of the connecting bonding wires, thereby reducing the overall inductance of the power module and improving the electrical performance of the power module.

[0062] As an optional embodiment, the power module further includes a heat dissipation substrate 3 and an outer frame 4, the substrate 1 is arranged on the heat dissipation substrate, the power chip 2 is arranged in the outer frame 4, and the outer frame 4 is connected to the heat dissipation substrate 3 through a sealant 5. Figure 5 The substrate 1 can be a ceramic copper-clad substrate, the heat dissipation substrate 3 can be a copper substrate, the substrate 1 can be arranged on the heat dissipation substrate, and multiple power chips 2 are arranged on the substrate 1, the outer frame 4 is fixedly connected to the heat dissipation substrate 3 by a sealant 5, and the middle hollow area of the outer frame is used to accommodate the substrate 1 and the power chip 2. The multiple power chips can also include a temperature measuring element 7, which is arranged at the end side edge of the substrate 1 to detect the temperature of the power module. The temperature control element can be an NTC thermistor.

[0063] As an optional embodiment, the outer frame 4 may also be filled with an insulating adhesive 6, which is used to fix the multiple power chips 2 and the bonding wires 8 between the power chips. Figure 5 After multiple power chips are set in the outer frame, there are still bonding wires 8 connecting the chips. After the chips are bonded according to the connection relationship, the inner side of the outer frame is filled with insulating glue 6, which can further fix the power chips and the connecting bonding wires to prevent the bonding wires and chips from falling off. In addition, filling with insulating glue 6 can also isolate the air from the power chips, thereby improving the anti-aging ability of the power chips.

[0064] Another aspect of the present application further provides a device, which includes a power module. The power module has the same or similar technical features as the power modules in the above embodiments.

[0065] In this application, the power chip, NTC thermistor, and ceramic copper-clad substrate can be connected via solder, typically using silicon-based chips and alumina DBC (direct ceramic copper bonding technology). The solder can be made of silver-copper solder paste, printed on the DBC using an SMT steel mesh, and then the chip is placed using a placement machine. The chip and ceramic copper-clad substrate are sintered in a vacuum reflow oven. In addition, the ceramic copper-clad substrate can use alumina AMB (active metal bonding technology) or silicon carbide AMB. The thickness of the copper and ceramic layers can also be adjusted to improve cycle life, thermal conductivity, and reliability. The solder and soldering procedure can be adjusted based on the actual chip plating. Chip selection can use ultra-fast recovery diodes or silicon carbide MOS tubes as needed. The ceramic copper-clad substrate is sintered in a vacuum reflow oven using solder to a copper substrate. The copper substrate needs to be plated with a nickel sulfamate layer with a thickness of 5μm. It has good corrosion resistance and can pass a 24-hour NaCl salt spray corrosion test. The solder should be a copper-containing solder sheet that matches the size of the DBC. The copper substrate can be replaced with an aluminum silicon carbide (SiCp / Al) substrate. SiCp / Al offers excellent mechanical and physical properties, such as low density, high stiffness, good conductivity, and a low thermal expansion coefficient. Compared to metal substrates, aluminum silicon carbide substrates are more compatible with Si materials. Metal wire bonding is used to create the circuit architecture between the chip and the ceramic copper-clad substrate. 5, 8, 12, 15, or 20 mil aluminum wire is typically used, with the size selected based on the product's specific structure and current requirements. Ultrasonic bonding is used to bond the metal wires, using high-frequency ultrasonic vibrations to create friction between the material surfaces. Suitable copper wire sizes can be used for these metal bonding wires, providing enhanced current handling and reliability. When the outer frame is installed, the plastic housing can be bonded to the heat sink substrate using sealant. Metal rings are used to reinforce the copper substrate and housing. The outer housing can be made of PBT + 30% GF, requiring excellent insulation, flame retardancy, high-temperature and high-humidity aging resistance, and structural strength to maintain normal operation of the power devices under operating conditions. After mounting, silicone gel is poured into the outer frame to prevent moisture from entering. The outer frame can be molded integrally with the pins. The pins are required to pass a 24-hour NaCl salt spray corrosion test and are tin-plated to ensure a stable solder connection to the driver board in practical applications. The pin bonding area is copper-coated aluminum, requiring a stable bond with the aluminum wire and passing vibration and temperature shock tests.

[0066] White epoxy thermosetting sealant can be used, as it offers high bonding strength, excellent insulation and chemical properties, and minimal shrinkage upon curing, making it suitable for mass production. Silicone gel can be mixed in a suitable ratio (usually close to 1:1), melted, and poured into the outer frame to a height sufficient to cover all internal components. Curing in a vacuum environment removes air bubbles, improving insulation, withstand voltage, and safety.

[0067] The plastic outer frame can be made of PPS, which offers superior flame retardancy, insulation, and high-temperature, high-humidity aging resistance. When copper is used for the metal bonding wires, the electrode bonding area can be bare copper. Silicone sealants, such as those used for sealants, offer enhanced impact resistance and improved fatigue strength of the cured product, extending module life.

[0068] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0069] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0070] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0071] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A power module, characterized in that: include: substrate, A plurality of power chips are arranged on the substrate, and the plurality of power chips respectively constitute a rectifier stack circuit, a power factor correction circuit and an inverter circuit; the rectifier stack circuit and the power factor correction circuit are arranged at one end of the substrate, and the inverter circuit is arranged at the other end of the substrate.

2. The power module according to claim 1, wherein: The rectifier stack circuit and the power factor correction circuit are arranged in parallel.

3. The power module according to claim 1, wherein: The inverter circuit includes an upper bridge arm and a lower bridge arm, and the upper bridge arm and the lower bridge arm are arranged in parallel.

4. The power module according to claim 2, wherein: The rectifier stack circuit and the power factor correction circuit are arranged parallel to the long side direction of the power module.

5. The power module according to claim 3, wherein: The upper bridge arm and the lower bridge arm are arranged parallel to the long side direction of the power module.

6. The power module according to claim 3, characterized in that: The upper bridge arm includes three upper bridge single-phase bridge arms, and the three upper bridge single-phase bridge arms are arranged along the long side direction of the power module.

7. The power module according to claim 6, characterized in that: The lower bridge arm includes three lower bridge single-phase bridge arms, and the three lower bridge single-phase bridge arms are arranged along the long side direction of the power module.

8. The power module according to claim 7, characterized in that: The upper bridge single-phase bridge arm and the lower bridge single-phase bridge arm are electrically connected in a one-to-one correspondence.

9. The power module according to claim 7, wherein: The upper bridge single-phase bridge arm and / or the lower bridge single-phase bridge arm include at least one insulated gate bipolar transistor chip and at least one fast recovery diode chip.

10. The power module according to claim 9, characterized in that: The insulated gate bipolar transistor chips of the three upper bridge single-phase bridge arms and / or the three lower bridge single-phase bridge arms are arranged along the long side direction of the power module.

11. The power module according to claim 3, wherein: The power module also includes an inverter input terminal and an inverter output terminal, which are respectively arranged on the two long sides of the power module. The inverter input terminal is arranged close to the upper bridge arm, and the inverter output terminal is arranged close to the lower bridge arm.

12. The power module according to claim 2, wherein: The rectifier stack circuit includes a plurality of sub-rectifier stack circuits, and the plurality of sub-rectifier stack circuits are arranged along the long side direction of the power module.

13. The power module according to claim 12, wherein: The sub-rectifier stack circuit includes an upper sub-rectifier stack circuit and a lower sub-rectifier stack circuit, and the upper sub-rectifier stack circuit and the lower sub-rectifier stack circuit are arranged parallel to the short side direction of the power module.

14. The power module according to claim 13, characterized in that: Each of the sub-rectifier stack circuits includes at least two rectifier diodes, and the upper sub-rectifier stack circuit and / or the lower sub-rectifier stack circuit includes at least one rectifier diode.

15. The power module according to claim 2, characterized in that: The power factor correction circuit includes a plurality of sub-power factor correction circuits, and the plurality of sub-power factor correction circuits are arranged along the long side direction of the power module.

16. The power module according to claim 15, characterized in that: The sub-power factor correction circuit includes two groups of power chip pairs connected in series, and the two groups of power chip pairs are arranged along the long side direction of the power module.

17. The power module according to claim 16, characterized in that: The power chip pair includes at least one insulated gate bipolar transistor chip and at least one fast recovery diode chip, and the insulated gate bipolar transistor chip and the fast recovery diode chip are arranged along the short side direction of the power module.

18. The power module according to claim 1, wherein: The power module further includes a heat dissipation substrate and an outer frame. The substrate is arranged on the heat dissipation substrate, the substrate is arranged in the outer frame, and the outer frame is connected to the heat dissipation substrate through a sealant.

19. The power module according to claim 18, characterized in that The outer frame is filled with insulating glue, and the insulating glue is used to fix the multiple power chips and the connecting bonding wires between the power chips.

20. A device, characterized in that The device comprises the power module according to any one of claims 1 to 19.

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