Adaptive zero-crossing detection circuit and converter

Abstract

The application discloses an adaptive zero-crossing detection circuit and a converter, and relates to the technical field of switching power supplies.The adaptive zero-crossing detection circuit comprises an adaptive threshold adjusting module, a zero-crossing comparison module and an adaptive logic implementation module; the zero-crossing comparison module is connected with the adaptive threshold adjusting module, the adaptive logic implementation module and the converter; the zero-crossing comparison module is used for comparing an output voltage of the converter with an inductor voltage to obtain an inductor current zero-crossing result and sending the inductor current zero-crossing result to the adaptive logic implementation module; the adaptive logic implementation module is used for generating a short pulse signal and sending the short pulse signal to the adaptive threshold adjusting module; the short pulse signal comprises a positive short pulse signal and a negative short pulse signal; the adaptive threshold adjusting module is used for adjusting a zero-crossing threshold of the zero-crossing comparison module according to the pulse width of the positive short pulse signal and the negative short pulse signal; and the zero-crossing comparison module is further used for comparing the zero-crossing threshold with the inductor voltage of the converter, so that adaptive zero-crossing detection is realized.

Description

Technical Field

[0001] The present application relates to the technical field of switching power supplies, and in particular to an adaptive zero-crossing detection circuit and a converter. Background Art

[0002] With the rapid development of power electronics technology, DC-DC converters, as core components for power conversion, have been widely used in fields such as renewable energy generation, electric vehicles, and portable electronic devices. The BOOST converter, due to its efficient voltage boost function, has become a key topology in scenarios such as photovoltaic inverters, battery management systems, and LED drivers. However, in the actual application of BOOST converters, especially under light load or no-load conditions, the inductor current may enter discontinuous conduction mode (DCM). If the turn-on and turn-off timing of the power transistor cannot be precisely controlled at this time, problems such as current reversal, increased switching losses, and increased electromagnetic interference (EMI) will occur, seriously limiting system efficiency and reliability.

[0003] Traditional zero-crossing detection technology primarily detects the zero-crossing point of the inductor current or voltage signal to determine the optimal turn-off moment for the switching device, thereby avoiding current reverse flow and reducing losses. However, zero-crossing comparators typically have offset and delay, making it impossible to accurately detect the point at which the inductor current crosses zero. Furthermore, there is a certain delay from the time the zero-crossing comparator detects that the inductor current has dropped to zero, triggering the freewheeling diode shutdown signal, to the time the freewheeling diode turns off. This delay can also cause an error between the inductor current and zero current when the freewheeling diode actually turns off, causing reverse current in the inductor and affecting the overall efficiency of the chip.

[0004] Traditional zero-crossing detection generally reduces errors by reducing the delay in the zero-crossing comparator and the transmission path, or artificially adding an offset factor to the comparator to cause the comparator to flip early. However, since it is impossible to accurately set the advance amount to offset the impact of the delay, traditional zero-crossing detection cannot solve the problem of zero-crossing error. Summary of the Invention

[0005] The main purpose of this application is to provide an adaptive zero-crossing detection circuit and converter, aiming to solve the technical problem that traditional zero-crossing detection cannot solve the zero-crossing point error.

[0006] To achieve the above object, the present application proposes an adaptive zero-crossing detection circuit, which is applied to a converter;

[0007] The adaptive zero-crossing detection circuit includes: an adaptive threshold adjustment module, a zero-crossing comparison module and an adaptive logic implementation module;

[0008] The zero-crossing comparison module is connected to the adaptive threshold adjustment module, the adaptive logic implementation module and the converter respectively;

[0009] The zero-crossing comparison module is used to compare the output voltage of the converter and the inductor voltage to obtain an inductor current zero-crossing result, and send the inductor current zero-crossing result to the adaptive logic implementation module; the inductor current zero-crossing result includes: an early zero-crossing signal and a delayed zero-crossing signal;

[0010] The adaptive logic implementation module is configured to generate a short pulse signal upon receiving the inductor current zero-crossing result and send the short pulse signal to the adaptive threshold adjustment module; the short pulse signal includes a positive short pulse signal and a negative short pulse signal;

[0011] The adaptive threshold adjustment module is used to adjust the zero-crossing threshold of the zero-crossing comparison module according to the pulse width of the positive short pulse signal and the negative short pulse signal;

[0012] The zero-crossing comparison module is further used to compare the zero-crossing threshold and the inductor voltage of the converter to achieve adaptive zero-crossing detection.

[0013] Optionally, the zero-crossing comparison module is further configured to send an early zero-crossing signal to the adaptive logic implementation module when the output voltage of the converter is less than the inductor voltage;

[0014] The zero-crossing comparison module is further configured to send a delayed zero-crossing signal to the adaptive logic implementation module when the output voltage of the converter is greater than the inductor voltage.

[0015] Optionally, the adaptive threshold adjustment module is further configured to charge an internal capacitor when the pulse width of the positive short pulse signal is greater than the pulse width of the negative short pulse signal, so as to adjust the zero-crossing threshold of the zero-crossing comparison module in a negative direction;

[0016] The adaptive threshold adjustment module is further configured to discharge the internal capacitor when the pulse width of the positive short pulse signal is smaller than the pulse width of the negative short pulse signal, so as to adjust the zero-crossing threshold of the zero-crossing comparison module in the positive direction.

[0017] Optionally, the adaptive threshold adjustment module includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor;

[0018] The source of the first NMOS transistor, the source of the third NMOS transistor, and the source of the fifth NMOS transistor are respectively grounded; the gate of the first NMOS transistor is respectively connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor, and the gate of the fifth NMOS transistor; the source of the second NMOS transistor is connected to the drain of the third NMOS transistor; the drain of the second NMOS transistor is respectively connected to the gate of the fourth NMOS transistor; the gate of the third NMOS transistor is connected to the negative pulse port of the adaptive logic implementation module; the drain of the fourth NMOS transistor is connected to the zero-crossing comparison module; and the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor.

[0019] Optionally, the adaptive threshold adjustment module further includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor;

[0020] The source of the first PMOS tube, the source of the second PMOS tube, and the source of the third PMOS tube are respectively connected to a power supply, the drain of the first PMOS tube is respectively connected to the gate of the first PMOS tube, the gate of the second PMOS tube, and the gate of the fourth PMOS tube, the drain of the second PMOS tube is connected to the drain of the first NMOS tube, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the gate of the third PMOS tube is connected to the positive pulse port of the adaptive logic implementation module, and the drain of the fourth PMOS tube is connected to the drain of the second NMOS tube.

[0021] Optionally, the adaptive threshold adjustment module further includes: a capacitor and a first current source;

[0022] A first end of the capacitor is respectively connected to the drain of the fourth PMOS transistor, the drain of the second NMOS transistor, and the gate of the fourth NMOS transistor, a second end of the capacitor is grounded, a positive electrode of the first current source is respectively connected to the gate of the first PMOS transistor, the gate of the second PMOS transistor, and the gate of the fourth PMOS transistor, and a negative electrode of the first current source is grounded.

[0023] Optionally, the zero-crossing comparison module includes: a first resistor, a second resistor, a third resistor and a fourth resistor;

[0024] The first end of the first resistor is connected to the voltage output end of the converter, the second end of the first resistor is connected to the first end of the third resistor, the second end of the third resistor is connected to the adaptive threshold adjustment module, the first end of the second resistor is connected to the first end of the inductor in the converter, and the second end of the second resistor is connected to the first end of the fourth resistor.

[0025] Optionally, the zero-crossing comparison module further includes: a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor;

[0026] The source of the sixth NMOS transistor, the source of the seventh NMOS transistor, the source of the eighth NMOS transistor, the source of the ninth NMOS transistor, and the source of the tenth NMOS transistor are respectively grounded; the gate of the sixth NMOS transistor is respectively connected to the drain of the sixth NMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor, and the gate of the tenth NMOS transistor; the drain of the ninth NMOS transistor is connected to the second end of the second resistor; and the drain of the tenth NMOS transistor is connected to the adaptive logic implementation module.

[0027] Optionally, the zero-crossing comparison module further includes: a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor and a second current source;

[0028] The gate of the fifth PMOS transistor is respectively connected to the drain of the fifth PMOS transistor, the gate of the sixth PMOS transistor, and the drain of the seventh NMOS transistor; the source of the fifth PMOS transistor is respectively connected to the adaptive threshold adjustment module and the second end of the third resistor; the source of the sixth PMOS transistor is connected to the second end of the fourth resistor; the drain of the sixth PMOS transistor is respectively connected to the gate of the seventh PMOS transistor and the drain of the eighth NMOS transistor; the source of the seventh PMOS transistor is respectively connected to the power supply and the positive electrode of the second current source; the drain of the seventh PMOS transistor is respectively connected to the drain of the tenth NMOS transistor and the adaptive logic implementation module; and the negative electrode of the second current source is connected to the drain of the sixth NMOS transistor.

[0029] In addition, to achieve the above-mentioned purpose, the present application also proposes a converter, which includes the adaptive zero-crossing detection circuit as described above.

[0030] One or more technical solutions proposed in this application have at least the following effects:

[0031] The present application discloses an adaptive zero-crossing detection circuit and a converter. The adaptive zero-crossing detection circuit is applied to a converter. The adaptive zero-crossing detection circuit includes: an adaptive threshold adjustment module, a zero-crossing comparison module, and an adaptive logic implementation module. The zero-crossing comparison module is respectively connected to the adaptive threshold adjustment module, the adaptive logic implementation module, and the converter. The zero-crossing comparison module is configured to compare the output voltage of the converter with the inductor voltage to obtain an inductor current zero-crossing result, and send the inductor current zero-crossing result to the adaptive logic implementation module. The inductor current zero-crossing result includes: an early zero-crossing signal and a delayed zero-crossing signal. The adaptive logic implementation module is configured to generate a short pulse signal upon receiving the inductor current zero-crossing result and send the short pulse signal to the adaptive threshold adjustment module. The short pulse signal includes a positive short pulse signal and a negative short pulse signal. The adaptive threshold adjustment module is configured to adjust the zero-crossing threshold of the zero-crossing comparison module according to the pulse widths of the positive short pulse signal and the negative short pulse signal. The zero-crossing comparison module is further configured to compare the zero-crossing threshold with the inductor voltage of the converter to implement adaptive zero-crossing detection. By adaptively adjusting the zero-crossing detection threshold, the system can ensure that the freewheeling tube is turned off near zero current and enter DCM mode. This can avoid the problem of early or delayed zero crossing caused by the architecture's own errors and PVT process problems, thereby reducing additional energy consumption, improving conversion efficiency under light load and reducing quiescent current under no-load. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 This is a schematic structural diagram of a first embodiment of an adaptive zero-crossing detection circuit proposed in an embodiment of the present application;

[0034] Figure 2 A circuit schematic diagram of a first embodiment of an adaptive zero-crossing detection circuit proposed in an embodiment of the present application;

[0035] Figure 3 This is the circuit schematic diagram of the BOOST converter;

[0036] Figure 4 This is the waveform diagram of the adaptive zero-crossing detection circuit when it is actually working;

[0037] Figure 5 Circuit schematic for the adaptive logic implementation module.

[0038] Description of Figure Numbers:

[0039]

[0040] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0041] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not intended to limit the present application.

[0042] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0043] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0044] In addition, the descriptions of "first", "second", etc. in this application are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0045] The main solution of the embodiment of the present application is: the adaptive zero-crossing detection circuit includes a zero-crossing comparator, an adaptive logic implementation circuit, and an adaptive threshold control circuit, wherein the zero-crossing comparator is used to compare the output voltage and the voltage at the inductor node LX, and output a control signal VTR to the adaptive logic implementation circuit to generate a corresponding short pulse signal to control the charging and discharging of the adaptive threshold control circuit, thereby adaptively adjusting the threshold of zero current detection, ensuring that the zero-crossing point is near zero current, and realizing adaptive zero-crossing detection.

[0046] The present application provides a solution, and discloses an adaptive zero-crossing detection circuit and a converter. The adaptive zero-crossing detection circuit is applied to the converter; the adaptive zero-crossing detection circuit comprises: an adaptive threshold adjustment module 1, a zero-crossing comparison module 2, and an adaptive logic implementation module 3; the zero-crossing comparison module 2 is connected to the adaptive threshold adjustment module 1, the adaptive logic implementation module 3, and the converter respectively; the zero-crossing comparison module 2 is used to compare the output voltage of the converter with the inductor voltage to obtain the inductor current zero-crossing result, and send the inductor current zero-crossing result to the adaptive logic implementation module 3; The inductor current zero-crossing result includes: an early zero-crossing signal and a delayed zero-crossing signal; the adaptive logic implementation module 3 is used to generate a short pulse signal when receiving the inductor current zero-crossing result and send the short pulse signal to the adaptive threshold adjustment module 1; the short pulse signal includes a positive short pulse signal and a negative short pulse signal; the adaptive threshold adjustment module 1 is used to adjust the zero-crossing threshold of the zero-crossing comparison module 2 according to the pulse width of the positive short pulse signal and the negative short pulse signal; the zero-crossing comparison module 2 is also used to compare the zero-crossing threshold with the inductor voltage of the converter to achieve adaptive zero-crossing detection. By adaptively adjusting the threshold of zero-crossing detection, it is ensured that the system turns off the freewheeling tube near zero current and enters the DCM mode, which can avoid the problem of early or delayed zero-crossing caused by the architecture's own errors and PVT process problems, thereby reducing additional energy consumption, improving conversion efficiency under light load, and reducing quiescent current under no-load.

[0047] Based on this, an embodiment of the present application provides an adaptive zero-crossing detection circuit.

[0048] refer to Figure 1 , Figure 1 This is a structural diagram of the first embodiment of the adaptive zero-crossing detection circuit proposed in the embodiments of the present application.

[0049] Considering that traditional zero-crossing detection generally reduces the error by reducing the delay of the zero-crossing comparator and the transmission path, or artificially adding an offset factor to the comparator to make the comparator flip in advance, but it is impossible to accurately set the advance amount to offset the influence of the delay, so traditional zero-crossing detection cannot solve the problem of zero-crossing error. Figure 1 As shown, the adaptive zero-crossing detection circuit of this embodiment is applied to a converter;

[0050] The adaptive zero-crossing detection circuit comprises: an adaptive threshold adjustment module 1, a zero-crossing comparison module 2 and an adaptive logic implementation module 3;

[0051] The zero-crossing comparison module 2 is connected to the adaptive threshold adjustment module 1, the adaptive logic implementation module 3 and the converter respectively;

[0052] The zero-crossing comparison module 2 is used to compare the output voltage of the converter and the inductor voltage to obtain the inductor current zero-crossing result, and send the inductor current zero-crossing result to the adaptive logic implementation module 3; the inductor current zero-crossing result includes: an early zero-crossing signal and a delayed zero-crossing signal;

[0053] The adaptive logic implementation module 3 is configured to generate a short pulse signal upon receiving the inductor current zero-crossing result and send the short pulse signal to the adaptive threshold adjustment module 1; the short pulse signal includes a positive short pulse signal and a negative short pulse signal;

[0054] The adaptive threshold adjustment module 1 is used to adjust the zero-crossing threshold of the zero-crossing comparison module 2 according to the pulse width of the positive short pulse signal and the negative short pulse signal;

[0055] The zero-crossing comparison module 2 is further configured to compare the zero-crossing threshold with the inductor voltage of the converter, thereby achieving adaptive zero-crossing detection.

[0056] It should be noted that the converter is a BOOST converter, a type of direct current (DC-DC) converter. It can boost an input DC voltage to a higher output DC voltage. In the field of power electronics, it is widely used in applications requiring voltage boosting. For example, in some battery-powered devices, when the battery voltage drops to a certain level, a BOOST converter is needed to boost the voltage to a suitable level to drive the circuit. The zero-crossing comparison module 2 can adopt a common-gate input structure or can be customized based on actual conditions, without limitation in this embodiment. The zero-crossing comparison module 2 in this embodiment is a zero-crossing comparator.

[0057] It should be noted that if Figure 2 and Figure 5 As shown, Figure 2 This is a circuit schematic diagram of the first embodiment of the adaptive zero-crossing detection circuit proposed in the embodiment of the present application. Figure 5 This is the circuit schematic of the adaptive logic implementation module. The three input signals of adaptive logic implementation module 3 are VTR, NG, and NDS. VTR is the output signal of the zero-crossing comparator (zero-crossing comparison module 2), NG is the reverse voltage of the freewheeling P-type transistor drive signal, and NDS is the drive signal for the power N-type transistor. Adaptive logic implementation module 3 is used to generate short pulse signals NPW (negative pulse width) and PPW (positive pulse width), corresponding to the negative short pulse signal and positive short pulse signal in this embodiment, to control the adaptive threshold adjustment circuit and generate a true ZCD signal (zero current detection signal) to shut down the freewheeling transistor. Figure 4The following waveforms illustrate the actual operation of the adaptive zero-crossing detection circuit, split into two scenarios: premature zero-crossing and delayed zero-crossing. When the system undergoes premature zero-crossing, that is, while the inductor current is still positive, the ZCD triggers and turns off the freewheeling diode. This causes the inductor current to flow from the inductor to the LX node, forcing the voltage at the LX node to Vout + VF (VF is the forward voltage drop of the MOS diode body, approximately 0.7V). This causes the body diode to conduct forward, and current flows to the output terminal. Therefore, the VTR signal rises high and then falls back, forming a short pulse. The falling edge of VTR causes NPW to drop to 0. Since T1 = Delay1 + T2, and Delay2 = T2 + T3, the time at which VTR drops to 0 determines the pulse width of NPW and PPW. By properly setting the lengths of Delay1 and Delay2, the pulse width of PPW can be made longer than that of NPW in the case of premature zero-crossing. When the system delays zero crossing, that is, when the inductor current is already negative, the ZCD is triggered and the freewheeling tube is turned off. The negative current of the inductor is freewheeling through the NMOS body diode, and the LX voltage drops from the high level (Vout) during normal freewheeling to -VF in an instant. Therefore, VTR will remain high until the charging tube conduction signal becomes high to reset it. In this case, Delay2=T2, T3=0.

[0058] It should be noted that the main structure of the adaptive threshold adjustment module 1 is a capacitor charging and discharging circuit. When PPW is high, the current on the MP4 branch charges the capacitor C. When NPW is high, the current on the MN2 branch discharges the capacitor C. Thus, the VGS (gate-source voltage) of the MN2 tube is changed by charging and discharging to control the current of the MN4 branch. The value of this current will adjust the zero-crossing threshold. Figure 2 As shown, the addition of the MN9 branch causes the system to cross zero prematurely during the initial phase of operation. Consequently, the adaptive logic implementation module 3 outputs the corresponding NPW and PPW pulse widths. Properly configured, the PPW pulse width is longer than the NPW pulse width, causing the current to charge capacitor C. This causes the voltage at point D to continuously rise, and the current in the MN5 branch to rise accordingly, increasing the current through R1 and R3. This in turn adjusts the zero-crossing threshold toward zero current. After a certain period, the zero-crossing threshold is adjusted to near zero current and fluctuates around it. If the zero-crossing threshold is adjusted to a negative value during a certain period (Delay2 = T2 and T3 = 0), the current discharges capacitor C, causing the zero-crossing threshold to adjust toward the positive direction. Thus, this circuit controls the offset of the zero-crossing comparator by charging and discharging capacitor C, thereby adjusting the zero-crossing threshold to ensure that the zero-crossing point is near zero current, thus achieving adaptive zero-crossing detection.

[0059] In a specific implementation, the zero-crossing comparison module 2 is used to compare the output voltage of the converter and the inductor voltage to obtain the inductor current zero-crossing result, and send the inductor current zero-crossing result to the adaptive logic implementation module 3; the inductor current zero-crossing result includes: an early zero-crossing signal and a delayed zero-crossing signal; the adaptive logic implementation module 3 is used to generate a short pulse signal when receiving the inductor current zero-crossing result and send the short pulse signal to the adaptive threshold adjustment module 1; the short pulse signal includes a positive short pulse signal and a negative short pulse signal; the adaptive threshold adjustment module 1 is used to adjust the zero-crossing threshold of the zero-crossing comparison module 2 according to the pulse width of the positive short pulse signal and the negative short pulse signal; the zero-crossing comparison module 2 is also used to compare the zero-crossing threshold and the inductor voltage of the converter to realize adaptive zero-crossing detection, thereby avoiding additional energy consumption caused by the actual zero-crossing point being advanced or delayed, and improving the conversion efficiency of the converter in the light-load DCM working mode.

[0060] Furthermore, the zero-crossing comparison module 2 of this embodiment is further configured to send an early zero-crossing signal to the adaptive logic implementation module 3 when the output voltage of the converter is less than the inductor voltage;

[0061] The zero-crossing comparison module 2 is further configured to send a delayed zero-crossing signal to the adaptive logic implementation module 3 when the output voltage of the converter is greater than the inductor voltage.

[0062] It can be understood that the early zero-crossing signal and the delayed zero-crossing signal represent two situations: early zero-crossing and delayed zero-crossing.

[0063] It should be noted that if Figure 3 As shown, Figure 3 The schematic diagram of the BOOST converter is shown in Figure 1. The inductor voltage in the converter is the voltage VLX at the junction LX between the freewheeling diode drain and the inductor. The converter's output voltage is VOUT. When VLX is less than VOUT, the comparator flips, indicating that the inductor current has crossed zero. An additional MN9 branch is added to the circuit, adding an offset to cause the comparator to flip early when the inductor current is still positive. The amount of advance can be expressed as: , where RON_P is the on-resistance of the freewheeling tube, such as Figure 2 As shown, R2=R1, R3=R4.

[0064] In a specific implementation, the zero-crossing comparison module 2 is further used to send an early zero-crossing signal to the adaptive logic implementation module 3 when the output voltage of the converter is less than the inductor voltage; the zero-crossing comparison module 2 is further used to send a delayed zero-crossing signal to the adaptive logic implementation module 3 when the output voltage of the converter is greater than the inductor voltage, thereby determining the inductor zero-crossing result.

[0065] Furthermore, the adaptive threshold adjustment module 1 of this embodiment is further configured to charge the internal capacitor C when the pulse width of the positive short pulse signal is greater than the pulse width of the negative short pulse signal, so as to adjust the zero-crossing threshold of the zero-crossing comparison module 2 in a negative direction;

[0066] The adaptive threshold adjustment module 1 is further configured to discharge the internal capacitor C when the pulse width of the positive short pulse signal is smaller than the pulse width of the negative short pulse signal, so as to adjust the zero-crossing threshold of the zero-crossing comparison module 2 in the positive direction.

[0067] It should be noted that the pulse width of the positive short pulse signal is PPW, and the pulse width of the negative short pulse signal is NPW.

[0068] In a specific implementation, the adaptive threshold adjustment module 1 is also used to charge the internal capacitor C when the pulse width of the positive short pulse signal is greater than the pulse width of the negative short pulse signal, so that the zero-crossing threshold of the zero-crossing comparison module 2 is adjusted in the negative direction; the adaptive threshold adjustment module 1 is also used to discharge the internal capacitor C when the pulse width of the positive short pulse signal is less than the pulse width of the negative short pulse signal, so that the zero-crossing threshold of the zero-crossing comparison module 2 is adjusted in the positive direction. By charging and discharging the capacitor C to control the offset (offset) of the zero-crossing comparator, and then adjusting the zero-crossing threshold, it can be ensured that the zero-crossing point is near zero current, thereby realizing adaptive zero-crossing detection.

[0069] Based on the second embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those in the second embodiment can be referred to the above introduction and will not be described in detail later. Figure 2 , Figure 2 This is a circuit schematic diagram of the first embodiment of the adaptive zero-crossing detection circuit proposed in the embodiments of the present application.

[0070] like Figure 2 As shown, the adaptive threshold adjustment module 1 of this embodiment includes: a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5;

[0071] The source of the first NMOS transistor MN1, the source of the third NMOS transistor MN3, and the source of the fifth NMOS transistor MN5 are respectively grounded; the gate of the first NMOS transistor MN1 is respectively connected to the drain of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2, and the gate of the fifth NMOS transistor MN5; the source of the second NMOS transistor MN2 is respectively connected to the drain of the third NMOS transistor MN3; the drain of the second NMOS transistor MN2 is respectively connected to the gate of the fourth NMOS transistor MN4; the gate of the third NMOS transistor MN3 is connected to the negative pulse port of the adaptive logic implementation module 3; the drain of the fourth NMOS transistor MN4 is connected to the zero-crossing comparison module 2; and the source of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5.

[0072] It should be noted that the NMOS tube is an N-type metal oxide semiconductor field effect transistor.

[0073] Furthermore, the adaptive threshold adjustment module 1 further includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3 and a fourth PMOS transistor MP4;

[0074] The source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2, and the source of the third PMOS transistor MP3 are respectively connected to a power supply, the drain of the first PMOS transistor MP1 is respectively connected to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the gate of the fourth PMOS transistor MP4, the drain of the second PMOS transistor MP2 is connected to the drain of the first NMOS transistor MN1, the drain of the third PMOS transistor MP3 is connected to the source of the fourth PMOS transistor MP4, the gate of the third PMOS transistor MP3 is connected to the positive pulse port of the adaptive logic implementation module 3, and the drain of the fourth PMOS transistor MP4 is connected to the drain of the second NMOS transistor MN2.

[0075] It should be noted that the PMOS tube is a P-type metal oxide semiconductor field effect transistor.

[0076] Furthermore, the adaptive threshold adjustment module 1 further includes: a capacitor C and a first current source I1;

[0077] A first end of the capacitor C is respectively connected to the drain of the fourth PMOS transistor MP4, the drain of the second NMOS transistor MN2, and the gate of the fourth NMOS transistor MN4. A second end of the capacitor C is grounded. A positive electrode of the first current source I1 is respectively connected to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the gate of the fourth PMOS transistor MP4. A negative electrode of the first current source I1 is grounded.

[0078] It should be noted that the current of the first current source I1 can be set according to actual conditions and is not limited in this embodiment.

[0079] Furthermore, the zero-crossing comparison module 2 includes: a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4;

[0080] The first end of the first resistor R1 is connected to the voltage output end of the converter, the second end of the first resistor R1 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is connected to the adaptive threshold adjustment module 1, the first end of the second resistor R2 is connected to the first end of the inductor in the converter, and the second end of the second resistor R2 is connected to the first end of the fourth resistor R4.

[0081] It should be noted that the first resistor R1 and the second resistor R2 have the same resistance value, and the third resistor R3 and the fourth resistor R4 have the same resistance value.

[0082] Furthermore, the zero-crossing comparison module 2 further includes: a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9 and a tenth NMOS transistor MN10;

[0083] The source of the sixth NMOS transistor MN6, the source of the seventh NMOS transistor MN7, the source of the eighth NMOS transistor MN8, the source of the ninth NMOS transistor MN9, and the source of the tenth NMOS transistor MN10 are respectively grounded; the gate of the sixth NMOS transistor MN6 is respectively connected to the drain of the sixth NMOS transistor MN6, the gate of the seventh NMOS transistor MN7, the gate of the eighth NMOS transistor MN8, the gate of the ninth NMOS transistor MN9, and the gate of the tenth NMOS transistor MN10; the drain of the ninth NMOS transistor MN9 is connected to the second end of the second resistor R2; and the drain of the tenth NMOS transistor MN10 is connected to the adaptive logic implementation module 3.

[0084] Furthermore, the zero-crossing comparison module 2 further includes: a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7 and a second current source I2;

[0085] The gate of the fifth PMOS transistor MP5 is respectively connected to the drain of the fifth PMOS transistor MP5, the gate of the sixth PMOS transistor MP6, and the drain of the seventh NMOS transistor MN7. The source of the fifth PMOS transistor MP5 is respectively connected to the adaptive threshold adjustment module 1 and the second end of the third resistor R3. The source of the sixth PMOS transistor MP6 is connected to the second end of the fourth resistor R4. The drain of the sixth PMOS transistor MP6 is respectively connected to the gate of the seventh PMOS transistor MP7 and the drain of the eighth NMOS transistor MN8. The source of the seventh PMOS transistor MP7 is respectively connected to the power supply and the positive electrode of the second current source I2. The drain of the seventh PMOS transistor MP7 is respectively connected to the drain of the tenth NMOS transistor MN10 and the adaptive logic implementation module 3. The negative electrode of the second current source I2 is connected to the drain of the sixth NMOS transistor MN6.

[0086] It should be noted that the current of the second current source I2 can be set according to actual conditions and is not limited in this embodiment.

[0087] In its implementation, the system monitors the actual turn-off time of the freewheeling diode and the actual zero-crossing current. If the system crosses zero prematurely, the current is controlled to charge capacitor C, adjusting the zero-crossing threshold toward zero current. If the system crosses zero later, that is, outputs the ZCD signal when the inductor current is negative, the current is controlled to discharge capacitor C, adjusting the zero-crossing threshold toward the positive direction. This enables an adaptive zero-crossing threshold, ensuring that the zero-crossing threshold is near and very close to zero current, avoiding the additional energy consumption caused by early or late actual zero crossings and improving the converter's conversion efficiency in the light-load DCM operating mode.

[0088] In addition, to achieve the above-mentioned purpose, the present application also proposes a converter, which includes the adaptive zero-crossing detection circuit as described above.

[0089] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An adaptive zero-crossing detection circuit, characterized in that: The adaptive zero-crossing detection circuit is applied to a converter; The adaptive zero-crossing detection circuit includes: an adaptive threshold adjustment module, a zero-crossing comparison module and an adaptive logic implementation module; The zero-crossing comparison module is connected to the adaptive threshold adjustment module, the adaptive logic implementation module and the converter respectively; The zero-crossing comparison module is used to compare the output voltage of the converter and the inductor voltage to obtain an inductor current zero-crossing result, and send the inductor current zero-crossing result to the adaptive logic implementation module; the inductor current zero-crossing result includes: an early zero-crossing signal and a delayed zero-crossing signal; The adaptive logic implementation module is configured to generate a short pulse signal upon receiving the inductor current zero-crossing result and send the short pulse signal to the adaptive threshold adjustment module; the short pulse signal includes a positive short pulse signal and a negative short pulse signal; The adaptive threshold adjustment module is used to adjust the zero-crossing threshold of the zero-crossing comparison module according to the pulse width of the positive short pulse signal and the negative short pulse signal; The zero-crossing comparison module is further used to compare the zero-crossing threshold with the inductor voltage of the converter to achieve adaptive zero-crossing detection; The zero-crossing comparison module is further configured to send an early zero-crossing signal to the adaptive logic implementation module when the output voltage of the converter is less than the inductor voltage; The zero-crossing comparison module is further configured to send a delayed zero-crossing signal to the adaptive logic implementation module when the output voltage of the converter is greater than the inductor voltage.

2. The adaptive zero-crossing detection circuit according to claim 1, wherein: The adaptive threshold adjustment module is further configured to charge the internal capacitor when the pulse width of the positive short pulse signal is greater than the pulse width of the negative short pulse signal, so as to adjust the zero-crossing threshold of the zero-crossing comparison module in a negative direction; The adaptive threshold adjustment module is further configured to discharge the internal capacitor when the pulse width of the positive short pulse signal is smaller than the pulse width of the negative short pulse signal, so as to adjust the zero-crossing threshold of the zero-crossing comparison module in the positive direction.

3. The adaptive zero-crossing detection circuit according to claim 1, wherein: The adaptive threshold adjustment module includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor; The source of the first NMOS transistor, the source of the third NMOS transistor, and the source of the fifth NMOS transistor are respectively grounded; the gate of the first NMOS transistor is respectively connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor, and the gate of the fifth NMOS transistor; the source of the second NMOS transistor is connected to the drain of the third NMOS transistor; the drain of the second NMOS transistor is respectively connected to the gate of the fourth NMOS transistor; the gate of the third NMOS transistor is connected to the negative pulse port of the adaptive logic implementation module; the drain of the fourth NMOS transistor is connected to the zero-crossing comparison module; and the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor.

4. The adaptive zero-crossing detection circuit according to claim 3, wherein: The adaptive threshold adjustment module further includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor; The source of the first PMOS tube, the source of the second PMOS tube, and the source of the third PMOS tube are respectively connected to a power supply, the drain of the first PMOS tube is respectively connected to the gate of the first PMOS tube, the gate of the second PMOS tube, and the gate of the fourth PMOS tube, the drain of the second PMOS tube is connected to the drain of the first NMOS tube, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the gate of the third PMOS tube is connected to the positive pulse port of the adaptive logic implementation module, and the drain of the fourth PMOS tube is connected to the drain of the second NMOS tube.

5. The adaptive zero-crossing detection circuit according to claim 4, wherein: The adaptive threshold adjustment module further includes: a capacitor and a first current source; A first end of the capacitor is respectively connected to the drain of the fourth PMOS transistor, the drain of the second NMOS transistor, and the gate of the fourth NMOS transistor, a second end of the capacitor is grounded, a positive electrode of the first current source is respectively connected to the gate of the first PMOS transistor, the gate of the second PMOS transistor, and the gate of the fourth PMOS transistor, and a negative electrode of the first current source is grounded.

6. The adaptive zero-crossing detection circuit according to claim 1, wherein: The zero-crossing comparison module includes: a first resistor, a second resistor, a third resistor and a fourth resistor; The first end of the first resistor is connected to the voltage output end of the converter, the second end of the first resistor is connected to the first end of the third resistor, the second end of the third resistor is connected to the adaptive threshold adjustment module, the first end of the second resistor is connected to the first end of the inductor in the converter, and the second end of the second resistor is connected to the first end of the fourth resistor.

7. The adaptive zero-crossing detection circuit according to claim 6, wherein: The zero-crossing comparison module further includes: a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor; The source of the sixth NMOS transistor, the source of the seventh NMOS transistor, the source of the eighth NMOS transistor, the source of the ninth NMOS transistor, and the source of the tenth NMOS transistor are respectively grounded; the gate of the sixth NMOS transistor is respectively connected to the drain of the sixth NMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor, and the gate of the tenth NMOS transistor; the drain of the ninth NMOS transistor is connected to the second end of the second resistor; and the drain of the tenth NMOS transistor is connected to the adaptive logic implementation module.

8. The adaptive zero-crossing detection circuit according to claim 7, wherein: The zero-crossing comparison module further includes: a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor and a second current source; The gate of the fifth PMOS transistor is respectively connected to the drain of the fifth PMOS transistor, the gate of the sixth PMOS transistor, and the drain of the seventh NMOS transistor; the source of the fifth PMOS transistor is respectively connected to the adaptive threshold adjustment module and the second end of the third resistor; the source of the sixth PMOS transistor is connected to the second end of the fourth resistor; the drain of the sixth PMOS transistor is respectively connected to the gate of the seventh PMOS transistor and the drain of the eighth NMOS transistor; the source of the seventh PMOS transistor is respectively connected to the power supply and the positive electrode of the second current source; the drain of the seventh PMOS transistor is respectively connected to the drain of the tenth NMOS transistor and the adaptive logic implementation module; and the negative electrode of the second current source is connected to the drain of the sixth NMOS transistor.

9. A converter, characterized in that: The converter comprises the adaptive zero-crossing detection circuit according to any one of claims 1 to 8.

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