Charge pump circuit based on closed-loop feedback control

Abstract

The invention discloses a charge pump circuit based on closed-loop feedback control, and relates to the technical field of analog integrated circuit power management. Comprising a two-phase non-overlapping clock generation circuit, a control signal generation circuit and a charge pump main body circuit. The charge pump main body circuit comprises a cross coupling circuit, a feedback circuit and an operational amplifier circuit. And the output voltage of the cross coupling circuit is output through an output port VCP, and the voltage at the output port VCP is fed back to the control signal generation circuit through an operational amplifier output port VPVB after being sequentially processed by the feedback circuit and the operational amplifier circuit, so that feedback control of the charge pump main body circuit is realized, and a high-voltage voltage source is obtained. The high-voltage source is high in voltage precision, and the absolute value of the voltage of the high-voltage source does not change along with the error of an integrated circuit manufacturing process and the change of temperature.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuit power management, and in particular to a charge pump circuit based on closed-loop feedback control. Background Art

[0002] The integrated circuit industry is the core of the information technology industry and a strategic, fundamental, and pioneering industry that supports economic and social development and safeguards national security. With the rapid development of electronic technology, inertial sensors are widely used in navigation, vibration measurement, attitude monitoring, and other fields. In practical applications, the output of inertial sensors may deviate or fluctuate due to various external interferences (such as temperature and humidity changes, electromagnetic interference, etc.) and internal factors (such as component aging and manufacturing errors).

[0003] In existing technology, inertial sensors often use traditional charge pump circuits, such as Dickson charge pumps, to generate high-voltage voltage sources. To provide precise feedback control for inertial sensors, a high-precision, low-temperature drift, high-voltage source is required. This source must be electrically connected to the inertial sensor. Finally, this source must be monitored and adjusted in real time during power supply to ensure that the supply voltage and current remain within the specified range.

[0004] The above-mentioned existing technology has the following drawbacks: the conventional charge pump circuit generates a high voltage source voltage, and the absolute value of the high voltage source voltage varies with the error of the integrated circuit manufacturing process and the change of temperature. Summary of the Invention

[0005] Based on this, it is necessary to provide a charge pump circuit based on closed-loop feedback control to address the above technical problems.

[0006] An embodiment of the present invention provides a charge pump circuit based on closed-loop feedback control, comprising: a two-phase non-overlapping clock generating circuit, a control signal generating circuit, and a charge pump main circuit; The charge pump main circuit includes: a cross-coupling circuit, a feedback circuit and an operational amplifier circuit; The input end of the cross-coupling circuit is connected to the power supply VDD, the output end of the cross-coupling circuit is connected to the output port VCP and the input end of the feedback circuit, and the output end of the feedback circuit is connected to the operational amplifier circuit; The feedback circuit includes a first adjustable resistor R1 and a second adjustable resistor R2; one end of the first adjustable resistor R1 is connected to the output end of the cross-coupling circuit, and the other end of the first adjustable resistor R1 is connected to one end of the second adjustable resistor R2 and the operational amplifier circuit; the other end of the second adjustable resistor R2 is grounded; The operational amplifier circuit includes a first operational amplifier OP1 and a second operational amplifier OP2; a non-inverting input terminal IN+ of the first operational amplifier OP1 is connected to a feedback circuit, an inverting input terminal IN- of the first operational amplifier OP1 is connected to a reference source port VREF, an output terminal OUT of the first operational amplifier OP1 is connected to a non-inverting input terminal IN+ of the second operational amplifier OP2; an inverting input terminal IN- of the second operational amplifier OP2 is connected to its output terminal OUT, and both are connected to an operational amplifier output port VPVB, which is connected to a control signal generating circuit; The output voltage of the cross-coupling circuit is output through the output port VCP. The voltage at the output port VCP is processed by the feedback circuit and the operational amplifier circuit in sequence and then fed back to the control signal generating circuit through the operational amplifier output port VPVB to realize feedback control of the charge pump main circuit and obtain a high voltage voltage source.

[0007] Optionally, the input end of the two-phase non-overlapping clock generating circuit is connected to the input port CLKIN, and the two-phase non-overlapping clock generating circuit is connected to the input end of the control signal generating circuit through the first output port CLK1, the first inverting output port CLK1N, the second output port CLK2 and the second inverting output port CLK2N; The control signal generating circuit is connected to the input end of the charge pump main circuit through the first output port CKOUT1, the first inverting output port CKNOUT1, the second output port CKOUT2 and the second inverting output port CKNOUT2; The two-phase non-overlapping clock generating circuit, the control signal generating circuit and the charge pump main circuit are all connected to the power supply VDD and the ground.

[0008] Optionally, the cross-coupling circuit includes: an A1 module, an A2 module and an A3 module; the input end of the A1 module is connected to the power supply VDD, the output end of the A1 module is connected to the input end of the A2 module, the output end of the A2 module is connected to the input end of the A3 module, and the output end of the A3 module is connected to the output port VCP.

[0009] Optionally, the A1 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, C1The other end is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3, and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the power supply VDD; The G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C. C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT2 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A1 module.

[0010] Optionally, the A2 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to the first output port CKOUT1 of the control signal generating circuit, and the first capacitor C C1 The other end is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A1 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the first inverting output port CKNOUT1 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A2 module.

[0011] Optionally, the A3 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, C1The other end is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A2 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT2 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 are connected to the output port VCP as the output end of the A3 module.

[0012] Optionally, the control signal generating circuit includes: a seventh P-type MOS transistor PM7, an eighth P-type MOS transistor PM8, a ninth P-type MOS transistor PM9, a fifth N-type MOS transistor NM5, a sixth N-type MOS transistor NM6, a tenth P-type MOS transistor PM10, an eleventh P-type MOS transistor PM11, a twelfth P-type MOS transistor PM12, a seventh N-type MOS transistor NM7, and an eighth N-type MOS transistor NM8; The S terminal of the seventh P-type MOS transistor PM7 is connected to the power supply VDD, the G terminal of the seventh P-type MOS transistor PM7 is connected to the operational amplifier output port VPVB, the D terminal of the seventh P-type MOS transistor PM7 is connected to the S terminal of the eighth P-type MOS transistor PM8 and the S terminal of the ninth P-type MOS transistor PM9; the G terminal of the eighth P-type MOS transistor PM8 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, the D terminal of the eighth P-type MOS transistor PM8 and the D terminal of the fifth N-type MOS transistor NM5 are connected to the second output port CKOUT2 of the control signal generating circuit, and the fifth N-type MOS transistor NM The G terminal of the fifth N-type MOS transistor NM5 is connected to the second output port CLK2 of the two-phase non-overlapping clock generation circuit, and the S terminal of the fifth N-type MOS transistor NM5 is grounded; the G terminal of the ninth P-type MOS transistor PM9 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generation circuit, and the D terminal of the ninth P-type MOS transistor PM9 and the D terminal of the sixth N-type MOS transistor NM6 are connected to the second inverting output port CKNOUT2 of the control signal generation circuit; the G terminal of the sixth N-type MOS transistor NM6 is connected to the first output port CLK1 of the two-phase non-overlapping clock generation circuit, and the S terminal of the sixth N-type MOS transistor NM6 is grounded; The S terminal of the tenth P-type MOS transistor PM10 is connected to VDD, the G terminal of the tenth P-type MOS transistor PM10 is connected to the operational amplifier output port VPVB, the D terminal of the tenth P-type MOS transistor PM10 is connected to the S terminal of the eleventh P-type MOS transistor PM11 and the S terminal of the twelfth P-type MOS transistor PM12; the G terminal of the eleventh P-type MOS transistor PM11 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, the D terminal of the eleventh P-type MOS transistor PM11 and the D terminal of the seventh N-type MOS transistor NM7 are connected to the first output port CKOUT1 of the control signal generating circuit; the seventh N-type MOS transistor The G terminal of the S-type MOS transistor NM7 is connected to the second output port CLK2 of the two-phase non-overlapping clock generation circuit, the S terminal of the seventh N-type MOS transistor NM7 is grounded, and the G terminal of the twelfth P-type MOS transistor PM12 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generation circuit; the D terminal of the twelfth P-type MOS transistor PM12 and the D terminal of the eighth N-type MOS transistor NM8 are connected to the first output port CKNOUT1 of the control signal generation circuit, the G terminal of the eighth N-type MOS transistor NM8 is connected to the first output port CLK1 of the two-phase non-overlapping clock generation circuit, and the S terminal of the eighth N-type MOS transistor NM8 is grounded.

[0013] The above-mentioned charge pump circuit based on closed-loop feedback control provided by the embodiment of the present invention has the following beneficial effects compared with the prior art: The output voltage of the cross-coupling circuit of the present invention is output through the output port VCP. The voltage at the output port VCP is processed by the feedback circuit and the operational amplifier circuit in sequence and then fed back to the control signal generating circuit through the operational amplifier output port VPVB to realize feedback control of the charge pump main circuit and obtain a high voltage voltage source.

[0014] In the above process, the output voltage of the cross-coupling circuit is determined by the resistance values of the first adjustable resistor R1 and the second adjustable resistor R2. The voltage at the output port VCP can be adjusted by changing the resistance values of the first adjustable resistor R1 and the second adjustable resistor R2. This circuit is insensitive to fluctuations in the supply voltage and process temperature fluctuations of other components. Therefore, the high-voltage source voltage of the present invention is highly accurate, and the absolute value of the high-voltage source voltage does not change with errors in the integrated circuit manufacturing process or changes in temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 1 is a circuit diagram of a charge pump circuit based on closed-loop feedback control provided in one embodiment; Figure 2 A schematic diagram of a control signal generating circuit of a charge pump circuit based on closed-loop feedback control provided in one embodiment; Figure 3 A schematic diagram of a charge pump main circuit of a charge pump circuit based on closed-loop feedback control provided in one embodiment. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0017] In one embodiment, a charge pump circuit based on closed-loop feedback control is provided, such as Figure 1 As shown, it includes: a two-phase non-overlapping clock generating circuit, a control signal generating circuit and a charge pump main circuit.

[0018] Among them, the input end of the two-phase non-overlapping clock generating circuit is connected to the input port CLKIN, and the two-phase non-overlapping clock generating circuit is connected to the input end of the control signal generating circuit through the first output port CLK1, the first inverting output port CLK1N, the second output port CLK2 and the second inverting output port CLK2N.

[0019] The control signal generating circuit is connected to the input end of the charge pump main circuit through the first output port CKOUT1 , the first inverting output port CKNOUT1 , the second output port CKOUT2 and the second inverting output port CKNOUT2 .

[0020] In addition, the two-phase non-overlapping clock generation circuit, the control signal generation circuit, and the charge pump main circuit are all connected to the power supply VDD and the ground (GND).

[0021] 1. Control signal generating circuit like Figure 2 As shown, the control signal generating circuit includes: a seventh P-type MOS transistor PM7, an eighth P-type MOS transistor PM8, a ninth P-type MOS transistor PM9, a fifth N-type MOS transistor NM5, a sixth N-type MOS transistor NM6, a tenth P-type MOS transistor PM10, an eleventh P-type MOS transistor PM11, a twelfth P-type MOS transistor PM12, a seventh N-type MOS transistor NM7, and an eighth N-type MOS transistor NM8; The S terminal of the seventh P-type MOS transistor PM7 is connected to the power supply VDD, the G terminal of the seventh P-type MOS transistor PM7 is connected to the operational amplifier output port VPVB, the D terminal of the seventh P-type MOS transistor PM7 is connected to the S terminal of the eighth P-type MOS transistor PM8 and the S terminal of the ninth P-type MOS transistor PM9; the G terminal of the eighth P-type MOS transistor PM8 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, the D terminal of the eighth P-type MOS transistor PM8 and the D terminal of the fifth N-type MOS transistor NM5 are connected to the second output port CKOUT2 of the control signal generating circuit, and the D terminal of the fifth N-type MOS transistor NM5 is connected to the second output port CKOUT2 of the control signal generating circuit. The G terminal of NM5 is connected to the second output port CLK2 of the two-phase non-overlapping clock generation circuit, and the S terminal of the fifth N-type MOS transistor NM5 is grounded; the G terminal of the ninth P-type MOS transistor PM9 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generation circuit, and the D terminal of the ninth P-type MOS transistor PM9 and the D terminal of the sixth N-type MOS transistor NM6 are connected to the second inverting output port CKNOUT2 of the control signal generation circuit; the G terminal of the sixth N-type MOS transistor NM6 is connected to the first output port CLK1 of the two-phase non-overlapping clock generation circuit, and the S terminal of the sixth N-type MOS transistor NM6 is grounded.

[0022] The S terminal of the tenth P-type MOS transistor PM10 is connected to VDD, the G terminal of the tenth P-type MOS transistor PM10 is connected to the operational amplifier output port VPVB, the D terminal of the tenth P-type MOS transistor PM10 is connected to the S terminal of the eleventh P-type MOS transistor PM11 and the S terminal of the twelfth P-type MOS transistor PM12; the G terminal of the eleventh P-type MOS transistor PM11 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, the D terminal of the eleventh P-type MOS transistor PM11 and the D terminal of the seventh N-type MOS transistor NM7 are connected to the first output port CKOUT1 of the control signal generating circuit; the seventh N-type MOS transistor The G terminal of the S-type MOS transistor NM7 is connected to the second output port CLK2 of the two-phase non-overlapping clock generation circuit, the S terminal of the seventh N-type MOS transistor NM7 is grounded, and the G terminal of the twelfth P-type MOS transistor PM12 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generation circuit; the D terminal of the twelfth P-type MOS transistor PM12 and the D terminal of the eighth N-type MOS transistor NM8 are connected to the first output port CKNOUT1 of the control signal generation circuit, the G terminal of the eighth N-type MOS transistor NM8 is connected to the first output port CLK1 of the two-phase non-overlapping clock generation circuit, and the S terminal of the eighth N-type MOS transistor NM8 is grounded.

[0023] 2. Charge pump main circuit like Figure 3 As shown, the charge pump main circuit includes a cross-coupling circuit, a feedback circuit and an operational amplifier circuit.

[0024] 2.1 Cross-coupled circuit The cross-coupling circuit includes: A1 module, A2 module and A3 module. The input end of A1 module is connected to the power supply VDD, the output end of A1 module is connected to the input end of A2 module, the output end of A2 module is connected to the input end of A3 module, and the output end of A3 module is connected to the output port VCP.

[0025] 2.1.1 A1 module The A1 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, C1 The other end is connected to the S terminal of the second N-type MOS transistor NM2, the S terminal of the third P-type MOS transistor PM3, the G terminal of the third N-type MOS transistor NM3, and the G terminal of the fourth P-type MOS transistor PM4. The D terminal of the second N-type MOS transistor NM2 and the D terminal of the third N-type MOS transistor NM3 are connected to the power supply VDD.

[0026] The G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C. C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT2 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A1 module.

[0027] 2.1.2 A2 module The A2 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to the first output port CKOUT1 of the control signal generating circuit, and the first capacitor C C1The other end is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A1 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the first inverting output port CKNOUT1 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A2 module.

[0028] 2.1.3 A3 module The A3 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, C1 The other end is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A2 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT2 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 are connected to the output port VCP as the output end of the A3 module.

[0029] 2.2 Feedback Circuit The feedback circuit includes a first adjustable resistor R1 and a second adjustable resistor R2. One end of the first adjustable resistor R1 is connected to the output end of the cross-coupling circuit, the other end of the first adjustable resistor R1 is connected to one end of the second adjustable resistor R2 and the operational amplifier circuit, and the other end of the second adjustable resistor R2 is grounded.

[0030] 2.3 Op amp circuit The operational amplifier circuit includes a first operational amplifier OP1 and a second operational amplifier OP2. The non-inverting input terminal IN+ of the first operational amplifier OP1 is connected to a feedback circuit, the inverting input terminal IN- of the first operational amplifier OP1 is connected to a reference source port VREF, and the output terminal OUT of the first operational amplifier OP1 is connected to the non-inverting input terminal IN+ of the second operational amplifier OP2. The inverting input terminal IN- and the output terminal OUT of the second operational amplifier OP2 are connected to the operational amplifier output port VPVB, which is connected to a control signal generating circuit.

[0031] 3. Working Principle The specific structure of the op amp circuit can be selected based on the required VCP accuracy. The voltage at the reference source port VREF is generated by a low-temperature drift reference source. This circuit can generate a high-precision high-voltage voltage source whose absolute value is independent of the power supply and process.

[0032] The basic principles of the above technical solution are as follows: (1) The overall circuit is divided into three modules. The first module is the charge pump main circuit, which is used to alternately charge the charge storage capacitor CC and output VCP under the control of the control signal, and detect the circuit output voltage to generate VPVB; the second module is the control signal generation circuit, which is used to adjust the amplitude of the charge pump control signal under the control of VPVB and the two-phase non-overlapping clock, and output it to the charge pump main circuit; the third module is the two-phase non-overlapping clock generation module, which is used to generate a two-phase non-overlapping clock and output it to the charge pump control signal generation module.

[0033] (2) The overall circuit is a closed-loop structure. The output voltage of the cross-coupling circuit is output through the output port VCP, and the voltage at the output port VCP is determined by the feedback coefficient composed of the first adjustable resistor R1 and the second adjustable resistor R2. Among them, V CP is the voltage value at the output port VCP, V REF The voltage at the reference source port VREF is R1, the resistance of the first adjustable resistor R1 is R2, and the resistance of the second adjustable resistor R2 is R2. The voltage at the output port VCP can be adjusted by changing the resistance of the first adjustable resistor R1 and the second adjustable resistor R2.

[0034] (3) According to the voltage of the output port VCP, the first adjustable resistor R1 and the second adjustable resistor R2 as well as the first operational amplifier OP1 and the second operational amplifier OP2 are adjusted to achieve dynamic adjustment of the voltage at the output port VPVB of the operational amplifier, and at the same time adjust the size of the charge stored on CC in each clock cycle.

[0035] (4) The main circuit of the charge pump adopts a cross-coupling circuit, which can effectively reduce the ripple size and improve efficiency. It should be noted that in order to eliminate the body effect and reduce the leakage current, the substrate of the NMOS tube and the PMOS tube need to be connected to the source end, so the performance is better when using the BCD process.

[0036] (5) The op amp structure, clock frequency and CC capacitor size in this patent can be designed based on the voltage accuracy of the output port VCP, load current size and other requirements.

[0037] The above-described embodiments merely illustrate several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.

Claims

1. A charge pump circuit based on closed-loop feedback control, characterized in that: include: Two-phase non-overlapping clock generating circuit, control signal generating circuit and charge pump main circuit; The charge pump main circuit includes: a cross-coupling circuit, a feedback circuit and an operational amplifier circuit; The input end of the cross-coupling circuit is connected to the power supply VDD, the output end of the cross-coupling circuit is connected to the output port VCP and the input end of the feedback circuit, and the output end of the feedback circuit is connected to the operational amplifier circuit; The feedback circuit includes a first adjustable resistor R1 and a second adjustable resistor R2; one end of the first adjustable resistor R1 is connected to the output end of the cross-coupling circuit, and the other end of the first adjustable resistor R1 is connected to one end of the second adjustable resistor R2 and the operational amplifier circuit; the other end of the second adjustable resistor R2 is grounded; The operational amplifier circuit includes a first operational amplifier OP1 and a second operational amplifier OP2; a non-inverting input terminal IN+ of the first operational amplifier OP1 is connected to the feedback circuit, an inverting input terminal IN- of the first operational amplifier OP1 is connected to a reference source port VREF, an output terminal OUT of the first operational amplifier OP1 is connected to a non-inverting input terminal IN+ of the second operational amplifier OP2; an inverting input terminal IN- and an output terminal OUT of the second operational amplifier OP2 are connected to an operational amplifier output port VPVB, and the operational amplifier output port VPVB is connected to the control signal generating circuit; The output voltage of the cross-coupling circuit is output through the output port VCP. The voltage at the output port VCP is processed by the feedback circuit and the operational amplifier circuit in sequence and then fed back to the control signal generating circuit through the operational amplifier output port VPVB to realize feedback control of the charge pump main circuit and obtain a high voltage voltage source.

2. A charge pump circuit based on closed-loop feedback control according to claim 1, characterized in that: The input end of the two-phase non-overlapping clock generating circuit is connected to the input port CLKIN, and the two-phase non-overlapping clock generating circuit is connected to the input end of the control signal generating circuit through the first output port CLK1, the first inverting output port CLK1N, the second output port CLK2 and the second inverting output port CLK2N; The control signal generating circuit is connected to the input end of the charge pump main circuit through the first output port CKOUT1, the first inverting output port CKNOUT1, the second output port CKOUT2 and the second inverting output port CKNOUT2; The two-phase non-overlapping clock generating circuit, the control signal generating circuit and the charge pump main circuit are all connected to a power supply VDD and ground.

3. A charge pump circuit based on closed-loop feedback control according to claim 2, characterized in that: The cross-coupling circuit includes: an A1 module, an A2 module and an A3 module; the input end of the A1 module is connected to the power supply VDD, the output end of the A1 module is connected to the input end of the A2 module, the output end of the A2 module is connected to the input end of the A3 module, and the output end of the A3 module is connected to the output port VCP.

4. A charge pump circuit based on closed-loop feedback control as claimed in claim 3, characterized in that: The A1 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, C1 The other end of the second N-type MOS transistor NM2 is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the power supply VDD; the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4 and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT2 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A1 module.

5. The charge pump circuit based on closed-loop feedback control according to claim 3, characterized in that: The A2 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to the first output port CKOUT1 of the control signal generating circuit, and the first capacitor C C1 The other end is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the third N-type MOS transistor NM3 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A1 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4, and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the first inverting output port CKNOUT1 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 serve as the output end of the A2 module.

6. The charge pump circuit based on closed-loop feedback control according to claim 3, characterized in that: The A3 module specifically includes: a first capacitor C C1 , the second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4; The first capacitor C C1 One end of the first capacitor C is connected to the second output port CKOUT2 of the control signal generating circuit, C1 The other end is connected to the S end of the second N-type MOS transistor NM2, the S end of the third P-type MOS transistor PM3, the G end of the second N-type MOS transistor NM2 and the G end of the fourth P-type MOS transistor PM4; the D end of the second N-type MOS transistor NM2 and the D end of the third N-type MOS transistor NM3 are connected to the output end of the A2 module, and the G end of the second N-type MOS transistor NM2, the S end of the third N-type MOS transistor NM3, the S end of the fourth P-type MOS transistor PM4, and the G end of the third P-type MOS transistor PM3 are connected to the second capacitor C C2 One end of the second capacitor C C2 The other end is connected to the second inverting output port CKNOUT2 of the control signal generating circuit, and the D end of the third P-type MOS transistor PM3 and the D end of the fourth P-type MOS transistor PM4 are connected to the output port VCP as the output end of the A3 module.

7. The charge pump circuit based on closed-loop feedback control according to claim 1, characterized in that: The control signal generating circuit includes: a seventh P-type MOS transistor PM7, an eighth P-type MOS transistor PM8, a ninth P-type MOS transistor PM9, a fifth N-type MOS transistor NM5, a sixth N-type MOS transistor NM6, a tenth P-type MOS transistor PM10, an eleventh P-type MOS transistor PM11, a twelfth P-type MOS transistor PM12, a seventh N-type MOS transistor NM7 and an eighth N-type MOS transistor NM8; The S terminal of the seventh P-type MOS transistor PM7 is connected to the power supply VDD, the G terminal of the seventh P-type MOS transistor PM7 is connected to the operational amplifier output port VPVB, the D terminal of the seventh P-type MOS transistor PM7 is connected to the S terminal of the eighth P-type MOS transistor PM8 and the S terminal of the ninth P-type MOS transistor PM9; the G terminal of the eighth P-type MOS transistor PM8 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, the D terminal of the eighth P-type MOS transistor PM8 and the D terminal of the fifth N-type MOS transistor NM5 are connected to the second output port CKOUT2 of the control signal generating circuit, and the D terminal of the fifth N-type MOS transistor NM5 is connected to the second output port CKOUT2 of the control signal generating circuit. The G terminal of NM5 is connected to the second output port CLK2 of the two-phase non-overlapping clock generation circuit, and the S terminal of the fifth N-type MOS transistor NM5 is grounded; the G terminal of the ninth P-type MOS transistor PM9 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generation circuit, and the D terminal of the ninth P-type MOS transistor PM9 and the D terminal of the sixth N-type MOS transistor NM6 are connected to the second inverting output port CKNOUT2 of the control signal generation circuit; the G terminal of the sixth N-type MOS transistor NM6 is connected to the first output port CLK1 of the two-phase non-overlapping clock generation circuit, and the S terminal of the sixth N-type MOS transistor NM6 is grounded; The S terminal of the tenth P-type MOS transistor PM10 is connected to VDD, the G terminal of the tenth P-type MOS transistor PM10 is connected to the operational amplifier output port VPVB, the D terminal of the tenth P-type MOS transistor PM10 is connected to the S terminal of the eleventh P-type MOS transistor PM11 and the S terminal of the twelfth P-type MOS transistor PM12; the G terminal of the eleventh P-type MOS transistor PM11 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, the D terminal of the eleventh P-type MOS transistor PM11 and the D terminal of the seventh N-type MOS transistor NM7 are connected to the first output port CKOUT1 of the control signal generating circuit; the seventh N-type MOS transistor The G terminal of the OS transistor NM7 is connected to the second output port CLK2 of the two-phase non-overlapping clock generating circuit, the S terminal of the seventh N-type MOS transistor NM7 is grounded, and the G terminal of the twelfth P-type MOS transistor PM12 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generating circuit; the D terminal of the twelfth P-type MOS transistor PM12 and the D terminal of the eighth N-type MOS transistor NM8 are connected to the first output port CKNOUT1 of the control signal generating circuit, the G terminal of the eighth N-type MOS transistor NM8 is connected to the first output port CLK1 of the two-phase non-overlapping clock generating circuit, and the S terminal of the eighth N-type MOS transistor NM8 is grounded.

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