Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device includes: a first current generator circuit that generates a first current, has a positive temperature coefficient, and is independent of a first power supply voltage; a second current generator circuit generating a second current, having a negative temperature coefficient and independent of the first power supply voltage; and a third current generator circuit that generates a third current based on the first current and the second current, the third current being neither temperature nor the first power supply voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The contents disclosed in Japanese Patent Application No. 2024-018375 filed on February 9, 2024 including the specification, drawings and abstract are incorporated herein by reference in their entirety. Background Art

[0003] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that generates a temperature-compensated current.

[0004] The technologies listed below are disclosed.

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-206633

[0006] Patent Document 1 discloses a technology for generating a reference voltage that is compensated for temperature and power supply voltage and is equal to or lower than 1.2V. Summary of the Invention

[0007] The reference voltage generator circuit described in Patent Document 1 has a problem in that it cannot generate a voltage that is compensated for temperature and power supply voltage and is equal to or higher than 1.2 V.

[0008] The present disclosure is designed to solve such a problem, and an object of the present disclosure is to realize a semiconductor device that generates a current that is compensated according to temperature and power supply voltage.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] According to an embodiment, a semiconductor device includes: a first current generator circuit, which generates a first current, the first current has a positive temperature coefficient and is independent of a first power supply voltage; a second current generator circuit, which generates a second current, the second current has a negative temperature coefficient and is independent of the first power supply voltage; and a third current generator circuit, which generates a third current based on the first current and the second current, the third current being independent of neither temperature nor the first power supply voltage.

[0011] According to the embodiment, a semiconductor device that generates a current that compensates for temperature and power supply voltage can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a circuit diagram showing the configuration of a semiconductor device according to the first embodiment.

[0013] Figure 2 is a graph showing the temperature dependence of current according to the first embodiment.

[0014] Figure 3 is a circuit diagram showing the configuration of a semiconductor device according to a second embodiment.

[0015] Figure 4 is a graph showing the temperature dependency of the reference voltage according to the second embodiment.

[0016] Figure 5 This is a diagram for explaining one of the effects of the second embodiment.

[0017] Figure 6 is a circuit diagram showing the configuration of a semiconductor device according to a third embodiment.

[0018] Figure 7 is a graph showing the temperature dependency of the reference voltage according to the third embodiment. DETAILED DESCRIPTION

[0019] For the sake of clarity, the following description and drawings are appropriately omitted or simplified. Throughout each of the drawings, the same components are identified by the same reference numerals, and repeated description thereof is omitted as needed.

[0020] First embodiment

[0021] Figure 1 1 is a circuit diagram showing the configuration of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 includes current generator circuits 11, 12, and 13. The current generator circuits 11, 12, and 13 are also referred to as a first current generator circuit, a second current generator circuit, and a third current generator circuit, respectively.

[0022] The current generator circuit 11 includes p-channel type MOS (Metal Oxide Semiconductor) transistors MP1 and MP2 , an n-channel type MOS transistor MN1 , npn type bipolar transistors Bip1 and Bip2 , a resistor R1 , and an amplifier Amp1 .

[0023] MOS transistor MP1 and bipolar transistor Bip1 are connected in series between a power supply voltage VCC and a ground voltage GND. Power supply voltage VCC is also referred to as a first power supply voltage. MOS transistor MP2, bipolar transistor Bip2, and resistor R1 are connected in series and in parallel to MOS transistor MP1 and bipolar transistor Bip1. The gates of bipolar transistors Bip1 and Bip2 are connected to the source of MOS transistor MN1, and the gate of MOS transistor MN1 is connected to the connection node between MOS transistor MP1 and bipolar transistor Bip1. The drain of MOS transistor MN1 is connected to power supply voltage VCC. Amplifier Amp1 has a negative input terminal connected to the connection node between MOS transistor MP1 and bipolar transistor Bip2. Amplifier Amp1 has a positive input terminal connected to the connection node between MOS transistor MP2 and bipolar transistor Bip2. Amplifier Amp1 has an output terminal connected to the gates of MOS transistors MP1 and MP2. Amplifier Amp1 controls MOS transistors MP1 and MP2 so that the voltage at the connection node connected to the positive input terminal and the voltage at the connection node connected to the negative input terminal are equal.

[0024] If the device sizes, in other words, the gate lengths and gate widths of the MOS transistors MP1 and MP2 are equal to each other, the current (also referred to as the first current) Iref1 flowing between the source and drain of the MOS transistor MP2 in the current generator circuit 11 is expressed by the following equation (1). The temperature coefficient ΔIref1 / ΔT of the current Iref1 is expressed by the following equation (2).

[0025] Iref1 = 1 / R1 * (kT / q) * (lnM) … Formula (1)

[0026] ΔIref1 / ΔT = (1 / R1) * (k / q) * (lnM) … Formula (2)

[0027] The term "M" herein represents the ratio of the emitter area of bipolar transistor Bip1 to the emitter area of bipolar transistor Bip2. The elementary charge is "q = 1.6 * 10^(-19) [C]," the Boltzmann constant is "k = 1.38 * 10^(-23) [J / K]," and the term "T" represents the absolute temperature [K]. It should be noted that the resistance value of resistor R1 is assumed to be "R1."

[0028] From formula (2), it can be seen that formula (3) "ΔIref1 / ΔT>0" holds.

[0029] The current generator circuit 12 includes p-channel MOS transistors MP3 and MP4 , n-channel MOS transistors MN2 and MN3 , an npn bipolar transistor Bip3 , and a resistor R2 .

[0030] MOS transistor MP3, MOS transistor MN1, and bipolar transistor Bip3 are connected in series between power supply voltage VCC and ground voltage GND. The collector and base of bipolar transistor Bip3 are connected to each other. MOS transistor MP4, MOS transistor MN3, and resistor R2 are connected in series and in parallel to MOS transistor MP3, MOS transistor MN1, and bipolar transistor Bip3. The gates of MOS transistors MP3 and MP4 are connected to the connection node between MOS transistor MP4 and MOS transistor MN3. The gates of MOS transistors MN2 and MN3 are connected to the connection node between MOS transistor MP3 and MOS transistor MN2. MOS transistors MP3, MP4, MN2, and MN3 form a current mirror circuit. If the device sizes of MOS transistors MP3, MP4, MN1, and MN2 are equal, the currents flowing in MOS transistors MP3, MP4, MN1, and MN2 are equal. The voltage at the connection node between MOS transistor MN2 and bipolar transistor Bip3 is equal to the voltage at the connection node between MOS transistor MN3 and resistor R2.

[0031] If the device sizes of MOS transistors MP3, MP4, MN1, and MN2 are equal to each other, the current Iref2 (also referred to as the second current) flowing in the MOS transistor MP4 of the current generator circuit 12 is expressed by the following equation (4). Its temperature coefficient ΔIref2 / ΔT is expressed by the following equation (5).

[0032] Iref2 = (VBE_Bip3) / R2 ... Equation (4)

[0033] ΔIref2 / ΔT = ((ΔVBE_Bip3) / ΔT) / R2 … Formula (5)

[0034] The term "VBE_Bip3" herein represents the voltage between the base and emitter of the bipolar transistor Bip3. Note that it is assumed that the resistance value of the resistor R2 is "R2".

[0035] Since “(ΔVBE_Bip3) / ΔT<0”, equation (6) is derived from equation (5).

[0036] ΔIref2 / ΔT < 0 … Equation (6)

[0037] The current generator circuit 13 includes p-channel MOS transistors MP5 and MP6. The source of MOS transistor MP5 is connected to the power supply voltage VCC, and the gate of MOS transistor MP5 is connected to the gate of MOS transistor MP4. MOS transistor MP6 is connected in parallel to MOS transistor MP5, and the gate of MOS transistor MP6 is connected to the gate of MOS transistor MP2. MOS transistor MP5 copies current Iref2 at a predetermined mirror ratio, with the current flowing between the source and drain of MOS transistor MP4. MOS transistor MP6 copies current Iref1 at a predetermined mirror ratio, with the current flowing between the source and drain of MOS transistor MP2. The current flowing between the source and drain of MOS transistor MP5 and the current flowing between the source and drain of MOS transistor MP6 are combined to generate current Iref3 (also referred to as a third current).

[0038] The current Iref3 is expressed by the following equation (7), and its temperature coefficient ΔIref3 / ΔT is expressed by the following equation (8).

[0039] Iref3=A*Iref1+B*Iref2…Equation (7)

[0040] ΔIref3 / ΔT = A * ΔIref1 / ΔT + B * ΔIref2 / ΔT … Equation (8)

[0041] The item “A” herein represents a mirror ratio between the MOS transistors MP2 and MP6 , and the item “B” herein represents a mirror ratio between the MOS transistors MP4 and MP5 .

[0042] By appropriately setting the terms "A" and "B", the current Iref3 that does not depend on temperature is derived from equations (8), (3), and (6). Furthermore, equation (8) does not include a term related to the power supply voltage VCC. Therefore, the semiconductor device according to the first embodiment can generate a current that does not depend on either the power supply voltage or the temperature.

[0043] Next, a case where the following condition (1) is set will be specifically described.

[0044] Condition (1): R1 = 50 [kΩ], M = 8, R2 = 900 [kΩ], A = 2, B = 4. The following equations (1'), (2'), (4'), (5'), (7'), and (8') are derived by substituting the numerical values of condition (1) into equations (1), (2), (4), (5), (7), and (8).

[0045] Iref1=(1 / 50K)*(kT / q)*(ln8)=1[μA]…Equation (1')

[0046] ΔIref1 / ΔT=(1 / 50K)*(k / q)*(ln8)=3.6[nA / °C]…Equation (2')

[0047] Iref2=(VBE_Bip3) / 900K=770[nA]…Formula (4')

[0048] ΔIref2 / ΔT=(ΔVBE / ΔT) / 900K=-1.62[mV / ℃] / 900[kΩ]=-1.8[nA / ℃]…Equation (5')

[0049] Iref3=2*Iref1+4*Iref2=5[μA]…Formula (7')

[0050] ΔIref3 / ΔT=2*ΔIref1 / ΔT+4*ΔIref2 / ΔT=0[A / ℃]…Equation (8')

[0051] The result "(ΔVBE / ΔT)=-1.62 [mV / °C]" herein is set from the simulation result on the temperature coefficient of VBE in the case of "emitter current: IE=770 nA".

[0052] Since the temperature coefficient in equation (8') is 0, it is confirmed that a current that does not depend on temperature can be generated.

[0053] Figure 2 The simulation results under the setting condition (1) are shown. The horizontal axis represents temperature, and the vertical axis represents current. Item "C1" represents the current flowing between the source and drain of the MOS transistor MP6, in other words, the temperature dependence of "Iref1*4". Item "C2" represents the current flowing between the source and drain of the MOS transistor MP5, in other words, the temperature dependence of "Iref2*4". Item "C3" represents the temperature dependence of "Iref3". The vertically extended dotted line represents 25°C. The temperature of 25°C satisfies "Iref1*2=2[μA]", "Iref2*4=3[μA]", and "Iref3=5[μA]". It is found that Iref1 has a positive dependence on temperature, Iref2 has a negative dependence on temperature, and Iref3 has no dependence on temperature.

[0054] Second embodiment

[0055] Figure 3 2 is a circuit diagram of a semiconductor device 1a according to a second embodiment. The semiconductor device 1a generates a reference voltage based on a current Iref3, and the reference voltage does not depend on either temperature or power supply voltage VCC.

[0056] exist Figure 1 and Figure 3 In comparison, the current generator circuit 13 of the semiconductor device 1a further includes a resistor R3. One end of the resistor R3 is connected to the connection node between the MOS transistor MP5 and the MOS transistor MP6. The other end of the resistor R3 is connected to the ground voltage GND. When the current Iref3 flows through the resistor R3, a reference voltage Vref3 is generated at one end of the resistor R3.

[0057] The reference voltage Vref3 is expressed by the following equation (9), and its temperature coefficient "ΔVref3 / ΔT" is expressed by the following equation (10).

[0058] Vref3=Iref3*R3…Equation (9)

[0059] ΔVref3 / ΔT = (ΔIref3 / ΔT) * R3 … Formula (10)

[0060] As described above, by appropriately setting the terms "A" and "B" in equation (8), it is possible to realize the current Iref3 which has a temperature coefficient "ΔIref3 / ΔT" in the following equation (11) and does not depend on temperature.

[0061] ΔIref3 / ΔT = 0 … Equation (11)

[0062] It is found that "ΔVref3 / ΔT = 0" is achieved by substituting the equation (11) into the equation (10).

[0063] As described above, it is found that by appropriately selecting the resistance value of the resistor R3, a selectable reference voltage Vref that is compensated according to temperature and power supply voltage can be generated. In particular, a reference voltage Vref equal to or higher than 1.2V can be generated.

[0064] Next, a case where the following condition (2) is set in addition to the condition (1) will be specifically described.

[0065] Condition (2): R3 = 500 kΩ

[0066] The following equation (9') is derived by substituting condition (2) and Iref3 calculated by equation (7') into equation (9). Furthermore, the following equation (10') is derived by substituting "ΔIref3 / ΔT=0" in equation (11) into equation (10).

[0067] Vref3=Iref3*R3=5[μA]*500[kΩ]=2.5[V]…Equation (9')

[0068] ΔVref3 / ΔT=(ΔIref3 / ΔT)*R3=0*500[kΩ]=0[V / ℃]…Equation (10')

[0069] It was confirmed that a reference voltage Vref having a temperature coefficient of 0 in equation (10) and not dependent on temperature can be generated. Referring to equation (9'), it was confirmed that a reference voltage equal to or higher than 1.2V can be generated.

[0070] Figure 4 The simulation results for the case where conditions (1) and (2) are set are shown. The horizontal axis represents temperature, and the vertical axis represents voltage. Item "C4" represents the temperature dependency of reference voltage Vref. Reference voltage Vref is approximately 2.5V, which is equal to or greater than 1.2V. As can be seen from the simulation results, the second embodiment can generate a reference voltage that is independent of temperature and equal to or greater than 1.2V.

[0071] Next, refer to Figure 5 One of the effects of generating a selectable reference voltage that is independent of temperature and power supply voltage and equal to or greater than 1.2 V will be described. Negative feedback amplifier circuit 2 includes amplifier circuit 3 and feedback circuit 4. Feedback circuit 4 returns a portion of the voltage amplified by amplifier circuit 3 to the input of amplifier circuit 3 of the opposite phase. For the input voltage Vin and output voltage Vout of negative feedback amplifier circuit 2, the following equation (12) holds true.

[0072] Vout / Vin = A / (1 + β F * A) … Equation (12)

[0073] The term “β F ” represents the feedback rate of the feedback circuit 4, and the term “A” herein represents the gain of the amplifier circuit 3.

[0074] Generally, the term "A" is sufficiently larger than 1, and is equal to or larger than 1000 times. Therefore, the equation (12) can be transformed into the following equation (13).

[0075] Vout / Vin = A / (1 + β F * A) ≈ 1 / β F … Formula (13)

[0076] It is known that the term “β F " is larger, the distortion is lower, and the speed is higher. For example, if the reference voltage "Vref = 2.5V" in the second embodiment is provided as Vin to provide "Vout = 2.5[V]", the relationship "β F=1". On the other hand, if the reference voltage "Vref=1.25V" in the related art is provided as Vin, the relationship "β F =0.5” holds true.

[0077] Since the feedback amount β of the negative feedback amplifier circuit F can be set to be larger, and the second embodiment can achieve low distortion and high speed of the negative feedback amplifier circuit.

[0078] Third embodiment

[0079] Figure 6 3 is a circuit diagram of a semiconductor device 1b according to the third embodiment. The semiconductor device 1b generates a reference voltage that refers to a power supply voltage Vbat based on a current Iref3.

[0080] exist Figure 1 and Figure 6 In comparison, the semiconductor device 1b further includes a reference voltage generator circuit 14 that references the power supply voltage Vbat. The reference voltage generator circuit 14 includes an n-channel MOS transistor MN5 and a resistor R4. The current generator circuit 13 further includes an n-channel MOS transistor MN4.

[0081] MOS transistor MN4 is arranged between ground voltage GND and a connection node between MOS transistors MP3 and MP4. Resistor R4 and MOS transistor MN5 are connected in series between power supply voltage Vbat and ground voltage GND. Power supply voltage Vbat is also referred to as a second power supply voltage. The gates of MOS transistors MN4 and MN5 are connected to the drain of MOS transistor MN4. One end of resistor R4 is connected to power supply voltage Vbat, and a reference voltage Vref4 is generated at the other end of resistor R4.

[0082] For example, the power supply voltage Vbat is the voltage of a battery installed in a vehicle. MOS transistors MN4 and MN5 configure a current mirror circuit, and MOS transistor MN5 causes a mirror current Iref4 of current Iref3 to flow through resistor R4. Therefore, a reference voltage Vref4 is generated at the connection node between resistor R4 and MOS transistor MN5.

[0083] The reference voltage Vref4 is expressed by the following equation (14), and its temperature coefficient "ΔVref4 / ΔT" is expressed by the following equation (15).

[0084] Vref4 = Vbat – (Iref4 * R4) … Formula (14)

[0085] ΔVref4 / ΔT = -(ΔIref4 / ΔT) * R4 … Formula (15)

[0086] The term "Iref4" herein represents the mirror current of the aforementioned current Iref3. Since the relationship "ΔIref3 / ΔT = 0" in equation (11) holds, the relationship "ΔIref4 / ΔT = 0" also holds. Therefore, as can be seen from equation (15), the relationship "ΔVref4 / ΔT = 0" is achieved.

[0087] Therefore, the third embodiment can provide an optional reference voltage Vref4 that is temperature compensated and refers to a power supply voltage Vbat that is different from the power supply voltage VCC by appropriately selecting the resistor R4. The power supply voltage Vref4 is independent of the power supply voltage VCC.

[0088] Next, a case where the following condition (3) is set in addition to the condition (1) will be specifically described.

[0089] Condition (3): R4 = 200 [kΩ], Vbat = 12.5 [V]

[0090] The following equation (14') is derived by substituting condition (3) into equation (14). The following equation (15') is derived by substituting condition (3) into equation (15). Due to the relationship "Iref3 = 5 [μA]" in equation (7'), the relationship "Iref4 = 5 [μA]" is set.

[0091] Vref4=Vbat–(Iref4*R4)=12.5[V]-5[μA]*200[kΩ]=11.5[V]…Equation (14')

[0092] ΔVref4 / ΔT=-(ΔIref4 / ΔT)*R4=0*200[kΩ]=0...Formula (15')

[0093] It was confirmed that the reference voltage Vref4 can be generated, which has a temperature coefficient of 0 in the equation (15') and does not depend on the temperature.

[0094] Figure 7 The simulation results under the setting conditions (1) and (3) are shown. The horizontal axis represents temperature, and the vertical axis represents voltage. Item "C5" represents the power supply voltage Vbat, and item "C6" represents the temperature dependence of the reference voltage Vref. The power supply voltage Vbat is 12.5V, and the reference voltage Vref4 is approximately 11.5V. As can be seen from the simulation results, the third embodiment can generate a reference voltage Vref4 that is not dependent on temperature.

[0095] In the third embodiment, a mirror current Iref4 of a current Iref3 generated with reference to the ground voltage GND flows in a resistor R4 connected to the power supply voltage Vbat. Therefore, the third embodiment can generate a reference voltage Vref with reference to the power supply voltage Vbat.

[0096] Generally, in order to generate a reference voltage for the reference power supply voltage Vbat, in addition to a reference voltage source for the reference ground voltage GND, a reference voltage source for the reference power supply voltage Vbat is also required. In the third embodiment, since there is no need to prepare a reference voltage source for the reference power supply voltage Vbat, the circuit area and the consumed current can be reduced.

[0097] The reference voltage generator circuit 14 may be included in a semiconductor device that is different from the semiconductor device that includes the current generator circuits 11, 12, and 13. For example, the semiconductor device that includes the reference voltage generator circuit 14 may be an intelligent power device (IPD) that includes a power MOSFET, and the semiconductor device that includes the current generator circuits 11, 12, and 13 may be an MCU that controls the IPD. The IPD may include a controller circuit that is connected to a battery power source (Vbat) and controls the power MOSFET. If a reference voltage is necessary for the controller circuit in the IPD, the IPD may need to include a reference voltage source (such as a bandgap reference circuit) that is referenced to the battery power source Vbat. In this case, the reference voltage source included in the IPD may need to be made of a high-voltage withstand device. However, by using a simpler circuit configuration than a bandgap reference circuit as the reference potential generator circuit included in the IPD, the third embodiment can generate a reference voltage that is referenced to the battery power source Vbat. Therefore, the circuit area and current consumed by the IPD can be reduced.

[0098] In the foregoing, the invention made by the inventors of this application has been specifically described based on the embodiments. However, the present invention is not limited to the foregoing embodiments, and various modifications can be made within the scope of the present invention.

[0099] For example, the voltage regulator according to the embodiment can be configured so that the conductivity type (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. is interchanged. Therefore, if either the n-type or the p-type is set as the first conductivity type and the other conductivity type is set as the second conductivity type, the first conductivity type can be the p-type and the second conductivity type can be the n-type, and conversely, the first conductivity type can be the n-type and the second conductivity type can be the p-type.

Claims

1. A semiconductor device comprising: a first current generator circuit that generates a first current having a positive temperature coefficient and being independent of a first power supply voltage; a second current generator circuit that generates a second current having a negative temperature coefficient and that is independent of the first power supply voltage; as well as A third current generator circuit generates a third current based on the first current and the second current, the third current being independent of neither the temperature nor the first power supply voltage.

2. The semiconductor device according to claim 1, wherein the third current is generated by synthesizing a current copied from the first current at a first mirror ratio and a current copied from the second current at a second mirror ratio, and The first mirror ratio and the second mirror ratio are set so that a temperature coefficient of the third current is zero.

3. The semiconductor device according to claim 1, A reference voltage is formed based on the third current, and the reference voltage is independent of neither the temperature nor the first supply voltage.

4. The semiconductor device according to claim 3, The reference voltage is greater than 1.2V.

5. The semiconductor device according to claim 3, further comprising: The negative feedback amplifier circuit amplifies the reference voltage.

6. The semiconductor device according to claim 5, The feedback rate of the negative feedback amplifier circuit is greater than 0.

5.

7. The semiconductor device according to claim 3, further comprising: a current mirror circuit causing a current copied from the third current to flow to a resistor, one end of the resistor being connected to a second power supply voltage, The reference voltage is generated at the other end of the resistor.

8. The semiconductor device according to claim 7, The second power supply voltage is a battery voltage.

9. The semiconductor device according to claim 1, The second current is generated based on a voltage between a base and an emitter of the bipolar transistor.

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