Clock duty ratio adjusting circuit

Abstract

The invention discloses a clock duty ratio adjusting circuit. The clock duty ratio adjusting circuit comprises an integrator, an adjusting control unit, a charging and discharging unit, a first shaping unit and a phase detection unit. The integrator is used for generating a control signal based on a clock output signal and a reference signal; the adjusting control unit is used for generating an adjusting signal based on power supply voltage and a control signal; the charging and discharging unit is used for generating a charging and discharging signal based on the clock input signal and adjusting the charging and discharging signal based on the adjusting signal; the first shaping unit is used for shaping the charging and discharging signal to generate a shaped signal; the phase detection unit is used for performing phase detection on the clock input signal and the shaping signal to generate a clock output signal. According to the clock duty ratio adjusting circuit, clock signals which are stable in duty ratio and can be well subjected to self-adaptive adjustment can be obtained.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a clock duty cycle adjustment circuit. Background Art

[0002] In high-speed A / D converters, DDR systems using dual-edge sampling, or high-speed digital circuits, there are very high requirements for the duty cycle of the clock signal.

[0003] However, the clock signal generated by the existing clock generation circuit has a duty cycle that is easily interfered with, has poor stability and poor adaptability, and also has a complex circuit structure and high cost.

[0004] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0005] An object of the present invention is to provide a clock duty cycle adjustment circuit, which can provide a stable and adaptively adjustable clock duty cycle.

[0006] To achieve the above-mentioned object, a specific embodiment of the present invention provides a technical solution as follows: a clock duty cycle adjustment circuit, configured to generate a clock output signal based on a clock input signal, the clock duty cycle adjustment circuit comprising:

[0007] an integrator for generating a control signal based on the clock output signal and a reference signal;

[0008] a regulation control unit connected to the power supply voltage and the integrator, and configured to generate a regulation signal based on the power supply voltage and the control signal;

[0009] a charge and discharge unit, configured to generate a charge and discharge signal based on a clock input signal, wherein the charge and discharge unit is connected to an adjustment control unit to adjust the charge and discharge signal based on the adjustment signal;

[0010] A first shaping unit, connected to the charge and discharge unit to shape the charge and discharge signal to generate a shaped signal; and

[0011] The phase detection unit is used to perform phase detection on the clock input signal and the shaped signal to generate a clock output signal.

[0012] In one or more embodiments of the present invention, the clock duty cycle adjustment circuit further includes a signal processing unit connected to the regulation control unit and configured to perform power jitter elimination processing on a signal generated by the power supply voltage on the regulation control unit.

[0013] In one or more embodiments of the present invention, the signal processing unit includes a filtering unit, and the filtering unit is used to filter the signal generated by the power supply voltage on the regulation control unit.

[0014] In one or more embodiments of the present invention, the signal processing unit includes a jitter compensation unit, which is configured to generate a compensation signal that varies in an anti-phase with the power supply voltage jitter to compensate the adjustment control unit.

[0015] In one or more embodiments of the present invention, the signal processing unit includes a filtering unit and a jitter compensation unit. The filtering unit is used to filter the signal generated by the power supply voltage on the regulation control unit, and the jitter compensation unit is used to generate a compensation signal that changes in antiphase with the power supply voltage jitter to compensate the regulation control unit.

[0016] In one or more embodiments of the present invention, the jitter compensation unit includes a fourth inverter, a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, and a coupling resistor, wherein a first end of the first coupling capacitor is connected to a power supply voltage, a second end of the first coupling capacitor is connected to an input end of the fourth inverter, a first end of the second coupling capacitor, and a first end of the coupling resistor, a second end of the second coupling capacitor and a second end of the coupling resistor are connected to an output end of the fourth inverter and a first end of the third coupling capacitor, and a second end of the third coupling capacitor is connected to the adjustment control unit; or

[0017] The jitter compensation unit includes a fourth inverter, a first coupling capacitor, a third coupling capacitor, and a coupling resistor. A first end of the first coupling capacitor is connected to a power supply voltage, a second end of the first coupling capacitor is connected to an input end of the fourth inverter and a first end of the coupling resistor, a second end of the coupling resistor is connected to an output end of the fourth inverter and a first end of the third coupling capacitor, and a second end of the third coupling capacitor is connected to the adjustment control unit.

[0018] In one or more embodiments of the present invention, the regulation control unit includes a first current source, a first transistor and a first current mirror, wherein the first end of the first current source is connected to the power supply voltage, the second end of the first current source is connected to the second end of the first transistor and is connected to the first current mirror and the ground voltage through the filtering unit, the control end of the first transistor is used to receive a control signal, the first end of the first transistor is connected to the ground voltage, and the first current mirror is also connected to the charge and discharge unit.

[0019] In one or more embodiments of the present invention, the regulation control unit includes a first current source, a first transistor and a first current mirror, wherein the first end of the first current source is connected to the power supply voltage, the second end of the first current source is connected to the second end of the first transistor and the first current mirror, the control end of the first transistor is used to receive a control signal, the first end of the first transistor is connected to the ground voltage, and the first current mirror is connected to the jitter compensation unit and the charge and discharge unit at the same time.

[0020] In one or more embodiments of the present invention, the regulation control unit includes a first current source, a first transistor and a first current mirror, wherein the first end of the first current source is connected to the power supply voltage, the second end of the first current source is connected to the second end of the first transistor and is connected to the first current mirror and the ground voltage through the filtering unit, the control end of the first transistor is used to receive a control signal, the first end of the first transistor is connected to the ground voltage, and the first current mirror is simultaneously connected to the jitter compensation unit and the charge and discharge unit.

[0021] In one or more embodiments of the present invention, the regulation control unit includes a first transistor and a first current mirror, the first end of the first transistor is connected to the power supply voltage through a filtering unit, the second end of the first transistor is connected to the first current mirror, the control end of the first transistor is used to receive a control signal, and the first current mirror is also connected to the charging and discharging unit.

[0022] In one or more embodiments of the present invention, the regulation control unit includes a first transistor and a first current mirror, the first end of the first transistor is connected to the power supply voltage, the second end of the first transistor is connected to the first current mirror, the control end of the first transistor is used to receive a control signal, and the first current mirror is simultaneously connected to the jitter compensation unit and the charge and discharge unit.

[0023] In one or more embodiments of the present invention, the regulation control unit includes a first transistor and a first current mirror, the first end of the first transistor is connected to the power supply voltage through a filtering unit, the second end of the first transistor is connected to the first current mirror, the control end of the first transistor is used to receive a control signal, and the first current mirror is simultaneously connected to the jitter compensation unit and the charge and discharge unit.

[0024] In one or more embodiments of the present invention, the regulating control unit further includes a filter capacitor, a first end of the filter capacitor is connected to the second end of the first transistor, and a second end of the filter capacitor is connected to the ground voltage.

[0025] In one or more embodiments of the present invention, the charge and discharge unit includes an inverting unit and a first capacitor, the control end of the inverting unit is used to receive a clock input signal, the output end of the inverting unit is connected to the first end of the first capacitor and the first shaping unit, the second end of the first capacitor is connected to the ground voltage, the inverting unit is simultaneously connected to the power supply voltage and the regulation control unit, and the inverting unit adjusts the magnitude of the current drawn from the first capacitor based on the regulation signal.

[0026] In one or more embodiments of the present invention, the clock duty cycle adjustment circuit also includes a first pulse generating unit and / or a second pulse generating unit, the input end of the first pulse generating unit is used to receive a clock input signal, the output end of the first pulse generating unit is connected to the charge and discharge unit, the first pulse generating unit is used to generate a first pulse signal based on the clock input signal, the charge and discharge unit is used to generate a charge and discharge signal based on the first pulse signal, the input end of the second pulse generating unit is connected to the first shaping unit, the output end of the second pulse generating unit is connected to the phase detection unit, the second pulse generating unit is used to generate a second pulse signal based on the shaping signal, and the phase detection unit is used to perform phase detection on the clock input signal and the second pulse signal to generate a clock output signal.

[0027] In one or more embodiments of the present invention, the clock duty cycle adjustment circuit further includes a switching unit and a frequency detection unit, wherein the frequency detection unit is connected to the adjustment control unit to generate a characterization signal representing the frequency of the clock input signal based on a signal on the adjustment control unit, the first input end of the switching unit is used to receive the clock input signal, the second input end of the switching unit is connected to the output end of the phase detection unit, the selection control end of the switching unit is used to receive the characterization signal, and the output end of the switching unit is used to generate a clock output signal.

[0028] In one or more embodiments of the present invention, the frequency detection unit includes a second current source, a second transistor, a fourth capacitor, and a second shaping unit, wherein the first end of the second current source is connected to the power supply voltage, the second end of the second current source is connected to the second end of the second transistor, the first end of the fourth capacitor, and the input end of the second shaping unit, the control end of the second transistor is connected to the regulation control unit, the first end of the second transistor and the second end of the fourth capacitor are connected to the ground voltage, and the output end of the second shaping unit is used to output the characterization signal.

[0029] In one or more embodiments of the present invention, the frequency detection unit further includes a burr elimination circuit, which is configured to eliminate burrs on the signal output by the second shaping unit to generate a characterization signal.

[0030] In one or more embodiments of the present invention, the glitch elimination circuit includes a third transistor, a current unit, a fifth capacitor, and a third shaping unit, wherein the control terminal of the third transistor is connected to the output terminal of the second shaping unit, the second terminal of the third transistor is connected to the current unit, the first terminal of the fifth capacitor, and the input terminal of the third shaping unit, the first terminal of the third transistor is connected to the ground voltage, the second terminal of the fifth capacitor is connected to the ground voltage, and the output terminal of the third shaping unit is used to output the characterization signal; or

[0031] The glitch elimination circuit includes a second inverter, a third transistor, a current unit, a fifth capacitor, a third shaping unit and a third inverter, wherein the input end of the second inverter is connected to the output end of the second shaping unit, the output end of the second inverter is connected to the control end of the third transistor, the second end of the third transistor is connected to the current unit, the first end of the fifth capacitor and the input end of the third shaping unit, the first end of the third transistor is connected to the ground voltage, the second end of the fifth capacitor is connected to the ground voltage, the output end of the third shaping unit is connected to the input end of the third inverter, and the output end of the third inverter is used to output a characterization signal.

[0032] In one or more embodiments of the present invention, the frequency detection unit further includes a synchronous stabilization circuit, which is configured to synchronize the signal output by the second shaping unit to generate a characterization signal based on the control of a clock input signal.

[0033] In one or more embodiments of the present invention, the synchronous stabilization circuit includes a first D flip-flop and a second D flip-flop, which are connected in series and perform signal synchronous transmission based on the control of a clock control signal.

[0034] Compared with the prior art, the clock duty cycle adjustment circuit of the present invention generates a charge and discharge signal based on a clock input signal through a charge and discharge unit, shapes the charge and discharge signal to generate a shaped signal, performs phase detection on the clock input signal and the shaped signal through a phase detection unit to generate a clock output signal, generates a control signal based on the clock output signal and a reference signal through an integrator, generates an adjustment signal based on a power supply voltage and a control signal through an adjustment control unit, and adjusts the charge and discharge signal based on the adjustment signal, thereby obtaining a clock signal with a stable duty cycle and capable of good adaptive adjustment.

[0035] The clock duty cycle adjustment circuit of the present invention can effectively reduce the influence of power supply voltage jitter on the duty cycle of the clock output signal through the signal processing unit;

[0036] The clock duty cycle adjustment circuit of the present invention can automatically turn off the output of the clock duty cycle adjustment loop when the frequency of the clock input signal is low through a switching unit in conjunction with a frequency detection unit, and can output the clock output signal without burrs to improve working stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 This is a circuit schematic diagram of the clock duty cycle adjustment circuit in Example 1 of the present invention.

[0039] Figure 2 This is a circuit diagram of the hysteresis trigger in Example 1 of the present invention.

[0040] Figure 3 This is a circuit schematic diagram of the burr elimination circuit in Example 1 of the present invention.

[0041] Figure 4 1 is a waveform diagram of signals at each node of the clock duty cycle adjustment circuit under an ideal state in the first embodiment of the present invention.

[0042] Figure 5 1 is a waveform diagram of signals at various nodes of the clock duty cycle adjustment circuit when no signal processing unit is provided and the power supply voltage jitters in the first embodiment of the present invention.

[0043] Figure 6 This is a circuit schematic diagram of a clock duty cycle adjustment circuit in a second embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0045] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0046] In the detailed description of the specification, reference is made to the accompanying drawings forming a part hereof, wherein like reference numerals designate like parts throughout, and wherein exemplary embodiments that may be implemented are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. Therefore, the following detailed description should not be construed in a limiting sense.

[0047] The various operations in the specification may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0048] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0049] Various components and devices may be referred to or shown in the singular form in this document (for example, "MOS tube", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element referred to in the singular form may include multiple such elements according to the teachings of this document.

[0050] The description uses the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which can each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of this application are synonymous.

[0051] Example 1

[0052] like Figure 1As shown, a clock duty cycle adjustment circuit in one embodiment of the present invention is used to generate a clock output signal based on a clock input signal. The clock duty cycle adjustment circuit includes: a first pulse generating unit 10, a charging and discharging unit 20, a first shaping unit 30, a second pulse generating unit 40, a phase detection unit 50, an integrator 60, an adjustment control unit 70, a signal processing unit, a frequency detection unit 80 and a switching unit 90.

[0053] The input end of the first pulse generating unit 10 is used to receive the clock input signal CLKIN. The output end of the first pulse generating unit 10 is connected to the charge-discharge unit 20 and the phase detection unit 50. The first pulse generating unit 10 is used to generate a first pulse signal V1 based on the clock input signal CLKIN, and the charge-discharge unit 20 is used to generate a charge-discharge signal V2 based on the first pulse signal V1. In other embodiments, the first pulse generating unit 10 may not be provided.

[0054] The first shaping unit 30 is connected to the charge-discharge unit 20 to shape the charge-discharge signal V2 to generate a shaped signal V3. The input end of the second pulse generating unit 40 is connected to the first shaping unit 30, and the output end of the second pulse generating unit 40 is connected to the phase detection unit 50. The second pulse generating unit 40 is configured to generate a second pulse signal V4 based on the shaped signal V3. The phase detection unit 50 is configured to perform phase detection on the first pulse signal V1 and the second pulse signal V4. In other embodiments, the second pulse generating unit 40 may not be provided.

[0055] The integrator 60 is configured to generate a control signal V5 based on the signal output by the phase detection unit 50 and the reference signal VREF. A regulation control unit 70 is connected to the power supply voltage VDD and the integrator 60 and is configured to generate a regulation signal based on the power supply voltage VDD and the control signal V5. The charge-discharge unit 20 is connected to the regulation control unit 70 to regulate the charge-discharge signal V2 based on the regulation signal. A signal processing unit is connected to the regulation control unit 70 and is configured to perform power supply jitter elimination processing on the current and voltage signals generated by the power supply voltage VDD on the regulation control unit 70.

[0056] The frequency detection unit 80 is connected to the regulation control unit 70 to generate a characterization signal representing the frequency of the clock input signal CLKIN based on the voltage signal on the regulation control unit 70. The first input end of the switching unit 90 is used to receive the clock input signal CLKIN, the second input end of the switching unit 90 is connected to the output end of the phase detection unit 50, the selection control end of the switching unit 90 is used to receive the characterization signal, and the output end of the switching unit 90 is used to generate the clock output signal CLKOUT.

[0057] like Figure 1As shown, the first pulse generating unit 10 includes a first inverter INV1 and a first NAND gate NAND1. The input of the first inverter INV1 is connected to the first input of the first NAND gate NAND1 and simultaneously receives the clock input signal CLKIN. The second input of the first NAND gate NAND1 is connected to the output of the first inverter INV1, and the output of the first NAND gate NAND1 outputs the first pulse signal V1. In one embodiment, the first pulse signal V1 is a negative pulse signal generated by the first pulse generating unit 10 based on the rising edge of the clock input signal CLKIN. In other embodiments, the first pulse generating unit 10 may be another circuit that generates positive or negative pulse signals.

[0058] like Figure 1 As shown, the charge and discharge unit 20 includes an inverting unit and a first capacitor C1. The control end of the inverting unit is used to receive the first pulse signal V1. The output end of the inverting unit is connected to the first end of the first capacitor C1 and the first shaping unit 30. The second end of the first capacitor C1 is connected to the ground voltage.

[0059] In one embodiment, the inverting unit includes a first switch transistor MP1 and a second switch transistor MN1. A first terminal of the first switch transistor MP1 is connected to a power supply voltage VDD. A control terminal of the first switch transistor MP1 and a control terminal of the second switch transistor MN1 are connected to an output terminal of a first NAND gate NAND1. A second terminal of the first switch transistor MP1 and a second terminal of the second switch transistor MN1 are connected to a first terminal of a first capacitor C1. A first terminal of the second switch transistor MN1 is connected to an adjustment control unit 70. The magnitude of the adjustment signal can adjust the magnitude of the current drawn from the first capacitor C1 through a channel path of the second switch transistor MN1.

[0060] In one embodiment, the first shaping unit 30 includes a first Schmitt trigger SMT1, the input end of the first Schmitt trigger SMT1 is connected to the first end of the first capacitor C1, and the output end of the first Schmitt trigger SMT1 is used to output the shaping signal V3. Figure 2As shown, the first Schmitt trigger SMT1 includes a first MOS transistor MO1, a second MOS transistor MO2, a third MOS transistor MO3, a fourth MOS transistor MO4, a fifth MOS transistor MO5, and a sixth MOS transistor MO6. The first end of the first MOS transistor MO1 is connected to the power supply voltage VDD, the second end of the first MOS transistor MO1 is connected to the first end of the second MOS transistor MO2 and the first end of the fifth MOS transistor MO5, the second end of the second MOS transistor MO2 is connected to the second end of the third MOS transistor MO3, the control end of the fifth MOS transistor MO5, and the control end of the sixth MOS transistor MO6 to form the output end of the first Schmitt trigger SMT1, the first end of the third MOS transistor MO3 is connected to the second end of the fourth MOS transistor MO4 and the first end of the sixth MOS transistor MO6, the second end of the sixth MOS transistor MO6 is connected to the power supply voltage VDD, the first end of the fourth MOS transistor MO4 is connected to the ground voltage, and the control ends of the first MOS transistor MO1, the second MOS transistor MO2, the third MOS transistor MO3, and the fourth MOS transistor MO4 are connected to form the input end of the first Schmitt trigger SMT1. In other embodiments, the first Schmitt trigger SMT1 can have other circuit structures.

[0061] like Figure 1 As shown, the second pulse generating unit 40 includes a second inverter INV2 and a second NAND gate NAND2. The input of the second inverter INV2 is connected to the first input of the second NAND gate NAND2 and simultaneously receives the shaped signal V3. The second input of the second NAND gate NAND2 is connected to the output of the second inverter INV2, and the output of the second NAND gate NAND2 outputs the second pulse signal V4. In one embodiment, the second pulse signal V4 is a negative pulse signal generated by the second pulse generating unit 40 based on the rising edge of the shaped signal V3. In other embodiments, the second pulse generating unit 40 may be another circuit that generates a positive or negative pulse signal.

[0062] like Figure 1 As shown, the phase detection unit 50 includes a third NAND gate NAND3 and a fourth NAND gate NAND4. The first input of the third NAND gate NAND3 is used to receive the first pulse signal V1, the second input of the third NAND gate NAND3 is connected to the output of the fourth NAND gate NAND4, the first input of the fourth NAND gate NAND4 is used to receive the second pulse signal V4, and the second input of the fourth NAND gate NAND4 is connected to the output of the third NAND gate NAND3 to form the output of the phase detection unit 50. In other embodiments, the phase detection unit 50 may be other circuits.

[0063] like Figure 1As shown, integrator 60 includes a second capacitor C2, a first resistor R1, and an amplifier AMP. The first end of first resistor R1 is used to receive the signal output by phase detection unit 50. The second end of first resistor R1 is connected to the first input end of amplifier AMP and the first end of second capacitor C2. The second input end of amplifier AMP is used to receive reference signal VREF. The second end of second capacitor C2 is connected to the output end of amplifier AMP to generate control signal V5. In one embodiment, the first input end of amplifier AMP is a negative input end, and the second input end of amplifier AMP is a positive input end. In other embodiments, the first input end of amplifier AMP is a positive input end, and the second input end of amplifier AMP is a negative input end.

[0064] In one embodiment, the signal processing unit includes a filtering unit and a jitter compensation unit. The filtering unit is configured to filter the current signal generated by the power supply voltage VDD on the regulation control unit 70, and the jitter compensation unit is configured to generate a compensation signal that varies in antiphase with the jitter of the power supply voltage VDD to compensate for the voltage signal on the regulation control unit 70. Specifically, the second end of the first current source I1 is connected to the second end of the first transistor M1 and is connected to the first current mirror and the ground voltage through the filtering unit. The first current mirror is also connected to the charge and discharge unit 20 and is connected to the power supply voltage VDD through the jitter compensation unit. In other embodiments, the filtering unit or the jitter compensation unit may not be provided.

[0065] like Figure 1 As shown, the regulation control unit 70 includes a first current source I1, a first transistor M1 and a first current mirror. The first end of the first current source I1 is connected to the power supply voltage VDD, the second end of the first current source I1 is connected to the second end of the first transistor M1 and is connected to the first current mirror and the ground voltage through the filtering unit. At this time, the filtering unit filters the current signal flowing into the first current mirror; the control end of the first transistor M1 is used to receive the control signal V5, the first end of the first transistor M1 is connected to the ground voltage, and the first current mirror is connected to the jitter compensation unit and the charge and discharge unit 20 at the same time. At this time, the jitter compensation unit generates a compensation signal that changes in antiphase with the power supply voltage VDD to compensate for the voltage signal on the first current mirror.

[0066] In one embodiment, the first current mirror includes a fourth transistor M4 and a fifth transistor M5. The control terminal and the second terminal of the fourth transistor M4 are connected to the filtering unit and the control terminal of the fifth transistor M5. The first terminal of the fourth transistor M4 and the first terminal of the fifth transistor M5 are connected to the ground voltage. The second terminal of the fifth transistor M5 is connected to the first terminal of the second switch MN1. The control terminal of the fifth transistor M5 is connected to the jitter compensation unit. In other embodiments, the first current mirror may also adopt other circuit structures.

[0067] like Figure 1 As shown, the filtering unit includes a second resistor R2 and a third capacitor C3. The first end of the second resistor R2 is connected to the second end of the first current source I1 of the regulation control unit 70, the second end of the second resistor R2 is connected to the control end of the fourth transistor M4 of the first current mirror, the first end of the third capacitor C3 is connected to the second end of the second resistor R2, and the second end of the third capacitor C3 is connected to the ground voltage. In other embodiments, the filtering unit may also adopt other circuit structures.

[0068] like Figure 1 As shown, the jitter compensation unit includes a first inverter N1, a first coupling capacitor Cc1, a second coupling capacitor Cc2, a third coupling capacitor Cc3, and a coupling resistor Rr. The first end of the first coupling capacitor Cc1 is connected to the power supply voltage VDD, the second end of the first coupling capacitor Cc1 is connected to the input of the first inverter N1, the first end of the second coupling capacitor Cc2, and the first end of the coupling resistor Rr. The second end of the second coupling capacitor Cc2 and the second end of the coupling resistor Rr are connected to the output of the first inverter N1 and the first end of the third coupling capacitor Cc3. The second end of the third coupling capacitor Cc3 is connected to the control terminal of the fifth transistor M5 of the first current mirror. The first coupling capacitor Cc1 and the third coupling capacitor Cc3 are used for AC transmission, the second coupling capacitor Cc2 is used to improve circuit stability, and the coupling resistor Rr is used to establish a static operating point. In other embodiments, the second coupling capacitor Cc2 may not be provided. In other embodiments, the jitter compensation unit may also adopt other circuit structures.

[0069] like Figure 1 As shown, the frequency detection unit 80 includes a second current source I2, a second transistor M2, a fourth capacitor C4, a second shaping unit, a glitch elimination circuit, and a synchronous stabilization circuit. The first end of the second current source I2 is connected to the power supply voltage VDD, the second end of the second current source I2 is connected to the second end of the second transistor M2, the first end of the fourth capacitor C4, and the input end of the second shaping unit. The control end of the second transistor M2 is connected to the control end of the fourth transistor M4 of the regulation control unit 70, and the first end of the second transistor M2 and the second end of the fourth capacitor C4 are connected to the ground voltage. The glitch elimination circuit is used to eliminate glitch in the signal output by the second shaping unit, and the synchronous stabilization circuit is used to synchronize the signal output by the glitch elimination circuit to generate the characteristic signal DCC_IND based on the control of the clock input signal CLKIN. In one embodiment, the second shaping unit includes a second hysteresis flip-flop SMT2. In other embodiments, the frequency detection unit 80 may also adopt other circuit structures.

[0070] like Figure 3As shown, the glitch elimination circuit includes a second inverter N2, a third transistor M3, a current unit, a fifth capacitor C5, a third shaping unit, and a third inverter N3. The input end of the second inverter N2 is connected to the output end of the second shaping unit, the output end of the second inverter N2 is connected to the control end of the third transistor M3, the second end of the third transistor M3 is connected to the current unit, the first end of the fifth capacitor C5, and the input end of the third shaping unit, the first end of the third transistor M3 is connected to the ground voltage, the second end of the fifth capacitor C5 is connected to the ground voltage, the output end of the third shaping unit is connected to the input end of the third inverter N3, and the output end of the third inverter N3 is used to output the characterization signal. In other embodiments, based on the different high and low levels of the output signal of the second shaping unit, the second inverter N2 and the third inverter N3 may not be provided, and the glitch elimination circuit may also adopt other circuit structures.

[0071] In one embodiment, the current unit includes a current mirror formed by a sixth transistor M6 and a seventh transistor M7, and a third resistor R3. The first end of the sixth transistor M6 and the first end of the seventh transistor M7 are connected to the power supply voltage VDD. The control end of the sixth transistor M6 is connected to the control end of the seventh transistor M7, the second end of the seventh transistor M7, and the first end of the third resistor R3. The second end of the third resistor R3 is connected to the ground voltage. The second end of the sixth transistor M6 is connected to the second end of the third transistor M3 and the first end of the fifth capacitor C5. In other embodiments, the current unit may also adopt other circuit structures.

[0072] In one embodiment, the third shaping unit includes a third hysteresis trigger SMT3. The structures of the third hysteresis trigger SMT3 and the second hysteresis trigger SMT2 can be the same as the structure of the first hysteresis trigger SMT1. In other embodiments, the third hysteresis trigger SMT3 and the second hysteresis trigger SMT2 can also have other circuit structures. In other embodiments, the third shaping unit can also adopt other circuit structures.

[0073] like Figure 1 As shown, the synchronous stabilization circuit includes a first D flip-flop DFF1 and a second D flip-flop DFF2, which are connected in series to the output terminal of the glitch elimination circuit. The clock control terminals of the first and second D flip-flops DFF1 and DFF2 are both configured to receive a clock input signal CLKIN and to synchronously transmit signals based on the control of the clock input signal CLKIN to generate the characteristic signal DCC_IND. In other embodiments, the synchronous stabilization circuit may also employ other circuit structures.

[0074] like Figure 1As shown, the switching unit 90 includes a selector MUX1. A first input terminal of the selector MUX1 is used to receive the clock input signal CLKIN. A second input terminal of the selector MUX1 is connected to the output terminal of the phase detection unit 50. A selection control terminal of the selector MUX1 is used to receive the characterization signal DCC_IND. The output terminal of the switching unit 90 is used to generate the clock output signal CLKOUT. In other embodiments, the switching unit 90 may also adopt other circuit structures.

[0075] In one embodiment, the first switch transistor MP1, the first MOS transistor MO1, the second MOS transistor MO2, and the fifth MOS transistor MO5 are P-channel MOS transistors; the second switch transistor MN1, the third MOS transistor MO3, the fourth MOS transistor MO4, the sixth MOS transistor MO6, the first transistor M1, the fourth transistor M4, the fifth transistor M5, the second transistor M2, the third transistor M3, the sixth transistor M6, and the seventh transistor M7 are N-channel MOS transistors. In other embodiments, the first switch transistor MP1, the first MOS transistor MO1, the second MOS transistor MO2, and the fifth MOS transistor MO5 may be N-channel MOS transistors; the second switch transistor MN1, the third MOS transistor MO3, the fourth MOS transistor MO4, the sixth MOS transistor MO6, the first transistor M1, the fourth transistor M4, the fifth transistor M5, the second transistor M2, the third transistor M3, the sixth transistor M6, and the seventh transistor M7 may be P-channel MOS transistors.

[0076] The first end of the first switch transistor MP1, the first end of the first MOS transistor MO1, the first end of the second MOS transistor MO2, the first end of the fifth MOS transistor MO5, the first end of the second switch transistor MN1, the first end of the third MOS transistor MO3, the first end of the fourth MOS transistor MO4, the first end of the sixth MOS transistor MO6, the first end of the first transistor M1, the first end of the fourth transistor M4, the first end of the fifth transistor M5, the first end of the second transistor M2, the first end of the third transistor M3, the first end of the sixth transistor M6 and the first end of the seventh transistor M7 are source electrodes; the second end of the first switch transistor MP1, the second end of the first MOS transistor MO1, the second end of the second MOS transistor MO2, the second end of the fifth MOS transistor MO5, the second end of the second switch transistor MN1, the second end of the third MOS transistor MO3, the second end of the fourth MOS transistor MO4, the first end of the sixth transistor M6 and the first end of the seventh transistor M7 are source electrodes; The second end of the MOS transistor MO6, the second end of the first transistor M1, the second end of the fourth transistor M4, the second end of the fifth transistor M5, the second end of the second transistor M2, the second end of the third transistor M3, the second end of the sixth transistor M6, and the second end of the seventh transistor M7 are drains; the control end of the first switch transistor MP1, the control end of the first MOS transistor MO1, the control end of the second MOS transistor MO2, the control end of the fifth MOS transistor MO5, the control end of the second switch transistor MN1, the control end of the third MOS transistor MO3, the control end of the fourth MOS transistor MO4, the control end of the sixth MOS transistor MO6, the control end of the first transistor M1, the control end of the fourth transistor M4, the control end of the fifth transistor M5, the control end of the second transistor M2, the control end of the third transistor M3, the control end of the sixth transistor M6, and the control end of the seventh transistor M7 are gates.

[0077] like Figure 1 As shown, the reference signal VREF at the second input terminal of the amplifier AMP in the integrator 60 is typically set to half the power supply voltage VDD, so that the duty cycle of the clock output signal CLKOUT can ultimately be adjusted to 50%. The integrator 60 detects the high and low level widths of the clock output signal CLKOUT, thereby generating a control signal V5 related to the duty cycle of the clock output signal CLKOUT. The control regulation control unit 70 further controls the charge and discharge unit 20 to generate the required discharge delay, and then the phase detection unit 50 adjusts the duty cycle of the clock output signal CLKOUT until the output clock output signal CLKOUT has a duty cycle close to 50%. The ideal voltage waveforms of each node are shown as follows: Figure 4 shown.

[0078] Furthermore, when the duty cycle of the clock output signal CLKOUT is less than 50%, the control signal V5 output by the integrator 60 will gradually increase, the current on the first transistor M1 will decrease accordingly, and the current Imn2 (regulation signal) on the fifth transistor M5 will also gradually decrease, so that the discharge speed of the first capacitor C1 will slow down, that is, the falling edge of the charge and discharge signal V2 will gradually slow down, and the second pulse signal V4 will be generated after adding more delay, so that the duty cycle of the clock output signal CLKOUT generated by the phase detection unit 50 will increase to 50%.

[0079] When the duty cycle of the clock output signal CLKOUT is greater than 50%, the control signal V5 output by the integrator 60 will gradually decrease, the current on the first transistor M1 will increase accordingly, and the current Imn2 (regulation signal) on the fifth transistor M5 will also gradually increase, making the falling edge of the charge-discharge signal V2 gradually steeper, and the second pulse signal V4 will be generated after further delay reduction, so that the duty cycle of the clock output signal CLKOUT generated by the phase detection unit 50 is reduced to 50%.

[0080] However, if Figure 5 As shown, when the power supply voltage VDD fluctuates at a high frequency, the clock duty cycle adjustment loop cannot keep up with the change in the power supply voltage VDD in a timely manner. The output control signal V5 of the integrator 60 remains substantially unchanged while the power supply voltage VDD still fluctuates. The current Imn3 on the fourth transistor M4 and the current Imn2 on the fifth transistor M5 are related to the power supply voltage VCC, so that the slope of the falling edge of the final charge-discharge signal V2 is also related to the power supply voltage VCC, resulting in the duty cycle of the final clock output signal CLKOUT fluctuating with the power supply voltage VCC.

[0081] The output of the integrator 60 controls the gate of the N-channel first transistor M1 to cooperate with the fixed first current source I1, thereby improving the power supply rejection ratio PSRR and reducing the fluctuation of the current Imn2 caused by the jitter of the power supply voltage VDD.

[0082] The filtering unit, comprised of the second resistor R2 and the third capacitor C3, further filters out the effects of power supply voltage VDD jitter on the gate potential of the fifth transistor M5. Furthermore, a jitter compensation unit is provided, generating a signal with a phase opposite to the power supply voltage VDD jitter and outputting it to the gate of the fifth transistor M5 to further offset the effects of power supply voltage VDD jitter. In one embodiment, the jitter of the power supply voltage VDD is detected by the first inverter N1, the first coupling capacitor Cc1, the second coupling capacitor Cc2, the third coupling capacitor Cc3, and the coupling resistor Rr, generating a phase-inverted signal that is output to the gate of the fifth transistor M5 to offset the effects of high-frequency power supply jitter on the gate of the fifth transistor M5.

[0083] The frequency detection unit 80 is capable of detecting the frequency range of the clock input signal CLKIN. When the frequency of the clock input signal CLKIN is too low, the regulation control unit 70 controls the charge-discharge unit 20 to generate a greater delay. Therefore, the gate voltage VC of the fifth transistor M5 is relatively low, causing the current in the second transistor M2 to be less than the current of the preset second current source I2 (here, the current in the second transistor M2 can be considered to be generated by mirroring the current Imn2 (regulation signal) in the fifth transistor M5). This causes the voltage VD1 at the first end of the fourth capacitor C4 to be high, and the output voltage VD2 after passing through the second Schmitt trigger SMT2 and the glitch elimination circuit to be low. The characteristic signal DCC_IND after passing through the synchronous stabilization circuit is also low, controlling the selector MUX1 to select the clock input signal CLKIN for output. Because the synchronous stabilization circuit is composed of the first D-type flip-flop DFF1 and the second D-type flip-flop DFF2, the signal is transmitted step by step, and the selector MUX1 outputs the clock output signal CLKOUT without generating glitches during switching.

[0084] The present invention also provides a chip including the above-mentioned clock duty cycle adjustment circuit.

[0085] Example 2

[0086] like Figure 6 As shown, compared with the first embodiment, the structure of the adjustment control unit 70 and the connection method with the signal processing unit are improved in this embodiment.

[0087] Specifically, the signal processing unit includes a filtering unit and a jitter compensation unit, and the adjustment control unit 70 includes a first transistor M1 and a first current mirror.

[0088] A first end of the first transistor M1 is connected to the power supply voltage VDD via a filter unit. A second end of the first transistor M1 is connected to a first current mirror. A control end of the first transistor M1 is configured to receive a control signal V5. The first current mirror is also connected to the jitter compensation unit and the charge-discharge unit 20. In one embodiment, the first transistor M1 is a P-channel MOS transistor. The first end of the first transistor M1 is a source, the second end of the first transistor M1 is a drain, and the control end of the first transistor M1 is a gate.

[0089] The specific structure of the jitter compensation unit is the same as that in the first embodiment, and the connection position between the jitter compensation unit and the first current mirror is also the same, so it is not repeated here. In other embodiments, the filter unit or the jitter compensation unit may not be provided.

[0090] In one embodiment, the filtering unit includes a second resistor R2 and a third capacitor C3, a first end of the second resistor R2 is connected to the power supply voltage VDD, a second end of the second resistor R2 is connected to the first end of the third capacitor C3 and the first end of the first transistor M1, and a second end of the third capacitor C3 is connected to the ground voltage.

[0091] The regulating control unit 70 further includes a filter capacitor Cp, a first end of the filter capacitor Cp is connected to the second end of the first transistor M1, and a second end of the filter capacitor Cp is connected to the ground voltage. In other embodiments, the filter capacitor Cp may not be provided.

[0092] The filter unit formed by the second resistor R2 and the third capacitor C3 reduces the influence of the power supply voltage VDD jitter on the source potential of the first transistor M1, and the filter capacitor Cp reduces the influence of the power supply voltage VDD jitter on the gate potential of the fifth transistor M5, thereby reducing the influence on the charge and discharge unit 20.

[0093] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0094] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A clock duty cycle adjustment circuit, characterized in that: For generating a clock output signal based on a clock input signal, the clock duty cycle adjustment circuit comprises: an integrator for generating a control signal based on the clock output signal and a reference signal; a regulation control unit connected to the power supply voltage and the integrator, and configured to generate a regulation signal based on the power supply voltage and the control signal; a charge and discharge unit, configured to generate a charge and discharge signal based on a clock input signal, wherein the charge and discharge unit is connected to an adjustment control unit to adjust the charge and discharge signal based on the adjustment signal; A first shaping unit, connected to the charge and discharge unit to shape the charge and discharge signal to generate a shaped signal; and The phase detection unit is used to perform phase detection on the clock input signal and the shaped signal to generate a clock output signal.

2. The clock duty cycle adjustment circuit according to claim 1, wherein: The clock duty cycle adjustment circuit further includes a signal processing unit, which is connected to the adjustment control unit and is used to perform power supply jitter elimination processing on the signal generated by the power supply voltage on the adjustment control unit.

3. The clock duty cycle adjustment circuit according to claim 2, wherein: The signal processing unit includes a filtering unit, which is used to filter the signal generated by the power supply voltage on the regulating control unit.

4. The clock duty cycle adjustment circuit according to claim 2, wherein: The signal processing unit includes a jitter compensation unit, which is used to generate a compensation signal that changes in phase opposite to the power supply voltage jitter to compensate the adjustment control unit.

5. The clock duty cycle adjustment circuit according to claim 2, wherein: The signal processing unit includes a filtering unit and a jitter compensation unit. The filtering unit is used to filter the signal generated by the power supply voltage on the regulation control unit. The jitter compensation unit is used to generate a compensation signal that changes in antiphase with the power supply voltage jitter to compensate the regulation control unit.

6. The clock duty cycle adjustment circuit according to claim 4 or 5, characterized in that: The jitter compensation unit includes a fourth inverter, a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, and a coupling resistor, wherein a first end of the first coupling capacitor is connected to a power supply voltage, a second end of the first coupling capacitor is connected to an input end of the fourth inverter, a first end of the second coupling capacitor, and a first end of the coupling resistor, a second end of the second coupling capacitor and a second end of the coupling resistor are connected to an output end of the fourth inverter and a first end of the third coupling capacitor, and a second end of the third coupling capacitor is connected to the adjustment control unit; or The jitter compensation unit includes a fourth inverter, a first coupling capacitor, a third coupling capacitor, and a coupling resistor. A first end of the first coupling capacitor is connected to a power supply voltage, a second end of the first coupling capacitor is connected to an input end of the fourth inverter and a first end of the coupling resistor, a second end of the coupling resistor is connected to an output end of the fourth inverter and a first end of the third coupling capacitor, and a second end of the third coupling capacitor is connected to the adjustment control unit.

7. The clock duty cycle adjustment circuit according to claim 3, wherein: The regulation control unit includes a first current source, a first transistor and a first current mirror, wherein the first end of the first current source is connected to the power supply voltage, the second end of the first current source is connected to the second end of the first transistor and is connected to the first current mirror and the ground voltage through the filtering unit, the control end of the first transistor is used to receive a control signal, the first end of the first transistor is connected to the ground voltage, and the first current mirror is also connected to the charging and discharging unit.

8. The clock duty cycle adjustment circuit according to claim 4, wherein: The regulation control unit includes a first current source, a first transistor, and a first current mirror. The first end of the first current source is connected to the power supply voltage, the second end of the first current source is connected to the second end of the first transistor and the first current mirror, the control end of the first transistor is used to receive a control signal, the first end of the first transistor is connected to the ground voltage, and the first current mirror is connected to both the jitter compensation unit and the charge and discharge unit.

9. The clock duty cycle adjustment circuit according to claim 5, wherein: The regulation control unit includes a first current source, a first transistor, and a first current mirror. The first end of the first current source is connected to the power supply voltage, the second end of the first current source is connected to the second end of the first transistor and is connected to the first current mirror and the ground voltage through the filtering unit. The control end of the first transistor is used to receive a control signal, the first end of the first transistor is connected to the ground voltage, and the first current mirror is connected to the jitter compensation unit and the charge and discharge unit at the same time.

10. The clock duty cycle adjustment circuit according to claim 3, wherein: The regulation control unit includes a first transistor and a first current mirror, the first end of the first transistor is connected to the power supply voltage through a filtering unit, the second end of the first transistor is connected to the first current mirror, the control end of the first transistor is used to receive a control signal, and the first current mirror is also connected to the charging and discharging unit.

11. The clock duty cycle adjustment circuit according to claim 4, wherein: The regulation control unit includes a first transistor and a first current mirror, wherein the first end of the first transistor is connected to the power supply voltage, the second end of the first transistor is connected to the first current mirror, the control end of the first transistor is used to receive a control signal, and the first current mirror is connected to the jitter compensation unit and the charge and discharge unit at the same time.

12. The clock duty cycle adjustment circuit according to claim 5, wherein: The regulation control unit includes a first transistor and a first current mirror, wherein the first end of the first transistor is connected to the power supply voltage through the filtering unit, the second end of the first transistor is connected to the first current mirror, the control end of the first transistor is used to receive a control signal, and the first current mirror is simultaneously connected to the jitter compensation unit and the charge and discharge unit.

13. The clock duty cycle adjustment circuit according to any one of claims 7 to 12, wherein: The regulating control unit further includes a filter capacitor, a first end of the filter capacitor is connected to the second end of the first transistor, and a second end of the filter capacitor is connected to the ground voltage.

14. The clock duty cycle adjustment circuit according to claim 1, wherein: The charge and discharge unit includes an inverting unit and a first capacitor. The control end of the inverting unit is used to receive a clock input signal. The output end of the inverting unit is connected to the first end of the first capacitor and the first shaping unit. The second end of the first capacitor is connected to the ground voltage. The inverting unit is also connected to the power supply voltage and the regulation control unit. The inverting unit adjusts the amount of current drawn from the first capacitor based on the regulation signal.

15. The clock duty cycle adjustment circuit according to claim 1, wherein: The clock duty cycle adjustment circuit also includes a first pulse generating unit and / or a second pulse generating unit, the input end of the first pulse generating unit is used to receive a clock input signal, the output end of the first pulse generating unit is connected to the charge and discharge unit, the first pulse generating unit is used to generate a first pulse signal based on the clock input signal, the charge and discharge unit is used to generate a charge and discharge signal based on the first pulse signal, the input end of the second pulse generating unit is connected to the first shaping unit, the output end of the second pulse generating unit is connected to the phase detection unit, the second pulse generating unit is used to generate a second pulse signal based on the shaping signal, and the phase detection unit is used to perform phase detection on the clock input signal and the second pulse signal to generate a clock output signal.

16. The clock duty cycle adjustment circuit according to claim 1, wherein: The clock duty cycle adjustment circuit also includes a switching unit and a frequency detection unit. The frequency detection unit is connected to the adjustment control unit to generate a characterization signal representing the frequency of the clock input signal based on the signal on the adjustment control unit. The first input end of the switching unit is used to receive the clock input signal, the second input end of the switching unit is connected to the output end of the phase detection unit, the selection control end of the switching unit is used to receive the characterization signal, and the output end of the switching unit is used to generate a clock output signal.

17. The clock duty cycle adjustment circuit according to claim 16, wherein: The frequency detection unit includes a second current source, a second transistor, a fourth capacitor and a second shaping unit, wherein the first end of the second current source is connected to the power supply voltage, the second end of the second current source is connected to the second end of the second transistor, the first end of the fourth capacitor, and the input end of the second shaping unit, the control end of the second transistor is connected to the regulation control unit, the first end of the second transistor and the second end of the fourth capacitor are connected to the ground voltage, and the output end of the second shaping unit is used to output the characterization signal.

18. The clock duty cycle adjustment circuit according to claim 17, wherein: The frequency detection unit further includes a burr elimination circuit, which is used to eliminate burrs on the signal output by the second shaping unit to generate a characterization signal.

19. The clock duty cycle adjustment circuit according to claim 18, wherein: The burr elimination circuit includes a third transistor, a current unit, a fifth capacitor and a third shaping unit, wherein the control end of the third transistor is connected to the output end of the second shaping unit, the second end of the third transistor is connected to the current unit, the first end of the fifth capacitor and the input end of the third shaping unit, the first end of the third transistor is connected to the ground voltage, the second end of the fifth capacitor is connected to the ground voltage, and the output end of the third shaping unit is used to output the characterization signal; or The glitch elimination circuit includes a second inverter, a third transistor, a current unit, a fifth capacitor, a third shaping unit and a third inverter, wherein the input end of the second inverter is connected to the output end of the second shaping unit, the output end of the second inverter is connected to the control end of the third transistor, the second end of the third transistor is connected to the current unit, the first end of the fifth capacitor and the input end of the third shaping unit, the first end of the third transistor is connected to the ground voltage, the second end of the fifth capacitor is connected to the ground voltage, the output end of the third shaping unit is connected to the input end of the third inverter, and the output end of the third inverter is used to output a characterization signal.

20. The clock duty cycle adjustment circuit according to claim 17, wherein: The frequency detection unit further includes a synchronous stabilization circuit, which is used to synchronize the signal output by the second shaping unit based on the control of the clock input signal to generate a characterization signal.

21. The clock duty cycle adjustment circuit according to claim 20, wherein: The synchronous stabilization circuit includes a first D flip-flop and a second D flip-flop, which are connected in series and perform signal synchronous transmission based on the control of a clock control signal.

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