Driving circuit and method of SiC MOSFET device, and driving chip

Abstract

The invention discloses a driving circuit and method of a SiC MOSFET device and a driving chip. The driving circuit comprises a switching signal decomposition module, a level shift module and a multi-segment driving module, and the switching signal decomposition module is used for decomposing an input signal into M turn-on PWM signals and M turn-off PWM signals; the level shift module is used for amplifying the voltage and power of the M turn-on PWM signals and the M turn-off PWM signals; and the multi-section driving module is used for outputting different driving currents based on the amplified M turn-on PWM signals and M turn-off PWM signals. According to the invention, driving current and driving voltage of different magnitudes can be provided in each stage of the turn-on and turn-off processes of the SiC MOSFET device, so that a relatively high switching speed is maintained, the magnitudes of dv / dt and di / dt of the device in part of the switching process are limited, and the EMI and peak problems in the switching process are inhibited; the switching loss and delay can be effectively reduced while the peak level is reduced, and the switching stress problem of the device under high-voltage and high-frequency application is relieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of wide bandgap power semiconductor device driving, and in particular relates to a driving circuit and method for a SiC MOSFET device, and a driving chip. Background Art

[0002] Wide bandgap semiconductor materials represented by SiC and GaN materials have the characteristics of large bandgap width, high breakdown voltage, high thermal conductivity, high electron saturation drift velocity, small dielectric constant, strong radiation resistance, and stable chemical properties. Therefore, their application in optoelectronic devices, high-frequency and high-power, high-temperature electronic devices, etc. has attracted much attention.

[0003] At present, power devices based on SiC materials and related drive circuits are the research focus in the field of power electronics applications. Compared with traditional Si-based IGBT devices, SiC MOSFET devices have the characteristics of high switching frequency, low on-resistance, and high power density, and are expected to replace traditional IGBT devices in high-voltage applications.

[0004] Currently, a key area of research related to the application of SiC MOSFET devices is the design of their driver chips. Compared to traditional driver chips, driver chips suitable for SiC MOSFETs require high switching frequency, large drive current, and small drive delay, which brings many challenges to the design of the drive circuit. In addition, because current driver chips use the same drive current level during the switching process, they cannot effectively optimize the switching process of SiC MOSFET devices. When the drive circuit adopts a high drive speed, the device will experience high dv / dt and high di / dt, and the device will have more prominent EMI and spike problems, which limits the operating range of voltage and current during device application. When the drive circuit adopts a low drive speed, the switching loss and switching delay of the device will increase sharply, which limits the high-frequency application of the device.

[0005] Therefore, how to realize a driving circuit that maintains low switching loss and switching delay at the same EMI level is the key problem to be solved by the present invention. Summary of the Invention

[0006] The object of the present invention is to address the deficiencies of the above-mentioned prior art and provide a drive circuit, method, and driver chip for a SiC MOSFET device, which can provide different drive currents and drive voltages at various stages of the SiC MOSFET device's turn-on and turn-off processes, thereby maintaining a relatively fast switching speed and limiting the magnitude of the device's dv / dt and di / dt during some switching processes, thereby suppressing EMI and spike problems that occur during the device's switching process. Compared with traditional drive circuits with the same EMI level, the present invention can reduce the spike level while effectively reducing the device's switching loss and switching delay, thereby alleviating the switching stress problem of SiC MOSFET devices in high-voltage and high-frequency applications.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is: A driving circuit for a SiC MOSFET device is characterized by comprising a switching signal decomposition module, a level shift module, and a multi-stage driving module, wherein: Switch signal decomposition module: used to convert the input signal into PWM in Decomposed into M turn-on PWM signals and M turn-off PWM signals; Level shift module: used to amplify the voltage and power of M turn-on PWM signals and M turn-off PWM signals; Multi-stage drive module: used to output drive currents of different sizes based on the amplified M turn-on PWM signals and M turn-off PWM signals.

[0008] As a preferred embodiment, the switch signal decomposition module includes: a module for converting the input signal PWM in The open signal decomposition circuit decomposes the input signal into M open PWM signals; in A shutdown signal decomposition circuit decomposes the signal into M shutdown PWM signals; a level shift module includes: M on-level shift circuits for amplifying the voltage and power of the M on-PWM signals; and M off-level shift circuits for amplifying the voltage and power of the M off-PWM signals; a multi-stage drive module includes: M-1 cascaded first current source drive circuits and a second current source drive circuit; each first current source drive circuit and second current source drive circuit is configured to output drive currents of different magnitudes based on the amplified M on-PWM signals and the M off-PWM signals.

[0009] As a preferred embodiment, the activation signal decomposition circuit includes cascaded M-1 first delay modules, M-1 first NOT gates, and M first AND gates; wherein: The input ends of the 1st to M-1st first NOT gates are connected to the output ends of the 1st to M-1st first delay modules; the output ends of the 1st to M-2nd first NOT gates are connected to the first input ends of the 1st to M-2nd first AND gates, and the output end of the M-1th first NOT gate is connected to the first input end of the Mth first AND gate. The second input terminals of the 1st to M-1st first AND gates are connected to the input terminals of the 1st to M-1st first delay modules respectively; the second input terminal of the Mth first AND gate is connected to the input terminal of the M-1th first delay module; the first input terminal of the M-1th first AND gate is connected to the input terminal of the 1st first delay module; The input end of the first delay module is the input end of the turn-on signal decomposition circuit; the output ends of the first to M first AND gates correspond to the output ends of the first to M turn-on PWM signals.

[0010] As a preferred embodiment, the shutdown signal decomposition circuit includes M-1 second delay modules, M second NOT gates and M second AND gates connected in cascade; wherein: The output end of the first second NOT gate is connected to the input end of the first second delay module; the input end of the first second NOT gate is the input end of the shutdown signal decomposition circuit; the output ends of the first to M second AND gates correspond to the output ends of the first to M shutdown PWM signals; The input ends of the 2nd to Mth second NOT gates are correspondingly connected to the output ends of the 1st to M-1st second delay modules; the output ends of the 2nd to M-1st second NOT gates are correspondingly connected to the first input ends of the 1st to M-2nd second AND gates, and the output end of the Mth second NOT gate is connected to the first input end of the Mth second AND gate; The second input ends of the 1st to M-1st second AND gates are correspondingly connected to the input ends of the 1st to M-1st second delay modules; the second input end of the Mth second AND gate is connected to the input end of the M-1th second delay module; and the first input end of the M-1th second AND gate is connected to the input end of the 1st second delay module.

[0011] As a preferred embodiment, each of the turn-on level shift circuits includes a voltage boosting circuit for boosting voltage and a multi-stage first inverter chain circuit for amplifying power; wherein: The output end of the voltage boosting circuit is connected to the input end of the first inverter chain circuit; the input end of the voltage boosting circuit is the input end of the turn-on level shift circuit, and the output end of the first inverter chain circuit is the output end of the turn-on level shift circuit.

[0012] As a preferred embodiment, each shutdown level shift circuit includes a voltage reduction circuit for reducing voltage and a multi-stage second inverter chain circuit for amplifying power; wherein: The output end of the voltage reduction circuit is connected to the input end of the second inverter chain circuit; the input end of the voltage reduction circuit is the input end of the shutdown level shift circuit, and the output end of the second inverter chain circuit is the output end of the shutdown level shift circuit.

[0013] As a preferred embodiment, each of the first current source type driving circuit and the second current source type driving circuit includes a set of on-loop and off-loop; the input end of each on-loop is correspondingly connected to the output end of each on-level shifting circuit, and the input end of each off-loop is correspondingly connected to the output end of each off-level shifting circuit; the output end of each on-loop and the output end of each off-loop are both connected to the output end of the multi-stage driving module.

[0014] Based on the same inventive concept, the present invention also provides a driving method for a SiC MOSFET device, which is characterized by comprising: Step A: PWM the input signal in Decomposed into M turn-on PWM signals and M turn-off PWM signals; Step B, amplifying the voltage and power of the M turn-on PWM signals and the M turn-off PWM signals; Step C: outputting drive currents of different magnitudes based on the amplified M on-PWM signals and the M off-PWM signals.

[0015] As a preferred method, in step A, the input signal PWM in Decomposition into M turn-on PWM signals and M turn-off PWM signals includes: The input signal PWM in Decompose the transient waveform at the time of opening to obtain M opening PWM signals; in The transient waveform at the turn-off moment is decomposed in time sequence to obtain M turn-off PWM signals.

[0016] Based on the same inventive concept, the present invention also provides a driver chip for a SiC MOSFET device, which is characterized by including the driver circuit of the SiC MOSFET device.

[0017] Compared with the prior art, the present invention has the following beneficial effects: (1) The drive circuit control adopts an open-loop drive mode. There is no feedback loop in the drive circuit, so there will be no loop stability problem of the traditional feedback drive circuit, and the device selection is relatively flexible.

[0018] (2) The multi-stage drive signal is generated by using logic circuits, which does not rely on control chips such as FPGA or DSP. It can effectively reduce the complexity of the system and realize the miniaturization of the drive circuit.

[0019] (3) The basic part of the driving module adopts M-1 first current source type driving circuits, which open M turn-on PWM signals and M turn-off PWM signals for group control, and can effectively realize the switching of the driving current of the turn-on process and the driving current of the turn-off process.

[0020] (4) The additional part of the drive module adopts a second current source drive circuit as a charge and discharge circuit, which can make the gate-source voltage rise to the high level of the drive voltage (15V) or drop to the low level of the drive voltage (-5V) more quickly, reducing the time required for the M-1 stage of the turn-on process and the M-1 stage of the turn-off process, thereby reducing the switching loss of this process. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a block diagram of the driving circuit in the driver chip of the SiC MOSFET device provided by the present invention.

[0022] Figure 2 for Figure 1 Schematic diagram of the circuit structure of the open signal decomposition.

[0023] Figure 3 This is the timing diagram of the opening signal of the present invention.

[0024] Figure 4 for Figure 1 Schematic diagram of the shutdown signal decomposition circuit structure.

[0025] Figure 5 This is a shutdown signal timing diagram of the present invention.

[0026] Figure 6 Schematic diagram of the structure of each enabled level shift circuit in the present invention.

[0027] Figure 7 Schematic diagram of the structure of each turn-off level shift circuit in the present invention.

[0028] Figure 8 for Figure 1 Schematic diagram of the multi-stage drive module structure.

[0029] Among them, 1 is a switch signal decomposition module, 101 is an on-signal decomposition circuit, 102 is a off-signal decomposition circuit, 2 is a level shift module, 201 is an on-level shift circuit, 2011 is a voltage raising circuit, 2012 is a first inverter chain circuit, 202 is a off-level shift circuit, 2021 is a voltage lowering circuit, 2022 is a second inverter chain circuit, 3 is a multi-stage driving module, 301 is a first current source type driving circuit, and 302 is a second current source type driving circuit. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the solutions of the present invention, the following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present invention.

[0031] The terms "first", "second", "third", "fourth", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way are interchangeable where appropriate so that the embodiments described herein can be used in an order other than that shown or described herein. In addition, the terms "including" and "having" and any variations thereof in the description and claims of the present invention are intended to cover but not exclude his inclusion. For example, a process, method, system, product or device that includes one or two series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or devices.

[0032] like Figures 1 to 8 As shown, the driving circuit of the SiC MOSFET device of the present invention includes a switching signal decomposition module 1, a level shift module 2, and a multi-stage driving module 3, wherein: Switch signal decomposition module 1: used to convert the input signal into PWM in Decomposed into M turn-on PWM signals and M turn-off PWM signals; Level shift module 2: used to amplify the voltage and power of M turn-on PWM signals and M turn-off PWM signals; Multi-stage drive module 3: used to output different drive currents based on the amplified M on-state PWM signals and M off-state PWM signals. The output terminal of multi-stage drive module 3 is connected to the drive terminal of the SiC MOSFET device.

[0033] Preferably, the switch signal decomposition module 1 includes: a module for converting the input signal PWM in The turn-on signal decomposition circuit 101 decomposes the transient waveform of the turn-on moment into M turn-on PWM signals; in A shutdown signal decomposition circuit 102 for decomposing a transient waveform into M shutdown PWM signals at the shutdown moment; The level shift module 2 includes: M on-level shift circuits 201 for amplifying the voltage and power of M on-PWM signals; M off-level shift circuits 202 for amplifying the voltage and power of M off-PWM signals; The multi-stage driving module 3 includes: M-1 cascaded first current source driving circuits 301 and a second current source driving circuit 302; each first current source driving circuit 301 and second current source driving circuit 302 is used to output driving currents of different sizes based on the amplified M turn-on PWM signals and M turn-off PWM signals.

[0034] Preferably, the activation signal decomposition circuit 101 comprises M-1 first delay modules, M-1 first NOT gates and M first AND gates connected in cascade; wherein, The input ends of the 1st to M-1st first NOT gates are connected to the output ends of the 1st to M-1st first delay modules; the output ends of the 1st to M-2nd first NOT gates are connected to the first input ends of the 1st to M-2nd first AND gates, and the output end of the M-1th first NOT gate is connected to the first input end of the Mth first AND gate. The second input terminals of the 1st to M-1st first AND gates are connected to the input terminals of the 1st to M-1st first delay modules respectively; the second input terminal of the Mth first AND gate is connected to the input terminal of the M-1th first delay module; the first input terminal of the M-1th first AND gate is connected to the input terminal of the 1st first delay module; The input end of the first delay module is the input end of the turn-on signal decomposition circuit; the output ends of the first to M first AND gates correspond to the output ends of the first to M turn-on PWM signals.

[0035] Preferably, the shutdown signal decomposition circuit 102 includes M-1 second delay modules, M second NOT gates and M second AND gates connected in cascade; wherein, The output end of the first second NOT gate is connected to the input end of the first second delay module; the input end of the first second NOT gate is the input end of the shutdown signal decomposition circuit; the output ends of the first to M second AND gates correspond to the output ends of the first to M shutdown PWM signals; The input ends of the 2nd to Mth second NOT gates are correspondingly connected to the output ends of the 1st to M-1st second delay modules; the output ends of the 2nd to M-1st second NOT gates are correspondingly connected to the first input ends of the 1st to M-2nd second AND gates, and the output end of the Mth second NOT gate is connected to the first input end of the Mth second AND gate; The second input ends of the 1st to M-1st second AND gates are correspondingly connected to the input ends of the 1st to M-1st second delay modules; the second input end of the Mth second AND gate is connected to the input end of the M-1th second delay module; and the first input end of the M-1th second AND gate is connected to the input end of the 1st second delay module.

[0036] Preferably, each of the turn-on level shift circuits 201 includes a voltage boosting circuit 2011 for boosting voltage and a multi-stage first inverter chain circuit 2012 for amplifying power; wherein, The output end of the voltage boosting circuit 2011 is connected to the input end of the first inverter chain circuit 2012; the input end of the voltage boosting circuit 2011 is the input end of the turn-on level shift circuit 201, and the output end of the first inverter chain circuit 2012 is the output end of the turn-on level shift circuit 201.

[0037] Preferably, each shutdown level shift circuit 202 includes a voltage reduction circuit 2021 for reducing voltage and a multi-stage second inverter chain circuit 2022 for amplifying power; wherein, The output end of the voltage reduction circuit 2021 is connected to the input end of the second inverter chain circuit 2022 ; the input end of the voltage reduction circuit 2021 is the input end of the shutdown level shift circuit 202 , and the output end of the second inverter chain circuit 2022 is the output end of the shutdown level shift circuit 202 .

[0038] Preferably, each first current source type driving circuit and each second current source type driving circuit includes a set of on-loop and off-loop; the input end of each on-loop is correspondingly connected to the output end of each on-level shifting circuit, and the input end of each off-loop is correspondingly connected to the output end of each off-level shifting circuit; the output end of each on-loop and the output end of each off-loop are both connected to the output end of the multi-stage driving module.

[0039] In the present invention, M can be set as needed. Figures 1 to 8 Taking M=5 as an example, the circuit structure and working principle of the present invention are described in detail below. When M is other integers, the circuit structure and working principle are similar and are not described in detail here.

[0040] like Figure 2 As shown, the turn-on signal decomposition circuit 101 includes four cascaded delay modules Delay1, Delay2, Delay3, Delay4, four NOT gates NOT1, NOT2, NOT3, NOT4 and five AND gates AND1, AND2, AND3, AND4, AND5.

[0041] like Figure 4As shown, the shutdown signal decomposition circuit 102 includes four cascaded delay modules Delay5, Delay6, Delay7, Delay8, five NOT gates NOT5, NOT6, NOT7, NOT8, NOT9 and M AND gates AND6, AND7, AND8, AND9, AND 10 .

[0042] Furthermore, each delay module group Delay1, Delay2, Delay3, Delay4, Delay5, Delay6, Delay7, and Delay8 is composed of two cascaded CMOS inverters and parallel capacitors. The corresponding parallel capacitors are C1, C2, C3, C4, C5, C6, C7, and C8 respectively.

[0043] The delay time τ of each delay module Delay1, Delay2, Delay3, Delay4, Delay5, Delay6, Delay7, and Delay8 is related to the parallel capacitor C X The size relationship is as follows:

[0044] in R eq is the on-resistance of the CMOS inverter, C oss is the equivalent output junction capacitance of the CMOS inverter.

[0045] The signal at the input of NOT gate NOT1 is the PWM output of delay module Delay1. d1 The signal, the output port of NOT gate NOT1 is connected to AND gate AND1.

[0046] The signal at the NOT2 input is the PWM output of the delay module Delay2. d2 The signal, the output port of NOT gate NOT2 is connected to AND gate AND2.

[0047] The signal at the input of NOT3 is the PWM output of the delay module Delay3. d3 The signal, the output port of NOT gate NOT3 is connected to AND gate AND3.

[0048] The signal at the input end of the NOT gate NOT4 is the PWMd4 signal output by the delay module Delay4, and the output port of the NOT gate NOT4 is connected to the AND gate AND5.

[0049] The signal at the input end of the NOT gate NOT5 is the input PWM signal, and the output port of the NOT gate NOT5 is connected to the input end of the delay module Delay5.

[0050] The signal at the input end of the NOT gate NOT6 is the PWMd5 signal output by the delay module Delay5, and the output port of the NOT gate NOT6 is connected to the AND gate AND6.

[0051] The signal at the input end of the NOT gate NOT7 is the PWMd6 signal output by the delay module Delay6, and the output port of the NOT gate NOT7 is connected to the AND gate AND7.

[0052] The signal at the input end of the NOT gate NOT8 is the PWMd7 signal output by the delay module Delay7, and the output port of the NOT gate NOT8 is connected to the AND gate AND8.

[0053] The signal at the input of NOT gate NOT9 is the PWMd8 signal output by the delay module Delay8, and the output port of NOT gate NOT9 is connected to the AND gate AND. 10 connect.

[0054] Correspondingly, the level shift module 2 includes five on-level shift circuits 201 and five off-level shift circuits 202 .

[0055] like Figure 6 As shown, each open level shift circuit 201 is composed of a PMOS transistor M p1 , M p2 , M hp1 , M hp2 、NMOS tube M hn1 , M hn2 , capacitor C H1 , C H2 and NOT gate H composition.

[0056] like Figure 7 As shown, each shutdown level shift circuit 202 is composed of an NMOS transistor M n1 , M n2 , M ln1 , M ln2 、PMOS tube M lp1 , M lp2 , capacitor C L1 , C L2 and NOT gate L composition.

[0057] like Figure 6 As shown, in the open level shift circuit 201, the PMOS tube M p1 The source is connected to 15V or 20V, M p1 The gate and M p2 The drain, M hp1 Gate, M hn1 The gate and C H2 Positive connection, M p1 The drain and Mp2 The gate connection and C H1 The positive connection of PMOS tube M p2 The source is connected to 15V or 20V, M p2 The gate and M p1 The drain and C H1 Positive connection, M p2 The drain and M p1 The gate connection and C H2 The positive terminal of capacitor C H1 The positive electrode and M p1 The drain, M p2 The gate connection, capacitor C H1 The negative electrode of the NOT gate H The output terminal is connected to the capacitor C H2 The positive electrode and M p2 The drain, M p1 Gate, M hp1 The gate and M hn1 The gate connection, capacitor C H2 The negative pole of the signal PWM 1~5(on) and NOT gate H The input terminal of the PMOS tube M hp1 The source is connected to 15V or 20V, M hp1 The drain and M hn1 The drain, M hp2 The gate and M hn2 Gate connection, M hp1 The gate and M p2 The drain, M p1 The gate and C H2 The positive electrode of NMOS tube M hn1 The drain and M hp1 The drain, M hp2 The gate and M hn2 Gate connection. M hn1 The source is connected to 10V or 15V. hn1 The gate and M p2 The drain, M p1 Gate, M hp1 The gate and capacitor C H2 The positive connection of the M hp2 The source is connected to 15V or 20V, M hp2 The drain and M hn2 Drain and PWM 1~5 Output signal connection. M hp2 The gate and M hp1 The drain and M hn1 Drain connection, M hn2The drain and M hp2 Drain connection, M hn2 The source is connected to 10V or 15V.

[0058] like Figure 7 As shown, in the shutdown level shift circuit 202, the NMOS tube M n1 The source is connected to -5V or -10V, M n1 The gate and M n2 The drain, M lp1 Gate, M ln1 The gate and C L2 The negative connection of M n1 The drain and M n2 The gate connection and C L1 The negative electrode of NMOS tube M n2 The source is connected to -5V or -10V, M n2 The gate and M n1 The drain and C L1 The negative connection of M n2 The drain and M n1 The gate connection and C L2 The negative terminal of capacitor C L1 The negative electrode and M n1 The drain, M n2 The gate connection, capacitor C L1 The positive electrode of the NOT gate L The output terminal is connected to the capacitor C L2 The negative electrode and M n2 The drain, M n1 Gate, M lp1 The gate and M ln1 The gate connection, capacitor C L2 The positive pole of the signal PWM 1~5(off) and NOT gate L The input terminal of NMOS tube M ln1 The source is connected to -5V or -10V, M ln1 The drain and M lp1 The drain, M lp2 The gate and M ln2 Gate connection, M ln1 The gate and M n2 The drain, M n1 The gate and C L2 The negative electrode of the PMOS tube M lp1 The drain and M ln1 The drain, M lp2 The gate and M ln2 Gate connection. M lp1The source is connected to -5V or 0V. lp1 The gate and M n2 The drain, M n1 Gate, M ln1 The gate and capacitor C L2 The negative connection of M ln2 The source is connected to -5V or -10V, M ln2 The drain and M lp2 Drain and PWM 6~10 Output signal connection. M ln2 The gate and M ln1 The drain and M lp1 Drain connection, M lp2 The drain and M ln2 Drain connection, M lp2 The source is connected to -5 or -10V.

[0059] Correspondingly, such as Figure 8 As shown, the multi-stage driving module 3 comprises a combination of a 4-way -5 / 15V first current source type driving circuit 301 and a -10 / 20V second current source type driving circuit 302. p1 ~T p5 , NMOS tube T n1 ~T n5 , diodes D1~D 10 Composition. Among them, T p1 ~T p4 The source is connected to 15V, T p5 The source is connected to +20V, T p1 ~T p5 The drain of is connected to the anode of D1~D5 respectively. n1 ~T n4 The source is connected to -5V, T n5 The source is connected to -10V, T n1 ~T n5 The drain of D6~D 10 The cathode of D1~D5 is connected to the cathode of D6~D 10 The anode of the SiC MOSFET is directly connected to the output drive port and is ultimately used to connect to the drive end of the SiC MOSFET device.

[0060] The peak current that each drive circuit can provide is determined by the aspect ratio of the device and the carrier mobility. p The relationship with device parameters is as follows:

[0061] in, μis the carrier mobility of the push-pull transistor PMOS or NMOS, W / L is the width-to-length ratio of PMOS or NMOS, C ox is the gate oxide capacitance of PMOS or NMOS, V th is the threshold voltage of PMOS or NMOS.

[0062] The present invention also provides a driving method for a SiC MOSFET device, comprising: Step A: PWM the input signal in Decomposed into M turn-on PWM signals and M turn-off PWM signals; Step B, amplifying the voltage and power of the M turn-on PWM signals and the M turn-off PWM signals; Step C: outputting drive currents of different magnitudes based on the amplified M on-PWM signals and the M off-PWM signals.

[0063] Preferably, in step A, the input signal PWM in Decomposition into M turn-on PWM signals and M turn-off PWM signals includes: The input signal PWM in Decompose the transient waveform at the time of opening to obtain M opening PWM signals; in The transient waveform at the turn-off moment is decomposed in time sequence to obtain M turn-off PWM signals.

[0064] The present invention also provides a driver chip for a SiC MOSFET device, which includes the driver circuit of the SiC MOSFET device.

[0065] The working principle of the present invention is as follows: refer to Figure 2 , the principle of opening the signal decomposition circuit 101 is as follows: During the opening process, the PWM signal jumps from low level to high level, and passes through 4 groups of delay modules Delay1, Delay2, Delay3, and Delay4 to obtain 4 groups of delayed signals PWM. d1 、PWM d2 、PWM d3 、PWM d4 The signal after the four groups of delayed signals are calculated by NOT gates NOT1, NOT2, NOT3, and NOT4 is PWM. dn1 、PWM dn2 、PWM dn3 、PWM dn4 . Input PWM signal and delayed inverse signal PWM dn1 After the AND gate AND1 operation, it reaches the first group of opening signals PWM 1(on), the pulse width is 20ns. Delay signal PWM d1 With delayed inverted signal PWM dn2 After the AND gate AND2 operation, it reaches the second group of opening signals PWM 2(on) , the pulse width is 15ns. Delay signal PWM d2 With delayed inverted signal PWM dn3 After the AND gate AND3 operation, it reaches the third group of opening signals PWM 3(on) , the pulse width is 15ns. Delay signal PWM d3 With delayed inverted signal PWM dn4 After the AND5 operation, it reaches the fifth group of open signal PWM 5(on) , the pulse width is 25ns. In addition, the input PWM signal and the delayed signal PWM d3 After the AND4 operation, it reaches the fourth group of open signal PWM 4(on) The pulse width of this set of opening signals is based on the PWM pulse width minus 50ns. Input PWM signal and output 4 sets of opening signals PWM 1(on) 、PWM 2(on) 、PWM 3(on) 、PWM 4(on) 、PWM 5(on) The temporal relationship of Figure 3 shown.

[0066] refer to Figure 4 , the principle of shutting down the signal decomposition circuit 102 is as follows: During the shutdown process, the PWM signal jumps from high level to low level, and the inverted signal PWM is obtained through the NOT gate NOT5 operation. n . Inverted signal PWM n After 4 groups of delay modules Delay5, Delay6, Delay7 and Delay8, 4 groups of inverse delay signals PWM are obtained. dn5 、PWM dn6 、PWM dn7 、PWM dn8 The signal after the four groups of delayed inverted signals are calculated by NOT gates NOT6, NOT7, NOT8, and NOT9 is PWM. d5 、PWM d6 、PWM d7 、PWM d8 . Input inverted signal PWM n With delayed signal PWM d5 After the AND gate AND6 operation, it reaches the first group of shutdown signals PWM 1(off) , the pulse width is 25ns. Delayed inverting signal PWM dn5 With delayed signal PWM d6After the AND gate AND7 operation, it reaches the second group of shutdown signals PWM 2(off) , the pulse width is 15ns. Delayed inverting signal PWM dn6 With delayed signal PWM d7 After the AND gate AND8 operation, it reaches the third group of shutdown signals PWM 3(off) , the pulse width is 15ns. Delayed inverting signal PWM dn7 With delayed signal PWM d8 Through the AND gate 10 After calculation, the 5th group of shutdown signal PWM 5(off) , the pulse width is 20ns. In addition, the input inverted signal PWM n With delayed inverted signal PWM dn7 After the AND gate AND9 operation, it reaches the fourth group of shutdown signal PWM 4(off) The pulse width of this group of shutdown signals is based on the PWM low level pulse width minus 55ns. Input PWM signal and output 4 groups of shutdown signals PWM 1(off) 、PWM 2(off) 、PWM 3(off) 、PWM 4(off) 、PWM 4(off) The temporal relationship of Figure 5 shown.

[0067] refer to Figure 6 , the level shift circuit 201 is composed of 5 groups of circuits with the same structure, and its principle is as follows: Use cross-coupling circuit to input 0~5V PWM 1~5(on) The signal is raised to a 10~15V or 15~20V drive signal, and then connected to a two-stage inverter chain circuit powered by 10~15V or 15~20V for power amplification to obtain PWM 1~5 signal and output.

[0068] refer to Figure 7 The shutdown level shift circuit 202 is composed of five groups of circuits with the same structure, and its principle is as follows: Use cross-coupling circuit to input 0~5V PWM 1~5(off) The signal is reduced to a driving signal of -5~0V or -10~-5V, and then connected to a two-stage inverter chain circuit powered by -5~0V or -10~-5V for power amplification, thereby obtaining PWM 6~7 signal and output.

[0069] refer to Figure 8 The multi-stage drive module 3 includes a total of 10 switch tubes, of which 8 switch tubes T p1~4 and T n1~4It is a -5 / 15V current source circuit, and the other two switch tubes T p5 、T n5 It is a -10 / 20V current source circuit. The basic principle of the multi-stage drive module 3 is as follows: When the input PWM is at a high level, the multi-stage drive module 3 is in the on-state process, and the multi-stage drive module 3 only has the upper half loop switch tube T p1 、T p2 、T p3 、T p4 、T p5 Work, according to the timing control sequence of opening the logic circuit, first T p1 The first open circuit is turned on, the peak drive current is 3A, and it lasts for 20ns. p1 Turn off, then T p2 The second open circuit is turned on, the peak drive current is 2A, and it lasts for 15ns. p2 Then T p3 The third open circuit is turned on, the peak drive current is 1A, and it lasts for 15ns. p3 Turn off. Last T p4 , T p5 The 4th open loop and the 5th open loop are turned on at the same time. The peak drive current of the 4th open loop is 3A, and there is a +20V high level pull-up drive current. After the 5th open loop lasts for 25ns, T p5 The 4th circuit is turned off, and the T p4 It continues to conduct until the PWM high level ends.

[0070] When the input PWM is at a low level, the multi-stage drive module 3 is in the off process, and the multi-stage drive module 3 only has the lower half loop switch tube T n1 、T n2 、T n3 、T n4 、T n5 Work, according to the timing control sequence of the shutdown logic circuit, first T n1 The first stage circuit is turned on, the peak drive current is 3A, and it lasts for 25ns. n1 Turn off, then T n2 The second off-circuit is turned on, the peak drive current is 1A, and it lasts for 15ns. n2 Then T n3 The third off-circuit is turned on, the peak drive current is 2A, and it lasts for 15ns. n3 Turn off. Last T n4 、T n5At the same time, the 4th shutdown loop and the 5th shutdown loop are turned on at the same time. The peak driving current of the 4th shutdown loop is 3A. At the same time, there is a -10V low-level pull-down driving current. After the 5th shutdown loop lasts for 20ns, T n5 Shut off, and the 4th shut-off circuit T n4 It continues to conduct until the PWM low level ends.

[0071] In summary, the present invention has the following beneficial effects: (1) The drive circuit control adopts an open-loop drive mode. There is no feedback loop in the drive circuit, so there is no loop stability problem of the traditional feedback drive circuit. It is relatively flexible in device selection.

[0072] (2) The multi-stage drive signal is generated by using logic circuits, which does not rely on control chips such as FPGA or DSP. It can effectively reduce the complexity of the system and realize the miniaturization of the drive circuit.

[0073] (3) The basic part of the drive module adopts a 4-way -5 / 15V current source drive structure, and the opening circuit drive signal and the closing circuit drive signal are grouped and controlled, which can effectively realize the switching of the opening process drive current and the closing process drive current. (4) The additional part of the driver module adopts a -10 / 20V charge and discharge circuit, which can make the gate-source voltage rise to the high level of the driving voltage (15V) or drop to the low level of the driving voltage (-5V) more quickly, reducing the time required for the fourth stage of the turn-on process and the fourth stage of the turn-off process, and reducing the switching delay of this process.

[0074] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific embodiments. The above-mentioned specific embodiments are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which fall within the scope of protection of the present invention.

Claims

1. A driving circuit for a SiC MOSFET device, characterized in that: It includes a switch signal decomposition module, a level shift module, and a multi-stage drive module, among which: Switch signal decomposition module: used to convert the input signal into PWM in Decomposed into M turn-on PWM signals and M turn-off PWM signals; Level shift module: used to amplify the voltage and power of M turn-on PWM signals and M turn-off PWM signals; Multi-stage drive module: used to output drive currents of different sizes based on the amplified M turn-on PWM signals and M turn-off PWM signals.

2. The SiC MOSFET device driving circuit according to claim 1, wherein: The switch signal decomposition module includes: a module for converting the input signal into PWM in The open signal decomposition circuit decomposes the input signal into M open PWM signals; in a shutdown signal decomposition circuit for decomposing the signal into M shutdown PWM signals; The level shift module includes: M on-level shift circuits for amplifying the voltage and power of M on-PWM signals; M off-level shift circuits for amplifying the voltage and power of M off-PWM signals; The multi-stage drive module includes: M-1 cascaded first current source drive circuits and a second current source drive circuit; each first current source drive circuit and second current source drive circuit is used to output drive currents of different sizes based on the amplified M turn-on PWM signals and M turn-off PWM signals.

3. The driving circuit of the SiC MOSFET device according to claim 2, wherein: The open signal decomposition circuit includes cascaded M-1 first delay modules, M-1 first NOT gates and M first AND gates; wherein, The input ends of the 1st to M-1st first NOT gates are connected to the output ends of the 1st to M-1st first delay modules; the output ends of the 1st to M-2nd first NOT gates are connected to the first input ends of the 1st to M-2nd first AND gates, and the output end of the M-1th first NOT gate is connected to the first input end of the Mth first AND gate. The second input terminals of the 1st to M-1st first AND gates are connected to the input terminals of the 1st to M-1st first delay modules respectively; the second input terminal of the Mth first AND gate is connected to the input terminal of the M-1th first delay module; the first input terminal of the M-1th first AND gate is connected to the input terminal of the 1st first delay module; The input end of the first delay module is the input end of the turn-on signal decomposition circuit; the output ends of the first to M first AND gates correspond to the output ends of the first to M turn-on PWM signals.

4. The driving circuit of the SiC MOSFET device according to claim 2, wherein: The shutdown signal decomposition circuit includes cascaded M-1 second delay modules, M second NOT gates and M second AND gates; wherein, The output end of the first second NOT gate is connected to the input end of the first second delay module; the input end of the first second NOT gate is the input end of the shutdown signal decomposition circuit; the output ends of the first to M second AND gates correspond to the output ends of the first to M shutdown PWM signals; The input ends of the 2nd to Mth second NOT gates are correspondingly connected to the output ends of the 1st to M-1st second delay modules; the output ends of the 2nd to M-1st second NOT gates are correspondingly connected to the first input ends of the 1st to M-2nd second AND gates, and the output end of the Mth second NOT gate is connected to the first input end of the Mth second AND gate; The second input ends of the 1st to M-1st second AND gates are correspondingly connected to the input ends of the 1st to M-1st second delay modules; the second input end of the Mth second AND gate is connected to the input end of the M-1th second delay module; and the first input end of the M-1th second AND gate is connected to the input end of the 1st second delay module.

5. The driving circuit of the SiC MOSFET device according to claim 2, wherein: Each of the turn-on level shift circuits includes a voltage boosting circuit for boosting voltage and a multi-stage first inverter chain circuit for amplifying power; wherein, The output end of the voltage boosting circuit is connected to the input end of the first inverter chain circuit; the input end of the voltage boosting circuit is the input end of the turn-on level shift circuit, and the output end of the first inverter chain circuit is the output end of the turn-on level shift circuit.

6. The driving circuit of the SiC MOSFET device according to claim 2, wherein: Each shutdown level shift circuit includes a voltage reduction circuit for reducing voltage and a multi-stage second inverter chain circuit for amplifying power; wherein, The output end of the voltage reduction circuit is connected to the input end of the second inverter chain circuit; the input end of the voltage reduction circuit is the input end of the shutdown level shift circuit, and the output end of the second inverter chain circuit is the output end of the shutdown level shift circuit.

7. The driving circuit of the SiC MOSFET device according to claim 2, wherein: Each of the first current source type driving circuit and the second current source type driving circuit includes a set of on-loop and off-loop; the input end of each on-loop is correspondingly connected to the output end of each on-level shifting circuit, and the input end of each off-loop is correspondingly connected to the output end of each off-level shifting circuit; the output end of each on-loop and the output end of each off-loop are both connected to the output end of the multi-stage driving module.

8. A driving method for a SiC MOSFET device, characterized in that: include: Step A: PWM the input signal in Decomposed into M turn-on PWM signals and M turn-off PWM signals; Step B, amplifying the voltage and power of the M turn-on PWM signals and the M turn-off PWM signals; Step C: outputting drive currents of different magnitudes based on the amplified M on-PWM signals and the M off-PWM signals.

9. The driving method of a SiC MOSFET device according to claim 8, wherein: In step A, the input signal PWM in Decomposition into M turn-on PWM signals and M turn-off PWM signals includes: The input signal PWM in Decompose the transient waveform at the time of opening to obtain M opening PWM signals; in The transient waveform at the turn-off moment is decomposed in time sequence to obtain M turn-off PWM signals.

10. A driver chip for a SiC MOSFET device, characterized in that: A driving circuit comprising a SiC MOSFET device as claimed in any one of claims 2 to 7.

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