Carrier wave, chip and data homologous modulation system

Abstract

A carrier wave, chip and data homologous modulation system is characterized by comprising a power supply remote control telemetering unit, a crystal oscillator reference unit, a power division matching unit, a carrier wave generation unit, a work clock generation unit, a data processing unit and a radio frequency channel unit. The power supply remote control telemetering unit, the crystal oscillator reference unit, the power division matching unit, the carrier generation unit and the radio frequency channel unit are sequentially connected in series, and the power division matching unit is further sequentially connected with the work clock generation unit, the data processing unit and the radio frequency channel unit in series; the output of the power supply remote-control telemetering unit is connected with the input of the work clock generation unit, and the power supply remote-control telemetering unit is connected with the data processing unit. The carrier wave, the chip and the data clock of one single machine are from the same signal source, the complexity of a ground receiving system is effectively reduced, excellent communication performance is guaranteed, and the requirements of a special receiving terminal for mobility, small size, light weight, low power consumption and high reliability can be met.

Description

Technical Field

[0001] The present invention belongs to the technical field of satellite communications, and in particular relates to a modulation system with carrier waves, code chips and data of the same source. Background Art

[0002] With the continuous development of the satellite industry, high speed, diversity, and large capacity have become the mainstream trends in satellite development, and technologies such as high-speed data coding and modulation and large-aperture ground reception have rapidly advanced. However, for some specialized applications, receiving terminals must meet performance requirements such as high mobility, small size, light weight, and low power consumption. In systems where the carrier chips and data are driven by clocks from different sources, the relationship between data information and carrier phase is uncertain, requiring multiple clock recovery and synchronization operations at the receiving end. This results in complex receiving terminal systems and high implementation challenges. Summary of the Invention

[0003] In response to the above problems, the purpose of the present invention is to provide a modulation system in which the carrier, code bits and data are of the same origin, so as to solve the problems of poor universality of functions and performance indicators of commonly used modulation devices and different sources of carrier, code bits and data.

[0004] To achieve the above-mentioned purpose, the technical solutions adopted by the present invention include:

[0005] A modulation system with a carrier wave, code chips and data of the same source, comprising a power supply remote control and telemetry unit, a crystal oscillator reference unit, a power dividing and matching unit, a carrier wave generating unit, a working clock generating unit, a data processing unit and a radio frequency channel unit; the power supply remote control and telemetry unit, the crystal oscillator reference unit, the power dividing and matching unit, the carrier wave generating unit and the radio frequency channel unit are connected in series in sequence, and the power dividing and matching unit is also connected in series with the working clock generating unit, the data processing unit and the radio frequency channel unit in sequence; the output of the power supply remote control and telemetry unit is connected to the input of the working clock generating unit, and the power supply remote control and telemetry unit and the data processing unit are interconnected.

[0006] Preferably, the working clock generating unit includes a second phase detector, a second loop filter, a second voltage-controlled oscillator, a frequency divider and a first amplifier connected in series in sequence, and the output of the second phase detector is also connected to the input of the second voltage-controlled oscillator.

[0007] Preferably, the power supply port of the power supply remote control and telemetry unit is connected in series with the second phase detector and the first amplifier respectively.

[0008] Preferably, the data processing unit includes an FPGA and a data receiving chip interconnected with the FPGA. The FPGA is also connected in series with a first operational amplifier and a second operational amplifier connected in parallel with each other; the output of the first amplifier is connected to the input of the FPGA.

[0009] Preferably, the power supply port of the power supply remote control telemetry unit is connected in series with the power supply interface of the FPGA, and the IO interface of the FPGA is interconnected with the telemetry information interface of the power supply remote control telemetry unit.

[0010] Preferably, the FPGA includes an input global buffer, a first global buffer, a direct digital frequency synthesizer, a second global buffer, a first frequency division module, a third global buffer, a second frequency division module and a fourth global buffer; the input global buffer, the first global buffer, the direct digital frequency synthesizer and the second global buffer are connected in series in sequence, the first global buffer includes 2 output ports, and the second global buffer includes 3 output ports; the second output port of the second global buffer is connected in series with the first frequency division module and the third global buffer in sequence; the third output port of the second global buffer is connected in series with the second frequency division module and the fourth global buffer in sequence.

[0011] Preferably, the RF channel unit includes a second amplifier, a mixer chip, a third amplifier, an electrically adjustable attenuator, a fourth amplifier, a detector and an isolator connected in series with the carrier generating unit in sequence, and also includes an amplification comparison control circuit connected between the output of the detector and the input of the electrically adjustable attenuator, and also includes a compensation circuit connected to the output of the data processing unit, and the output of the compensation circuit is connected to the input of the mixer chip.

[0012] Preferably, the output of the first operational amplifier and the output of the second operational amplifier are both connected to the input of the compensation circuit.

[0013] Preferably, the carrier generation unit includes a first phase detector, a first loop filter and a first voltage-controlled oscillator connected in series in sequence, and the output of the first phase detector is also connected to the input of the first voltage-controlled oscillator.

[0014] Preferably, the output of the first voltage-controlled oscillator is connected to the input of the second amplifier.

[0015] Compared with the prior art, the advantages of the present invention are:

[0016] (1) The present invention provides a modulation system with carrier, code and data of the same source. By rationally arranging the component structure, the carrier, code and data clock of a single machine are realized to come from the same signal source, which effectively reduces the complexity of the ground receiving system. In addition to ensuring excellent communication performance, it can meet the requirements of special receiving terminals that are portable, small in size, light in weight, low in power consumption and high in reliability.

[0017] (2) The present invention provides a modulation system with carrier waves, code bits and data of the same source. Each unit implements a modular design and uses the internal resources of the FPGA to generate working clocks such as spread spectrum coding, data processing, remote control and telemetry. The system is flexible and configurable, with a high degree of universality, effectively reducing the weight and volume of the product. It has the conditions to form a universal product, can significantly shorten the R&D cycle, and reduce the development cost.

[0018] (3) The modulation system of the present invention, in which the carrier, code chip and data are of the same source, has variable output power and information rate, and can meet diverse user needs.

[0019] (4) The present invention provides a modulation system with carrier, code and data of the same origin. The same origin design effectively reduces the ground modulation and demodulation loss to within 1.5dB. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0021] Figure 1 Schematic diagram of the structure of the modulation system of the present invention in which the carrier, code chip and data are of the same source;

[0022] Figure 2 for Figure 1 Schematic diagram of the structure of the FPGA in the power division and matching unit, carrier generation unit, working clock generation unit and data processing unit;

[0023] Figure 3 for Figure 1 Schematic diagram of the structure of the data processing unit;

[0024] Figure 4 for Figure 1 Schematic diagram of the structure of the RF channel unit. DETAILED DESCRIPTION

[0025] The invention is not limited to the following specific embodiments, and all equivalent modifications made on the basis of the technical solution of this application fall within the protection scope of the present invention.

[0026] It should be noted that, unless otherwise specified, all components and devices in the present invention are components and devices known in the prior art.

[0027] Example

[0028] This embodiment discloses a modulation system for carrier, code, and data with the same source, including a power supply, remote control, and telemetry unit 1, a crystal oscillator reference unit 2, a power splitter and matching unit 3, a carrier generation unit 4, a working clock generation unit 5, a data processing unit 6, and a radio frequency channel unit 7. The power supply, remote control, and telemetry unit 1, the crystal oscillator reference unit 2, the power splitter and matching unit 3, the carrier generation unit 4, and the radio frequency channel unit 7 are connected in series in sequence, and the power splitter and matching unit 3 is also connected in series with the working clock generation unit 5, the data processing unit 6, and the radio frequency channel unit 7 in sequence. The output of the power supply, remote control, and telemetry unit 1 is connected to the input of the working clock generation unit 5, and the power supply, remote control, and telemetry unit 1 and the data processing unit 6 are interconnected.

[0029] Its functions are as follows: the power supply remote control and telemetry unit 1 is used to receive the external input remote control signal, control the power on and off of the system, provide the required secondary power to the crystal oscillator reference unit 2, the working clock generating unit 5 and the data processing unit 6, receive the external remote control signal and input it into the data processing unit 6, generate and output various telemetry information of the system; the crystal oscillator reference unit 2 is used to perform impedance and power matching on the generated sinusoidal wave signal and then output the sinusoidal wave signal f2 to the power dividing matching unit 3 as a reference signal; the power dividing matching unit 3 is used to receive the sinusoidal wave signal f2 generated by the crystal oscillator reference unit, and power-divide the sinusoidal wave signal into two signals, which are respectively sent to the carrier generating unit 4 and the working clock generating unit 5 after power matching; the carrier generating unit 4 is used to receive the signal f3 output by the power dividing matching unit 3, generate a microwave direct current, and generate a microwave direct current. A variable-frequency Ka-band carrier signal f5 with appropriate frequency, power, phase noise and other indicators required for modulation is connected; the working clock generating unit 5 receives another signal f4 output by the power splitter matching unit 3, and generates a suitable frequency signal f6 required for subsequent processing; the data processing unit 6 is used to receive an external data signal, encode it, and then perform spectrum spreading and constellation mapping according to the corresponding modulation method, and then obtain a baseband signal after passing through an operational amplifier and matched filtering and transmit it to the RF channel unit 7; the RF channel unit 7 receives the Ka-band carrier signal f5 output by the carrier generating unit 4, performs power amplification on it, and then drives the mixer to realize microwave modulation and amplification of the baseband signal output by the data processing unit 6 and output and transmit the signal, and adopts an automatic gain control loop to achieve stable power output within a wide temperature range;

[0030] The overall system realizes that the carrier, code chip and data clock of a single machine come from the same signal source, effectively reducing the complexity of the ground receiving system. In addition to ensuring excellent communication performance, it can meet the requirements of special receiving terminals for portability, small size, light weight, low power consumption and high reliability.

[0031] The crystal oscillator reference unit 2 of this embodiment can use a temperature-compensated crystal oscillator that is stable, fast, low-cost and has a small package. Otherwise, a high-stable crystal oscillator or an ultra-high-stable crystal oscillator can be used. The sinusoidal wave signal generated by the crystal oscillator is output to the power division matching unit 3 after the impedance and power matching network is performed by the matching circuit in the crystal oscillator reference unit 2. The power division matching unit 3 includes a power divider 301, and the power divider 301 can be selected as a radio frequency power divider or a microwave power divider.

[0032] In this embodiment, the 100MHz sine wave signal generated by the crystal oscillator reference unit 2 has an output power of 5dBm. The power divider inside the power division and matching unit 3 divides the input signal power into two 100MHz sine wave signals. Considering the device insertion loss and the impedance matching results of the back-end device, the power of the two signals is 1dBm and 0.5dBm respectively.

[0033] The carrier generation unit 4 of this embodiment includes a first phase detector 401, a first loop filter 402, and a first voltage-controlled oscillator 403 connected in series. The output of the first phase detector 401 is also connected to the input of the first voltage-controlled oscillator 403. In other words, the first signal f3 is transmitted through the circuit consisting of the first phase detector 401, the first loop filter 402, and the first voltage-controlled oscillator 403 connected end to end to obtain and output the Ka-band carrier signal f5.

[0034] The working clock generation unit 5 of this embodiment includes a second phase detector 501, a second loop filter 502, a second voltage-controlled oscillator 503, a frequency divider 504, and a first amplifier 505, which are connected in series. The output of the second phase detector 501 is also connected to the input of the second voltage-controlled oscillator 503. The power supply port of the power supply, remote control, and telemetry unit 1 of this embodiment is connected in series with the second phase detector 501 and the first amplifier 505, respectively. This means that the power supply, remote control, and telemetry unit 1 provides the required secondary power to the second phase detector 501 and the first amplifier 505. Another signal f4 output by the power splitter and matching unit 3 is passed through a phase-locked loop circuit consisting of the second phase detector 501, the second loop filter 502, the second voltage-controlled oscillator 503, the frequency divider 504, and the first amplifier 505, which are connected end-to-end, to output a frequency signal f6.

[0035] The data processing unit 6 of this embodiment includes an FPGA 606 and a data receiving chip 605 interconnected with the FPGA 606. The FPGA 606 is also connected in series with a first operational amplifier 607 and a second operational amplifier 608 connected in parallel with each other. The output of the first amplifier 505 is also connected to the input of the FPGA 606, that is, the frequency signal f6 output by the first amplifier 505 is input into the FPGA 606. The data receiving chip 605 converts the external data signal into multiple parallel signals and sends them to the FPGA 606. The FPGA 606 receives the frequency signal f6 output by the first amplifier 505 and the external data signal, and performs AOS framing, encoding, scrambling, bit width conversion, spectrum spreading, bit width conversion, I / O delay and other processing internally before sending them to the first operational amplifier 607 and the second operational amplifier 608. The first operational amplifier 607 and the second operational amplifier 608 convert the differential digital signal processed by the FPGA 606 into a single-ended analog signal and send it to the RF channel unit 7. The FPGA 606 can output baseband signals with different symbol rates by controlling the frequency division ratio. That is, the first operational amplifier 607 outputs baseband I data, and the second operational amplifier 608 outputs baseband Q data.

[0036] In this embodiment, the power supply port of the power supply remote control and telemetry unit 1 is connected in series with the power supply interface of FPGA606, that is, the power supply remote control and telemetry unit 1 provides the required secondary power to FPGA606; at the same time, the IO interface of FPGA606 is interconnected with the telemetry information interface of the power supply remote control and telemetry unit 1, receives external remote control signals and inputs them into the data processing unit 6, generates and outputs various telemetry information of the system.

[0037] The FPGA 606 of this embodiment includes at least an input global buffer 606 - 1 , a first global buffer 606 - 2 , a direct digital frequency synthesizer 606 - 3 , a second global buffer 606 - 4 , a first frequency division module 606 - 5 , a third global buffer 606 - 6 , a second frequency division module 606 - 7 , and a fourth global buffer 606 - 8 .

[0038] The input global buffer 606-1, the first global buffer 606-2, the direct digital frequency synthesizer 606-3, and the second global buffer 606-4 are connected in series. The first global buffer 606-2 includes two output ports. After the frequency signal f6 obtained by the working clock generation unit 5 enters the input global buffer 606-1 and the first global buffer 606-2 in sequence, the first output port of the first global buffer 606-2 directly generates and outputs the spread spectrum coded working clock f7. Simultaneously, the second output port of the first global buffer 606-2 enters the direct digital frequency synthesizer 606-3 and the second global buffer 606-4 in sequence. The second global buffer 606-4 includes three output ports. The first output port of the second global buffer 606-4 directly generates and outputs the remote control and telemetry working clock f8.

[0039] The second output port of the second global buffer 606-4 is connected in series with the first frequency dividing module 606-5 and the third global buffer 606-6. That is, the frequency signal f6 passes through the input global buffer 606-1, the second output port of the first global buffer 606-2, the direct digital frequency synthesizer 606-3 and the second output port of the second global buffer 606-4, the first frequency dividing module 606-5 and the third global buffer 606-6 in sequence to obtain and output the data processing working clock f9.

[0040] The third output port of the second global buffer 606-4 is connected in series with the second frequency division module 606-7 and the fourth global buffer 606-8, that is, the frequency signal f6 passes through the input global buffer 606-1, the second output port of the first global buffer 606-2, the direct digital frequency synthesizer 606-3 and the third output port of the second global buffer 606-4, the second frequency division module 606-7 and the fourth global buffer 606-8 in sequence to obtain and output other working clocks f10.

[0041] In this embodiment, the input global buffer 606-1, the first global buffer 606-2, the direct digital frequency synthesizer 606-3, the second global buffer 606-4, the first frequency division module 606-5, the third global buffer 606-6, the second frequency division module 606-7 and the fourth global buffer 606-8 use the clock generation circuit inside the FPGA. The output spread spectrum coding working clock f7, the remote control and telemetry working clock f8, the data processing working clock f9 and other working clocks f10 all come from the sinusoidal wave signal f2 of the crystal oscillator reference unit 2, ensuring homology.

[0042] The RF channel unit 7 of this embodiment includes a second amplifier 701, a mixer chip 702, a third amplifier 704, an electrically adjustable attenuator 705, a fourth amplifier 706, a detector 707, and an isolator 708, which are sequentially connected in series with the carrier generation unit 4. The unit also includes an amplification and comparison control circuit 709 connected between the output of the detector 707 and the input of the electrically adjustable attenuator 705. Furthermore, the unit also includes a compensation circuit 703 connected to the output of the data processing unit 6, and the output of the compensation circuit 703 is connected to the input of the mixer chip 702. The output of the first voltage-controlled oscillator 403 is connected to the input of the second amplifier 701. The output of the first operational amplifier 607 and the output of the second operational amplifier 608 are both connected to the input of the compensation circuit 703.

[0043] Compensation circuit 703 suppresses the DC component of the I and Q signal leakage output by data processing unit 6, thereby achieving a carrier suppression of over 30 dB in the system of the present invention, ensuring that carrier leakage has no impact on the system's modulation and demodulation performance. Second amplifier 701 amplifies Ka-band carrier signal f5 input by carrier generation unit 4 to meet the RF drive power requirements of mixer chip 702. Mixer chip 702 functions as an orthogonal analog modulator. Baseband I and Q data output by compensation circuit 703 phase-modulate the carrier signal output by second amplifier 701. The resulting modulated signal is fed into third amplifier 704 for primary amplification. Electrically adjustable attenuator 705 dynamically compensates the output signal of third amplifier 704. Fourth amplifier 706 performs secondary amplification on the output signal of electrically adjustable attenuator 705, ensuring that it meets the system's back-end output power requirements after passing through detector 707 and isolator 708. Detector 707 converts the RF signal output by fourth amplifier 706 into a detection voltage and a reference voltage through microstrip coupling. Amplification and comparison control circuit 709 amplifies the difference between the reference voltage and the detection voltage output by detector 707, compares it with the reference voltage, and generates a control voltage to control the attenuation of the attenuator within electrically adjustable attenuator 705, forming an automatic level control loop and achieving stable power output over a wide temperature range. Isolator 708 is used to achieve impedance matching at the output signal port and isolate the modulation system's RF output port from detector 707.

[0044] In this embodiment, the RF channel unit 7 outputs a center frequency of 23.xxGHz, an output power of 0dBm at normal temperature, an output power fluctuation of less than 1dB in the range of -25°C to +60°C, a modulation mode of QPSK, and a spread spectrum pre-code rate of 512Kbps@SQPSK or 1024Kbps@SQPSK.

[0045] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details of the above embodiments. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the scope of protection of the present disclosure.

[0046] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0047] In addition, the various different implementation methods disclosed in this solution can also be arbitrarily combined, as long as they do not violate the ideas of this disclosure, they should also be regarded as the contents of the invention of this disclosure.

Claims

1. A modulation system in which carrier, chips and data are of the same origin, characterized in that: It comprises a power supply, remote control and telemetry unit (1), a crystal oscillator reference unit (2), a power division and matching unit (3), a carrier generation unit (4), a working clock generation unit (5), a data processing unit (6) and a radio frequency channel unit (7); The power supply remote control and telemetry unit (1), the crystal oscillator reference unit (2), the power division matching unit (3), the carrier generation unit (4) and the radio frequency channel unit (7) are sequentially connected in series, and the power division matching unit (3) is also sequentially connected in series with the working clock generation unit (5), the data processing unit (6) and the radio frequency channel unit (7); The output of the power supply remote control and telemetry unit (1) is connected to the input of the working clock generating unit (5), and the power supply remote control and telemetry unit (1) and the data processing unit (6) are interconnected.

2. The modulation system with carrier, code chip and data of the same source as claimed in claim 1, characterized in that: The working clock generating unit (5) comprises a second phase detector (501), a second loop filter (502), a second voltage-controlled oscillator (503), a frequency divider (504) and a first amplifier (505) which are sequentially connected in series, and the output of the second phase detector (501) is also connected to the input of the second voltage-controlled oscillator (503).

3. The modulation system with carrier, code chip and data of the same source as claimed in claim 2, characterized in that: The power supply port of the power supply remote control and telemetry unit (1) is connected in series with the second phase detector (501) and the first amplifier (505) respectively.

4. The modulation system with carrier, code chip and data of the same source as claimed in claim 2, characterized in that: The data processing unit (6) includes an FPGA (606) and a data receiving chip (605) interconnected with the FPGA (606); the FPGA (606) is further connected in series with a first operational amplifier (607) and a second operational amplifier (608) connected in parallel with each other; The output of the first amplifier (505) is connected to the input of the FPGA (606).

5. The modulation system with carrier, code chip and data of the same source as claimed in claim 4, characterized in that: The power supply port of the power supply remote control and telemetry unit (1) is connected in series with the power supply interface of the FPGA (606), and the IO interface of the FPGA (606) is interconnected with the telemetry information interface of the power supply remote control and telemetry unit (1).

6. The modulation system with carrier, code chip and data of the same source as claimed in claim 4, characterized in that: The FPGA (606) includes an input global buffer (606-1), a first global buffer (606-2), a direct digital frequency synthesizer (606-3), a second global buffer (606-4), a first frequency division module (606-5), a third global buffer (606-6), a second frequency division module (606-7) and a fourth global buffer (606-8); The input global buffer (606-1), the first global buffer (606-2), the direct digital frequency synthesizer (606-3) and the second global buffer (606-4) are sequentially connected in series, the first global buffer (606-2) includes two output ports, and the second global buffer (606-4) includes three output ports; The second output port of the second global buffer (606-4) is sequentially connected in series with the first frequency division module (606-5) and the third global buffer (606-6); The third output port of the second global buffer (606-4) is sequentially connected in series with the second frequency division module (606-7) and the fourth global buffer (606-8).

7. The modulation system with carrier, code chip and data of the same source as claimed in claim 6, characterized in that: The radio frequency channel unit (7) comprises a second amplifier (701), a mixer chip (702), a third amplifier (704), an electrically adjustable attenuator (705), a fourth amplifier (706), a detector (707) and an isolator (708) which are sequentially connected in series with the carrier generation unit (4), an amplification comparison control circuit (709) connected between the output of the detector (707) and the input of the electrically adjustable attenuator (705), and a compensation circuit (703) connected to the output of the data processing unit (6), wherein the output of the compensation circuit (703) is connected to the input of the mixer chip (702).

8. The modulation system with carrier, code chip and data of the same source as claimed in claim 7, characterized in that: The output of the first operational amplifier (607) and the output of the second operational amplifier (608) are both connected to the input of the compensation circuit (703).

9. The modulation system with carrier, code chip and data of the same source as claimed in claim 8, characterized in that: The carrier generation unit (4) comprises a first phase detector (401), a first loop filter (402) and a first voltage-controlled oscillator (403) connected in series in sequence, and the output of the first phase detector (401) is also connected to the input of the first voltage-controlled oscillator (403).

10. The modulation system with carrier, code chip and data of the same source as claimed in claim 9, characterized in that: The output of the first voltage-controlled oscillator (403) is connected to the input of the second amplifier (701).

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