Silicon carbide device and manufacturing method thereof

Abstract

This invention discloses a silicon carbide device and its manufacturing method, belonging to the field of integrated circuit technology. The manufacturing method of the silicon carbide device includes providing a substrate and an epitaxial layer on top of it. The epitaxial layer has a body region, a contact region, and at least two source / drain regions. A gate oxide layer, a gate, and a dielectric layer are sequentially disposed on the top of the epitaxial layer. An opening is provided on the top of the contact region. A sacrificial oxide layer is formed by thermal oxidation in the top of the contact region and the exposed areas of the source / drain regions. The top surface of the contact region is lower than the bottom surface of the source / drain regions. The sacrificial oxide layer and part of the sidewall material layer are etched away to form sidewalls on the sidewalls of the dielectric layer, with a gap between the bottom of the sidewalls and the top of the source / drain regions. By etching the holes to the bottom of the source / drain regions, it is easier to form subsequent Schottky diodes. Simultaneously, the gap below the sidewalls forms a more ideal contact hole profile structure, improving device performance and saving process costs and production cycle time.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a silicon carbide device and its manufacturing method. Background Technology

[0002] Third-generation semiconductors, represented by SiC, have wide applications in the lighting industry, photovoltaic power supplies, power electronics, and microwave radio frequency. Furthermore, due to its wider bandgap, critical breakdown electric field, and higher thermal conductivity, SiC is more suitable for manufacturing high-voltage, high-power semiconductor devices. However, optimizing the manufacturing process and reducing costs in silicon carbide device manufacturing has become a major concern in the industry. With continuous process iteration and evolution, the design size of silicon carbide devices has gradually shrunk, while manufacturing costs have continued to rise, ultimately leading to persistently high product prices. Traditional silicon carbide device manufacturing processes have encountered bottlenecks in via etching and contact resistance reduction. One approach is to increase the via size to reduce contact resistance, but this increases input capacitance and affects switching speed; another is to increase the implantation concentration, but this method has also reached its limits.

[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon carbide device and its manufacturing method to solve the problem of contact resistance.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a silicon carbide device, comprising the following steps:

[0006] A substrate and an epitaxial layer on top of it are provided. The epitaxial layer has a body region, a contact region and at least two source / drain regions. The body region is disposed on the opposite side and bottom of two adjacent source / drain regions. The contact region is disposed between two adjacent source / drain regions and its two sides are connected to the body region. A gate oxide layer, a gate and a dielectric layer are sequentially disposed on the top of the epitaxial layer. An opening is provided on the top of the contact region. The opening penetrates the dielectric layer and exposes at least a portion of the sidewall and at least a portion of the top surface of the source / drain region on the side near the contact region.

[0007] A sacrificial oxide layer is formed by thermal oxidation in the top of the contact area and in the area exposed by the source / drain region. The top surface of the contact area is lower than the bottom surface of the source / drain region and higher than the bottom surface of the body region.

[0008] A sidewall material layer is formed on the sacrificial oxide layer and the dielectric layer. The sacrificial oxide layer and part of the sidewall material layer are etched away to form a sidewall on the sidewall of the dielectric layer. A gap is also present between the bottom of the sidewall and the top of the source / drain region.

[0009] A concave contact metal layer is provided at the top of the contact area and in the gap.

[0010] Preferably, the method of forming the body region and the source / drain region on the epitaxial layer includes: sequentially forming a first oxide layer, a first hard mask layer, and a first photoresist layer on the epitaxial layer; etching the first hard mask layer through the first photoresist layer to expose a portion of the first oxide layer for ion implantation to form the body region; forming a sidewall mask layer on the sidewall of the first hard mask layer; performing ion implantation on the exposed area to form the source / drain region; and annealing to activate the source / drain region and the body region.

[0011] Preferably, after forming the body region and the source / drain region, the first hard mask layer is removed, a second hard mask layer is formed on the first oxide layer, the second hard mask layer, the first oxide layer and the epitaxial layer are etched, an opening is formed between two adjacent source / drain regions, the bottom surface of the opening is higher than the lower surface of the body region, an oxide is formed in the opening, the oxide and the remaining first oxide layer are connected to form a second oxide layer, and ion implantation is performed on the bottom of the opening to form a contact region.

[0012] Preferably, after forming the second oxide layer and the contact area, the second hard mask layer is removed, a polysilicon layer is formed on the second oxide layer, the polysilicon layer is etched to form a gate, and the opening and the second oxide layer on top of part of the source / drain region are exposed. A dielectric material layer is deposited on the gate and the second oxide layer, and the dielectric material layer and the second oxide layer are wet etched until at least part of the sidewalls and at least part of the top surface of the source / drain region are exposed, forming a stepped structure. The remaining second oxide layer serves as the gate oxide layer.

[0013] Preferably, the sidewall is made of silicon nitride.

[0014] Preferably, etching away the sacrificial oxide layer and part of the sidewall material layer includes: first etching the sidewall material layer to expose the sacrificial oxide layer, and then wet etching the sacrificial oxide layer to expose the gap between the bottom of the sidewall and the top of the source / drain region.

[0015] Preferably, the concave contact metal layer in the top of the contact area and the gap includes: depositing a contact metal material layer, the contact metal material layer covering the top of the dielectric layer, the sidewall, the top of the contact area and the gap, and etching away excess contact metal material layer on the top of the dielectric layer and the sidewall to form a concave contact metal layer.

[0016] Preferably, the conductivity type of the source / drain region is N-type; and the conductivity type of the contact region is P-type.

[0017] A silicon carbide device is manufactured using the silicon carbide device manufacturing method described above.

[0018] A silicon carbide device, comprising:

[0019] A substrate has an epitaxial layer on its top. The epitaxial layer has a body region, a contact region, and at least two source / drain regions. The body region is located on the opposite side and bottom of two adjacent source / drain regions. The contact region is located between two adjacent source / drain regions, and its two sides are connected to the body region. A gate oxide layer, a gate, and a dielectric layer are sequentially disposed on the top of the epitaxial layer. The top of the contact region has an opening that penetrates the dielectric layer and exposes the sidewall of the source / drain region near the contact region and at least part of its top surface, forming a stepped structure. The top surface of the contact region is lower than the bottom surface of the source / drain region but higher than the bottom surface of the body region.

[0020] A sidewall is disposed on the sidewall of the medium layer, and a gap exists between the bottom of the sidewall and the source / drain area;

[0021] A concave contact metal layer is disposed on the top of the contact area and extends along the exposed sidewalls and top of the source / drain area into the gap.

[0022] In the silicon carbide device manufacturing method provided by this invention, a more ideal cross-sectional structure is obtained by using a back-end thin film deposition process as a mask and then performing hole photolithography, hole etching, and wet etching. The characteristics of the process and design are utilized to allow the contact holes to be etched into the body region, which facilitates the formation of subsequent Schottky diodes. At the same time, this structure utilizes the sidewall process and the "inward extension structure" under the sidewall to form a more ideal contact hole cross-sectional structure. The contact metal layer and the implanted contact area can not only form a more ideal ohmic contact, but also effectively increase the contact area of ​​the hole and improve the performance of the device. At the same time, the composite sidewall structure is adopted to effectively reduce the capacitance and obtain a more ideal device figure of merit.

[0023] The silicon carbide device provided by this invention and the manufacturing method of the silicon carbide device provided by this invention belong to the same inventive concept. Therefore, the silicon carbide device provided by this invention has at least all the advantages of the manufacturing method of the silicon carbide device provided by this invention, which will not be repeated here. Attached Figure Description

[0024] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0025] Figure 1 This is a schematic diagram of a substrate structure according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of a hard mask layer structure according to an embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of the body region structure according to an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of the source / drain region structure according to an embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of the second photoresist layer structure according to an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of the structure etched along the second photoresist layer according to an embodiment of the present invention;

[0031] Figure 7 This is a schematic diagram of the second oxide layer structure according to an embodiment of the present invention;

[0032] Figure 8 This is a schematic diagram of annealing according to an embodiment of the present invention;

[0033] Figure 9 This is a schematic diagram of a polycrystalline silicon layer structure according to an embodiment of the present invention;

[0034] Figure 10 This is a schematic diagram of the gate structure according to an embodiment of the present invention;

[0035] Figure 11 This is a schematic diagram of the dielectric material layer structure according to an embodiment of the present invention;

[0036] Figure 12 This is a schematic diagram of a dielectric layer structure according to an embodiment of the present invention;

[0037] Figure 13 This is a schematic diagram of the sidewall material layer structure according to an embodiment of the present invention;

[0038] Figure 14 This is a schematic diagram of the sidewall structure according to an embodiment of the present invention;

[0039] Figure 15 This is a schematic diagram of the contact metal material layer structure according to an embodiment of the present invention;

[0040] Figure 16 This is a schematic cross-sectional view of a silicon carbide device according to an embodiment of the present invention;

[0041] Figure 17 This is an execution flowchart of an embodiment of the present invention.

[0042] In the attached image:

[0043] 100. Substrate; 101. Epitaxial layer; 102. First oxide layer; 102a. First oxide layer pattern; 103. Body region; 104. Source / drain region; 105. Opening; 106. Second oxide layer; 107. Contact region; 108. Gate oxide layer; 109. Sacrificial oxide layer; 110. Polysilicon layer; 111. Gate; 120. Dielectric material layer; 121. Dielectric layer; 130. Sidewall material layer; 131. Sidewall; 140. Contact metal material layer; 141. Contact metal layer; 200. First hard mask layer; 201. Sidewall mask layer; 202. Second hard mask layer; 300. First photoresist layer; 301. Second photoresist layer; 302. Third photoresist layer; 400. Capping layer; 500. Conductive layer. Detailed Implementation

[0044] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0045] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0046] Research has found that third-generation semiconductors, represented by SiC, have wide applications in the lighting industry, photovoltaic power supplies, power electronics, and microwave radio frequency. Furthermore, due to its larger bandgap, critical breakdown electric field, and higher thermal conductivity, SiC is more suitable for manufacturing high-voltage, high-power semiconductor devices. However, optimizing and reducing the contact resistance of vias during the manufacturing process of silicon carbide devices has become a major focus and research hotspot in the industry. With continuous process iteration and evolution, the design size of silicon carbide devices has gradually shrunk, and the size of the vias has also decreased accordingly, ultimately leading to an increase in the contact resistance. This increase in contact resistance has a very detrimental effect on device performance, such as increased threshold voltage, increased specific on-resistance, and increased heat generation.

[0047] Based on this, the core idea of ​​this invention is to propose a high-performance, low-cost SiC MOSFET device fabrication process. By using a back-end thin-film deposition process as a mask, followed by photolithography, etching, and implantation, a more ideal implantation profile structure can be obtained. The characteristics of the process and design allow the holes to be etched to the bottom of the source and drain regions, facilitating the formation of subsequent Schottky diodes. At the same time, this structure utilizes the sidewall process and the "inward extension structure" under the sidewall to form a more ideal contact hole profile structure, improving device performance and saving process costs and production cycle.

[0048] For details, please refer to Figures 1-17 This is a schematic diagram of an embodiment of the present invention. Figure 17 As shown, a method for manufacturing a silicon carbide device includes the following steps.

[0049] A substrate 100 and an epitaxial layer 101 on top of it are provided. The epitaxial layer 101 is provided with a body region 103, a contact region 107 and at least two source / drain regions 104. The body region 103 is provided on the opposite side and bottom of two adjacent source / drain regions 104. The contact region 107 is provided between two adjacent source / drain regions 104 and its two sides are connected to the body region 103. A gate oxide layer 108, a gate 111 and a dielectric layer 121 are sequentially provided on the top of the epitaxial layer 101. An opening 105 is provided on the top of the contact region 107. The opening 105 penetrates the dielectric layer 121 and exposes at least a portion of the sidewall and at least a portion of the top surface of the source / drain region 104 on the side near the contact region 107.

[0050] In the top of the contact area 107 and the area exposed by the source / drain area 104, a sacrificial oxide layer 109 is formed by a thermal oxidation process, wherein the top surface of the contact area 107 is lower than the bottom surface of the source / drain area 104 and higher than the bottom surface of the body area 103.

[0051] A sidewall material layer 130 is formed on the sacrificial oxide layer 109 and the dielectric layer 121. The sacrificial oxide layer 109 and part of the sidewall material layer 130 are etched away to form a sidewall 131 on the sidewall of the dielectric layer 121. A gap is also present between the bottom of the sidewall 131 and the top of the source / drain region 104.

[0052] A concave contact metal layer 141 is provided on the top of the contact area 107, the exposed area of ​​the body area 103, the exposed sidewalls of the source / drain area 104, and the top.

[0053] like Figure 12The structure of the substrate 100 and epitaxial layer 101 shown is illustrated. The epitaxial layer 101 has a body region 103, a contact region 107, and at least two source / drain regions 104. A gate oxide layer 108, a gate 111, and a dielectric layer 121 are sequentially disposed on the top of the epitaxial layer 101. The top of the contact region 107 and parts of the top and sidewalls of the source / drain regions 104 are exposed through an opening 105. A thin sacrificial oxide layer 109 is grown as a buffer etching layer to form sidewalls 131. The sidewall process and the "inward structure" of the contact metal layer 141 formed in the gap below the sidewalls create a relatively ideal contact hole profile.

[0054] Furthermore, the formation of the sacrificial oxide layer 109 consumes a portion of the source / drain region 104 and the contact region 107, which can modify the cross-sectional structure of the contact hole, so that the bottom of the opening 105 is etched into the body region 103. The bottom of the opening 105 is also the top surface of the contact region 107. The top surface of the contact region 107 is lower than the bottom surface of the source / drain region 104 and higher than the bottom surface of the body region 103, which facilitates the formation of the subsequent Schottky diode.

[0055] The following will be combined with the appendix Figures 1 to 16 The manufacturing method of the silicon carbide device provided in this embodiment will be described in more detail.

[0056] First, a body region 103 and a source / drain region 104 are formed on the epitaxial layer 101 by ion implantation. The formation of the body region 103 and the source / drain region 104 on the epitaxial layer 101 includes: sequentially forming a first oxide layer 102, a first hard mask layer 200, and a first photoresist layer 300 on the epitaxial layer 101; etching the first hard mask layer 200 through the first photoresist layer 300 to expose a portion of the first oxide layer 102 for ion implantation to form the body region 103; forming a sidewall mask layer 201 on the sidewall of the first hard mask layer 200; performing ion implantation on the exposed area to form the source / drain region 104; and annealing to activate the source / drain region 104 and the body region 103.

[0057] like Figure 1 As shown, the wafer in this case uses a multilayer epitaxial substrate 100. For example, the epitaxial layer 101 is made of SiC. The entire wafer containing the silicon carbide epitaxial layer 101 is cleaned using an RCA process. A first hard mask layer 200 is deposited on the entire wafer. The deposition method includes, but is not limited to, PECVD (plasma-enhanced chemical vapor deposition), ALD (atomic layer deposition), and LPCVD (low-pressure chemical vapor deposition). Subsequently, resist coating, photolithography, etching, and ion implantation processes are performed on the first hard mask layer 200 to form the body region 103. The desired photoresist pattern is formed by photolithography of the first photoresist layer 300. The exposed first hard mask layer 200 is etched, and the exposed area of ​​the first hard mask layer 200 is ion implanted to form the body region 103, such as... Figure 2As shown, then as Figure 3 As shown, a sidewall mask layer 201 is deposited on the top and sidewalls of the first hard mask layer 200 to form a source / drain region 104 within the body region 103. The source / drain region 104 is formed by ion implantation and then directly annealed to activate the body region 103 and the source / drain region 104. Conventional processes would then involve hard mask deposition in the contact region 107; however, this process is omitted in this invention due to optimization. Therefore, annealing is performed directly to activate the body region 103 and the source / drain region 104.

[0058] Next, after forming the body region 103 and the source / drain region 104, the first hard mask layer 200 is removed, and a second hard mask layer 202 is formed on the first oxide layer 102. The second hard mask layer 202, the first oxide layer 102, and the epitaxial layer 101 are etched to form an opening between two adjacent source / drain regions 104. The bottom surface of the opening 105 is higher than the lower surface of the body region 103. An oxide is formed in the opening 105. The oxide and the remaining first oxide layer 102 are connected to form a second oxide layer 106. Ion implantation is performed on the bottom of the opening 105 to form a contact region 107.

[0059] like Figure 5 As shown, after removing the first hard mask layer 200, a second hard mask layer 202 and a second photoresist layer 301 are formed on the entire wafer. The second photoresist layer 301 is photolithographically etched to define the region between two adjacent source / drain regions 104. The second hard mask layer 202 is etched, along with a portion of the first oxide layer 102 and the epitaxial layer 101, forming an opening 105 between the source / drain regions 104. Figure 6 As shown, the first oxide layer 102 is separated by the opening 105 to form a first oxide layer pattern 102a, as... Figure 7 As shown, an oxide is formed in the opening 105, and the oxide and the remaining first oxide layer 102 are connected to form a second oxide layer 106. Exemplarily, the opening 105 region is treated using a thermal oxidation process to form the oxide. Ion implantation is performed on the bottom of the opening 105 to form a contact region 107.

[0060] In one embodiment, a photoresist layer is deposited, and the opening 105 region between the source and drain regions 104 is defined by photolithography. Ion implantation is then performed to form the contact region 107, followed by photoresist removal. Figure 8 As shown, a cover layer 400 is formed, and annealing is performed to activate the contact area 107.

[0061] Next, after forming the second oxide layer 106 and the contact region 107, the second hard mask layer 202 is removed, and a polysilicon layer 110 is formed on the second oxide layer 106. The polysilicon layer 110 is etched to form the gate 111, exposing the opening 105 and the second oxide layer 106 on top of part of the source / drain region 104. A dielectric material layer 120 is deposited on the gate 111 and the second oxide layer 106. The dielectric material layer 120 and the second oxide layer 106 are wet-etched until at least part of the sidewalls and at least part of the top surface of the source / drain region 104 are exposed, forming a stepped structure. The remaining second oxide layer 106 serves as the gate oxide layer 108. The first oxide layer 102, the second oxide layer 106, the gate oxide layer 108, and the sacrificial oxide layer 109 are all made of silicon oxide, and the dielectric material layer 120 is also made of silicon oxide.

[0062] like Figure 9 As shown, after removing the second hard mask layer 202, a polysilicon layer 110 is formed, and the polysilicon layer 110 is etched to form the gate 111, as follows. Figure 10 As shown, the dielectric material layer 120 and the third photoresist layer 302 are deposited, followed by photolithography etching of the contact holes. After the etching process is completed, wet etching is performed to increase the hole area. It is important to note that the amount of wet etching needs to be controlled to ensure the formation of the step structure, such as... Figure 12 The structure shown.

[0063] Next, a sacrificial oxide layer 109 is formed by thermal oxidation in the top of the contact area 107 and the area exposed by the source / drain area 104, wherein the top surface of the contact area 107 is lower than the bottom surface of the source / drain area 104 and higher than the bottom surface of the body area 103.

[0064] In this embodiment, a thin sacrificial oxide layer 109 is grown as a buffer etching layer. The generated sacrificial oxide layer 109 makes the top surface of the contact area 107 lower than the bottom surface of the source / drain area 104 and higher than the bottom surface of the body area 103. After removing the sacrificial oxide layer 109, the opening 105 will completely expose one sidewall of the source / drain area 104 and expose a part of the body area 103.

[0065] A sidewall material layer 130 is then formed on the sacrificial oxide layer 109 and the dielectric layer 121. The sacrificial oxide layer 109 and a portion of the sidewall material layer 130 are etched away to form a sidewall 131 on the sidewall of the dielectric layer 121. A gap exists between the bottom of the sidewall 131 and the top of the source / drain region 104. For example, the sidewall 131 is made of silicon nitride.

[0066] Specifically, etching away the sacrificial oxide layer 109 and part of the sidewall material layer 130 includes: first etching the sidewall material layer 130 to expose the sacrificial oxide layer 109, and then wet etching the sacrificial oxide layer 109 to expose the gap between the bottom of the sidewall 131 and the top of the source / drain region 104.

[0067] like Figure 13 As shown, a silicon nitride sidewall material layer 130 of a certain thickness is deposited on the entire wafer, and then etched to completely remove the bottom silicon nitride sidewall material layer 130, thus fully exposing the sacrificial oxide layer 109. Subsequently, wet etching is performed to expose the required contact hole areas, such as... Figure 14 As shown, the contact hole region includes the gap between the bottom of the opening 105 and the sidewall 131 and the top of the source / drain region 104.

[0068] A concave contact metal layer 141 is provided on the top of the contact area 107 and in the gap. That is, a concave contact metal layer 141 is provided on the top of the contact area 107, the exposed area of ​​the body area 103, the exposed sidewalls of the source / drain area 104, and the top.

[0069] Ohmic contact metal deposition and ohmic contact annealing processes are performed, and unreacted metal is removed by wet etching. Specifically, forming a concave contact metal layer 141 on the top of the contact area 107 and in the gap includes: depositing a contact metal material layer 140, which covers the top of the dielectric layer 121, the sidewall 131, the top of the contact area 107, and the gap; and etching away excess contact metal material layer 140 on the top of the dielectric layer 121 and the sidewall of the sidewall 131 to form a concave contact metal layer 141.

[0070] like Figure 14 As shown, after removing the sacrificial oxide layer 109, a slightly wider and deeper new opening 105 is obtained. The bottom surface of the opening 105 is also the top surface of the contact area 107. The opening 105 exposes the sidewalls of the source / drain region 104, part of the body region 103, and the top surface of the contact area 107. Figure 15 As shown, a contact metal material layer 140 is deposited on the entire wafer, and the contact metal material layer 140 is also filled in the gap between the sidewall 131 and the source / drain region 104. The excess contact metal material layer 140 on the sidewall 131 is removed, and the concave contact metal layer 141 covers the top surface of the contact region 107, the sidewall and part of the top surface of the source / drain region 104, and a part of the body region 103.

[0071] In one embodiment, the source / drain region 104 has an N-type conductivity and the contact region 107 has a P-type conductivity.

[0072] like Figure 16 As shown, a conductive layer 500 is deposited and filled into the opening 105. The conductive layer 500 fills the opening 105 and covers the top surface of the dielectric layer 121. The conductive layer 500 can be made of aluminum.

[0073] Based on the same technical concept, the present invention also provides a silicon carbide device, which is manufactured using the silicon carbide device manufacturing method described above.

[0074] Based on the same technical concept, the present invention also provides a silicon carbide device, comprising:

[0075] A substrate 100 has an epitaxial layer 101 on its top. The epitaxial layer 101 has a body region 103, a contact region 107, and at least two source / drain regions 104. The body region 103 is located on the opposite side and bottom of two adjacent source / drain regions 104. The contact region 107 is located between two adjacent source / drain regions 104, and its two sides are connected to the body region 103. A gate oxide layer 108, a gate 111, and a dielectric layer 121 are sequentially disposed on the top of the epitaxial layer 101. An opening 105 is provided on the top of the contact region 107. The opening 105 penetrates the dielectric layer 121 and exposes the sidewall of the source / drain region 104 near the contact region 107 and at least part of its top surface, forming a stepped structure. The top surface of the contact region 107 is lower than the bottom surface of the source / drain region 104 and higher than the bottom surface of the body region 103.

[0076] Sidewall 131 is disposed on the sidewall of the medium layer 121, and there is a gap between the bottom of the sidewall 131 and the source / drain region 104.

[0077] A concave contact metal layer 141 is disposed on the top of the contact area 107 and extends along the exposed sidewalls and top of the source / drain area 104 into the gap.

[0078] The top surface of the contact area 107 is lower than the bottom surface of the source / drain area 104 and higher than the bottom surface of the body area 103. A portion of the body area 103 is exposed through the opening 105. The exposed body area 103 facilitates the formation of a Schottky diode. The contact metal layer 141 is filled in the gap below the sidewall 131 to form an "inward structure", which forms a more ideal ohmic contact, effectively increases the contact area of ​​the hole, improves the performance of the device, and at the same time adopts a composite sidewall structure, which effectively reduces the capacitance and obtains a more ideal device figure of merit.

[0079] At least two source / drain regions 104 are provided in the epitaxial layer 101. A body region 103 is provided on the outer side of the source / drain regions 104. An opening 105 is provided between two adjacent source / drain regions 104. The bottom of the opening 105 is a contact region 107. A gate oxide layer 108, a gate 111 and a dielectric layer 121 are also provided on the epitaxial layer 101. The gate oxide layer 108 exposes part of the top surface of the source / drain regions 104. The gate oxide layer 108 and the dielectric layer 121 together cover the gate 111, forming a stepped structure between the opening 105 and the top surface of the source / drain regions 104. The contact metal layer 141 covers the bottom surface of the opening 105 and extends along the exposed body region 103 and the sidewalls of the source / drain regions 104 to form the stepped structure, and fills the gap between the bottom of the sidewall 131 and the top surface of the source / drain regions 104.

[0080] For example, the gate oxide layer 108 and the dielectric layer 121 are both silicon oxide, the gate 111 is polysilicon, and the sidewall 131 is made of silicon nitride.

[0081] like Figure 16 As shown, the contact metal layer 141 and the sidewall 131 are also filled with a conductive layer 500. The source / drain region 104 has an N-type conductivity; the contact region 107 has a P-type conductivity.

[0082] This invention provides a fabrication process for a high-performance, low-capacitance SiC MOSFET device. It utilizes a back-end thin-film deposition process as a mask, followed by hole lithography, hole etching, and wet etching to obtain a relatively ideal cross-sectional structure. The process and design features allow the contact holes to be etched into the body region 103, facilitating the subsequent formation of a Schottky diode. Simultaneously, this structure utilizes sidewall technology and an "inward extension structure" beneath the sidewalls to create a relatively ideal contact hole cross-sectional structure. The contact metal layer 141 and the implanted N-type SiC contact not only form a relatively ideal ohmic contact but also effectively increase the contact area of ​​the hole, improving device performance. Furthermore, the composite sidewall structure effectively reduces capacitance, achieving a relatively ideal device figure of merit.

[0083] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a silicon carbide device, characterized in that, Includes the following steps: A substrate and an epitaxial layer on top of it are provided. The epitaxial layer has a body region, a contact region and at least two source / drain regions. The body region is disposed on the opposite side and bottom of two adjacent source / drain regions. The contact region is disposed between two adjacent source / drain regions and its two sides are connected to the body region. A gate oxide layer, a gate and a dielectric layer are sequentially disposed on the top of the epitaxial layer. An opening is provided on the top of the contact region. The opening penetrates the dielectric layer and exposes at least a portion of the sidewall and at least a portion of the top surface of the source / drain region on the side near the contact region. A sacrificial oxide layer is formed by thermal oxidation in the top of the contact area and in the area exposed by the source / drain region. The top surface of the contact area is lower than the bottom surface of the source / drain region and higher than the bottom surface of the body region. A sidewall material layer is formed on the sacrificial oxide layer and the dielectric layer. The sacrificial oxide layer and part of the sidewall material layer are etched away to form a sidewall on the sidewall of the dielectric layer. A gap is also present between the bottom of the sidewall and the top of the source / drain region. A concave contact metal layer is provided at the top of the contact area and in the gap.

2. The method for manufacturing a silicon carbide device according to claim 1, characterized in that, The process of setting the body region and source / drain region on the epitaxial layer includes: sequentially forming a first oxide layer, a first hard mask layer, and a first photoresist layer on the epitaxial layer; etching the first hard mask layer through the first photoresist layer to expose a portion of the first oxide layer for ion implantation to form the body region; forming a sidewall mask layer on the sidewall of the first hard mask layer; performing ion implantation on the exposed area to form the source / drain region; and annealing to activate the source / drain region and the body region.

3. The method for manufacturing a silicon carbide device according to claim 2, characterized in that, After forming the body region and source / drain region, the first hard mask layer is removed, and a second hard mask layer is formed on the first oxide layer. The second hard mask layer, the first oxide layer, and the epitaxial layer are etched to form an opening between two adjacent source / drain regions. The bottom surface of the opening is higher than the lower surface of the body region. An oxide is formed in the opening. The oxide and the remaining first oxide layer are connected to form a second oxide layer. Ion implantation is performed on the bottom of the opening to form a contact region.

4. The method for manufacturing a silicon carbide device according to claim 3, characterized in that, After forming the second oxide layer and the contact area, the second hard mask layer is removed, a polysilicon layer is formed on the second oxide layer, the polysilicon layer is etched to form the gate, and the second oxide layer on top of the opening and part of the source / drain region is exposed. A dielectric material layer is deposited on the gate and the second oxide layer, and the dielectric material layer and the second oxide layer are wet etched until at least part of the sidewalls and at least part of the top surface of the source / drain region are exposed, forming a stepped structure. The remaining second oxide layer serves as the gate oxide layer.

5. The method for manufacturing a silicon carbide device according to claim 1, characterized in that, The sidewall is made of silicon nitride.

6. The method for manufacturing a silicon carbide device according to claim 1, characterized in that, Etching away the sacrificial oxide layer and part of the sidewall material layer includes: first etching the sidewall material layer to expose the sacrificial oxide layer, and then wet etching the sacrificial oxide layer to expose the gap between the bottom of the sidewall and the top of the source / drain region.

7. The method for manufacturing a silicon carbide device according to claim 1, characterized in that, The method of setting a concave contact metal layer on the top of the contact area and in the gap includes: depositing a contact metal material layer, the contact metal material layer covering the top of the dielectric layer, the sidewall, the top of the contact area and the gap, and etching away excess contact metal material layer on the top of the dielectric layer and the sidewall to form a concave contact metal layer.

8. The method for manufacturing a silicon carbide device according to claim 1, characterized in that, The source / drain regions are of N-type conductivity; the contact regions are of P-type conductivity.

9. A silicon carbide device, characterized in that, The silicon carbide device is manufactured using the manufacturing method of any one of claims 1-8, comprising: A substrate has an epitaxial layer on its top. The epitaxial layer has a body region, a contact region, and at least two source / drain regions. The body region is located on the opposite side and bottom of two adjacent source / drain regions. The contact region is located between two adjacent source / drain regions, and its two sides are connected to the body region. A gate oxide layer, a gate, and a dielectric layer are sequentially disposed on the top of the epitaxial layer. The top of the contact region has an opening that penetrates the dielectric layer and exposes the sidewall of the source / drain region near the contact region and at least part of its top surface, forming a stepped structure. The top surface of the contact region is lower than the bottom surface of the source / drain region but higher than the bottom surface of the body region. A sidewall is disposed on the sidewall of the medium layer, and a gap exists between the bottom of the sidewall and the source / drain area; A concave contact metal layer is disposed on the top of the contact area and extends along the exposed sidewalls and top of the source / drain area into the gap.

Images