SOI LDMOS device with double-buried-layer structure and manufacturing method of SOI LDMOS device

Abstract

The invention provides an SOI LDMOS device with a double-buried-layer structure and a manufacturing method thereof. The device comprises a bulk silicon layer, a buried oxide layer and a top silicon layer which are sequentially stacked from bottom to top, the first conductive type drift region, the second conductive type body region and the polycrystalline silicon field plate are formed in the top silicon layer; the second conduction type first buried layer and the second conduction type second buried layer are formed in the first conduction type drift region, and the transverse size of the first buried layer and the transverse size of the second buried layer are smaller than the transverse size of the first conduction type drift region. And forming a transverse super junction with the first conduction type drift region through the second conduction type first buried layer and the second conduction type second buried layer. The tail ends of the second conductive type first buried layer and the second conductive type second buried layer generate high electric fields, so that the electric field near the drain electrode of the device is improved, the breakdown voltage is improved, the concentration of the first conductive type drift region is improved, and the specific on-resistance is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a SOI LDMOS device with a double-buried layer structure and a manufacturing method thereof. Background Art

[0002] MOSFET power semiconductor devices are very important in the field of power integrated circuits, especially lateral double-diffused MOSFET power devices (LDMOS) among MOSFET power devices. Due to their good compatibility with CMOS processes, good frequency characteristics, low noise and fast switching speed, they are widely used in fields such as switching power supplies and motor drives.

[0003] A silicon-on-insulator (SOI) LDMOS device comprises a P-type silicon substrate, a buried oxide layer, and a top silicon layer stacked vertically from bottom to top. Laterally, the top silicon layer includes an N-type drift region and a P-type body region that form a reverse-biased depletion layer for a PN junction, with an inversion layer forming at the interface between the top silicon and the buried oxide layer. The device drain is formed in the N-type drift region, and the source is formed in the P-type body region. As the device drain voltage increases, the lateral depletion layer expands into the N-type drift region and connects to the inversion layer. Existing SOI LDMOS devices have poor vertical withstand voltage, and vertical breakdown is prone to occur at the interface between the top silicon and the buried oxide layer. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a SOIL DMOS device with a double buried layer structure and a manufacturing method thereof, so as to solve the problem of poor longitudinal withstand voltage and low breakdown voltage of the existing SOI LDMOS device.

[0005] To achieve the above-mentioned objectives and other related objectives, the present application provides a SOI LDMOS device with a dual-buried layer structure, comprising: a body silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially from bottom to top; a first conductivity type drift region, a second conductivity type body region, and a polysilicon field plate formed in the top silicon layer, the first conductivity type drift region being vertically adjacent to the buried oxide layer, and the polysilicon field plate being laterally adjacent to the second conductivity type body region; a second conductivity type first buried layer and a second conductivity type second buried layer formed in the first conductivity type drift region, the first buried layer and the second buried layer having lateral dimensions smaller than those of the first conductivity type drift region, and forming a lateral super junction with the first conductivity type drift region through the second conductivity type first buried layer and the second conductivity type second buried layer; a drain (D) being formed at one end of the first conductivity type drift region away from the second conductivity type body region, a source (S) being formed in the second conductivity type body region, and the polysilicon field plate constituting a gate (G).

[0006] Preferably, the distance between the top of the second conductive type second buried layer and the top of the first conductive type drift region is 2 μm-5 μm, and the distance between the bottom of the second buried layer and the top of the first buried layer is 2 μm-3 μm.

[0007] Preferably, the lateral dimension of the first buried layer is smaller than the lateral dimension of the second buried layer.

[0008] Preferably, the lateral size of the first buried layer is 6 μm-12 μm, and the lateral size of the second buried layer is 10 μm-16 μm.

[0009] Preferably, the first buried layer and the second buried layer have different doping concentrations.

[0010] Preferably, the first conductivity type is N-type, and the second conductivity type is P-type.

[0011] Preferably, the bottom end of the second conductive type body region is not longitudinally adjacent to the buried oxide layer, the longitudinal dimension of the polysilicon field plate is larger than the longitudinal dimension of the second conductive type body region and the bottom end is not longitudinally adjacent to the buried oxide layer.

[0012] The present application also provides a method for manufacturing a SOI LDMOS device having a double buried layer structure, comprising:

[0013] Step 1: manufacturing a semiconductor base layer, wherein the semiconductor base layer includes a bulk silicon layer, a buried oxide layer, and a first portion of a top silicon layer stacked sequentially from bottom to top;

[0014] Step 2, forming a first buried layer in the first portion of the top silicon layer;

[0015] Step 3, after forming a second portion of the top silicon layer on the first portion of the top silicon layer, forming a second buried layer in the second portion of the top silicon layer;

[0016] Step 4: after forming the third portion of the top silicon layer on the second portion of the top silicon layer, forming a first conductivity type drift region in the top silicon layer vertically adjacent to the buried oxide layer;

[0017] Step 5: after forming a second conductive type body region in the first conductive type drift region, forming a polysilicon field plate laterally adjacent to the second conductive type body region;

[0018] Step six: forming a drain injection region in the first conductivity type drift region near one end of the second buried layer, and forming a source injection region in the second conductivity type body region.

[0019] Preferably, an oxygen implantation isolation process is performed on the substrate to obtain a semiconductor base layer.

[0020] Preferably, the temperature during annealing in the oxygen implantation isolation process is 1100° C.-1300° C.

[0021] Preferably, the lateral size of the first buried layer is 6 μm-12 μm, and the lateral size of the second buried layer is 10 μm-16 μm.

[0022] Preferably, the second buried layer and the first buried layer have the second conductivity type, and the second buried layer and the first buried layer have different doping concentrations.

[0023] Preferably, the distance between the bottom of the second buried layer and the top of the first buried layer is 2μm-3μm, and the distance between the bottom of the second buried layer and the top of the first buried layer is adjusted by regulating the thickness of the second part of the epitaxially grown top silicon layer.

[0024] Preferably, the distance between the top of the second buried layer and the top of the first conductive type drift region is 2μm-5μm, and the distance between the top of the second buried layer and the top of the first conductive type drift region is adjusted by regulating the thickness of the third part of the epitaxially grown top silicon layer.

[0025] Preferably, the bottom end of the second conductive type body region is not longitudinally adjacent to the buried oxide layer, the longitudinal dimension of the polysilicon field plate is larger than the longitudinal dimension of the second conductive type body region and the bottom end is not longitudinally adjacent to the buried oxide layer.

[0026] Preferably, after implementing step six, metal contacts are formed on the top of the polysilicon field plate, the drain injection region and the source injection region respectively, completing the fabrication of the gate (G), the drain (D) and the source (S).

[0027] As described above, the SOI LDMOS device with a dual buried layer structure and the manufacturing method thereof provided in the present application have the following beneficial effects: a PL-SOI LDMOS structure with a lateral super junction is formed by utilizing the second conductive type dual buried layer and the first conductive type drift region, thereby achieving the purpose of increasing the device breakdown voltage while reducing the specific on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 A schematic cross-sectional view of a SOIL DMOS device with a double buried layer structure provided in an embodiment of the present application is shown;

[0030] Figure 2 A flow chart showing a method for manufacturing a SOI LDMOS device with a double buried layer structure provided by an embodiment of the present application;

[0031] Figures 3A-3F The figure shows a schematic diagram of a cross-sectional structure of a device formed after completing each step in the manufacturing method of a SOIL DMOS device with a double buried layer structure provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present application through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present application from the disclosure herein. The present application may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0034] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating positions or location relationships, are used solely to facilitate the description of this application and simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0036] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0037] See also Figure 1 , which shows a schematic cross-sectional structure diagram of a SOIL DMOS device with a double buried layer structure provided by an embodiment of the present application. Figure 1As shown, the SOI LDMOS device with a double buried layer structure includes: a body silicon layer 100, a buried oxide layer 110 and a top silicon layer 120 stacked in sequence from bottom to top; a first conductive type drift region, a second conductive type body region 150 and a polysilicon field plate 160 formed in the top silicon layer 120; a second conductive type first buried layer 130 and a second conductive type second buried layer 131 formed in the first conductive type drift region, wherein the lateral dimensions of the first buried layer 130 and the second buried layer 131 are smaller than the lateral dimensions of the first conductive type drift region, and a lateral super junction is formed with the first conductive type drift region through the second conductive type first buried layer 130 and the second conductive type second buried layer 131.

[0038] This embodiment is explained by taking the first conductivity type as N type and the second conductivity type as P type as an example. In other embodiments, the first conductivity type may be P type and the second conductivity type may be N type.

[0039] The first conductivity type drift region is vertically adjacent to the buried oxide layer 110, i.e., the bottom end of the first conductivity type drift region contacts the upper surface of the buried oxide layer 110. The second conductivity type body region 150 is formed in the first conductivity type drift region, and its bottom end does not contact the upper surface of the buried oxide layer 110. The polysilicon field plate 160 is laterally adjacent to the second conductivity type body region 150, and its bottom end does not contact the upper surface of the buried oxide layer 110. Its longitudinal dimension is greater than the longitudinal dimension of the second conductivity type body region 150.

[0040] A drain (D) is formed at one end of the first conductive type drift region away from the second conductive type body region 150 , a source (S) is formed in the second conductive type body region 150 , and the polysilicon field plate 160 constitutes a gate (G).

[0041] The first buried layer 130 has a smaller lateral dimension than the second buried layer 131. Preferably, the lateral dimension of the first buried layer 130 is 6 μm-12 μm, and the lateral dimension of the second buried layer 131 is 10 μm-16 μm. The first buried layer 130 and the second buried layer 131 have different doping concentrations.

[0042] In the figure, the left ends of the first buried layer 130 and the second buried layer 131 are adjacent to the polysilicon field plate 160, but this is not limited to the case; the first buried layer 130 and the second buried layer 131 are located below the second conductive type body region 150, but this is not limited to the case, as long as the area where the first buried layer 130 and the second buried layer 131 are located and the area where the second conductive type body region 150 is located do not overlap.

[0043] The ends of the first buried layer 130 and the second buried layer 131 (the right end in the figure) both generate a high electric field, thereby improving the electric field near the device drain, preventing premature breakdown of the device drain, and achieving the purpose of increasing the breakdown voltage. At the same time, the second conductive type first buried layer 130 and the second conductive type second buried layer 131 are mutually depleted with the first conductive type drift region, which can increase the concentration of the first conductive type drift region and reduce the specific on-resistance. Compared with traditional SOI LDMOS, the purpose of increasing the breakdown voltage while reducing the specific on-resistance is achieved (the specific on-resistance of traditional SOI LDMOS will increase to the 2.5th power as the breakdown voltage increases).

[0044] In order to better achieve the above purpose, the distance between the top of the second conductive type second buried layer 131 and the top of the first conductive type drift region is 2μm-5μm, and the distance between the bottom of the second buried layer 131 and the top of the first buried layer 130 is 2μm-3μm.

[0045] See also Figure 2 , which shows a flow chart of a method for manufacturing a SOI LDMOS device with a double buried layer structure provided by an embodiment of the present application.

[0046] like Figure 2 As shown, the method for manufacturing the SOI LDMOS device with a double buried layer structure includes the following steps:

[0047] Step 1: manufacturing a semiconductor base layer, wherein the semiconductor base layer includes a bulk silicon layer, a buried oxide layer, and a first portion of a top silicon layer stacked sequentially from bottom to top;

[0048] Step 2, forming a first buried layer in the first portion of the top silicon layer;

[0049] Step 3, after forming a second portion of the top silicon layer on the first portion of the top silicon layer, forming a second buried layer in the second portion of the top silicon layer;

[0050] Step 4: after forming the third portion of the top silicon layer on the second portion of the top silicon layer, forming a first conductivity type drift region in the top silicon layer vertically adjacent to the buried oxide layer;

[0051] Step 5: after forming a second conductive type body region in the first conductive type drift region, forming a polysilicon field plate laterally adjacent to the second conductive type body region;

[0052] Step six: forming a drain injection region in the first conductivity type drift region near one end of the second buried layer, and forming a source injection region in the second conductivity type body region.

[0053] In step 1, the substrate is subjected to an isolation by implantation of oxygen (SIMOX) process to obtain a semiconductor base layer. Under high temperature conditions, high-dose oxygen ions are implanted into the single crystal silicon to form an isolation layer. Under ultra-high temperature annealing conditions, a semiconductor base layer with a three-layer structure of top silicon, silicon dioxide buried layer, and bulk silicon is formed. Figure 3A As shown, the semiconductor base layer includes a bulk silicon layer 100, a buried oxide layer 110 and a first portion 1201 of a top silicon layer stacked sequentially from bottom to top.

[0054] As an example, the temperature of ultra-high temperature annealing is 1100°C-1300°C.

[0055] In step 2, if Figure 3B As shown, the steps of forming the first buried layer 130 include: forming a first mask layer having a pattern of the first buried layer 130 on the first part 1201 of the top silicon layer; performing a first ion implantation using the first mask layer as a mask to form the first buried layer 130 in the first part 1201 of the top silicon layer; and removing the first mask layer.

[0056] As an example, the lateral dimension of the first buried layer 130 is 6 μm-12 μm.

[0057] In step three, if Figure 3C As shown, a second portion 1202 of the top silicon layer is first formed on the first portion 1201 of the top silicon layer through an epitaxial growth process, and then a second buried layer 131 is formed in the second portion 1202 of the top silicon layer.

[0058] The steps of forming the second buried layer 131 include: forming a second mask layer having a pattern of the second buried layer 131 on the second portion 1202 of the top silicon layer; performing a second ion implantation using the second mask layer as a mask to form the second buried layer 131 in the second portion 1202 of the top silicon layer; and removing the second mask layer.

[0059] As an example, the lateral dimension of the second buried layer 131 is 10 μm-16 μm. The second buried layer 131 and the first buried layer 130 have different doping concentrations.

[0060] After repeated experiments and verification, it was found that if the distance between the bottom end of the second buried layer 131 and the top end of the first buried layer 130 is too large or too small, the electric field near the drain of the SOI LDMOS device cannot be optimized. Preferably, the distance between the bottom end of the second buried layer 131 and the top end of the first buried layer 130 is 2μm-3μm. The distance between the bottom end of the second buried layer 131 and the top end of the first buried layer 130 can be adjusted by controlling the thickness of the second portion 1202 of the epitaxially grown top silicon layer.

[0061] In step 4, if Figure 3DAs shown, the third part 1203 of the top silicon layer is first formed on the second part 1202 of the top silicon layer by an epitaxial growth process, and then a first conductive type drift region vertically adjacent to the buried oxide layer 110 is formed in the top silicon layer 120 by ion implantation, that is, the bottom end of the first conductive type drift region is in contact with the upper surface of the buried oxide layer 110.

[0062] Repeated experiments have shown that when the distance between the top of the second buried layer 131 and the top of the first conductivity type drift region is 2μm-5μm, the high electric field generated at the end of the second buried layer 131 (the right end in the figure) can better modulate the electric field within the device and reduce the specific on-resistance. The distance between the top of the second buried layer 131 and the top of the first conductivity type drift region can be adjusted by controlling the thickness of the third portion 1203 of the epitaxially grown top silicon layer. The second buried layer 131 and the first buried layer 130 have the second conductivity type.

[0063] In step five, if Figure 3E As shown, a second conductive type body region 150 is first formed in the first conductive type drift region by ion implantation, and the bottom end of the second conductive type body region 150 does not contact the upper surface of the buried oxide layer 110 .

[0064] Next, a polysilicon field plate 160 is formed laterally adjacent to the second conductivity type body region 150 , with its bottom end not in contact with the upper surface of the buried oxide layer 110 and its longitudinal dimension greater than that of the second conductivity type body region 150 .

[0065] The steps of forming the polysilicon field plate 160 include: forming a trench with a high aspect ratio in the top silicon layer 120 by an etching process; depositing a polysilicon layer in the trench; and removing the polysilicon layer outside the trench by a grinding or etch-back process.

[0066] In step six, if Figure 3F As shown, a drain implantation region 170 is formed in the first conductive type drift region near the end of the second buried layer 131 by ion implantation, and a source implantation region 180 is formed in the second conductive type body region 150 .

[0067] Next, metal contacts are formed on the top of the polysilicon field plate 160 , the drain implant region 170 , and the source implant region 180 , respectively, to complete the fabrication of the gate (G), drain (D), and source (S).

[0068] The ends of the first buried layer 130 and the second buried layer 131 (the right end in the illustration) both generate high electric fields, thereby improving the electric field near the device drain, preventing premature breakdown of the device drain and increasing the breakdown voltage. Furthermore, the mutual depletion between the second-conductivity-type first buried layer 130 and the second-conductivity-type second buried layer 131 and the first-conductivity-type drift region increases the concentration of the first-conductivity-type drift region, thereby reducing the specific on-resistance. Compared to traditional SOI LDMOS, this achieves both increased breakdown voltage and reduced specific on-resistance.

[0069] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present application. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0070] In summary, the SOI LDMOS device with a dual buried layer structure and its manufacturing method provided by this application improves the device breakdown voltage while reducing the device's specific on-resistance. Therefore, this application effectively overcomes various shortcomings of the prior art and has high industrial application value.

[0071] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed herein shall be covered by the claims of this application.

Claims

1. A SOI LDMOS device with a double buried layer structure, characterized in that: The device includes: a body silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top; a first conductive type drift region, a second conductive type body region and a polysilicon field plate formed in the top silicon layer, the first conductive type drift region is vertically adjacent to the buried oxide layer, and the polysilicon field plate is laterally adjacent to the second conductive type body region; a second conductive type first buried layer and a second conductive type second buried layer are formed in the first conductive type drift region, the lateral dimensions of the first buried layer and the second buried layer are smaller than the lateral dimensions of the first conductive type drift region, and a lateral super junction is formed with the first conductive type drift region through the second conductive type first buried layer and the second conductive type second buried layer; a drain (D) is formed at one end of the first conductive type drift region away from the second conductive type body region, a source (S) is formed in the second conductive type body region, and the polysilicon field plate constitutes a gate (G).

2. The device according to claim 1, characterized in that The distance between the top of the second conductive type second buried layer and the top of the first conductive type drift region is 2 μm-5 μm, and the distance between the bottom of the second buried layer and the top of the first buried layer is 2 μm-3 μm.

3. The device according to claim 1, characterized in that A lateral dimension of the first buried layer is smaller than a lateral dimension of the second buried layer.

4. The device according to claim 3, characterized in that The lateral size of the first buried layer is 6 μm-12 μm, and the lateral size of the second buried layer is 10 μm-16 μm.

5. The device according to claim 1, wherein The first buried layer and the second buried layer have different doping concentrations.

6. The device according to claim 1, characterized in that The first conductivity type is N-type, and the second conductivity type is P-type.

7. The device according to claim 1, characterized in that The bottom end of the second conductive type body region is not longitudinally adjacent to the buried oxide layer. The longitudinal dimension of the polysilicon field plate is larger than that of the second conductive type body region and the bottom end is not longitudinally adjacent to the buried oxide layer.

8. A method for manufacturing a SOI LDMOS device having a double buried layer structure, characterized in that: The method comprises: Step 1: preparing a semiconductor base layer, wherein the semiconductor base layer includes a bulk silicon layer, a buried oxide layer, and a first portion of a top silicon layer stacked sequentially from bottom to top; Step 2: forming a first buried layer in the first portion of the top silicon layer; Step three, after forming a second portion of the top silicon layer on the first portion of the top silicon layer, forming a second buried layer in the second portion of the top silicon layer; Step 4: after forming the third portion of the top silicon layer on the second portion of the top silicon layer, forming a first conductivity type drift region in the top silicon layer vertically adjacent to the buried oxide layer; Step 5: after forming a second conductive type body region in the first conductive type drift region, forming a polysilicon field plate laterally adjacent to the second conductive type body region; Step six: forming a drain injection region in the first conductivity type drift region near one end of the second buried layer, and forming a source injection region in the second conductivity type body region.

9. The method according to claim 8, characterized in that An oxygen implantation isolation process is performed on the substrate to obtain the semiconductor base layer.

10. The method according to claim 9, characterized in that The temperature during annealing in the oxygen injection isolation process is 1100° C.-1300° C.

11. The method according to claim 8, characterized in that The lateral size of the first buried layer is 6 μm-12 μm, and the lateral size of the second buried layer is 10 μm-16 μm.

12. The method according to claim 8, characterized in that The second buried layer and the first buried layer have a second conductivity type, and the second buried layer and the first buried layer have different doping concentrations.

13. The method according to claim 8, characterized in that The distance between the bottom end of the second buried layer and the top end of the first buried layer is 2μm-3μm, and the distance between the bottom end of the second buried layer and the top end of the first buried layer is adjusted by regulating the thickness of the second part of the epitaxially grown top silicon layer.

14. The method according to claim 8, characterized in that The distance between the top of the second buried layer and the top of the first conductive type drift region is 2μm-5μm, and the distance between the top of the second buried layer and the top of the first conductive type drift region is adjusted by regulating the thickness of the third part of the epitaxially grown top silicon layer.

15. The method according to claim 8, characterized in that The bottom end of the second conductive type body region is not longitudinally adjacent to the buried oxide layer. The longitudinal dimension of the polysilicon field plate is larger than that of the second conductive type body region and the bottom end is not longitudinally adjacent to the buried oxide layer.

16. The method according to claim 8, characterized in that After implementing step six, metal contacts are formed on the top of the polysilicon field plate, the drain injection region, and the source injection region, respectively, to complete the fabrication of the gate (G), drain (D), and source (S).

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