A vertical light-emitting diode chip and its preparation method

Abstract

The present invention relates to the technical field of LEDs and discloses a vertical light-emitting diode chip and a method for fabricating the same. The chip comprises an epitaxial layer and a conductive substrate, wherein an N-type conductive step and an isolation trench are formed on the epitaxial layer. A current spreading layer, a first insulating layer, a P-type metal reflective layer, and a P-type metal conductive layer are disposed on one side of the epitaxial layer. The first insulating layer covers the current spreading layer, a first through-hole is formed on the first insulating layer, the P-type metal reflective layer is disposed on the first insulating layer and contacts the current spreading layer through the first through-hole, and the P-type metal conductive layer covers the P-type metal reflective layer. The first insulating layer comprises a first insulating sublayer, a second insulating sublayer, and a third insulating sublayer stacked in sequence, each of which is a SiO2 thin film formed by reacting N2O and SiH4 gases. Implementation of the present invention can significantly reduce stress in the insulating layer and improve the substrate stripping yield.

Description

Technical Field

[0001] The present invention relates to the technical field of LEDs, and in particular to a vertical light emitting diode chip and a preparation method thereof. Background Art

[0002] Light-emitting diode chips are widely used in lighting, display and other fields due to their advantages of energy saving and high efficiency. Many of these applications involve extremely high power, such as outdoor lighting, automotive lighting, etc. These high-power chips require the use of vertically structured light-emitting diode chips.

[0003] The fabrication process for vertically structured LED chips requires peeling the epitaxial layer from the substrate. After substrate peeling, the epitaxial layer wrinkles and peels off. This peeling is caused by numerous factors, the most important of which is the stress of the first insulating layer formed on the epitaxial layer. The greater the stress in the first insulating layer, the more severe the epitaxial layer peeling after substrate peeling. Commonly used insulating layer materials include SiO2 or SiNx. SiO2 produced using existing processes exhibits very high stress, while SiNx absorbs a portion of the chip's light at specific wavelengths, ultimately reducing the light output efficiency of the LED. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a vertical light emitting diode chip and a preparation method thereof, which can significantly reduce the stress of the insulating layer and improve the stripping yield of the substrate.

[0005] To solve the above technical problems, the present invention provides a vertical light-emitting diode chip in a first aspect, comprising an epitaxial layer and a conductive substrate, wherein an N-type conductive step and an isolation trench are formed on the epitaxial layer, and a current spreading layer, a first insulating layer, a P-type metal reflective layer, and a P-type metal conductive layer are provided on one side of the epitaxial layer, wherein the first insulating layer covers the current spreading layer, a first through-hole is formed on the first insulating layer, the P-type metal reflective layer is provided on the first insulating layer and contacts the current spreading layer through the first through-hole, and the P-type metal conductive layer covers the P-type metal reflective layer and contacts the first insulating layer;

[0006] A second insulating layer is provided on the P-type metal conductive layer, and a second through hole is provided on the second insulating layer and penetrates the N-type conductive step. An N-type metal conductive layer is provided on the second insulating layer, and the N-type metal conductive layer contacts the epitaxial layer through the second through hole.

[0007] A third insulating layer is provided on the other side of the epitaxial layer, and the third insulating layer covers the isolation trench. A third through hole is formed at the location of the isolation trench, penetrating from the third insulating layer to the P-type metal conductive layer, and a P-type pad is provided at the third through hole.

[0008] The conductive substrate is bonded to the N-type metal conductive layer through a bonding layer;

[0009] Among them, the first insulating layer includes a first insulating sublayer, a second insulating sublayer and a third insulating sublayer stacked in sequence; the first insulating sublayer, the second insulating sublayer and the third insulating sublayer are all SiO2 films formed by the reaction of N2O and SiH4 gases.

[0010] As an improvement to the above solution, the first insulating sublayer includes a first SiO2 film and a second SiO2 film that are grown alternately periodically, with the number of periods being 5-7;

[0011] The second insulating sublayer includes a third SiO2 film and a fourth SiO2 film that are grown alternately in a periodic manner, with the number of periods being 5-7;

[0012] The third insulating sublayer includes a fifth SiO2 film and a sixth SiO2 film that are grown alternately in a periodic manner, with the number of periods being 5-7.

[0013] As an improvement to the above solution, during the formation of the first SiO2 film, the third SiO2 film and the fifth SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is controlled within the range of (9-26):1;

[0014] During the formation of the second SiO2 film, the fourth SiO2 film and the sixth SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is controlled within the range of (2.2-6):1.

[0015] As an improvement to the above solution, during the formation of the first SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α1, during the formation of the second SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α2, during the formation of the third SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α3, during the formation of the fourth SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α4, during the formation of the fifth SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α5, and during the formation of the sixth SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α6, satisfying:

[0016] α1=(16-26): 1, α2=(3.3-6): 1;

[0017] α3=(12-20):1, α4=(2.6-5):1;

[0018] α5=(9-13.3):1, α6=(2.2-3.4):1.

[0019] As an improvement to the above solution, during the formation of the first SiO2 film, the flow rate of N2O is 2400sccm-2600sccm, and the flow rate of SiH4 is 100sccm-150sccm;

[0020] During the formation of the second SiO2 film, the flow rate of N2O is 1000sccm-1200sccm, and the flow rate of SiH4 is 200sccm-300sccm;

[0021] During the formation of the third SiO2 film, the flow rate of N2O is 1800sccm-2000sccm, and the flow rate of SiH4 is 100sccm-150sccm;

[0022] During the formation of the fourth SiO2 film, the flow rate of N2O is 800 sccm-1000 sccm, and the flow rate of SiH4 is 200 sccm-300 sccm;

[0023] During the formation of the fifth SiO2 film, the flow rate of N2O is 1800 sccm-2000 sccm, and the flow rate of SiH4 is 150 sccm-200 sccm;

[0024] During the formation of the sixth SiO2 film, the flow rate of N2O is 800 sccm-1000 sccm, and the flow rate of SiH4 is 300 sccm-350 sccm.

[0025] As an improvement of the above solution, in each cycle, the deposition thickness of the first SiO2 film is 100Å-200Å, and the deposition thickness of the second SiO2 film is 100Å-200Å;

[0026] The deposition thickness of the third SiO2 film is 400Å-600Å, and the deposition thickness of the fourth SiO2 film is 400Å-600Å;

[0027] The deposition thickness of the fifth SiO2 film is 200Å-300Å, and the deposition thickness of the sixth SiO2 film is 200Å-300Å.

[0028] As an improvement to the above solution, the deposition thickness of the first SiO2 film and the second SiO2 film are equal;

[0029] The deposition thickness of the third SiO2 film and the fourth SiO2 film are equal;

[0030] The deposition thicknesses of the fifth SiO 2 film and the sixth SiO 2 film are equal.

[0031] As an improvement to the above solution, the second insulating layer includes an Al2O3 thin film layer and a SiO2 thin film layer stacked in sequence, the Al2O3 thin film layer is deposited to a thickness of 600Å-1200Å, and the SiO2 thin film layer is deposited to a thickness of 6000Å-8000Å;

[0032] The third insulating layer is an Al2O3 layer.

[0033] Accordingly, the second aspect of the present invention further provides a method for preparing the vertical light-emitting diode chip, comprising:

[0034] Providing a temporary substrate, preparing an epitaxial layer on the temporary substrate, and forming an N-type conductive step on the epitaxial layer;

[0035] Preparing a current spreading layer and a first insulating layer on the epitaxial layer, and etching the first insulating layer to form a first through hole to expose a portion of the current spreading layer;

[0036] preparing a P-type metal reflective layer on the first insulating layer and the first through hole;

[0037] forming a P-type metal conductive layer on the first insulating layer, so that the P-type metal conductive layer covers the P-type metal reflective layer;

[0038] forming a second insulating layer on the first insulating layer so that the second insulating layer covers the P-type metal conductive layer, and etching the second insulating layer until the N-type conductive step is exposed to form a second through hole;

[0039] preparing an N-type metal conductive layer on the second insulating layer, and filling the second through hole with the N-type metal conductive layer;

[0040] Providing a conductive substrate, arranging a bonding layer on the conductive substrate and / or the N-type metal conductive layer, and performing a bonding process on the conductive substrate and the N-type metal conductive layer;

[0041] peeling off the temporary substrate to form a patterned structure on the epitaxial layer;

[0042] Etching the epitaxial layer until the first insulating layer is exposed to form an isolation trench;

[0043] forming a third insulating layer on the patterned structure and the isolation trench of the epitaxial layer;

[0044] The corresponding position of the isolation groove is etched until the P-type metal conductive layer is exposed to form a third through hole, and a P-type pad is prepared at the third through hole.

[0045] As an improvement to the above solution, a bonding layer is provided on the conductive substrate and / or the N-type metal conductive layer, comprising:

[0046] performing a thinning process on the temporary substrate, and then providing a bonding layer on the N-type metal conductive layer;

[0047] The thickness of the temporary substrate after thinning is 200 μm-350 μm;

[0048] The temporary substrate is peeled off by a laser peeling process, wherein the process parameters of the laser peeling process are: a laser spot radius of 12 μm-16 μm, a spot moving speed of 2500 mm / s-3000 mm / s, and a laser power of 80 W-100 W.

[0049] The implementation of the present invention has the following beneficial effects:

[0050] In the present invention, the first insulating layer covers the current spreading layer, a first through-hole is formed in the first insulating layer, the P-type metal reflective layer is disposed on the first insulating layer and contacts the current spreading layer through the first through-hole, and the P-type metal conductive layer covers the P-type metal reflective layer and contacts the first insulating layer. The first insulating layer isolates the current spreading layer and the P-type metal reflective layer, ensuring that current flows along the designed path. However, the portion of the current spreading layer exposed at the first through-hole is in direct contact with the P-type metal reflective layer, forming a conductive path that allows current to be smoothly transmitted from the current spreading layer to the P-type metal reflective layer, thereby improving the chip's luminous efficiency and heat dissipation performance. A P-type metal conductive layer is then disposed on the P-type metal reflective layer, which can serve as part of an electrode, providing a current channel and ensuring that current can be smoothly transmitted to an external circuit.

[0051] Furthermore, the first insulating layer includes a first insulating sublayer, a second insulating sublayer and a third insulating sublayer stacked in sequence. The first insulating sublayer, the second insulating sublayer and the third insulating sublayer are all SiO2 films formed by the reaction of N2O and SiH4 gases. The three sublayers form multiple interfaces through interlayer molecular bonding. When the peeling stress acts on the substrate, the multilayer structure can disperse the concentrated stress to the interfaces of each layer, and convert the lateral shear stress into interlayer micro-deformation, avoiding stress concentration leading to film cracking, greatly reducing the stress of the SiO2 film layer, and thus greatly reducing the abnormality of epitaxial layer falling off after substrate peeling. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 : A schematic structural diagram of a vertical light-emitting diode chip in the present invention;

[0053] Figure 2: A schematic structural diagram of the first insulating layer in the present invention;

[0054] Figure 3 : A schematic structural diagram of the structure obtained after step (101) of the present invention is completed;

[0055] Figure 4 : A schematic structural diagram of the structure obtained after step (102) of the present invention is completed;

[0056] Figure 5 : A schematic structural diagram of the structure obtained after step (201) of the present invention is completed;

[0057] Figure 6 : A schematic structural diagram of the structure obtained after step (202) of the present invention is completed;

[0058] Figure 7 : A schematic structural diagram of the structure obtained after step (3) in the present invention is completed;

[0059] Figure 8 : A schematic structural diagram of the structure obtained after step (4) of the present invention is completed;

[0060] Figure 9 : A schematic structural diagram of the structure obtained after step (5) of the present invention is completed;

[0061] Figure 10 : A schematic structural diagram of the structure obtained after step (6) of the present invention is completed;

[0062] Figure 11 : A schematic structural diagram of the structure obtained after step (701) of the present invention is completed;

[0063] Figure 12 : A schematic structural diagram of the structure obtained after step (703) of the present invention is completed;

[0064] Figure 13 : A schematic structural diagram of the structure obtained after step (8) of the present invention is completed;

[0065] Figure 14 : A schematic structural diagram of the structure obtained after step (9) of the present invention is completed;

[0066] Figure 15 : A structural diagram of the structure obtained after step (10) in the present invention is completed.

[0067] Figure numerals: 10-temporary substrate; 11-epitaxial layer; 111-N-type semiconductor layer; 112-active light-emitting layer; 113-P-type semiconductor layer; 114-N-type conductive step; 12-current spreading layer; 13-first insulating layer; 131-first insulating sublayer; 1311-first SiO2 film; 1312-second SiO2 film; 132-second insulating sublayer; 1321-third SiO2 film; 1322-fourth SiO2 film; 133-third insulating sublayer; 1331-fifth SiO2 film; 1332-sixth SiO2 film; 134-first through hole; 14-P-type metal reflective layer; 15-P-type metal conductive layer; 16-second insulating layer; 161-second through hole; 17-N-type metal conductive layer; 18-conductive substrate; 19-bonding layer; 20-isolation trench; 21-third insulating layer; 22-P-type pad. DETAILED DESCRIPTION

[0068] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail with reference to specific embodiments below.

[0069] In order to solve the above problems, the first aspect of the present invention provides a vertical light emitting diode chip, see Figure 1 , including an epitaxial layer 11, a current spreading layer 12, a first insulating layer 13, a P-type metal reflective layer 14, a P-type metal conductive layer 15, a second insulating layer 16, an N-type metal conductive layer 17, a conductive substrate 18, a bonding layer 19, a third insulating layer 21 and a P-type pad 22.

[0070] Specifically, an N-type conductive step 114 and an isolation trench 20 are formed on the epitaxial layer 11. A current spreading layer 12, a first insulating layer 13, a P-type metal reflective layer 14, and a P-type metal conductive layer 15 are provided on one side of the epitaxial layer 11. The first insulating layer 13 covers the current spreading layer 12. A first through-hole 134 is formed on the first insulating layer 13. The P-type metal reflective layer 14 is provided on the first insulating layer 13 and contacts the current spreading layer 12 through the first through-hole 134. The P-type metal conductive layer 15 covers the P-type metal reflective layer 14 and contacts the first insulating layer 13. The first insulating layer 13 isolates the current spreading layer 12 and the P-type metal reflective layer 14, ensuring that the current flows along the designed path. However, the portion of the current spreading layer 12 exposed at the first through-hole 134 is in direct contact with the P-type metal reflective layer 14, forming a conductive path. This allows the current to be smoothly transmitted from the current spreading layer 12 to the P-type metal reflective layer 14, thereby improving the luminous efficiency and heat dissipation performance of the chip. Subsequently, a P-type metal conductive layer 15 is provided on the P-type metal reflective layer 14, which can serve as part of the electrode, provide a current channel, and ensure that the current can be smoothly transmitted to the external circuit.

[0071] Specifically, a second insulating layer 16 is disposed on the P-type metal conductive layer 15, and a second through-hole 161 is disposed on the second insulating layer 16, penetrating to the N-type conductive step 114. An N-type metal conductive layer 17 is disposed on the second insulating layer 16, and the N-type metal conductive layer 17 contacts the epitaxial layer 11 through the second through-hole 161. The second insulating layer 16 can isolate the P-type metal conductive layer 15 and the N-type metal conductive layer 17, preventing direct contact between the two and causing a short circuit, ensuring the stability and safety of the chip's internal structure, forming a low-resistance ohmic connection, and promoting efficient injection of current from the N-type electrode into the N-type semiconductor layer 111.

[0072] Specifically, a third insulating layer 21 is provided on the other side of the epitaxial layer 11, and the third insulating layer 21 covers the isolation groove 20 to prevent current crosstalk or leakage between adjacent light-emitting units. A third through hole (not marked in the figure) is formed at the position of the isolation groove 20, which passes through the third insulating layer 21 to the P-type metal conductive layer 15. A P-type pad 22 is provided at the third through hole to form a vertical current path, reduce the resistance loss caused by the lateral current expansion, and improve the current injection efficiency.

[0073] Specifically, the conductive substrate 18 is bonded to the N-type metal conductive layer 17 through the bonding layer 19, forming a vertical current path from the N-type semiconductor layer 111 to the conductive substrate 18, thereby reducing resistance loss and voltage drop, suppressing current crowding effect, improving luminous efficiency, and forming a low thermal resistance vertical heat dissipation channel, which can quickly transfer the Joule heat and junction temperature generated when the chip is working to the external environment.

[0074] Preferably, see Figure 2 The first insulating layer 13 comprises a first insulating sublayer 131, a second insulating sublayer 132, and a third insulating sublayer 133, stacked sequentially. The three sublayers form multiple interfaces through interlayer molecular bonding. When peeling stress acts on the temporary substrate 10, the multilayer structure disperses the concentrated stress to the interfaces between the layers, converting the lateral shear stress into micro-deformations between the layers, thereby preventing stress concentration from causing film cracking. Preferably, the first insulating sublayer 131, the second insulating sublayer 132, and the third insulating sublayer 133 are all SiO2 films formed by the reaction of N2O and SiH4 gases.

[0075] Furthermore, the first insulating sublayer 131 includes a first SiO2 film 1311 and a second SiO2 film 1312 that are periodically grown alternately, with a period number of 5-7; the second insulating sublayer 132 includes a third SiO2 film 1321 and a fourth SiO2 film 1322 that are periodically grown alternately, with a period number of 5-7; the third insulating sublayer 133 includes a fifth SiO2 film 1331 and a sixth SiO2 film 1332 that are periodically grown alternately, with a period number of 5-7; the first insulating sublayer 131, the second insulating sublayer 132 and the third insulating sublayer 133 are all designed to be a periodic stacking structure, and a stress buffer layer can be formed between the layers to effectively disperse local stress concentration, further reduce the stress of the first insulating layer 13, and reduce the possibility of the epitaxial layer 11 falling off after the temporary substrate 10 is peeled off.

[0076] Furthermore, during the formation of the first SiO2 film 1311, the third SiO2 film 1321 and the fifth SiO2 film 1331, the ratio of the N2O flow rate to the SiH4 flow rate is controlled within the range of (9-26):1; during the formation of the second SiO2 film 1312, the fourth SiO2 film 1322 and the sixth SiO2 film 1332, the ratio of the N2O flow rate to the SiH4 flow rate is controlled within the range of (2.2-6):1. When the ratio of the N2O flow rate to the SiH4 flow rate is small, excessive SiH4 results in residual Si-H bonds that are not completely oxidized, forming a relatively loose SiO2 film. When the ratio of the N2O flow rate to the SiH4 flow rate is large, more oxygen promotes complete oxidation, forming a Si-O-Si network, and forming a highly dense SiO2 film. In the present application, the first insulating sublayer 131, the second insulating sublayer 132 and the third insulating sublayer 133 are all formed by alternating stacking of SiO2 films with a large flow ratio and SiO2 films with a small flow ratio, so that the compressive stress layer and the tensile stress layer can alternate, offset each other's macroscopic stress, hinder crack expansion through the multi-layer interface, improve the peeling strength of the epitaxial layer 11, and reduce thermal stress mismatch, further reduce the stress of the first insulating layer 13, and reduce the possibility of the epitaxial layer 11 falling off after the temporary substrate 10 is peeled off.

[0077] Furthermore, during the formation of the first SiO2 film 1311, the ratio of the N2O flow rate to the SiH4 flow rate is α1, during the formation of the second SiO2 film 1312, the ratio of the N2O flow rate to the SiH4 flow rate is α2, during the formation of the third SiO2 film 1321, the ratio of the N2O flow rate to the SiH4 flow rate is α3, during the formation of the fourth SiO2 film 1322, the ratio of the N2O flow rate to the SiH4 flow rate is α4, during the formation of the fifth SiO2 film 1331, the ratio of the N2O flow rate to the SiH4 flow rate is α5, during the formation of the sixth SiO2 film 1332, the ratio of the N2O flow rate to the SiH4 flow rate is α6, The ratio of the O flow rate to the SiH4 flow rate is α6, satisfying: α1=(16-26):1, α2=(3.3-6):1; α3=(12-20):1, α4=(2.6-5):1; α5=(9-13.3):1, α6=(2.2-3.4):1, which can improve the adhesion between the first insulating layer 13 and the epitaxial layer 11, form a stress gradient in the vertical direction, and avoid excessive stress accumulation in a single direction. The reduction in the ratio of the N2O flow rate to the SiH4 flow rate, on the one hand, forms a loose and porous structure, which absorbs stress and participates in stress release through local plastic deformation, and on the other hand, alleviates the interfacial shear stress caused by temperature change through the gradual change of the thermal expansion coefficient, thereby reducing the risk of peeling from many aspects.

[0078] In some specific and preferred embodiments, during the formation of the first SiO2 film 1311, the flow rate of N2O is 2400sccm-2600sccm, exemplarily 2400sccm, 2450sccm, 2500sccm, 2550sccm, and 2600sccm, but not limited thereto; the flow rate of SiH4 is 100sccm-150sccm, exemplarily 100sccm, 110sccm, 120sccm, 130sccm, 140sccm, and 150sccm, but not limited thereto; during the formation of the second SiO2 film 1312, the flow rate of N2O is 1000sccm-150sccm, exemplarily 100sccm, 110sccm, 120sccm, 130sccm, 140sccm, and 150sccm, but not limited thereto. sccm-1200sccm, exemplarily 1000sccm, 1050sccm, 1100sccm, 1150sccm, 1200sccm, but not limited thereto; the flow rate of SiH4 is 200sccm-300sccm, exemplarily 200sccm, 220sccm, 240sccm, 260sccm, 280sccm, 300sccm, but not limited thereto; during the formation of the third SiO2 film 1321, the flow rate of N2O is 1800sccm-2000sccm, exemplarily 1800sccm, 1850sccm, 1900sccm, 1950sccm, sccm, 2000sccm, but not limited thereto, the flow rate of SiH4 is 100sccm-150sccm, exemplarily 100sccm, 110sccm, 120sccm, 130sccm, 140sccm, 150sccm, but not limited thereto; during the formation of the fourth SiO2 film 1322, the flow rate of N2O is 800sccm-1000sccm, exemplarily 800sccm, 850sccm, 900sccm, 950sccm, 1000sccm, but not limited thereto, the flow rate of SiH4 is 200sccm-300sccm, exemplarily 200sccm ccm, 220 sccm, 240 sccm, 260 sccm, 280 sccm, and 300 sccm, but not limited thereto; during the formation of the fifth SiO2 film 1331, the flow rate of N2O is 1800 sccm-2000 sccm, and exemplarily is 1800 sccm, 1850 sccm, 1900 sccm, 1950 sccm, and 2000 sccm, but not limited thereto; the flow rate of SiH4 is 150 sccm-200 sccm, and exemplarily is 150 sccm, 160 sccm, 170 sccm, 180 sccm, 190 sccm, and 200 sccm, but not limited thereto;During the formation of the sixth SiO2 film 1332, the flow rate of N2O is 800 sccm-1000 sccm, exemplarily 800 sccm, 850 sccm, 900 sccm, 950 sccm, and 1000 sccm, but not limited thereto. The flow rate of SiH4 is 300 sccm-350 sccm, exemplarily 300 sccm, 310 sccm, 320 sccm, 330 sccm, 340 sccm, and 350 sccm, but not limited thereto.

[0079] Preferably, the deposition thickness of the first SiO2 film 1311 is 100Å-200Å, exemplarily 100Å, 120Å, 140Å, 160Å, 180Å, 200Å, but not limited thereto; the deposition thickness of the second SiO2 film 1312 is 100Å-200Å, exemplarily 100Å, 120Å, 140Å, 160Å, 180Å, 200Å, but not limited thereto. The deposition thickness of the third SiO2 film 1321 is 400Å-600Å, and examples are 400Å, 450Å, 500Å, 550Å, and 600Å, but not limited thereto. The deposition thickness of the fourth SiO2 film 1322 is 400Å-600Å, and examples are 400Å, 450Å, 500Å, 550Å, and 600Å, but not limited thereto. The deposition thickness of the fifth SiO2 film 1331 is 200Å-300Å, and examples are 200Å, 220Å, 240Å, 260Å, 280Å, and 300Å, but not limited thereto. The deposition thickness of the sixth SiO2 film 1332 is 200Å-300Å, and examples are 200Å, 220Å, 240Å, 260Å, 280Å, and 300Å, but not limited thereto.

[0080] Furthermore, the first SiO2 film 1311 and the second SiO2 film 1312 are deposited with the same thickness; the third SiO2 film 1321 and the fourth SiO2 film 1322 are deposited with the same thickness; the fifth SiO2 film 1331 and the sixth SiO2 film 1332 are deposited with the same thickness, so that the compressive stress of the first insulating layer 13 is less than 150 Dyne / cm 2 , the peeling yield of the temporary substrate 10 reaches more than 95%.

[0081] Preferably, the second insulating layer 16 includes an Al 2 O 3 thin film layer and a SiO 2 thin film layer stacked in sequence, which can effectively isolate the P-type metal conductive layer 15 and the N-type metal conductive layer 17 .

[0082] Furthermore, the deposition thickness of the Al2O3 thin film layer is 600Å-1200Å, exemplified by 600Å, 700Å, 800Å, 900Å, 1000Å, 1100Å, and 1200Å, but not limited thereto; the deposition thickness of the SiO2 thin film layer is 6000Å-8000Å, exemplified by 6000Å, 6200Å, 6400Å, 6600Å, 6800Å, 7000Å, 7200Å, 7400Å, 7600Å, 7800Å, and 8000Å, but not limited thereto.

[0083] Preferably, the third insulating layer 21 is an Al2O3 layer, which can effectively isolate external electric field interference and prevent leakage current. It can also block the penetration of water vapor and corrosive substances in the environment, avoid the performance degradation of the LED chip due to moisture absorption, and reduce the total reflection loss of light on the chip surface, thereby improving the light extraction efficiency.

[0084] Accordingly, the present invention also provides a method for preparing the vertical light-emitting diode chip, comprising the following steps:

[0085] (1) providing a temporary substrate 10, preparing an epitaxial layer 11 on the temporary substrate 10, and forming an N-type conductive step 114 on the epitaxial layer 11;

[0086] (2) preparing a current spreading layer 12 and a first insulating layer 13 on the epitaxial layer 11, and etching the first insulating layer 13 to form a first through hole 134 to expose a portion of the current spreading layer 12;

[0087] (3) Preparing a P-type metal reflective layer 14 on the first insulating layer 13 and the first through hole 134;

[0088] (4) preparing a P-type metal conductive layer 15 on the first insulating layer 13 so that the P-type metal conductive layer 15 covers the P-type metal reflective layer 14;

[0089] (5) Preparing a second insulating layer 16 on the first insulating layer 13 so that the second insulating layer 16 covers the P-type metal conductive layer 15, and etching the second insulating layer 16 until the N-type conductive step 114 is exposed to form a second through hole 161;

[0090] (6) Preparing an N-type metal conductive layer 17 on the second insulating layer 16 , and allowing the N-type metal conductive layer 17 to fill the second through hole 161 ;

[0091] (7) Providing a conductive substrate 18, disposing a bonding layer 19 on the conductive substrate 18 and / or the N-type metal conductive layer 17, and bonding the conductive substrate 18 and the N-type metal conductive layer 17;

[0092] (8) peeling off the temporary substrate 10 and forming a patterned structure on the epitaxial layer 11;

[0093] (9) Etching the epitaxial layer 11 until the first insulating layer 13 is exposed to form an isolation trench 20;

[0094] (10) Preparing a third insulating layer 21 on the patterned structure of the epitaxial layer 11 and the isolation trench 20;

[0095] (11) Etching is performed on the corresponding position of the isolation trench 20 until the P-type metal conductive layer 15 is exposed to form a third through hole, and a P-type pad 22 is prepared at the third through hole.

[0096] Each step is described in detail below. Figure 3-Figure 14 .

[0097] Regarding step (1), a temporary substrate 10 is provided, an epitaxial layer 11 is prepared on the temporary substrate 10, and an N-type conductive step 114 is formed on the epitaxial layer 11;

[0098] This step specifically includes:

[0099] Step (101) provides a temporary substrate 10, and sequentially prepares an epitaxial layer 11 on the temporary substrate 10. The epitaxial layer 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113, which are sequentially arranged. Figure 3 As shown;

[0100] Preferably, the temporary substrate 10 may be a sapphire substrate or the like.

[0101] Preferably, the N-type semiconductor layer 111 may be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited thereto; the active light-emitting layer 112 may be an InGaN / GaN layer, an InGaN / AlGaN layer, or an AlGaN / AlGaN layer, but is not limited thereto; the P-type semiconductor layer 113 may be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but is not limited thereto.

[0102] Optionally, the N-type semiconductor layer 111 , the active light-emitting layer 112 and the P-type semiconductor layer 113 may be prepared by deposition or other conventionally known methods, exemplified by metal organic chemical vapor deposition (MOCVD), which will not be described in detail herein.

[0103] Step (102) performs photolithography and etching on the P-type semiconductor layer 113 until the N-type semiconductor layer 111 is exposed, forming an N-type conductive step 114, as shown in FIG. Figure 4 shown.

[0104] Exemplarily, a photoresist is coated on the P-type semiconductor layer 113 . After exposure and development, the P-type semiconductor layer 113 is etched until the N-type semiconductor layer 111 is exposed. The photoresist is removed to form the N-type conductive step 114 .

[0105] Optionally, the photoresist may be a positive photoresist. After exposure and development, the exposed portion is the portion to be etched. The etching process may be dry etching or wet etching. More preferably, the etching process is dry etching, which can better control the size of the N-type conductive step 114. Exemplary dry etching methods include inductively coupled plasma etching (ICP) etching, reactive ion etching (RIE) etching, and the like.

[0106] Regarding step (2), a current spreading layer 12 and a first insulating layer 13 are prepared on the epitaxial layer 11, and the first insulating layer 13 is etched to form a first through hole 134 to expose a portion of the current spreading layer 12;

[0107] This step specifically includes:

[0108] Step (201) deposits the material of the current spreading layer 12 on the epitaxial layer 11 and the N-type conductive step 114, and then performs photolithography and etching to obtain the current spreading layer 12. Figure 5 ;

[0109] Exemplarily, the material for the current spreading layer 12 is deposited on the P-type semiconductor layer 113 and the N-type conductive step 114 to form a layer structure. Subsequently, a photoresist is coated on the layer structure. After exposure and development, the excess portion is exposed. The exposed portion is then etched away, and the photoresist is removed to obtain the current spreading layer 12. Optionally, the etching process includes, but is not limited to, wet etching, and the removal can be performed using an etching solution.

[0110] Optionally, the material of the current spreading layer 12 includes but is not limited to indium tin oxide, and the deposition method of the material of the current spreading layer 12 includes but is not limited to magnetron sputtering. The thickness of the current spreading layer 12 is determined according to actual conditions, and the present invention does not make any specific limitations on this.

[0111] Step (202) deposits the material of the first insulating layer 13 on the current spreading layer 12 and on the P-type semiconductor layer 113 and the N-type conductive step 114 not covered by the current spreading layer 12, and then performs photolithography and etching to form a first through hole 134 to expose a portion of the current spreading layer 12, thereby obtaining the first insulating layer 13. Figure 6 ;

[0112] Exemplarily, the material of the first insulating layer 13 is deposited on the current spreading layer 12 and on the P-type semiconductor layer 113 and the N-type conductive step 114 not covered by the current spreading layer 12 to form a layer structure. Subsequently, a positive photoresist is coated on the surface of the layer structure. After exposure and development, the excess portion is exposed. The exposed portion is then removed by etching to form the first through hole 134 and expose a portion of the current spreading layer 12. The positive photoresist is removed to obtain the first insulating layer 13. Optionally, the etching process includes, but is not limited to, wet etching, and specifically, BOE etching can be used for removal.

[0113] Furthermore, the first insulating layer 13 includes a first insulating sublayer 131, a second insulating sublayer 132 and a third insulating sublayer 133 stacked in sequence. The first insulating sublayer 131, the second insulating sublayer 132 and the third insulating sublayer 133 are all SiO2 films formed by the reaction of N2O and SiH4 gases. The first insulating sublayer 131 includes a first SiO2 film 1311 and a second SiO2 film 1312 that are periodically grown alternately, with a period number of 5-7. The second insulating sublayer 132 includes a third SiO2 film 1321 and a fourth SiO2 film 1322 that are periodically grown alternately, with a period number of 5-7. The third insulating sublayer 133 includes a fifth SiO2 film 1331 and a sixth SiO2 film 1332 that are periodically grown alternately, with a period number of 5-7.

[0114] It can be understood that the material of the first insulating layer 13 is deposited on the P-type semiconductor layer 113, including: alternately depositing a first SiO2 film 1311 and a second SiO2 film 1312 on the P-type semiconductor layer 113 to form a first insulating sub-layer 131, then alternately depositing a third SiO2 film 1321 and a fourth SiO2 film 1322 to form a second insulating sub-layer 132, and finally alternately depositing a fifth SiO2 film 1331 and a sixth SiO2 film 1332 to form a third insulating sub-layer 133. The deposition processes of the first SiO2 film 1311, the second SiO2 film 1312, the third SiO2 film 1321, the fourth SiO2 film 1322, the fifth SiO2 film 1331 and the sixth SiO2 film 1332 include but are not limited to MOCVD.

[0115] Regarding step (3), a P-type metal reflective layer 14 is prepared on the first insulating layer 13 and the first through hole 134;

[0116] This step specifically includes:

[0117] A photoresist is coated on the surface of the first insulating layer 13 and in the first through-hole 134. After exposure and development, a patterned photoresist structure is formed. Subsequently, the material of the P-type metal reflective layer 14 is plated using the patterned photoresist structure as a mask. Finally, a lift-off process is used to remove the material layer and the photoresist on the photoresist, leaving the material layer of the P-type metal reflective layer 14 on the surface of the first insulating layer 13 and in the first through-hole 134, thereby forming the P-type metal reflective layer 14. Please refer to 7.

[0118] Optionally, the plating process of the material of the P-type metal reflective layer 14 can be one of sputtering and evaporation, and the stripping process uses a stripping liquid to remove the material layer and the photoresist. The stripping liquid can be a stripping liquid commonly used in the field and is not specifically limited in this application.

[0119] Furthermore, the material of the P-type metal reflective layer 14 is one or more of Ag, Ni, and Ti; more preferably, the P-type metal reflective layer 14 includes an Ag layer, a Ni layer, and a Ti layer stacked in sequence, the deposition thickness of the Ag layer is 1500Å-2000Å, the deposition thickness of the Ni layer is 300Å-500Å, and the deposition thickness of the Ti layer is 300Å-500Å.

[0120] Regarding step (4), a P-type metal conductive layer 15 is prepared on the first insulating layer 13 so that the P-type metal conductive layer 15 covers the P-type metal reflective layer 14;

[0121] This step specifically includes:

[0122] A photoresist is coated on the P-type metal reflective layer 14 and on the first insulating layer 13 not covered by the P-type metal reflective layer 14. After exposure and development, a patterned photoresist structure is formed. The patterned photoresist structure is then used as a mask to plate the material of the P-type metal conductive layer 15. Finally, a stripping process is used to remove the material layer and the photoresist on the photoresist, leaving a material layer of the P-type metal conductive layer 15 on the first insulating layer 13 and the P-type metal reflective layer 14, thereby forming a P-type metal conductive layer 15 covering the P-type metal reflective layer 14. Figure 8 ;

[0123] Optionally, the plating process of the material of the P-type metal conductive layer 15 can be one of sputtering and evaporation, and the stripping process can specifically use a stripping liquid to remove the material layer and the photoresist. The stripping liquid can be a stripping liquid conventionally used in the field and is not specifically limited in this application.

[0124] Furthermore, the material of the P-type metal conductive layer 15 is one or more of Ti, Pt, Au, and Cr; more preferably, the P-type metal conductive layer 15 includes a Ti layer, a Pt layer, an Au layer, and a Cr layer stacked in sequence, the deposition thickness of the Ti layer is 200Å-300Å, the deposition thickness of the Pt layer is 1500Å-2000Å, the deposition thickness of the Au layer is 4000Å-8000Å, and the deposition thickness of the Cr layer is 200Å-500Å.

[0125] Regarding step (5), a second insulating layer 16 is formed on the first insulating layer 13 so that the second insulating layer 16 covers the P-type metal conductive layer 15, and the second insulating layer 16 is etched until the N-type conductive step 114 is exposed, thereby forming a second through hole 161;

[0126] This step specifically includes:

[0127] A second insulating layer 16 is deposited on the P-type metal conductive layer 15 and on the first insulating layer 13 not covered by the P-type metal conductive layer 15 to form a second insulating layer 16 structure. A positive photoresist is then coated on the surface of the second insulating layer 16. After exposure and development, the excess portion is exposed. The exposed portion is then removed by etching until the N-type conductive step 114 is exposed. The positive photoresist is removed to form a second through hole 161. Figure 9 , the second through hole 161 can be used as an N-type conductive through hole.

[0128] Optionally, the etching process may be dry etching or wet etching. More preferably, the etching process is dry etching. Exemplary dry etching methods include ICP etching, RIE etching, and the like.

[0129] Furthermore, the material of the second insulating layer 16 is Al2O3 and / or SiO2; more preferably, the second insulating layer 16 includes an Al2O3 thin film layer and a SiO2 thin film layer stacked in sequence, the Al2O3 thin film layer can be deposited by an atomic layer deposition process, the Al2O3 thin film layer can be deposited by a PECVD deposition process, the deposition thickness of the Al2O3 thin film layer is 600Å-1200Å, and the deposition thickness of the SiO2 thin film layer is 6000Å-8000Å.

[0130] Regarding step (6), an N-type metal conductive layer 17 is prepared on the second insulating layer 16, and the N-type metal conductive layer 17 is filled into the second through hole 161;

[0131] This step specifically includes:

[0132] The material of the N-type metal conductive layer 17 is deposited on the surface of the second insulating layer 16 and the second through hole 161 to form the N-type metal conductive layer 17. Figure 10 .

[0133] Optionally, the material of the N-type metal conductive layer 17 is selected from one or more of Cr, Al, Ti, and Pt. More preferably, the N-type metal conductive layer 17 comprises a Cr layer, an Al layer, a Ti layer, and a Pt layer stacked in sequence, wherein the Cr layer is deposited to a thickness of 20Å-50Å, the Al layer is deposited to a thickness of 2000Å-5000Å, the Ti layer is deposited to a thickness of 1500Å-2000Å, and the Pt layer is deposited to a thickness of 1500Å-2000Å. The deposition process of the material of the N-type metal conductive layer 17 includes, but is not limited to, electron beam evaporation.

[0134] Regarding step (7), a conductive substrate 18 is provided, a bonding layer 19 is provided on the conductive substrate 18 and / or the N-type metal conductive layer 17, and the conductive substrate 18 and the N-type metal conductive layer 17 are bonded;

[0135] This step specifically includes:

[0136] Step (701) provides a conductive substrate 18 and sets a bonding layer 19 on the conductive substrate 18, see Figure 11 ;

[0137] Optionally, the conductive substrate 18 includes but is not limited to a doped conductive silicon wafer.

[0138] Preferably, the material of the bonding layer 19 is deposited on the conductive substrate 18 to form the bonding layer 19. The bonding layer 19 is a metal bonding layer. The material of the bonding layer 19 is one or more of Ti, Sn, and Ni. The process for depositing the material of the bonding layer 19 includes but is not limited to electron beam evaporation.

[0139] Furthermore, the bonding layer 19 includes a Ti layer and a Sn layer / Ni layer with a periodic structure stacked in sequence, the deposition thickness of the Ti layer is 3000Å-4000Å, the number of periods of the Sn layer / Ni layer is 2-5, and in each period, the deposition thickness of the Sn layer is 5000Å-10000Å, and the deposition thickness of the Ni layer is 2000Å-4000Å.

[0140] Step (702) thinning the temporary substrate 10, and then providing a bonding layer 19 on the N-type metal conductive layer 17;

[0141] Preferably, the thickness of the temporary substrate 10 after thinning is 200μm-350μm. Specifically, the thinning process can be performed by grinding or other processes. By thinning the temporary substrate 10, some internal stress can be released first, avoiding stress mutation at the moment of laser peeling, and improving the peeling yield of the temporary substrate 10.

[0142] Preferably, the bonding layer 19 provided on the N-type metal conductive layer 17 and the bonding layer 19 provided on the conductive substrate 18 may have the same layer structure, so they will not be described in detail here.

[0143] Step (703) is to perform thermocompression bonding on the bonding layer 19 on the conductive substrate 18 and the bonding layer 19 on the N-type metal conductive layer 17, so that the conductive substrate 18 is bonded to the N-type metal conductive layer 17 through the bonding layer 19. Figure 12 .

[0144] It can be understood that the thermal compression bonding is a conventional bonding process in the art, and the specific process parameters such as temperature, time, pressure, etc. can be reasonably adjusted according to actual conditions.

[0145] Regarding step (8), the temporary substrate 10 is peeled off, and a patterned structure is formed on the epitaxial layer 11;

[0146] Preferably, the temporary substrate 10 is peeled off by a laser lift-off process to form a patterned structure on the N-type semiconductor layer 111. Figure 13 Specifically, an ultraviolet laser with a wavelength of 266 nm is used to irradiate the surface of the temporary substrate 10. The energy of the laser decomposes GaN at the interface between the temporary substrate 10 and the N-type semiconductor layer 111, generating metallic gallium and nitrogen, thereby decomposing and removing the temporary substrate 10.

[0147] Furthermore, the process parameters of the laser lift-off process are: laser spot radius is 12 μm-16 μm, spot moving speed is 2500 mm / s-3000 mm / s, and laser power is 80 W-100 W.

[0148] Regarding step (9), the epitaxial layer 11 is etched until the first insulating layer 13 is exposed, thereby forming an isolation trench 20;

[0149] This step specifically includes:

[0150] A photoresist is coated on the patterned surface of the N-type semiconductor layer 111. After exposure and development, the redundant portion is exposed. The exposed portion is then removed by etching until the first insulating layer 13 is exposed. The photoresist is then removed to form an isolation trench 20. Figure 14 .

[0151] Optionally, the etching process may be dry etching or wet etching. More preferably, the etching process is dry etching. Exemplary dry etching methods include ICP etching, RIE etching, and the like.

[0152] Regarding step (10), a third insulating layer 21 is prepared on the patterned structure of the epitaxial layer 11 and the isolation trench 20;

[0153] Optionally, the material of the third insulating layer 21 is deposited on the patterned structure of the N-type semiconductor layer 111 and the isolation trench 20 using an atomic layer deposition process to obtain the third insulating layer 21. Figure 15 The material of the third insulating layer 21 is preferably Al2O3, and the deposition thickness of the Al2O3 thin film layer can be reasonably adjusted according to actual conditions.

[0154] Regarding step (11), the corresponding position of the isolation groove 20 is etched until the P-type metal conductive layer 15 is exposed to form a third through hole, and a P-type pad 22 is prepared at the third through hole.

[0155] This step specifically includes:

[0156] A photoresist is coated on the surface of the third insulating layer 21. After exposure and development, the excess portion is exposed. Then, etching is performed downward from the surface of the third insulating layer 21 until the P-type metal conductive layer 15 is exposed, forming a third through hole. Finally, a P-type pad 22 layer is evaporated at the third through hole. The material layer and the photoresist on the photoresist are removed by a stripping process, leaving the P-type pad 22 layer in the third through hole to form a P-type pad 22. Figure 1 .

[0157] Optionally, the etching process includes but is not limited to wet etching, which can be specifically removed by BOE corrosion; the process of evaporating the material of the P-type pad 22 layer includes but is not limited to electron beam evaporation; the stripping process uses a stripping liquid to remove the material layer and the photoresist, and the stripping liquid can be a stripping liquid conventionally used in the field and is not specifically limited in this application.

[0158] Furthermore, the material of the P-type pad 22 layer is selected from one or more of Ti, Pt, Au, and Ni. More preferably, the P-type pad 22 layer includes a Ti layer, a Pt layer, a first Au layer, a Ni layer, and a second Au layer stacked in sequence, the deposition thickness of the Ti layer is 400Å-600Å, the deposition thickness of the Pt layer is 900Å-1100Å, the deposition thickness of the first Au layer is 4000Å-6000Å, the deposition thickness of the Ni layer is 1900Å-2100Å, and the deposition thickness of the second Au layer is 9000Å-11000Å.

[0159] The present invention will be further described below with specific embodiments:

[0160] Example 1

[0161] This embodiment provides a vertical light-emitting diode chip, including an epitaxial layer and a conductive substrate. An N-type conductive step and an isolation trench are formed on the epitaxial layer. A current spreading layer, a first insulating layer, a P-type metal reflective layer, and a P-type metal conductive layer are provided on one side of the epitaxial layer. The first insulating layer covers the current spreading layer. A first through-hole is formed on the first insulating layer. The P-type metal reflective layer is provided on the first insulating layer and contacts the current spreading layer through the first through-hole. The P-type metal conductive layer covers the P-type metal reflective layer and contacts the first insulating layer.

[0162] A second insulating layer is provided on the P-type metal conductive layer, and a second through hole is provided on the second insulating layer and penetrates the N-type conductive step. An N-type metal conductive layer is provided on the second insulating layer, and the N-type metal conductive layer contacts the epitaxial layer through the second through hole.

[0163] A third insulating layer is provided on the other side of the epitaxial layer, and the third insulating layer covers the isolation trench, a third through hole is formed at the location of the isolation trench, penetrating downward from the third insulating layer to the P-type metal conductive layer, and a P-type pad is provided at the third through hole;

[0164] The conductive substrate is bonded to the N-type metal conductive layer through a bonding layer.

[0165] Wherein, the material of the current spreading layer is indium tin oxide;

[0166] The first insulating layer includes a first insulating sublayer, a second insulating sublayer and a third insulating sublayer stacked in sequence,

[0167] The first insulating sublayer includes a first SiO2 film and a second SiO2 film that are periodically and alternately grown, with the number of periods being 7. During the formation of the first SiO2 film, the flow rate of N2O is 2600 sccm, the flow rate of SiH4 is 100 sccm, and α1 is 26; during the formation of the second SiO2 film, the flow rate of N2O is 1200 sccm, the flow rate of SiH4 is 200 sccm, and α2 is 6.

[0168] The second insulating sublayer includes a third SiO2 film and a fourth SiO2 film that are periodically and alternately grown, with the number of periods being 7. During the formation of the third SiO2 film, the flow rate of N2O is 2000 sccm, the flow rate of SiH4 is 100 sccm, and α3=20. During the formation of the fourth SiO2 film, the flow rate of N2O is 1000 sccm, the flow rate of SiH4 is 200 sccm, and α4=5.

[0169] The third insulating sublayer includes a fifth SiO2 film and a sixth SiO2 film that are periodically and alternately grown, with the number of periods being 7. During the formation of the fifth SiO2 film, the flow rate of N2O is 2000 sccm, the flow rate of SiH4 is 150 sccm, and α5 is 13.3. During the formation of the sixth SiO2 film, the flow rate of N2O is 1000 sccm, the flow rate of SiH4 is 300 sccm, and α6 is 3.3.

[0170] In each cycle, the first SiO2 film is deposited to a thickness of 100Å, the second SiO2 film is deposited to a thickness of 100Å, the third SiO2 film is deposited to a thickness of 400Å, the fourth SiO2 film is deposited to a thickness of 400Å, the fifth SiO2 film is deposited to a thickness of 200Å, and the sixth SiO2 film is deposited to a thickness of 200Å;

[0171] The P-type metal reflective layer includes an Ag layer, a Ni layer, and a Ti layer stacked in sequence, wherein the deposition thickness of the Ag layer is 1700Å, the deposition thickness of the Ni layer is 400Å, and the deposition thickness of the Ti layer is 400Å;

[0172] The P-type metal conductive layer includes a Ti layer, a Pt layer, an Au layer, and a Cr layer stacked in sequence, wherein the Ti layer has a deposition thickness of 250 Å, the Pt layer has a deposition thickness of 1700 Å, the Au layer has a deposition thickness of 6000 Å, and the Cr layer has a deposition thickness of 350 Å;

[0173] The second insulating layer includes an Al2O3 thin film layer and a SiO2 thin film layer stacked in sequence, the Al2O3 thin film layer is deposited to a thickness of 900Å, and the SiO2 thin film layer is deposited to a thickness of 7000Å;

[0174] The N-type metal conductive layer includes a Cr layer, an Al layer, a Ti layer, and a Pt layer stacked in sequence, wherein the Cr layer has a deposition thickness of 35 Å, the Al layer has a deposition thickness of 3500 Å, the Ti layer has a deposition thickness of 1800 Å, and the Pt layer has a deposition thickness of 1700 Å;

[0175] The bonding layer includes a Ti layer and a Sn layer / Ni layer with a periodic structure stacked in sequence, the Ti layer has a deposition thickness of 3500Å, the number of Sn layer / Ni layer periods is 3, and in each period, the Sn layer has a deposition thickness of 7500Å and the Ni layer has a deposition thickness of 3000Å;

[0176] The third insulating layer is an Al2O3 layer;

[0177] The P-type pad includes a Ti layer, a Pt layer, a first Au layer, a Ni layer and a second Au layer stacked in sequence, the deposition thickness of the Ti layer is 500Å, the deposition thickness of the Pt layer is 1000Å, the deposition thickness of the first Au layer is 5000Å, the deposition thickness of the Ni layer is 2000Å, and the deposition thickness of the second Au layer is 10000Å.

[0178] Accordingly, this embodiment further provides a method for preparing a vertical light-emitting diode chip, comprising the following steps:

[0179] 1. Providing a temporary sapphire substrate, sequentially preparing epitaxial layers on the temporary sapphire substrate, wherein the epitaxial layers include an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer arranged in sequence; then coating the P-type semiconductor layer with a positive photoresist, and after exposure and development, performing ICP etching on the P-type semiconductor layer until the N-type semiconductor layer is exposed, and removing the photoresist to form an N-type conductive step;

[0180] 2. Depositing indium tin oxide on the P-type semiconductor layer and the N-type conductive step by magnetron sputtering to form a layer structure, then coating the layer structure with a positive photoresist, exposing excess portions after exposure and development, then removing the exposed portions by etching with an etching solution, removing the positive photoresist, and obtaining a current spreading layer; then, depositing a first insulating layer material on the current spreading layer and on the P-type semiconductor layer and the N-type conductive step not covered by the current spreading layer, to form a layer structure, then coating the layer structure with a positive photoresist, exposing excess portions after exposure and development, removing the exposed portions by etching with BOE, forming a first through hole and exposing a portion of the current spreading layer, and removing the positive photoresist to obtain a first insulating layer;

[0181] 3. coating a photoresist on the surface of the first insulating layer and at the first through-hole, and after exposure and development, forming a patterned photoresist structure; then using the patterned photoresist structure as a mask, sequentially depositing an Ag layer, a Ni layer, and a Ti layer by an electron beam evaporation process; and finally removing the material layer and the photoresist on the photoresist by a stripping process to form a P-type metal reflective layer;

[0182] 4. coating a photoresist on the P-type metal reflective layer and on the first insulating layer not covered by the P-type metal reflective layer, exposing and developing the photoresist to form a patterned photoresist structure, then using the patterned photoresist structure as a mask to deposit a Ti layer, a Pt layer, an Au layer, and a Cr layer by electron beam evaporation, and finally removing the material layer and the photoresist on the photoresist by a stripping process to form a P-type metal conductive layer covering the P-type metal reflective layer;

[0183] 5. On the P-type metal conductive layer and on the first insulating layer not covered by the P-type metal conductive layer, first depositing an Al2O3 thin film layer by an atomic layer deposition process, and then depositing a SiO2 thin film layer by a PECVD process to form a second insulating layer structure, then coating a positive photoresist on the surface of the second insulating layer, exposing excess portions after exposure and development, and then removing the exposed portions by ICP etching until the N-type conductive step is exposed, thereby forming a second through hole;

[0184] 6. On the surface of the second insulating layer and at the second through hole, sequentially depositing a Cr layer, an Al layer, a Ti layer, and a Pt layer using an electron beam evaporation process to form an N-type metal conductive layer;

[0185] 7. Providing a doped conductive silicon wafer, thinning a temporary sapphire substrate to a thickness of 300 μm, and using an electron beam evaporation process to first evaporate a Ti layer on the doped conductive silicon wafer and the N-type metal conductive layer, and then periodically evaporate Sn layers and Ni layers to form a bonding layer, and hot-compression bonding the bonding layer on the doped conductive silicon wafer and the bonding layer on the N-type metal conductive layer;

[0186] 8. Using an ultraviolet laser lift-off process with a wavelength of 266 nm to lift off the temporary sapphire substrate, forming a patterned structure on the N-type semiconductor layer; wherein the process parameters of the laser lift-off process are: a laser spot radius of 14 μm, a spot movement speed of 2800 mm / s, and a laser power of 90 W;

[0187] 9. Coating a positive photoresist on the patterned structure surface of the N-type semiconductor layer, exposing and developing the surface to expose excess portions, and then removing the exposed portions by ICP etching until the first insulating layer is exposed, thereby forming an isolation trench;

[0188] 10. Depositing Al2O3 on the patterned structure and isolation trench of the epitaxial layer using an atomic layer deposition device to obtain a third insulating layer;

[0189] 11. Coat a positive photoresist on the surface of the third insulating layer, expose the excess part after exposure and development, and then use BOE corrosion to etch downward from the surface of the third insulating layer until the P-type metal conductive layer is exposed to form a third through hole. Finally, use an electron beam evaporation process to sequentially evaporate a Ti layer, a Pt layer, a first Au layer, a Ni layer and a second Au layer at the third through hole, and use a stripping process to remove the material layer and the photoresist on the photoresist to form a P-type pad.

[0190] Example 2

[0191] This embodiment provides a vertical light-emitting diode chip, which is basically the same as the first embodiment, except that:

[0192] The first insulating sublayer includes a first SiO2 film and a second SiO2 film that are periodically and alternately grown, with the number of periods being 5. During the formation of the first SiO2 film, the flow rate of N2O is 2400 sccm, the flow rate of SiH4 is 150 sccm, and α1 is 16; during the formation of the second SiO2 film, the flow rate of N2O is 1000 sccm, the flow rate of SiH4 is 300 sccm, and α2 is 3.3.

[0193] The second insulating sublayer includes a third SiO2 film and a fourth SiO2 film that are periodically and alternately grown, with the number of periods being 5. During the formation of the third SiO2 film, the flow rate of N2O is 1800 sccm, the flow rate of SiH4 is 150 sccm, and α3 is 12. During the formation of the fourth SiO2 film, the flow rate of N2O is 800 sccm, the flow rate of SiH4 is 300 sccm, and α4 is 2.6.

[0194] The third insulating sublayer includes a fifth SiO2 film and a sixth SiO2 film that are periodically and alternately grown, with the number of periods being 5. During the formation of the fifth SiO2 film, the flow rate of N2O is 1800 sccm, the flow rate of SiH4 is 200 sccm, and α5=9; during the formation of the sixth SiO2 film, the flow rate of N2O is 800 sccm, the flow rate of SiH4 is 350 sccm, and α6=2.3.

[0195] In each cycle, the deposition thickness of the first SiO2 film is 200Å, the deposition thickness of the second SiO2 film is 200Å, the deposition thickness of the third SiO2 film is 600Å, the deposition thickness of the fourth SiO2 film is 600Å, the deposition thickness of the fifth SiO2 film is 300Å, and the deposition thickness of the sixth SiO2 film is 300Å.

[0196] Example 3

[0197] This embodiment provides a vertical light-emitting diode chip, which is basically the same as the first embodiment, except that:

[0198] The first insulating sublayer includes a first SiO2 film and a second SiO2 film that are periodically and alternately grown, with the number of periods being 6. During the formation of the first SiO2 film, the flow rate of N2O is 2500 sccm, the flow rate of SiH4 is 125 sccm, and α1 is 20. During the formation of the second SiO2 film, the flow rate of N2O is 1100 sccm, the flow rate of SiH4 is 250 sccm, and α2 is 4.4.

[0199] The second insulating sublayer includes a third SiO2 film and a fourth SiO2 film that are periodically and alternately grown, with the number of periods being 6. During the formation of the third SiO2 film, the flow rate of N2O is 1900 sccm, the flow rate of SiH4 is 125 sccm, and α3 is 15.2. During the formation of the fourth SiO2 film, the flow rate of N2O is 900 sccm, the flow rate of SiH4 is 250 sccm, and α4 is 3.6.

[0200] The third insulating sublayer includes a fifth SiO2 film and a sixth SiO2 film that are periodically and alternately grown, with the number of periods being 6. During the formation of the fifth SiO2 film, the flow rate of N2O is 1900 sccm, the flow rate of SiH4 is 175 sccm, and α5 is 10.9. During the formation of the sixth SiO2 film, the flow rate of N2O is 900 sccm, the flow rate of SiH4 is 325 sccm, and α6 is 2.8.

[0201] In each cycle, the deposition thickness of the first SiO2 film is 150Å, the deposition thickness of the second SiO2 film is 150Å, the deposition thickness of the third SiO2 film is 500Å, the deposition thickness of the fourth SiO2 film is 500Å, the deposition thickness of the fifth SiO2 film is 250Å, and the deposition thickness of the sixth SiO2 film is 250Å.

[0202] Comparative Example 1

[0203] This comparative example provides a vertical light-emitting diode chip, which is basically the same as Example 1, except that:

[0204] The first insulating layer is a single-layer SiO2 thin film layer with a thickness of 12000Å. During the formation of the SiO2 thin film layer, the flow rate of N2O is 1800sccm and the flow rate of SiH4 is 155sccm.

[0205] Performance Testing

[0206] The stress of the structure obtained after step (8) of the embodiment and the comparative example and the peeling yield of the temporary substrate were tested. The test results are shown in Table 1 below.

[0207] Table 1 Performance test results of examples and comparative examples

[0208]

[0209] From the above results, it can be seen that one side of the epitaxial layer described in the present application is provided with a current spreading layer, a first insulating layer, a P-type metal reflective layer and a P-type metal conductive layer, the first insulating layer covers the current spreading layer, a first through hole is formed on the first insulating layer, the P-type metal reflective layer is arranged on the first insulating layer, and contacts the current spreading layer through the first through hole, the P-type metal conductive layer covers the P-type metal reflective layer, and the first insulating layer is limited to include a first insulating sublayer, a second insulating sublayer and a third insulating sublayer stacked in sequence, which can greatly reduce the stress of the first insulating layer, thereby greatly reducing the abnormality of the epitaxial layer falling off after the substrate is peeled off.

[0210] The above disclosure is only a preferred embodiment of the present invention and certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A vertical light-emitting diode chip, characterized in that: including an epitaxial layer and a conductive substrate; An N-type conductive step and an isolation trench are formed on the epitaxial layer; a current spreading layer, a first insulating layer, a P-type metal reflective layer, and a P-type metal conductive layer are provided on one side of the epitaxial layer; the first insulating layer covers the current spreading layer; a first through-hole is formed on the first insulating layer; the P-type metal reflective layer is provided on the first insulating layer and contacts the current spreading layer through the first through-hole; the P-type metal conductive layer covers the P-type metal reflective layer and contacts the first insulating layer; A second insulating layer is provided on the P-type metal conductive layer, and a second through hole is provided on the second insulating layer and penetrates the N-type conductive step. An N-type metal conductive layer is provided on the second insulating layer, and the N-type metal conductive layer contacts the epitaxial layer through the second through hole. A third insulating layer is provided on the other side of the epitaxial layer, and the third insulating layer covers the isolation trench. A third through hole is formed at the location of the isolation trench, penetrating from the third insulating layer to the P-type metal conductive layer, and a P-type pad is provided at the third through hole. The conductive substrate is bonded to the N-type metal conductive layer through a bonding layer; Among them, the first insulating layer includes a first insulating sublayer, a second insulating sublayer and a third insulating sublayer stacked in sequence; the first insulating sublayer, the second insulating sublayer and the third insulating sublayer are all SiO2 films formed by the reaction of N2O and SiH4 gases.

2. The vertical light emitting diode chip according to claim 1, wherein: The first insulating sublayer includes a first SiO2 film and a second SiO2 film that are grown alternately periodically, with the number of periods being 5-7; The second insulating sublayer includes a third SiO2 film and a fourth SiO2 film that are grown alternately in a periodic manner, with the number of periods being 5-7; The third insulating sublayer includes a fifth SiO2 film and a sixth SiO2 film that are grown alternately in a periodic manner, with the number of periods being 5-7.

3. The vertical light emitting diode chip according to claim 2, wherein: During the formation of the first SiO2 film, the third SiO2 film and the fifth SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is controlled within the range of (9-26):1; During the formation of the second SiO2 film, the fourth SiO2 film and the sixth SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is controlled within the range of (2.2-6):

1.

4. The vertical light emitting diode chip according to claim 3, wherein: During the formation of the first SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α1, during the formation of the second SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α2, during the formation of the third SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α3, during the formation of the fourth SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α4, during the formation of the fifth SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α5, and during the formation of the sixth SiO2 film, the ratio of the N2O flow rate to the SiH4 flow rate is α6, satisfying: α1=（16-26）：1，α2=（3.3-6）：1； α3=（12-20）：1，α4=（2.6-5）：1； α5=（9-13.3）：1，α6=（2.2-3.4）：1。 5. The vertical light emitting diode chip according to claim 3 or 4, characterized in that: During the formation of the first SiO2 film, the flow rate of N2O is 2400 sccm-2600 sccm, and the flow rate of SiH4 is 100 sccm-150 sccm; During the formation of the second SiO2 film, the flow rate of N2O is 1000sccm-1200sccm, and the flow rate of SiH4 is 200sccm-300sccm; During the formation of the third SiO2 film, the flow rate of N2O is 1800 sccm-2000 sccm, and the flow rate of SiH4 is 100 sccm-150 sccm; During the formation of the fourth SiO2 film, the flow rate of N2O is 800sccm-1000sccm, and the flow rate of SiH4 is 200sccm-300sccm; During the formation of the fifth SiO2 film, the flow rate of N2O is 1800 sccm-2000 sccm, and the flow rate of SiH4 is 150 sccm-200 sccm; During the formation of the sixth SiO2 film, the flow rate of N2O is 800sccm-1000sccm, and the flow rate of SiH4 is 300sccm-350sccm.

6. The vertical light emitting diode chip according to claim 2, wherein: In each cycle, the deposition thickness of the first SiO2 film is 100Å-200Å, and the deposition thickness of the second SiO2 film is 100Å-200Å; The deposition thickness of the third SiO2 film is 400Å-600Å, and the deposition thickness of the fourth SiO2 film is 400Å-600Å; The deposition thickness of the fifth SiO2 film is 200Å-300Å, and the deposition thickness of the sixth SiO2 film is 200Å-300Å.

7. The vertical light emitting diode chip according to claim 2 or 6, characterized in that: The deposition thickness of the first SiO2 film and the second SiO2 film are equal; The deposition thickness of the third SiO2 film and the fourth SiO2 film are equal; The deposition thicknesses of the fifth SiO 2 film and the sixth SiO 2 film are equal.

8. The vertical light emitting diode chip according to claim 1, wherein: The second insulating layer includes an Al2O3 thin film layer and a SiO2 thin film layer stacked in sequence, wherein the deposition thickness of the Al2O3 thin film layer is 600Å-1200Å, and the deposition thickness of the SiO2 thin film layer is 6000Å-8000Å; The third insulating layer is an Al2O3 layer.

9. A method for preparing a vertical light-emitting diode chip according to any one of claims 1 to 8, characterized in that: include: Providing a temporary substrate, preparing an epitaxial layer on the temporary substrate, and forming an N-type conductive step on the epitaxial layer; Preparing a current spreading layer and a first insulating layer on the epitaxial layer, and etching the first insulating layer to form a first through hole to expose a portion of the current spreading layer; preparing a P-type metal reflective layer on the first insulating layer and the first through hole; forming a P-type metal conductive layer on the first insulating layer, so that the P-type metal conductive layer covers the P-type metal reflective layer; forming a second insulating layer on the first insulating layer so that the second insulating layer covers the P-type metal conductive layer, and etching the second insulating layer until the N-type conductive step is exposed to form a second through hole; preparing an N-type metal conductive layer on the second insulating layer, and filling the second through hole with the N-type metal conductive layer; Providing a conductive substrate, arranging a bonding layer on the conductive substrate and / or the N-type metal conductive layer, and performing a bonding process on the conductive substrate and the N-type metal conductive layer; peeling off the temporary substrate to form a patterned structure on the epitaxial layer; Etching the epitaxial layer until the first insulating layer is exposed to form an isolation trench; forming a third insulating layer on the patterned structure and the isolation trench of the epitaxial layer; The corresponding position of the isolation groove is etched until the P-type metal conductive layer is exposed to form a third through hole, and a P-type pad is prepared at the third through hole.

10. The method for preparing a vertical light emitting diode chip according to claim 9, wherein: Providing a bonding layer on the conductive substrate and / or the N-type metal conductive layer, comprising: performing a thinning process on the temporary substrate, and then providing a bonding layer on the N-type metal conductive layer; The thickness of the temporary substrate after thinning is 200 μm-350 μm; The temporary substrate is peeled off by a laser peeling process, wherein the process parameters of the laser peeling process are: a laser spot radius of 12 μm-16 μm, a spot moving speed of 2500 mm / s-3000 mm / s, and a laser power of 80 W-100 W.

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