Interrupt management on single wire bidirectional bus

Abstract

A data communication device includes: a line driver configured to couple the data communication device to a single wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses on the single wire serial bus after a sequence start condition (SSC) has been transmitted on the single wire serial bus, the plurality of synchronization pulses configured to synchronize one or more receiving devices coupled to the single wire serial bus to an untransmitted transmit clock signal; initiating an interrupt handling procedure when the plurality of synchronization pulses are encoded with a first value; and initiating a read or write transaction with at least one of the one or more receiving devices coupled to the single wire serial bus when the plurality of synchronization pulses are encoded with a second value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 18 / 155,499, filed on January 17, 2023, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to serial communications, and more particularly, to in-band interrupts and interrupt handling for devices configured for single-wire communications over a radio frequency front-end interface. Background Art

[0004] A mobile communication device may include various components, including circuit boards, integrated circuit (IC) devices, and / or system-on-chip (SoC) devices. These components may include processing circuitry, user interface components, storage devices, and other peripheral components that communicate via a serial bus. The serial bus may operate according to a standardized protocol or a proprietary protocol. In one example, the serial bus operates according to an inter-integrated circuit (I2C bus or I 2 The I2C bus operates with the I2C protocol. The I2C bus was developed to connect low-speed peripheral devices to processors, where the I2C bus is configured as a multi-drop bus. The two-wire I2C bus includes a serial data line (SDA) that carries the data signal and a serial clock line (SCL) that carries the clock signal. In another example, the Improved Inter-Integrated Circuit (I3C) protocol defined by the Mobile Industry Processor Interface (MIPI) Alliance derives certain implementation aspects from the I2C protocol, which includes separate clock and data lines.

[0005] In another example, the radio frequency front-end (RFFE) interface defined by the MIPI Alliance provides a communication interface for controlling various radio frequency (RF) front-end devices, including power amplifiers (PAs), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, etc. These devices can be co-located in a single IC device or provided in multiple IC devices. In mobile communication devices, multiple antennas and radio transceivers can support multiple concurrent RF links.

[0006] In another example, the System Power Management Interface (SPMI) defined by the MIPI Alliance provides a hardware interface that can be implemented between a baseband or application processor and peripheral components. In some implementations, SPMI is deployed to support power management operations within a device.

[0007] Using a MIPI-defined serial bus instead of a parallel bus reduces the number of physical general-purpose input / output (GPIO) pins required to support communication between multiple devices. As device complexity increases, the demand for GPIO pins also increases, and there is a continuous demand for simplified bus architectures. Summary of the Invention

[0008] Certain aspects of the present disclosure relate to systems, apparatuses, methods, and techniques that can support communication with devices that interface using a single-wire link. In some implementations, a combination of control signaling and Manchester encoding can be used to maintain synchronization between clock signals in the transmitting and receiving devices. The single-wire link can format datagrams according to a protocol defined by RFFE, SPMI, or another standard.

[0009] In various aspects of the present disclosure, a method of data communication performed at a host device includes: sending a plurality of synchronization pulses on a single-wire serial bus after a sequence start condition (SSC) has been sent on the single-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the single-wire serial bus to an untransmitted transmit clock signal; initiating an interrupt handling process when the plurality of synchronization pulses are encoded with a first value; and initiating a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the single-wire serial bus when the plurality of synchronization pulses are encoded with a second value.

[0010] In various aspects of the present disclosure, a data communication apparatus includes: a line driver configured to couple the data communication apparatus to a single-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses on the single-wire serial bus after an SSC has been transmitted on the single-wire serial bus, the plurality of synchronization pulses configured to synchronize one or more receiving devices coupled to the single-wire serial bus to an untransmitted transmit clock signal; initiate an interrupt handling process when the plurality of synchronization pulses are encoded with a first value; and initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the single-wire serial bus when the plurality of synchronization pulses are encoded with a second value.

[0011] In various aspects of the present disclosure, a method of data communication performed at a slave device includes: receiving a plurality of synchronization pulses from a single-wire serial bus after an SSC has been received from the single-wire serial bus; synchronizing an internal clock signal using the plurality of synchronization pulses; participating in an interrupt handling process when the plurality of synchronization pulses are encoded with a first value; and responding to a read command or a write command when the plurality of synchronization pulses are encoded with a second value and are followed by an address corresponding to a device address associated with the slave device.

[0012] In various aspects of the present disclosure, a data communication device includes: a line driver configured to couple the data communication device to a single-wire serial bus; and a controller configured to: receive a plurality of synchronization pulses from the single-wire serial bus after an SSC has been received from the single-wire serial bus; synchronize an internal clock signal using the plurality of synchronization pulses; participate in an interrupt handling process when the plurality of synchronization pulses are encoded with a first value; and respond to a read command or a write command when the plurality of synchronization pulses are encoded with a second value and are followed by an address corresponding to a device address associated with the data communication device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An apparatus is illustrated that employs a data link between IC devices that selectively operates according to one of a plurality of available standards.

[0014] Figure 2 A first example of an apparatus employing a data link that can be used to communicatively couple two or more devices is illustrated.

[0015] Figure 3 A second example of an apparatus employing a data link that can be used to communicatively couple two or more devices including various radio frequency front-end devices is illustrated.

[0016] Figure 4 Included is a timing diagram illustrating the signaling sent to delineate the boundaries of RFFE and SPMI datagrams.

[0017] Figure 5 Illustrated is a system in which a host device communicates with one or more single-wire slave devices according to certain aspects disclosed herein.

[0018] Figure 6 An example of a single-wire serial interface that may be configured according to certain aspects of the present disclosure is illustrated.

[0019] Figure 7 Certain aspects of Manchester encoding and control signaling that may be used to exchange data between a master device and a single-wire slave device according to certain aspects of the present disclosure are illustrated.

[0020] Figure 8 An example of transaction initiation for a single-wire serial bus according to certain aspects of the present disclosure is illustrated.

[0021] Figure 9 A first example of a break identification transaction conducted on a single-wire serial bus configured or adapted according to certain aspects of the present disclosure is illustrated.

[0022] Figure 10A second example of a break identification transaction conducted on a single-wire serial bus configured or adapted according to certain aspects of the present disclosure is illustrated.

[0023] Figure 11 A read transaction performed on a single-wire serial bus configured according to certain aspects disclosed herein is illustrated.

[0024] Figure 12 One example of an apparatus employing processing circuitry that may be adapted according to certain aspects disclosed herein is illustrated.

[0025] Figure 13 is a first flow chart illustrating a method for communicating data at a host device in accordance with certain aspects disclosed herein.

[0026] Figure 14 is a second flow chart illustrating a method for communicating data at a bus slave device according to certain aspects disclosed herein.

[0027] Figure 15

[0066] Illustrated are examples of hardware implementations for apparatus adapted according to certain aspects disclosed herein. DETAILED DESCRIPTION

[0028] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations with which the concepts described herein may be practiced. In order to provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0029] Several aspects of the present invention will now be described with reference to various devices and methods. These devices and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0030] Certain aspects of the present disclosure relate to serial bus configurations in which multiple devices can communicate at various times. The described serial buses typically operate in a hierarchical manner, with one device controlling communications during a transaction. The controlling device may be referred to as a host device, bus master, management device, or another terminology supported by the standard defining the protocol implemented by the controlling device. In some serial bus configurations, a single controlling device manages or controls communications during all transactions conducted over the serial bus. In other serial bus configurations, multiple devices may operate as controlling devices, with one device acting as the controlling device for each transaction conducted over the serial bus. The controlling device may provide a common clock signal transmitted over a conventional two-wire serial bus. The controlling device may provide control signaling that identifies the type of transaction to be conducted over the conventional two-wire serial bus. During certain transactions, the controlling device may send commands directed to one or more receiving devices using address information provided in or with the command. Receiving devices may be referred to as slave devices, client devices, slave devices, peripheral devices, or another terminology supported by the standard defining the protocol implemented by the controlling device. For the purposes of this disclosure, the controlling device will be referred to as the host device, and the associated receiving devices will be referred to as slave devices.

[0031] Overview

[0032] Devices that include multiple SoCs and other IC devices often employ a shared communication interface that may include a serial bus or other data communication link to connect the processor to a modem and other peripheral devices. The serial bus or other data communication link may operate according to a variety of standards or protocols. For example, the serial bus may operate according to I2C, I3C, SPMI, and / or RFFE protocols, or another protocol that may be configured for half-duplex operation. The increased functionality and complexity of the operations involving devices coupled to the serial bus, as well as the tighter timing constraints imposed to support applications, peripherals, and sensors, may result in greater demands on GPIO pins and communication link throughput.

[0033] Certain aspects of the present disclosure relate to techniques for communicating over a single-wire serial bus using Manchester encoding and synchronization signaling that can be distinguished by devices coupled to the single-wire serial bus. The synchronization signaling can be configured to enable a receiving device to synchronize a clock signal generated in a device currently transmitting over the single-wire serial bus. In one aspect, a host device can be adapted to format datagrams according to an RFFE or SPMI protocol. In another aspect, a slave device can assert an interrupt by initiating a sequence start condition (SSC) when the single-wire serial bus is idle. In another aspect, a host device can use an encoded synchronization pattern to signal the type of transaction to be performed. One or more types of transactions can be configured to enable a host device to identify a slave device requesting or requiring interrupt service.

[0034] In one example, a host device configured according to certain aspects of the present disclosure may transmit synchronization pulses on a single-wire serial bus after transmitting an SSC on the single-wire serial bus. These synchronization pulses are configured to synchronize one or more slave devices coupled to the single-wire serial bus to an untransmitted transmit clock signal. The host device may initiate an interrupt handling process when the synchronization pulses are encoded with a first value, and may initiate a read transaction or a write transaction with the one or more slave devices when the plurality of synchronization pulses are encoded with a second value. The synchronization pulses may be encoded using Manchester encoding.

[0035] Certain aspects disclosed herein provide protocols that replace or supplement serial bus protocols, such as I2C, I3C, SPMI and / or RFFE protocols. Certain aspects are applicable to serial buses operating in half-duplex mode or full-duplex mode. Certain aspects are applicable to point-to-point universal asynchronous receiver / transmitter (UART) interfaces, line multiplexed UART (LM-UART) interfaces, or another type of point-to-point interface. In some specific implementations, certain aspects disclosed herein may be deployed to support the exchange of virtual GPIO (VGI) messages, which can be used to convey the state or state changes of physical GPIO pins without the need for a physical connection between devices. Certain aspects are applicable to multi-point interfaces, point-to-point interfaces, or interfaces that can switch between point-to-point mode and multi-point mode.

[0036] Example of a device using a serial data link

[0037] According to certain aspects of the present disclosure, serial data links may be used to interconnect electronic devices that are subcomponents of devices such as: cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similarly functional devices.

[0038] Figure 1 An example of an apparatus 100 that may employ a data communication bus is illustrated. Apparatus 100 may include processing circuitry 102 having a plurality of circuits or devices 104, 106, and / or 108, which may be implemented in a SoC or one or more ASICs. In one example, apparatus 100 may be a communications device, and processing circuitry 102 may include a processing device provided in ASIC 104, one or more peripheral devices 106, and a transceiver 108 that enables the apparatus to communicate with a radio access network, a core access network, the Internet, and / or another network via an antenna 124.

[0039] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuitry 116, and / or other logic circuitry or functionality. Processing circuit 102 may be controlled by an operating system, which may provide an application programming interface (API) layer that enables one or more processors 112 to execute software modules residing in onboard memory 114 or other processor-readable storage devices 122 provided on processing circuit 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable storage devices 122. ASIC 104 may access its onboard memory 114, processor-readable storage devices 122, and / or storage devices external to processing circuit 102. Onboard memory 114 and processor-readable storage devices 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash memory cards, or any other memory device useful in processing systems and computing platforms. The processing circuit 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information used to configure and operate the device 100 and / or the processing circuit 102. The local database can be implemented using registers, database modules, flash memory, magnetic media, EEPROM, floppy disks, or hard disks, etc. The processing circuit 102 can also be operatively coupled to external devices such as an antenna 124, a display 126, operator controls (such as switches or buttons 128, 130 and / or an integrated or external keyboard 132), and other components. The user interface module can be configured to operate with the display 126, external keyboard 132, etc. via a dedicated communication link or via one or more serial data interconnects.

[0040] Processing circuitry 102 may provide one or more buses 118a, 118b, 120 that enable certain devices 104, 106, and / or 108 to communicate. In one example, ASIC 104 may include bus interface circuitry 116 that includes a combination of circuits, counters, timers, control logic, and other configurable circuits or modules. In one example, bus interface circuitry 116 may be configured to operate according to a communication specification or protocol. Processing circuitry 102 may include or control power management functionality that configures and manages the operation of apparatus 100.

[0041] Figure 2 A first example of an apparatus 200 employing a data link that can be used to communicatively couple two or more devices is illustrated. Here, the apparatus 200 includes a plurality of devices 202 and 2220-222 coupled to a two-wire serial bus 220. N Devices 202 and 2220-222 NThe devices 202 and 2220-222 may be implemented in one or more semiconductor IC devices such as application processors, SoCs, or ASICs. N Some of the devices in the example may include, support, or operate as modems, signal processing devices, display drivers, cameras, user interfaces, sensors, sensor controllers, media players, transceivers, and / or other such components or devices. In some examples, one or more devices 2220-222 may be used. N To control, manage or monitor sensor devices. Devices 202 and 2220-222 N Communications between the devices over serial bus 220 are controlled by host device 202. Some types of buses can support multiple host devices 202.

[0042] In one example, host device 202 may include an interface controller 204 that manages access to the serial bus, configures dynamic addresses for slave devices, and / or generates a clock signal 228 to be sent on a clock line 218 of serial bus 220. Host device 202 may include configuration registers 206 or other storage 224 and other control logic 212 configured to handle protocols and / or higher-level functions. Control logic 212 may include processing circuitry such as a state machine, sequencer, signal processor, or general-purpose processor. Host device 202 includes a transceiver 210 and line drivers / receivers 214a and 214b. Transceiver 210 may include a receiver, a transmitter, and common circuitry, which may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on the timing in clock signal 228 provided by clock generation circuit 208. Other timing clocks 226 may be used by control logic 212 and other functions, circuits, or modules.

[0043] One or more devices 2220-222 NCan be configured to operate as a slave device. In some examples, the slave device may include circuits and modules that support a display, an image sensor, and / or circuits and modules that control and communicate with one or more sensors that measure environmental conditions. In one example, a device 2220 configured to operate as a slave device may provide control functionality, modules, or circuits 232, including circuits and modules for supporting a display, an image sensor, and / or circuits and modules that control and communicate with one or more sensors that measure environmental conditions. In this example, the device 2220 may include configuration registers 234 or other storage 236, control logic 242, a transceiver 240, and line drivers / receivers 244a and 244b. The control logic 242 may include processing circuitry such as a state machine, a sequencer, a signal processor, or a general-purpose processor. The transceiver 240 may include a receiver, a transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on the timing in a clock signal 248 provided by a clock generation and / or recovery circuit 246. In some examples, clock signal 248 can be derived from a signal received from clock line 218. Other timing clocks 238 can be used by control logic 242 and other functions, circuits, or modules.

[0044] The serial bus 220 may operate according to RFFE, I2C, I3C, SPMI, or other protocols. Devices 202 and 2220-222 N At least one of the devices 202 and 2220-222 may be configured to operate as a master device and a slave device on the serial bus 220. N Two or more of the two-wire serial bus 220 may be configured to operate as a host device on the serial bus 220. The protocol selected for controlling the operation of the serial bus 220 may define direct current (DC) characteristics that affect certain signal levels associated with the serial bus 220, and / or alternating current (AC) characteristics that affect certain timing aspects of signals sent on the serial bus 220. In various examples, the two-wire serial bus 220 transmits data on the data line 216 and transmits a clock signal on the clock line 218. In some instances, the data may be encoded in the signaling states, or transitions between the signaling states of the data line 216 and the clock line 218.

[0045] Figure 3A second example of an apparatus 300 employing a data link that can be used to communicatively couple two or more devices is illustrated. In this example, a chipset or device 302 employs multiple RFFE buses 330, 332, 334 to couple various RF front-end devices 318, 320, 322, 324, 326, 328. A modem 304 includes an RFFE interface 308 that couples the modem 304 to a first RFFE bus 330. The modem 304 can communicate with a baseband processor 306 and a radio frequency integrated circuit (RFIC 312) via one or more communication links 310, 336. The illustrated device 302 may be embodied in one or more of a mobile communication device, a mobile phone, a mobile computing system, a laptop computer, a tablet computing device, a media player, a gaming device, a wearable computing device, and / or a communication device, an appliance, and the like.

[0046] In various examples, the device 302 may be implemented with one or more baseband processors 306, a modem 304, an RFIC 312, multiple communication links 310, 336, multiple RFFE buses 330, 332, 334, and / or other types of buses. The device 302 may include other processors, circuits, modules, and may be configured for various operations and / or different functions. Figure 3 In the illustrated example, the modem is coupled to an RF tuner 318 via its RFFE interface 308 and a first RFFE bus 330. The RFIC 312 may include one or more RFFE interfaces 314, 316, a controller, a state machine, and / or a processor that configures and controls certain aspects of the RF front end. The RFIC 312 may communicate with the PA 320 and the power tracking module 322 via a first RFFE interface and a second RFFE bus 332 in its RFFE interface 314. The RFIC 312 may communicate with the switch 324 and one or more LNAs 326, 328 via a second RFFE interface and a third RFFE bus 334 in its RFFE interface 316.

[0047] Bus latency can affect the ability of a serial bus to handle high-priority, real-time, and / or other time-constrained messages. Low-latency messages, or messages requiring low bus latency, may involve sensor states, real-time events generated by devices, and virtualized GPIO states. In one example, bus latency can be measured as the time elapsed between the time a message becomes available for transmission and the delivery of the message, or in some instances, the start of transmission of the message. Other measures of bus latency can be used. Bus latency typically includes delays incurred when sending higher-priority messages, interrupt processing, the time required to terminate a datagram in progress on the serial bus, the time to send commands to cycle the bus between transmit and receive modes, bus arbitration, and / or the sending of commands specified by the protocol.

[0048] In some examples, latency-sensitive messages may include coexistence messages. Coexistence messages are sent in a multi-system platform to prevent or reduce conflicts between certain device types, including, for example, switches 324, LNAs 326, 328, PAs 320, and other types of devices operating concurrently in a manner that could generate inter-device interference or potentially cause damage to one or more devices. Devices that may interfere with each other may exchange coexistence management (CxM) messages to allow each device to signal impending actions that may cause interference or conflicts. CxM messages may be used to manage the operation of shared components, including switches 324, LNAs 326, 328, PAs 320, and / or antennas.

[0049] Multi-point interfaces (such as RFFE, SPMI, I3C, etc.) can reduce the number of physical input / output (I / O) pins used to communicate between multiple devices. The protocols that support communication over a multi-point serial bus define a datagram structure for sending command, control, and data payloads. The datagram structure for different protocols defines certain common features, including addressing for selecting a device to receive or send data, clock generation and management, interrupt handling, and device priority. In this disclosure, the example of the RFFE protocol may be used to illustrate certain aspects disclosed herein. However, the concepts disclosed herein are applicable to other serial bus protocols and standards.

[0050] Figure 4 The RFFE protocol includes timing diagrams 400 and 420 illustrating signaling sent to delineate the boundaries of a datagram sent in accordance with the RFFE protocol. The timing diagrams 400 and 420 show the relative timing of signals sent on a two-wire serial bus that provides a clock signal on SCLK 402 and data exchange via SDATA 404. The first timing diagram 400 illustrates the timing of a sequence start condition (SSC 408), which is sent to signal the start of a transaction, such as the transmission of a datagram 410. The SSC 408 is sent when the serial bus is in an idle state 406. In the idle state 406, SCLK 402 is driven at full strength by the master, while slave devices coupled to the serial bus present a high impedance to SCLK 402. SCLK 402 is held in a low signaling state (here, zero volts) by the master. In the idle state 406, SDATA 404 is driven weakly by the host or maintained in a weakly driven low signaling state 412 using a keeper circuit or a weak pull-down circuit. For example, when the host has put its line driver into a high impedance state and when no other device is driving SDATA 404, the keeper circuit or weak pull-down circuit can maintain the signaling state of SDATA 404. The weakly driven low signaling state 412 can be easily overcome by another line driver capable of driving SDATA 404 at full strength.

[0051] In the master-driven SSC 408, the host begins transmission on the SSC 408 at a first point in time 414, when the host begins driving the SDATA 404, which is initially in a low signaling state, at full strength. The host then provides a pulse 416 on the SDATA 404 while continuing to drive the SCLK 402 to a low signaling state. The pulse 416 has a duration of at least one cycle of the clock signal provided on the SCLK 402 during the transmission of the datagram 410. At a second point in time 418, the host begins sending clock pulses on the SCLK 402, thereby providing a clock signal for controlling or indicating the timing of the datagram 410 sent on the SDATA 404.

[0052] For example, the second timing diagram 420 illustrates the timing of a bus park cycle (BPC 424) that can be sent to signal the termination of a datagram 422. The BPC 424 is sent by providing a falling edge 428 on SDATA 404 while SCLK 402 is in a high signaling state 430. By protocol, transitions on SDATA 404 during the transmission of a datagram 422 are permitted only when the clock signal is in a low signaling state, and the falling edge 428 that occurs while SCLK 402 is in a high signaling state 430 is interpreted as control signaling (i.e., BPC 424). The falling edge 428 is provided by the host driving SDATA 404 low at full strength. The host then drives SCLK 402 low and continues to drive SCLK 402 at full strength through subsequent bus idle intervals 426, 436. After driving SCLK 402 low, the host initiates a bus idle interval 436 at time 432 when it places its line drivers into a high impedance state. When no other device is driving SDATA 404, SDATA 404 remains in a weakly driven low signaling state 434. BPC 424 is terminated, and the serial bus enters a bus idle interval 426 until the next datagram is ready to be sent.

[0053] Figure 5 1-504 according to certain aspects disclosed herein wherein a host device 502 and one or more single-wire slave devices 5041-504 N A system 500 for communication. A host device 502 may be provided in an RFIC, a modem, an application processor, or another type of device. The host device 502 may be adapted to communicate with single-wire slave devices 5041-504 via a single wire. N To exchange data, this single line is referred to as the SDATA line 506 in the illustrated system 500. The data is encoded in a signal sent over the SDATA line 506, where the signal includes embedded clock information that can be used by a receiving device to decode the data from the signal.

[0054] Master device 502 and single-wire slave devices 5041-504 N Typically includes corresponding protocol controllers 508, 5101-510 N Protocol controllers 508, 5101-510 N The host device 502 may have a processor, controller, state machine, or other logic circuit configured to support one or more protocols. The protocol controller 508 in the host device 502 may be further configured to manage communications over the SDATA line 506. In some examples, the protocol controller 508 performs some of the functions of the host. In some implementations, the protocol controller 508 in the host device 502 may be used to configure the single-wire slave devices 5041-504 N The host device 502 may determine the single-wire slave devices 5041-504 as the designated recipients of the data to be sent via the SDATA line 506. N The configuration can enable the protocol controller 508 to send and address to the single-wire slave devices 5041-504 via the SDATA line 506. N The signal pair is intended for the receiving single-wire slave device 5041-504 N Encode the data.

[0055] The host device 502 may include a transmit clock generator 512 that may be used to define the timing of transmissions over the SDATA line 506. N Each of the 1-514 circuits includes a local clock generation circuit 5141-514 N , which provides corresponding protocol controllers 5101-510 N Timing of local clock generation circuit 5141-514 N A synchronization pulse may be used which is sent by the master device 502 after the SSC, or by the master device 502 or by the single-wire slave devices 5041-504 after a line turnaround. N According to certain aspects of the present disclosure, the local clock generation circuits 5141-514 N Transitions in the Manchester-encoded command and data payload sent over the SDATA line 506 may be used for synchronization. Local clock generation circuits 5141-514 N A ring oscillator or a delay locked loop may be included. In some implementations, the local clock generation circuits 5141-514 N An injection locked oscillator may be included that responds to synchronization pulses and / or transitions in Manchester encoded command and data payload transmissions.

[0056] The keeper circuit 516 can be coupled to the SDATA line 506 to facilitate line turnaround, in-band interrupt requests, or arbitration processes according to certain aspects disclosed herein. In one example, the keeper circuit 516 can be configured as a positive feedback circuit that drives the SDATA line 506 through a high impedance output and receives feedback from the SDATA line 506 through a low impedance input. The keeper circuit 516 can be configured to maintain the last asserted voltage on the SDATA line 506. The keeper circuit 516 can be configured by the host device 502 or the single-line slave devices 5041-504 N The active line driver in one of them is easily overcome.

[0057] Conventional implementations of single-wire, bidirectional communication buses are hampered by restrictively slow data rates. Many conventional single-wire, bidirectional communication buses are limited to signaling rates below megahertz (MHz) and are unsuitable for high-speed RF front-end control applications that may require clock rates as high as 52 MHz. Some conventional single-wire, bidirectional communication buses attempt to increase data rates by using pulse width modulation and other data encoding schemes. However, due to various limitations of PWM signaling, for example, these latter communication buses are generally unable to achieve signaling rates greater than 4 MHz.

[0058] A single-wire bidirectional communication bus implemented according to certain aspects disclosed herein can achieve data rates up to and exceeding 52 MHz. In certain examples, the signaling scheme provided for communication over the single-wire communication bus uses a combination of the RFFE protocol, Manchester encoding, and modified control signaling that can indicate and distinguish between various types of transactions.

[0059] Figure 6 An example of a single-wire serial interface 600 that can be configured according to certain aspects of the present disclosure is illustrated. In this example, a host device 502 and a single-wire slave device 504 are illustrated. N (See Figure 5 ). The host device 502 includes a protocol controller 614. The protocol controller 614 may be implemented using a processor, a microcontroller, or a finite state machine and may be used to control the transmit and receive functions of the host device 502. The protocol controller 614 may include or be coupled to a signal generating circuit 604 that generates signals when coupling the host device 502 to one or more slave devices 504. N The signal generation circuit 604 can be configured to generate different types of SSC to initiate arbitration, initiate data transmission, or abandon arbitration. The signal generation circuit 604 can be configured to generate a synchronization pulse that is used to enable the slave device 504 to N The clock signal generated at is synchronized with the transmit clock signal generated in the host device 502.

[0060] The protocol controller 614 can be configured to selectively activate the Manchester encoder 606 and the Manchester decoder 608 based on the operating mode of the single-wire serial interface 600. The Manchester decoder 608 can extract data and clock information from the signal received from the SDATA line 620. The protocol controller 614 can be further configured to format datagrams for transmission over the SDATA line 620. The protocol controller 614 can be further configured to generate commands to be transmitted over the SDATA line 620.

[0061] In the illustrated example, the single-wire slave device 504 N A protocol controller 622 is included. The protocol controller 622 may be implemented using a processor, a microcontroller, or a finite state machine and may be used to control the single-wire slave device 504. N The protocol controller 622 may include or be coupled to a signal generating circuit 624 that generates signals when the single-wire slave device 504 N The protocol controller 622 may further be configured to cause the signal generation circuit 624 to drive the SDATA line 620 to initiate an SSC during an in-band interrupt process, and may further be configured to cause the signal generation circuit 624 to drive the SDATA line during an arbitration process. The synchronization pulses generated by the signal generation circuit 604 may be configured to synchronize the clock signal generated at the host device 502 with the clock signal generated at the slave device 504. N Synchronize with the transmit clock signal generated in .

[0062] The protocol controller 622 can be configured to selectively activate the Manchester encoder 626 and the Manchester decoder 628 based on the operating mode of the single-wire serial interface 600. The Manchester decoder 628 can extract data and clock information from the signal received from the SDATA line 620. The protocol controller 622 can be further configured to format datagrams for transmission over the SDATA line 620. The protocol controller 622 can be further configured to decompose datagrams and / or respond to commands received from the SDATA line 620.

[0063] The protocol controller 614 may be configured to manage and control the operation of the line driver 612 and the line receiver 610. The protocol controller 622 may be configured to manage and control the operation of the line driver 632 and the line receiver 630. When not activated or deactivated, the line drivers 612, 632 may present a high impedance to the SDATA line 620. For example, when the single-wire slave device 504 NWhen configured or expected to send data or control signals over the SDATA line 620, the output of the line driver 612 in the host device 502 may present a high impedance to the SDATA line 620. When the host device 502 is driving the SDATA line 620, the single-wire slave device 504 N The output of the line driver 632 in is normally in a high impedance state.

[0064] The keeper circuit 640 coupled to the SDATA line 620 facilitates line turnaround, in-band interrupt requests, and arbitration processes in a bidirectional single-wire serial bus. It is often desirable to maintain the state of the SDATA line 620 when all devices are in high-impedance mode, during line turnaround, or during arbitration. Line turnaround occurs when the master device 502 transitions from transmit to receive or vice versa. During the arbitration process, when the single-wire slave device 504 N The host device 502 may enter a high impedance mode when it has the option to transmit and the line driver in the host device 502 may present a high impedance to the SDATA line 620 to avoid contention. A keeper circuit 640 may be used to maintain the state of the SDATA line 620. In one example, the keeper circuit 640 may be configured as a positive feedback circuit that drives the SDATA line 620 through a high impedance output and receives feedback from the SDATA line 620 through a low impedance input. The keeper circuit 640 may be configured to maintain the last asserted voltage on the SDATA line 620. The keeper circuit 640 may be used by the host device 502 and the single-line slave device 504, respectively. N The line drivers 612, 632 in FIG.

[0065] Figure 7 The present invention illustrates certain aspects of Manchester encoding and control signaling that can be used to exchange data between a host device and a single-wire slave device over a single-wire serial bus according to certain aspects of the present disclosure. The signal line of the single-wire serial bus is referred to herein as SDATA 722 (reference Figure 5 and Figure 6). Referring to the first timing diagram 700, Manchester encoding encodes data based on the direction of transitions occurring in the middle of a bit transmission interval 702. In some implementations, SDATA 722 may initially be in a low state and a transition 704 to a high state indicates a "1" value bit. SDATA 722 may initially be in a high state and a transition 706 to a low state indicates a "0" value bit. In other implementations, SDATA 722 may initially be in a low state and a transition 704 to a high state indicates a "0" value bit. SDATA 722 may initially be in a high state and a transition 706 to a low state indicates a "1" value bit. Clock information is embedded in the data signal transitions occurring within each bit transmission interval 702. Certain examples illustrated in this disclosure are based on implementations in which a transition 704 to a high state indicates a "1" value bit and a transition 706 to a low state indicates a "0" value bit.

[0066] The second timing diagram 710 illustrates five bit transmission intervals 714a-714e in the signal carried on SDATA 712. The bit sequence {0,0,1,1,0} is transmitted in the five bit transmission intervals 714a-714e, and transitions within each of the five bit transmission intervals 714a-714e are illustrated. It will be observed that transitions may occur at some boundaries between the bit transmission intervals 714a-714e, and no transitions occur at other boundaries between the bit transmission intervals 714a-714e.

[0067] Control signaling provided according to certain aspects of the present disclosure may be used to indicate the start of a datagram, clock synchronization, the start of data exchange for both writing and reading datagrams, and the end of a datagram. Certain aspects of the present disclosure relate to the generation and processing of in-band interrupt requests. In-band interrupt requests are accommodated under the control of a host device. The host device may defer, reject, or ignore in-band interrupt requests, including when, for example, a higher priority message arrives for transmission over a single-wire serial bus controlled by the host device.

[0068] A third timing diagram 720 illustrates the configuration of an SSC 724 and the synchronization mode (Sync 726) defined for a basic transaction, in accordance with certain aspects of the present disclosure. The SSC 724 operates as a control signal that is sent via SDATA 722 to signal the start of a transaction or interrupt handling process. The SSC 724 has the form of a pulse that is initiated when SDATA 722 is idle. In the illustrated example, SDATA 722 is in a low signaling state when idle. The SSC 724 is initiated by driving SDATA 722 to a high signaling state. The SSC 724 is terminated by driving SDATA 722 to a low signaling state. In the illustrated example, the SSC 724 has a duration of three cycles of an internal transmit clock signal 730 used by the host device to control the timing of transmissions over the single-wire serial bus.

[0069] In some implementations, SSC 724 is separated from Sync 726 by a duration corresponding to one cycle of the internal transmit clock signal 730. Sync 726 has a duration defined by multiple cycles of the internal transmit clock signal 730. In the illustrated example, Sync 726 has a duration corresponding to two cycles of the internal transmit clock signal 730. Other implementations can specify a synchronization mode defined by any number of cycles of the internal transmit clock signal 730 or by a minimum and / or maximum number of cycles of the internal transmit clock signal 730.

[0070] Sync 726 includes synchronization pulses 732, 734, which are provided to enable the clock generation circuit in the receiving device to synchronize with the internal transmit clock signal 730 used by the host device. The synchronization pulses 732, 734 can achieve clock synchronization including frequency and phase synchronization. The number of synchronization pulses sent in sequence can be configured or selected based on the application, the receiver capabilities, or under the control of the application. The number of clock ticks can be selected to achieve clock frequency and phase synchronization for different types of clock generation circuits (including ring oscillators, delay locked loops, and other circuits). The use of Manchester encoding allows clock phase adjustment to be performed in each bit transmission interval and can support long-term datagrams without losing clock synchronization.

[0071] According to certain aspects of the present disclosure, Sync 726 may be encoded with a binary value. In the illustrated example, Sync 726 is sent as two Manchester-encoded bits with the value "01".

[0072] Figure 8 Initiation of a transaction over a single-wire serial bus configured for exception handling prompted by an asserted in-band interrupt is illustrated in accordance with certain aspects of the present disclosure. Figure 8The first timing diagram 800 in FIG. 1 shows an example of an SSC 804 and a Sync 806 configured to indicate a normal or standard datagram. The SSC 804 is transmitted over SDATA 802 to signal the start of a normal or standard transaction. The SSC 804 is initiated by the host device when SDATA 802 is idle. In the illustrated example, SDATA 802 is in a low signaling state when idle, and the SSC 804 is initiated when the host device drives SDATA 802 to a high signaling state. The SSC 804 terminates when the host device drives SDATA 802 to a low signaling state. In the illustrated example, the SSC 804 has a duration of three cycles of an internal transmit clock signal 810 used by the host device to control the timing of transmissions over the single-wire serial bus, and is separated from the Sync 806 by a duration corresponding to one cycle of the internal transmit clock signal 810.

[0073] Sync 806 has a duration that can be expressed as a number of cycles of the internal transmit clock signal 810. In the illustrated example, Sync 806 has a duration corresponding to two cycles of the internal transmit clock signal 810. Other implementations may specify a synchronization mode defined by any number of cycles of the internal transmit clock signal 810, or by a minimum and / or maximum number of cycles of the internal transmit clock signal 810. The duration of Sync 806 is generally selected to ensure that the clock generation circuitry in the receiving device can synchronize with the internal transmit clock signal 810 used by the host device.

[0074] In the illustrated example, Sync 806 is sent as two Manchester-encoded bits 812, 814 and has a combined value of "01" to indicate that Sync 806 precedes a normal or standard datagram. A normal or standard datagram may refer to a datagram initiated under the control of a master device. A normal or standard datagram may include a command addressed to a single slave device or a group of slave devices, or a broadcast command to all slave devices. The values encoded in the multi-bit sync pattern may be defined or pre-configured so that the master device can distinguish between the types of transmissions. In one example, the values encoded in the multi-bit sync pattern and their meaning may be configured during manufacturing, system configuration, or by an application.

[0075] Figure 8The second timing diagram 820 in FIG. 1 shows an example of an SSC 824 and a Sync 826 configured to indicate an exception transaction. In this example, the SSC 824 is sent via the SDATA 822 to signal the start of the interrupt handling process. The SSC 824 is initiated when the SDATA 822 is idle. As shown in this example, the SDATA 822 is in a low signaling state when idle, and the SSC 824 is initiated when the SDATA 822 is driven to a high signaling state. The SSC 824 terminates when the host device drives the SDATA 822 to a low signaling state.

[0076] The SSC 824 illustrated in the second timing diagram 820 may be considered an interrupt request. One or more slave devices may assert and interrupt request by driving SDATA 822 to a high signaling state. Figure 6 For example, when SDATA 822 is idle, the master device 602 may place the output of its line driver 612 into a high impedance state, thereby causing SDATA 620 to be weakly held low by the keeper circuit 640. The slave device 604 N The line driver 632 can easily overcome the keeper circuit 640 and drive SDATA 620 high.

[0077] Return to Figure 8 , the second timing diagram 820 may represent Figure 6 822 is in an idle state 828. The host device can be configured to monitor SDATA 822 when it is in an idle state 828. The host device detects that at least one slave device has driven SDATA 822 to a high signaling state 830. Any slave device that asserts an interrupt request is expected to maintain SDATA 822 in the high signaling state 830 for a period of time (this period of time is defined during manufacturing or configured by the application) to ensure sufficient time to detect the host device's interrupt request. In the illustrated example, the interrupt-asserting slave device continues to drive SDATA 822 high for two cycles of the internal transmit clock signal before placing its line driver into a high-impedance state. SDATA 822 remains in the high signaling state 832 based on a weak pull-down by a keeper circuit. The internal transmit clock signal can be used by the host device or a slave device to control the timing of transmissions on the single-wire serial bus. The host device and slave devices generate internal transmit clock signals that can be synchronized using the timing provided by the Manchester-encoded signal.

[0078] The host device may bring the output of its line driver out of the high impedance state and actively maintain SDATA 822 in the high signaling state 834 before driving SDATA 822 to the low signaling state, thereby terminating SSC 824. In the illustrated example, SSC 824 has a duration corresponding to three cycles of the internal transmit clock signal, but this duration may be defined during manufacturing or system configuration and / or selected based on application requirements. In the illustrated example, SSC 824 has a duration of three cycles of the internal transmit clock signal. After SSC 824 has terminated, all devices coupled to SDATA 822 interpret this transition as the start of a new datagram by the host device.

[0079] Sync 826 may follow SSC 824 after a configured or predefined delay. In the illustrated example, the delay corresponds to one cycle of the internal transmit clock signal 830. Sync 826 may have a duration that can be expressed as a plurality of cycles of the internal transmit clock signal 830. In the illustrated example, Sync 826 has a duration corresponding to two cycles of the internal transmit clock signal 830. Other implementations may specify a synchronization pattern defined by any number of cycles of the internal transmit clock signal 830 or by a minimum and / or maximum number of cycles of the internal transmit clock signal 830. The duration of Sync 826 is typically selected to ensure that the clock generation circuitry in the receiving device can synchronize with the internal transmit clock signal 830 used by the host device.

[0080] In the illustrated example, Sync 826 is sent as two Manchester-encoded bits 836, 838 having a value of "00" to indicate that Sync 826 precedes the interrupt processing process. In another example, the host device can send a synchronization pattern as two Manchester-encoded bits having a value of "01" to indicate that the synchronization pattern precedes a normal or standard datagram. In the latter example, the host device can process the interrupt request through a simple data exchange using a command code configured to initiate a read or write of one or more slave devices. In some instances, the host device can send a "01" pattern when ignoring or postponing the processing of the interrupt request.

[0081] The value encoded in the multi-bit synchronization pattern can be used by a master device to indicate different types of exception handling transactions, including hot join transactions for assigning addresses and / or priorities to slave devices, reset or error recovery procedures, etc. In some instances, the multi-bit synchronization pattern can be assigned to indicate the special transmission of a normal or standard datagram without an address to a preconfigured priority target slave device.

[0082] Certain aspects of the present disclosure relate to interrupt request processing and signaling and messaging formats and structures that can be used to identify slave devices that have requested interrupt service. In some implementations, address arbitration can be used to determine the highest-priority slave device requesting interrupt service. In one example, each requesting slave device drives its unique device identifier (address) over a single-wire serial bus, such that the highest-priority slave device wins arbitration based on the configuration of bits in its unique identifier. In some implementations, an arbitration process based on a "raise your hand" mechanism is used to identify all slave devices currently requesting interrupt service. In one example, each slave device coupled to the single-wire bus is assigned a time slot within an arbitration cycle and can affirmatively signal a request for interrupt service during its assigned time slot. A host device can identify and record each slave device requesting interrupt service and can service each requesting slave device based on device priority, a queuing algorithm, or based on priorities and parameters defined by an application or system configuration. In some implementations, the slave device currently requesting interrupt service can be identified through a query, in which the host device polls each slave device to determine the need for interrupt service. In one example, the host device may poll all devices and then determine the order of service based on device priority, a queuing algorithm, or based on priorities and parameters defined by an application or system configuration. In another example, the host device may poll the devices in an order determined by device priority, a queuing algorithm, or based on priorities and parameters defined by an application or system configuration, and then service the interrupt once a device indicates a need for service during the polling period.

[0083] The master device may also delay, postpone, or forgo interrupt servicing at any time after detecting an interrupt request or during arbitration, polling, or servicing an interrupt. After terminating the interrupt-related process, the master device may retain information about the slave device requesting interrupt servicing.

[0084] Figure 9 Included is a timing diagram 900 illustrating an arbitrated time slot transaction 904 conducted on a single-wire serial bus configured or adapted according to certain aspects of the present disclosure. The single-wire serial bus has an interconnect or line (SDATA 902) configured to carry bidirectional data between two or more devices. Figures 5 to 8 Consistent with the system and signaling shown in , a master device manages the operation of a single-wire serial bus by providing control signaling that can indicate, for example, the start of a datagram, the end of a datagram, or the start of an interrupt handling transaction. The master device also employs signaling and encoding techniques configured to synchronize clocks at slave devices and enable data exchange during read and write operations. Control signaling based on the configuration of a synchronous mode can be used to service and accommodate interrupt requests.

[0085] In the illustrated example, the SSC 906 is provided on the SDATA 902. The SSC 906 may be initiated as an interrupt request (e.g. Figure 8 906) and is subsequently terminated by the master device during an idle period when it recognizes the presence of signaling on SDATA 902. SSC 906 may be initiated and terminated by the master device, including when deferred interrupt request processing is initiated, or as part of a series of address arbitration procedures for identifying all slave devices requesting interrupt service.

[0086] The master device can initiate SSC 906, or one or more slave devices can initiate SSC 906 by driving SDATA 902 high during a bus idle period. In the case where SSC 906 is initiated by a slave device, the slave device can initiate SSC 906 after SDATA 902 has been idle for a minimum period defined by the protocol and / or preconfigured during system initialization. It is expected that the slave device releases SDATA 902 by causing its line driver coupled to SDATA 902 to present a high impedance to SDATA 902 within one clock cycle of an internally generated clock signal. The signaling of SDATA 902 can be maintained by a keeper circuit after the line driver in the slave device has entered a high impedance mode. The master device is configured to terminate SSC 906 by driving SDATA 902 low.

[0087] The host device may send Sync 908 after terminating SSC 906. In the illustrated example, Sync 908 is sent as two Manchester-encoded bits with a value of "00" to indicate that an interrupt service process is being initiated. The number of synchronization pulses sent in Sync 908 may be selected or configured during manufacturing, system integration, initial system configuration, and / or by an application or host device. The value encoded in Sync 1012 indicating that an interrupt service transaction will ensue may be selected or configured during manufacturing, system integration, initial system configuration, and / or by an application or host device.

[0088] Sync 908 may precede arbitration cycle 910. In some examples, arbitration cycle 910 allocates two-cycle arbitration time slots to each slave device registered with or coupled to the single-wire serial bus at the host device. Arbitration time slots are assigned to slave devices based on a device address that uniquely identifies and distinguishes the slave device. The value of the device address may indicate the priority of the slave device to which it is assigned. In one example, the slave device with the highest value device address is considered the highest priority slave device. In another example, the slave device with the lowest value device address is considered the highest priority slave device. Device addresses may be assigned during manufacturing, system integration, initial system configuration, and / or by an application or host device.

[0089] In the illustrated example, arbitration cycle 910 accommodates 16 devices and has a duration of 32 cycles of the transmit clock signal used by the master device. In this example, the slave device with the highest-valued device address has the highest priority device and is assigned the first arbitration slot 920, and the slave device with the lowest-valued device address has the lowest priority device and may be the last arbitration slot 930. This configuration of arbitration slots enables the master device to terminate arbitration slot transaction 904 after detecting the first assertion of an interrupt request. Alternatively or additionally, other techniques for handling high-priority interrupt requests may be facilitated by early termination of arbitration slot transactions 904. For example, arbitration slot transactions 904 may be terminated when the master detects assertion of an interrupt request by a slave device that has previously been identified as a high-priority participant, including when a lower-priority slave device has previously asserted an interrupt request within the same arbitration slot transaction 904.

[0090] According to certain aspects of the present disclosure, the first cycle of each arbitration time slot is reserved for signaling by the slave device to which the time slot is assigned. The second cycle of each arbitration time slot is reserved for signaling by the master device. A slave device may participate in bus arbitration by driving SDATA 902 high during the first cycle of its corresponding time slot in arbitration cycle 910. The participating slave device then places its line driver into a high-impedance state before the end of the first cycle of that time slot. SDATA 902 remains high due to operation of a keeper circuit or due to the master device activating its line driver to maintain SDATA 902 high for the entire first cycle. The master device drives SDATA 902 low during the second cycle of that time slot to explicitly signal participation in arbitration by the next slave device.

[0091] For two arbitration slots (in Figure 9 The symbol is a time slot N and Slot N+1 ) shows the timing of the signals on SDATA 902. SlotN Occurs first in time and is assigned a slot N The slave device can be N The interrupt is asserted by driving SDATA 902 high during the first clock cycle 922 of SDATA. Initially, SDATA 902 is not driven and is weakly held in a low signaling state 926 by a keeper circuit. The asserting slave device enables its line driver and drives SDATA 902 to a high signaling state 928. The asserting slave device deactivates its line driver, causing its output to enter a high impedance state. The keeper circuit weakly holds SDATA 902 in a high signaling state 928. N During the second clock cycle 924 of Slot 1, the host device enables its line drivers and drives SDATA 902 to a low signaling state 926. The host device disables its line drivers, causing their outputs to enter a high impedance state, whereby SDATA 902 is not driven and is weakly held in the low signaling state 926 by the keeper circuit. N+1 Appear in Slot N After that, and is assigned Slot N+1 The slave device does not assert the interrupt. SDATA 902 remains undriven and is weakly held in the low signaling state 926 by the keeper circuit. In some implementations, the master device can enable its line driver and actively drive SDATA 902 low before re-entering the high impedance state.

[0092] The master device identifies each device that drives SDATA 902 high during its corresponding time slot in the arbitration cycle 910 as a device seeking interrupt service. The master device can then schedule interrupt service for the participating slave devices in an order determined by the priority or sequence configured for the system. In the event that the master device abandons the arbitration process by sending an 8-cycle SSC, the master device can retain information identifying the participating slave devices in the arbitration cycle 910 and can schedule interrupt service based on the identification information.

[0093] The host device may idle SDATA 902 for a period of time 912 after the arbitration cycle 910 and before initiating the next transaction 914. SDATA 902 may be idled when the host device places its line drivers into a high impedance state. In the illustrated example, the next transaction 914 begins with SSC 916 and Sync 918. Sync 918 is sent as two Manchester-encoded bits with a value of "01" to indicate that a normal or standard datagram will ensue. The next transaction 914 may be executed to service one or more interrupt requests.

[0094] According to certain aspects of the present disclosure, control signaling provided by a host device may indicate the start of a datagram, the end of a datagram, the start of an interruptible transaction, and the abandonment of an interruption process (e.g., by sending an SSC). A datagram may also be referred to as a frame, or may be provided within a frame that includes an arbitration or other datagram. Control signaling provided by a host device may indicate a start of frame (SoF) or an end of frame (EoF). Signaling and encoding techniques may be configured to implement clock synchronization and data exchange for read and write operations.

[0095] Address scan arbitration performed according to certain aspects of the present disclosure can be used to determine the identity of one or more slave devices requesting interrupt service. Multiple slave devices can assert interrupts concurrently, and each asserting device may be unaware of the actions of the other asserting devices. In some instances, a slave device desiring to request interrupt service can refrain from initiating an SSC when another slave device has already initiated one.

[0096] According to certain aspects of the present disclosure, all slave devices coupled to a single-wire serial bus or registered for operation on the single-wire serial bus can participate in address scan arbitration. Address scan arbitration can be used to identify slave devices currently requesting or in interrupt service. Address scan arbitration can detect a slave device initiating an SSC on the single-wire serial bus to generate an interrupt request, a slave device preempted by another slave device initiating an SSC, and a slave device generating a demand for interrupt service after an interrupt request has been asserted.

[0097] In one aspect, each slave device is addressed in turn by the master device, prompting the slave device to signal a request for interrupt service. This response by the slave device can be referred to as a hand raise, which is used to indicate a pending interrupt request. The hand raise is signaled when the addressed slave device switches the single-wire serial bus to generate a pulse that can be detected by the master device. Slave devices that do not need or desire interrupt service do not drive the single-wire serial bus after their unique address is sent over the single-wire serial bus.

[0098] Figure 10 Included is a timing diagram 1000 illustrating address scan arbitration that may be performed on a single-wire serial bus configured or adapted according to certain aspects of the present disclosure. The single-wire serial bus has an interconnect or line (SDATA 1002) configured to carry bidirectional data between two or more devices. Figures 5 to 8Consistent with the system and signaling shown in , the host device manages the operation of the single-wire serial bus by providing control signaling that can indicate, for example, the start of a datagram, the end of a datagram, or the start of an interrupt handling transaction, as well as the abandonment of an interrupt handling or arbitration process (e.g., by sending an SSC). The host device also employs signaling and encoding techniques configured to achieve clock synchronization at the slave devices and to achieve data exchange during read and write operations.

[0099] According to certain aspects, address scan arbitration may be initiated as an immediate response to an interrupt request asserted by one or more slave devices. When one or more slave devices drive SDATA 1002 high during an idle period, the address scan arbitration may be initiated as follows: Figure 8 An interrupt request is initiated as shown in the second timing diagram 820. The host device may drive SDATA 1002 low to complete the SSC. The host device may then send a synchronization pattern encoded to indicate that interrupt processing will ensue. Interrupt processing may include initiating an address scan arbitration to identify at least one slave device that is requesting interrupt service. Address scan arbitration may be performed to identify all slave devices that are requesting interrupt service, and the host device may schedule or prioritize interrupt service for the requesting slave device. In some embodiments, the host device may postpone address scan arbitration when, for example, a high priority message becomes available for transmission by the host device. In some specific implementations, the host device may terminate address scan arbitration before all slave devices have been addressed. Early termination may occur when the requesting slave device is identified as a high priority device, or when other high priority messages become available for transmission by the host device. The terminated address scan arbitration process may subsequently be resumed and completed, or may be restarted.

[0100] The master device may initiate a deferred, resumed, or restarted address scan arbitration process by sending an SSC and a synchronization pattern encoded to indicate that interrupt processing will ensue. Subsequent SSCs 1010, 1018, 1028 are initiated and terminated by the master device as part of a series of address arbitration transactions used to identify all slave devices requesting interrupt service.

[0101] Figure 10The timing diagram 1000 in FIG. 1 illustrates two address scan arbitration transactions 1004 and 1006. The first address scan arbitration transaction 1004 involves a slave device that is not requesting or expecting interrupt service. The second address scan arbitration transaction 1006 involves a slave device that is requesting interrupt service. For each address scan arbitration transaction 1004 and 1006, an SSC 1010 and 1018 are sent after SDATA 1002 has been idle for a minimum period of time defined by the protocol and / or preconfigured during system initialization. Following the SSC 1010 and 1018, a synchronization pattern (Sync 1012 and 1020) encoded to indicate interrupt processing is sent via SDATA 1002. In the illustrated example, Sync 1012 and 1020 are sent as two Manchester-encoded bits having a value of "00" to indicate that an interrupt processing procedure is being initiated. The number of sync pulses sent in Sync 1012, 1020 may be selected or configured during manufacturing, system integration, initial system configuration, and / or by an application or host device. The value encoded in Sync 1012, 1020 indicating an interrupt service transaction may be selected or configured during manufacturing, system integration, initial system configuration, and / or by an application or host device.

[0102] Sync 1012 is followed by an address field, consistent with the structure and configuration of read and write commands sent in a normal transaction. The address field is encoded with a unique identifier that serves as the device address of the slave device to be polled. Response windows 1016, 1024 are provided for the addressed slave device to send a response. During response windows 1016, 1024, the master device places the outputs of its line drivers into a high-impedance state. Response windows 1016, 1024 can have a duration calculated to ensure that the least capable slave device can respond to the poll. In one example, response windows 1016, 1024 have a duration of at least three transmit clock cycles. An upper limit can be defined for the duration of response windows 1016, 1024 based on the number of transmit clock cycles, which is defined as the minimum idle time before an interrupt can be asserted.

[0103] In the example of the first address scan arbitration transaction 1004, the slave device responding to address 1022 (here, 0b0010) does not respond. In the example of the second address scan arbitration transaction 1004, the slave device responding to address 1014 (here, 0b0011) sends a pulse 1026 within the response window 1024. A third SSC 1028 may be sent to begin the third address scan arbitration transaction or to initiate a normal read or write transaction, which may be sent, for example, as part of an interrupt service to one or more slave devices.

[0104] In some implementations, the modified address scan arbitration process can be performed using normal read transactions. In these implementations, the host device can read the interrupt request status from a register located at an address defined by the protocol or configuration.

[0105] Figure 11 A read transaction 1100 is illustrated as being executed on a single-wire serial bus configured according to certain aspects disclosed herein. Read transaction 1100 may be protocol-specified for normal communication between a host device and one or more slave devices. According to certain aspects of the present disclosure, read transaction 1100 may also be used by the host device to process an interrupt. For example, the host device may read one or more registers in the slave device to determine whether to request interrupt service. The registers may be defined by the protocol or configuration and may directly indicate an interrupt request status or may indicate a status or status change that will prompt an interrupt request.

[0106] The master device may send a synchronization bit in the Sync 1104 field following SSC 1102 to indicate that a normal transaction will follow. In one example, the synchronization bit carry is Manchester encoded and carries a value indicating a normal transaction. The receiving device may use the synchronization bit to synchronize its local clock generation circuitry. A read command 1106 is sent to the slave device. Read command 1106 may have a structure and content that is compatible or conforms to one or more commands defined by the RFFE protocol. Read command 1106 may be encoded using Manchester encoding.

[0107] The master device provides a turnaround period 1108 during which the master device places its line drivers into a high-impedance state and the slave device addressed by the read command 1106 activates its line drivers. In one example, turnaround period 1108 includes two cycles of a transmit clock signal. The master device is configured to deactivate its line drivers during the first clock cycle of turnaround period 1108, and the addressed slave device is configured to activate its line drivers during the second clock cycle of turnaround period 1108. The slave device transmits a synchronization pulse 1110, which the master device can use to synchronize its transmit clock generation circuitry with the local clock generation circuitry of the addressed slave device. The slave device then transmits a payload 1112. Payload 1112 can be encoded using Manchester encoding.

[0108] A second turnaround period 1114 is provided. During the second turnaround period 1114, the slave device addressed by the read command 1106 places its line driver into a high-impedance state, and the master device activates its line driver. In one example, turnaround period 1114 includes two cycles of the transmit clock signal, with the addressed slave device configured to disable its line driver in the first clock cycle, and the master configured to enable its line driver in the second clock cycle. The read transaction 1100 is terminated by an End of Terminate (EoF) 1116. In some instances, the End of Terminate (EoF) 1116 can be indicated by SDATA being idle for several cycles. In one example, the End of Terminate (EoF) 1116 is indicated when SDATA is idle for seven cycles of the transmit clock.

[0109] In various examples provided herein, examples of single-wire serial buses are described in which data and commands are configured according to an RFFE protocol. The RFFE protocol is used to illustrate certain aspects of the present disclosure. The single-wire serial bus can operate according to different types of serial multi-point protocols, including, for example, the SPMI protocol or the I3C protocol. Certain aspects of the serial multi-point protocol selected for controlling and managing transmissions over the single-wire serial bus can be adapted, configured, or modified to support arbitration, line turnaround, and transmissions performed without an explicit clock reference (such as a clock signal sent on a dedicated clock line).

[0110] Examples of Processing Circuits and Methods

[0111] Figure 12 1 is a diagram illustrating an example of a hardware implementation of device 1200. In some examples, device 1200 can perform one or more functions disclosed herein. According to various aspects of the present disclosure, processing circuitry 1202 can be used to implement an element, any portion of an element, or any combination of elements disclosed herein. Processing circuitry 1202 may include one or more processors 1204 controlled by some combination of hardware and software modules. Examples of processors 1204 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic components, discrete hardware circuits, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors 1204 may include special-purpose processors that perform specific functions and may be configured, enhanced, or controlled by one of software modules 1216. One or more processors 1204 may be configured by a combination of software modules 1216 loaded during initialization, and may also be configured by loading or unloading one or more software modules 1216 during operation.

[0112] In the illustrated example, processing circuit 1202 may be implemented using a bus architecture, generally represented by bus 1210. Depending on the specific application of processing circuit 1202 and the overall design constraints, bus 1210 may include any number of interconnecting buses and bridges. Bus 1210 links various circuits together, including one or more processors 1204 and storage 1206. Storage 1206 may include memory devices and mass storage devices and may be referred to herein as computer-readable media and / or processor-readable media. Bus 1210 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuits. Bus interface 1208 may provide an interface between bus 1210 and one or more transceivers 1212a, 1212b. A transceiver 1212a, 1212b may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in transceivers 1212a, 1212b. Each transceiver 1212a, 1212b provides a means for communicating with various other devices via a transmission medium. In one example, transceiver 1212a can be used to couple device 1200 to a multi-wire bus. In another example, transceiver 1212b can be used to connect device 1200 to a radio access network. Depending on the nature of device 1200, a user interface 1218 (e.g., a keypad, display, speaker, microphone, joystick) may also be provided and may be communicatively coupled to bus 1210 directly or via bus interface 1208.

[0113] The processor 1204 may be responsible for managing the bus 1210 and for general processing, which may include executing software stored in a computer-readable medium, which may include a storage device 1206. In this regard, the processing circuit 1202 (including the processor 1204) may be used to implement any of the methods, functions, and techniques disclosed herein. The storage device 1206 may be used to store data that is manipulated by the processor 1204 when executing the software, and the software may be configured to implement any of the methods disclosed herein.

[0114] One or more processors 1204 in the processing circuit 1202 can execute software. Software should be interpreted broadly to mean instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form within the storage device 1206 or in an external computer-readable medium. The external computer-readable medium and / or the storage device 1206 may include non-transitory computer-readable media. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. Computer-readable media and / or storage 1206 may also include, for example, carrier waves, transmission lines, and any other suitable medium for transmitting software and / or instructions that can be accessed and read by a computer. Computer-readable media and / or storage 1206 may reside in processing circuit 1202, in processor 1204, external to processing circuit 1202, or distributed across multiple entities including processing circuit 1202. Computer-readable media and / or storage 1206 may be embodied as a computer program product. For example, a computer program product may include a computer-readable medium in packaging material. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

[0115] Storage device 1206 may maintain software maintained and / or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules 1216. Each of software modules 1216 may include instructions and data that, when installed or loaded into processing circuitry 1202 and executed by one or more processors 1204, contribute to a runtime image 1214 that controls the operation of one or more processors 1204. Certain instructions, when executed, may cause processing circuitry 1202 to perform functions according to certain methods, algorithms, and processes described herein.

[0116] Some of the software modules 1216 may be loaded during initialization of the processing circuit 1202, and these software modules 1216 may configure the processing circuit 1202 to enable the various functions disclosed herein. For example, some of the software modules 1216 may configure the internal devices and / or logic circuits 1222 of the processor 1204 and may manage access to external devices such as the transceivers 1212a, 1212b, the bus interface 1208, the user interface 1218, timers, math coprocessors, and the like. The software modules 1216 may include a control program and / or operating system that interacts with interrupt handlers and device drivers and controls access to various resources provided by the processing circuit 1202. Resources may include memory, processing time, access to the transceivers 1212a, 1212b, the user interface 1218, and the like.

[0117] The one or more processors 1204 of the processing circuit 1202 can be multifunctional, whereby some of the software modules 1216 are loaded and configured to perform different functions or different instances of the same function. The one or more processors 1204 can also be adapted to manage background tasks initiated in response to inputs from, for example, the user interface 1218, the transceivers 1212a, 1212b, and device drivers. To support the execution of multiple functions, the one or more processors 1204 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks serviced by the one or more processors 1204 as needed or desired. In one example, the multitasking environment can be implemented using a time-sharing program 1220 that transfers control of the processors 1204 between different tasks, whereby each task returns control of the one or more processors 1204 to the time-sharing program 1220 upon completion of any pending operations and / or in response to inputs such as interrupts. When a task controls one or more processors 1204, the processing circuit is effectively specialized for the purpose addressed by the function associated with the control task. The time sharing program 1220 may include an operating system, a main loop that sends control on a cyclic basis, functions that allocate control of one or more processors 1204 based on the priority of the functions, and / or an interrupt-driven main loop that responds to external events by providing control of one or more processors 1204 to processing functions.

[0118] Processing circuit 1202 can be configured to perform one or more of the functions disclosed herein. For example, processing circuit 1202 can be configured to operate as a master device coupled to a serial bus. Processing circuit 1202 can be configured to initiate a pulse on a line coupling processing circuit 1202 to a slave device, present a high impedance to the line after initiating the pulse, and determine whether the slave device has prematurely terminated the pulse, thereby indicating a first code value. If the slave device has not terminated the pulse, processing circuit 1202 can be configured to terminate the pulse after a duration sufficient to indicate a second code value. In one example, the first code value is assigned a binary 1 and the second code value is assigned a binary 0. In another example, the first code value is assigned a binary 0 and the second code value is assigned a binary 1. Processing circuit 1202 can be configured to determine the code value or can employ a separate PWM decoder.

[0119] Figure 13 Flowchart 1300 is a method for data communication that can be performed at a host device coupled to a single-wire serial bus. One or more slave devices can be coupled to the single-wire serial bus. The host device can exchange Manchester-encoded data with the slave devices. The host device can send Manchester-encoded commands to the slave devices. At block 1302, the host device can transmit a plurality of synchronization pulses on the single-wire serial bus after transmitting a sequence SSC on the single-wire serial bus. The plurality of synchronization pulses are configured to synchronize one or more receiving devices coupled to the single-wire serial bus to an untransmitted transmit clock signal. At block 1304, when the plurality of synchronization pulses are encoded with a first value, the host device can initiate an interrupt handling procedure. At block 1306, when the plurality of synchronization pulses are encoded with a second value, the host device can initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the single-wire serial bus. The plurality of synchronization pulses can be encoded using Manchester encoding.

[0120] In some instances, the host device may determine that SSC has been initiated when the single-wire serial bus transitions from a first signaling state to a second signaling state, and may terminate SSC by causing a line driver in the host device to drive the single-wire serial bus from the second signaling state to the first signaling state.

[0121] In some implementations, a host device may initiate an interrupt handling process by causing a line driver in the host device to present a high impedance to the single-wire serial bus after transmitting a plurality of synchronization pulses after driving the single-wire serial bus to transition to a first signaling state. A time slot may be defined or configured to have a duration corresponding to two cycles of an unsent transmit clock signal. For each time slot, the host device may cause the line driver to present a high impedance to the single-wire serial bus before the start of each time slot, determine whether the single-wire serial bus transitions from the first signaling state to the second signaling state during a first cycle of each time slot, determine that a slave device associated with each time slot is requesting interrupt service when the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot, and cause the line driver to drive the single-wire serial bus from the second signaling state to the first signaling state during a second cycle of each time slot when the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot.

[0122] In some implementations, a host device can initiate an interrupt handling process by sending a device address on the single-wire serial bus after sending a plurality of synchronization pulses, causing a line driver in the host device to present a high impedance to the single-wire serial bus after sending the device address, and determining that a slave device associated with the device address is requesting interrupt service when a pulse is received from the single-wire serial bus during a period corresponding to a configured number of cycles of the transmit clock signal.

[0123] In some examples, the master device may schedule interrupt service for one or more slave devices determined to be requesting interrupt service during the interrupt handling process.

[0124] In some examples, the host device may send a Manchester-encoded data payload on a single-wire serial bus after initiating a write transaction. The host device may receive a Manchester-encoded data payload on the single-wire serial bus after initiating a read transaction. The read transaction or the write transaction may be formatted according to the RFFE protocol.

[0125] Figure 14 1400 is a flow chart of a method that can be performed by a slave device coupled to a single-wire serial bus. One or more slave devices can be coupled to the single-wire serial bus. The slave devices can receive Manchester-encoded commands from a master device and can exchange Manchester-encoded data with the master device in response to the commands.

[0126] At block 1402, after receiving an SSC from a single-wire serial bus, a slave device may receive a plurality of synchronization pulses from the single-wire serial bus. At block 1404, the slave device may use the plurality of synchronization pulses to synchronize an internal clock signal. At block 1406, when the plurality of synchronization pulses are encoded with a first value, the slave device may participate in an interrupt handling process. At block 1408, when the plurality of synchronization pulses are encoded with a second value and followed by an address corresponding to a device address associated with the slave device, the slave device may respond to a read command or a write command. The plurality of synchronization pulses may be encoded using Manchester encoding.

[0127] In some examples, a slave device can initiate SSC by driving the single-wire serial bus from a first signaling state to a second signaling state and can present a high impedance to the single-wire serial bus after the initiation pulse.

[0128] In some implementations, participating in the interrupt handling process includes requesting interrupt service by driving the single-wire serial bus from a first signaling state to a second signaling state during a time slot associated with the slave device. The time slot can be one of a plurality of time slots. A device address associated with the slave device can determine a temporal position of the time slot within the plurality of time slots.

[0129] In some implementations, engaging in the interrupt handling process includes receiving a device address on the single-wire serial bus after receiving a plurality of synchronization pulses, and requesting interrupt servicing by sending a pulse on the single-wire serial bus when the device address is associated with a slave device.

[0130] In some implementations, responding to the read command or the write command includes sending or receiving a Manchester-encoded data payload on a single-wire serial bus.

[0131] Figure 151502 is a diagram illustrating an example of a hardware implementation for an apparatus 1500 employing a processing circuit 1502. The processing circuit typically has a controller or processor 1516, which may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. The processing circuit 1502 may be implemented using a bus architecture, generally represented by bus 1510. Bus 1510 may include any number of interconnecting buses and bridges, depending on the specific application of the processing circuit 1502 and the overall design constraints. Bus 1510 links together various circuits, including one or more processors and / or hardware modules, represented by controller or processor 1516, modules or circuits 1504, 1506, and 1508, and processor-readable storage media 1518. One or more physical layer circuits and / or modules 1514 may be provided to support communications over a communication link implemented using the multi-wire bus 1512, through an antenna or antenna array 1522 (e.g., to a radio access network), and the like. The bus 1510 may also link various other circuits, such as timing sources, peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0132] Processor 1516 is responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1518. Processor-readable storage medium 1518 may include non-transitory storage media. When executed by processor 1516, the software causes processing circuit 1502 to perform the various functions described herein and as described for any particular device. Processor-readable storage medium 1518 may be used to store data manipulated by processor 1516 when executing the software. Processing circuit 1502 also includes at least one of modules 1504, 1506, and 1508. Modules 1504, 1506, and 1508 may be software modules running on processor 1516, resident / stored on processor-readable storage medium 1518, one or more hardware modules coupled to processor 1516, or some combination thereof. Modules 1504, 1506, and 1508 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0133] In one configuration, the apparatus 1500 includes modules and / or circuits 1504 adapted to generate and process different types of SSC and synchronization pulses, modules and / or circuits 1506 adapted to synchronize an internal clock signal based on transitions in the synchronization pulses and Manchester-encoded data or commands, and modules and / or circuits 1508 adapted to encode and decode data and commands using Manchester encoding.

[0134] In one example, apparatus 1500 includes physical layer circuitry and / or modules 1514 implemented using interface circuitry having at least one line driver adapted or configured to couple apparatus 1500 to a single-wire serial bus. Apparatus 1500 may include a processor 1516 or a protocol controller. Apparatus 1500 may include a keeper circuit or be coupled to a keeper circuit via the single-wire serial bus. The keeper circuit is operable to maintain the single-wire serial bus in a constant signaling state after line drivers in a master device and a slave device present a high impedance to the single-wire serial bus.

[0135] In a first example, the processor 1516 or the protocol controller is configured to transmit a plurality of synchronization pulses on the single-wire serial bus after transmitting an SSC on the single-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the single-wire serial bus to an untransmitted transmit clock signal. The processor 1516 or the protocol controller may be further configured to initiate an interrupt handling process when the plurality of synchronization pulses are encoded with a first value, and to initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the single-wire serial bus when the plurality of synchronization pulses are encoded with a second value. The plurality of synchronization pulses may be encoded using Manchester encoding.

[0136] The processor 1516 or protocol controller may be further configured to determine that SSC has been initiated when the single-wire serial bus transitions from the first signaling state to the second signaling state, and terminate the SSC by causing a line driver in the host device to drive the single-wire serial bus from the second signaling state to the first signaling state.

[0137] The processor 1516 or protocol controller may be further configured to cause the line driver in the apparatus 1500 to present a high impedance to the single-wire serial bus after transmitting a plurality of synchronization pulses after driving the single-wire serial bus to transition to the first signaling state. A time slot may be configured with two cycles of a transmit clock signal. For each time slot having a duration corresponding to a pair of cycles of the transmit clock signal, the processor 1516 or protocol controller may cause the line driver to present a high impedance to the single-wire serial bus before the start of each time slot, determine whether the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot, determine that a slave device associated with each time slot is requesting interrupt service when the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot, and cause the line driver to drive the single-wire serial bus from the second signaling state to the first signaling state during the second cycle of each time slot when the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot.

[0138] The processor 1516 or protocol controller may be further configured to transmit a device address on the single-wire serial bus after transmitting the plurality of synchronization pulses, cause a line driver in the apparatus 1500 to present a high impedance to the single-wire serial bus after transmitting the device address, and determine that a slave device associated with the device address is requesting interrupt service when a pulse is received from the single-wire serial bus during a period corresponding to a configured number of cycles of the transmit clock signal.

[0139] The processor 1516 or protocol controller may be further configured to schedule interrupt service for one or more slave devices determined to be requesting interrupt service.

[0140] The processor 1516 or the protocol controller may be further configured to send a Manchester-encoded data payload on the single-wire serial bus after initiating a write transaction. The processor 1516 or the protocol controller may receive a Manchester-encoded data payload on the single-wire serial bus after initiating a read transaction. The read transaction or the write transaction may be formatted according to the RFFE protocol.

[0141] In a second example, the processor 1516 or protocol controller is configured to receive a plurality of synchronization pulses from the single-wire serial bus after having received an SSC from the single-wire serial bus, synchronize an internal clock signal using the plurality of synchronization pulses, participate in an interrupt handling process when the plurality of synchronization pulses are encoded with a first value, and respond to a read command or a write command when the plurality of synchronization pulses are encoded with a second value and are followed by an address corresponding to a device address associated with a slave device. The plurality of synchronization pulses may be encoded using Manchester encoding.

[0142] In some implementations, the processor 1516 or protocol controller can be further configured to initiate SSC by driving the single-wire serial bus from a first signaling state to a second signaling state and presenting a high impedance to the single-wire serial bus after initiating the pulse.

[0143] In some implementations, the processor 1516 or the protocol controller is further configured to request interrupt service by driving the single-wire serial bus from a first signaling state to a second signaling state in a time slot associated with the slave device. The time slot can be one of a plurality of time slots, and a device address associated with the slave device can determine a temporal position of the time slot within the plurality of time slots.

[0144] In some implementations, the processor 1516 or protocol controller is further configured to receive a device address on the single-wire serial bus after receiving the plurality of synchronization pulses and request interrupt servicing by sending a pulse on the single-wire serial bus when the device address is associated with a slave device.

[0145] In some implementations, the processor 1516 or protocol controller is further configured to send or receive Manchester-encoded data payloads on the single-wire serial bus.

[0146] Some specific implementation examples are described in the following numbered clauses:

[0147] 1. A method of data communication performed at a host device, comprising: transmitting a plurality of synchronization pulses on a single-wire serial bus after a sequence start condition (SSC) has been transmitted on the single-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the single-wire serial bus to an untransmitted transmit clock signal; initiating an interrupt handling procedure when the plurality of synchronization pulses are encoded with a first value; and initiating a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the single-wire serial bus when the plurality of synchronization pulses are encoded with a second value.

[0148] 2. The method of clause 1, wherein the plurality of synchronization pulses are encoded using Manchester encoding.

[0149] 3. The method according to clause 1 or clause 2 further includes: determining that the SSC has been initiated when the single-wire serial bus transitions from a first signaling state to a second signaling state; and terminating the SSC by causing a line driver in the host device to drive the single-wire serial bus from the second signaling state to the first signaling state.

[0150] 4. A method according to any one of clauses 1 to 3, wherein initiating the interrupt handling process includes: after driving the single-wire serial bus to the first signaling state and after sending the multiple synchronization pulses, causing the line driver in the host device to present a high impedance to the single-wire serial bus; and for each time slot of a pair of cycles including the transmit clock signal: causing the line driver to present the high impedance to the single-wire serial bus before the start of each time slot; determining whether the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot; when the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot, determining that the slave device associated with each time slot is requesting interrupt service; and when the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot, causing the line driver to drive the single-wire serial bus from the second signaling state to the first signaling state during the second cycle of each time slot.

[0151] 5. A method according to any one of clauses 1 to 3, wherein initiating the interrupt handling process includes: sending a device address on the single-wire serial bus after sending the multiple synchronization pulses; causing a line driver in the host device to present a high impedance to the single-wire serial bus after sending the device address; and when a pulse is received from the single-wire serial bus during a period including a configured number of cycles of the transmit clock signal, determining that a slave device associated with the device address is requesting interrupt service.

[0152] 6. The method of any one of clauses 1 to 5, further comprising: scheduling interrupt servicing for one or more slave devices determined to be requesting interrupt servicing during the interrupt handling process.

[0153] 7. The method of any of clauses 1 to 5, further comprising, after initiating the write transaction, sending a Manchester-encoded data payload on the single-wire serial bus.

[0154] 8. The method of any of clauses 1 to 5, further comprising, after initiating the read transaction, receiving a Manchester-encoded data payload on the single-wire serial bus.

[0155] 9. The method of any of clauses 1 to 8, wherein the read transaction or the write transaction is formatted according to a Radio Frequency Front End (RFFE) protocol.

[0156] 10. A data communication apparatus, comprising: a line driver configured to couple the data communication apparatus to a single-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses on the single-wire serial bus after a sequence start condition (SSC) has been transmitted on the single-wire serial bus, the plurality of synchronization pulses configured to synchronize one or more receiving devices coupled to the single-wire serial bus to an untransmitted transmit clock signal;

[0157] When the plurality of synchronization pulses are encoded with a first value, an interrupt handling process is initiated; and when the plurality of synchronization pulses are encoded with a second value, a read transaction or a write transaction is initiated with at least one of the one or more receiving devices coupled to the single-wire serial bus.

[0158] 11. The data communication device of clause 10, wherein the plurality of synchronization pulses are encoded using Manchester encoding.

[0159] 12. A data communication device according to clause 10 or clause 11, wherein the controller is further configured to: determine that the SSC has been initiated when the single-wire serial bus transitions from a first signaling state to a second signaling state; and terminate the SSC by causing the line driver to drive the single-wire serial bus from the second signaling state to the first signaling state.

[0160] 13. A data communications apparatus according to any of clauses 10 to 12, wherein the controller is further configured to: after driving the single-wire serial bus to a first signalling state and after transmitting the plurality of synchronisation pulses, cause the line driver to present a high impedance to the single-wire serial bus; and for each time slot comprising a pair of cycles of the transmit clock signal:

[0161] causing the line driver to present the high impedance to the single-wire serial bus before the start of each time slot; determining whether the single-wire serial bus transitions from the first signaling state to the second signaling state during a first cycle of each time slot; determining that a slave device associated with each time slot is requesting interrupt service when the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot; and causing the line driver to drive the single-wire serial bus from the second signaling state to the first signaling state during a second cycle of each time slot when the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot.

[0162] 14. A data communication device according to any one of clauses 10 to 12, wherein the controller is further configured to: send a device address on the single-wire serial bus after sending the multiple synchronization pulses; cause the line driver in the data communication device to present a high impedance to the single-wire serial bus after sending the device address; and when a pulse is received from the single-wire serial bus during a period including a configured number of cycles of the transmit clock signal, determine that the slave device associated with the device address is requesting interrupt service.

[0163] 15. The data communication apparatus according to any one of clauses 10 to 14, wherein the controller is further configured to schedule interrupt service for one or more slave devices determined to be requesting interrupt service.

[0164] 16. The data communications apparatus of any of clauses 10 to 15, wherein the controller is further configured to, after initiating the write transaction, send a Manchester-encoded data payload on the single-wire serial bus.

[0165] 17. The data communications apparatus of any of clauses 10 to 16, wherein the controller is further configured to, after initiating the read transaction, receive a Manchester-encoded data payload on the single-wire serial bus.

[0166] 18. A data communications device according to any of clauses 10 to 17, wherein the read transaction or the write transaction is formatted according to a Radio Frequency Front End (RFFE) protocol.

[0167] 19. A method of data communication performed at a slave device, comprising: receiving a plurality of synchronization pulses from a single-wire serial bus after a sequence start condition (SSC) has been received from the single-wire serial bus; synchronizing an internal clock signal using the plurality of synchronization pulses; participating in an interrupt handling process when the plurality of synchronization pulses are encoded with a first value; and responding to a read command or a write command when the plurality of synchronization pulses are encoded with a second value and are followed by an address corresponding to a device address associated with the slave device.

[0168] 20. The method of clause 19, wherein the plurality of synchronization pulses are encoded using Manchester encoding.

[0169] 21. The method of clause 19 or clause 20, further comprising: initiating the SSC by driving the single-wire serial bus from a first signaling state to a second signaling state; and presenting a high impedance to the single-wire serial bus after initiating the SSC.

[0170] 22. A method according to any one of clauses 19 to 21, wherein participating in the interrupt handling process includes: requesting interrupt service by driving the single-wire serial bus from a first signaling state to a second signaling state in a time slot associated with the slave device, wherein the time slot is one of a plurality of time slots, and wherein the device address associated with the slave device determines the time position of the time slot within the plurality of time slots.

[0171] 23. The method of any one of clauses 19 to 21, wherein participating in the interrupt handling process comprises: receiving the device address associated with the slave device on the single-wire serial bus after receiving the plurality of synchronization pulses;

[0172] and requesting interrupt servicing by sending a pulse on the single-wire serial bus.

[0173] 24. The method of any of clauses 19 to 23, wherein responding to the read command or the write command comprises sending or receiving a Manchester-encoded data payload on the single-wire serial bus.

[0174] 25. A data communication device comprising: a line driver configured to couple the data communication device to a single-wire serial bus; and a controller configured to: receive a plurality of synchronization pulses from the single-wire serial bus after a sequence start condition (SSC) has been received from the single-wire serial bus; synchronize an internal clock signal using the plurality of synchronization pulses; participate in an interrupt handling process when the plurality of synchronization pulses are encoded with a first value; and respond to a read command or a write command when the plurality of synchronization pulses are encoded with a second value and are followed by an address corresponding to a device address associated with the data communication device.

[0175] 26. The data communication device of clause 25, wherein the plurality of synchronization pulses are encoded using Manchester encoding.

[0176] 27. A data communication device according to clause 25 or clause 26, wherein the controller is further configured to: initiate the SSC by driving the single-wire serial bus from a first signaling state to a second signaling state; and after initiating the SSC, present a high impedance to the single-wire serial bus.

[0177] 28. A data communication device according to any one of clauses 25 to 27, wherein the controller is further configured to: request interrupt service by driving the single-wire serial bus from a first signaling state to a second signaling state in a time slot associated with the data communication device, wherein the time slot is one of a plurality of time slots, and wherein the device address associated with the data communication device determines the time position of the time slot within the plurality of time slots.

[0178] 29. A data communication device according to any one of clauses 25 to 27, wherein the controller is further configured to: receive the device address associated with the data communication device on the single-wire serial bus after receiving the multiple synchronization pulses; and request interrupt service by sending a pulse on the single-wire serial bus.

[0179] 30. The data communications device of any of clauses 25 to 29, wherein the controller is further configured to transmit or receive Manchester-encoded data payloads on the single-wire serial bus.

[0180] It should be understood that the specific order or hierarchy of steps in the disclosed processes is illustrative of exemplary methods. It should be understood that the specific order or hierarchy of steps in these processes may be rearranged based on design preferences. Furthermore, some steps may be combined or omitted. The accompanying method claims present elements of various steps in a sample order and are not meant to be limited to the specific order or hierarchy presented.

[0181] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but should be given the full scope consistent with the claims, wherein, unless otherwise specified, reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". Unless otherwise specifically stated, the term "some" refers to one or more. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or will later be known to a person of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. No claim element can be interpreted as a component plus function unless the element is explicitly stated using the phrase "component for..."

Claims

1. A method of data communication performed at a host device, comprising: transmitting a plurality of synchronization pulses on the single-wire serial bus after a sequence start condition (SSC) has been transmitted on the single-wire serial bus, the plurality of synchronization pulses configured to synchronize one or more receiving devices coupled to the single-wire serial bus to an untransmitted transmit clock signal; initiating an interrupt handling process when the plurality of synchronization pulses are encoded with a first value; as well as When the plurality of synchronization pulses are encoded with a second value, a read transaction or a write transaction is initiated with at least one of the one or more receiving devices coupled to the single-wire serial bus.

2. The method of claim 1, wherein the plurality of synchronization pulses are encoded using Manchester encoding.

3. The method according to claim 1, further comprising: When the single-wire serial bus transitions from a first signaling state to a second signaling state, determining that the SSC has been initiated; as well as The SSC is terminated by causing a line driver in the host device to drive the single-wire serial bus from the second signaling state to the first signaling state.

4. The method according to claim 1, wherein initiating the interrupt handling process comprises: causing a line driver in the host device to present a high impedance to the single-wire serial bus after driving the single-wire serial bus to a first signaling state and after sending the plurality of synchronization pulses; as well as For each time slot comprising a pair of cycles of the transmit clock signal: causing the line driver to present the high impedance to the single-wire serial bus before the start of each time slot; determining whether the single-wire serial bus transitions from the first signaling state to a second signaling state during a first cycle of each time slot; determining that a slave device associated with each time slot is requesting interrupt service when the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot; as well as When the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot, the line driver drives the single-wire serial bus from the second signaling state to the first signaling state during a second cycle of each time slot.

5. The method according to claim 1, wherein initiating the interrupt handling process comprises: After sending the plurality of synchronization pulses, sending a device address on the single-wire serial bus; After sending the device address, causing a line driver in the host device to present a high impedance to the single-wire serial bus; as well as When a pulse is received from the single-wire serial bus during a period that includes a configured number of cycles of the transmit clock signal, it is determined that a slave device associated with the device address is requesting interrupt servicing.

6. The method according to claim 1, further comprising: Interrupt servicing is scheduled for one or more slave devices determined to be requesting interrupt servicing during the interrupt handling process.

7. The method according to claim 1, further comprising: After initiating the write transaction, a Manchester-encoded data payload is transmitted over the single-wire serial bus.

8. The method according to claim 1, further comprising: After initiating the read transaction, a Manchester-encoded data payload is received on the single-wire serial bus.

9. The method of claim 1, wherein the read transaction or the write transaction is formatted according to a radio frequency front end (RFFE) protocol.

10. A data communication device comprising: a line driver configured to couple the data communication device to a single-wire serial bus; and A controller configured to: transmitting a plurality of synchronization pulses on the single-wire serial bus after a sequence start condition (SSC) has been transmitted on the single-wire serial bus, the plurality of synchronization pulses configured to synchronize one or more receiving devices coupled to the single-wire serial bus to an untransmitted transmit clock signal; initiating an interrupt handling process when the plurality of synchronization pulses are encoded with a first value; as well as When the plurality of synchronization pulses are encoded with a second value, a read transaction or a write transaction is initiated with at least one of the one or more receiving devices coupled to the single-wire serial bus.

11. The data communication device of claim 10, wherein the plurality of synchronization pulses are encoded using Manchester encoding.

12. The data communication device according to claim 10, wherein the controller is further configured to: When the single-wire serial bus transitions from a first signaling state to a second signaling state, determining that the SSC has been initiated; and The SSC is terminated by causing the line driver to drive the single-wire serial bus from the second signaling state to the first signaling state.

13. The data communication device according to claim 10, wherein the controller is further configured to: causing the line driver to present a high impedance to the single-wire serial bus after driving the single-wire serial bus to a first signaling state and after transmitting the plurality of synchronization pulses; as well as For each time slot comprising a pair of cycles of the transmit clock signal: causing the line driver to present the high impedance to the single-wire serial bus before the start of each time slot; determining whether the single-wire serial bus transitions from the first signaling state to a second signaling state during a first cycle of each time slot; determining that a slave device associated with each time slot is requesting interrupt service when the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot; as well as When the single-wire serial bus transitions from the first signaling state to the second signaling state during the first cycle of each time slot, the line driver drives the single-wire serial bus from the second signaling state to the first signaling state during a second cycle of each time slot.

14. The data communication device according to claim 10, wherein the controller is further configured to: After sending the plurality of synchronization pulses, sending a device address on the single-wire serial bus; After transmitting the device address, causing the line driver in the data communication apparatus to present a high impedance to the single-wire serial bus; and When a pulse is received from the single-wire serial bus during a period that includes a configured number of cycles of the transmit clock signal, it is determined that a slave device associated with the device address is requesting interrupt servicing.

15. The data communication device according to claim 10, wherein the controller is further configured to: Interrupt servicing is scheduled for one or more slave devices determined to be requesting interrupt servicing. 16 . The data communication device of claim 10 , wherein the controller is further configured to transmit a Manchester-encoded data payload on the single-wire serial bus after initiating the write transaction. 17 . The data communication device of claim 10 , wherein the controller is further configured to receive a Manchester-encoded data payload on the single-wire serial bus after initiating the read transaction.

18. The data communication device of claim 10, wherein the read transaction or the write transaction is formatted according to a radio frequency front end (RFFE) protocol.

19. A method of data communication performed at a slave device, comprising: receiving a plurality of synchronization pulses from the single-wire serial bus after a sequence start condition (SSC) has been received from the single-wire serial bus; synchronizing an internal clock signal using the plurality of synchronization pulses; participating in an interrupt handling process when the plurality of synchronization pulses are encoded with a first value; as well as When the plurality of synchronization pulses are encoded with a second value and followed by an address corresponding to a device address associated with the slave device, a response is made to a read command or a write command.

20. The method of claim 19, wherein the plurality of synchronization pulses are encoded using Manchester encoding.

21. The method of claim 19, further comprising: initiating the SSC by driving the single-wire serial bus from a first signaling state to a second signaling state; as well as After initiating the SSC, a high impedance is presented to the single-wire serial bus.

22. The method of claim 19, wherein participating in the interrupt handling process comprises: requesting interrupt servicing by driving the single-wire serial bus from a first signaling state to a second signaling state in a time slot associated with the slave device, wherein the time slot is one of a plurality of time slots, and wherein the device address associated with the slave device determines a temporal position of the time slot within the plurality of time slots.

23. The method of claim 19, wherein participating in the interrupt handling process comprises: receiving the device address associated with the slave device on the single-wire serial bus after receiving the plurality of synchronization pulses; as well as Interrupt servicing is requested by sending a pulse on the single-wire serial bus.

24. The method of claim 19, wherein responding to the read command or the write command comprises sending or receiving a Manchester-encoded data payload on the single-wire serial bus.

25. A data communication device comprising: a line driver configured to couple the data communication device to a single-wire serial bus; and A controller configured to: receiving a plurality of synchronization pulses from the single-wire serial bus after a sequence start condition (SSC) has been received from the single-wire serial bus; synchronizing an internal clock signal using the plurality of synchronization pulses; participating in an interrupt handling process when the plurality of synchronization pulses are encoded with a first value; as well as When the plurality of synchronization pulses are encoded with a second value and followed by an address corresponding to a device address associated with the data communication apparatus, a response is made to a read command or a write command.

26. The data communication device of claim 25, wherein the plurality of synchronization pulses are encoded using Manchester encoding.

27. The data communication device according to claim 25, wherein the controller is further configured to: initiating the SSC by driving the single-wire serial bus from a first signaling state to a second signaling state; and After initiating the SSC, a high impedance is presented to the single-wire serial bus.

28. The data communication device according to claim 25, wherein the controller is further configured to: requesting interrupt servicing by driving the single-wire serial bus from a first signaling state to a second signaling state in a time slot associated with the data communication device, wherein the time slot is one of a plurality of time slots, and wherein the device address associated with the data communication apparatus determines a temporal position of the time slot within the plurality of time slots.

29. The data communication device according to claim 25, wherein the controller is further configured to: receiving the device address associated with the data communication apparatus on the single-wire serial bus after receiving the plurality of synchronization pulses; and Interrupt servicing is requested by sending a pulse on the single-wire serial bus.

30. The data communication device of claim 25, wherein the controller is further configured to transmit or receive Manchester-encoded data payloads on the single-wire serial bus.

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