On-chip all-optical switch and preparation method thereof

Abstract

The present application relates to the field of intelligent manufacturing, and specifically discloses an on-chip all-optical switch and a preparation method thereof, which obtains the current etching rate and cumulative depth by real-time monitoring of laser interference signals, and establishes real-time process state feedback. Subsequently, the real-time state is fed into a PID control loop based on a rate profile recipe, and the etching power is dynamically adjusted by comparing it with the target rate. However, in order to eradicate the deep uncertainty caused by process fluctuations and measurement errors, before further PID control, the complex intrinsic relationship between the current etching rate and the PID gain parameter is intelligently analyzed, and a feedback adjustment pre-response encoding vector is generated, and then the correction factor for the cumulative etching depth is decoded. This pre-emptive intelligent correction ensures that the PID controller always makes decisions based on the most accurate state information and the most optimized goals. Thus, the intelligent preparation of the on-chip all-optical switch is realized.

Description

Technical Field

[0001] The present application relates to the field of intelligent manufacturing, and more specifically, to an on-chip all-optical switch and a method for preparing the same. Background Art

[0002] With the rapid development of information technology, optical communications and optical interconnection technologies have become the core of building high-speed, high-capacity information networks. Against this backdrop, on-chip all-optical switches, as key components in photonic integrated circuits, are becoming increasingly important. They enable rapid routing, modulation, and processing of optical signals, playing an irreplaceable role in increasing data transmission rates, reducing energy consumption, and enabling the miniaturization and integration of photonic chips. Therefore, developing efficient and reliable on-chip all-optical switch fabrication methods is a critical challenge currently underway in the optoelectronics field.

[0003] Currently, the fabrication of on-chip all-optical switches typically relies on semiconductor processes, with electron beam lithography and plasma etching being the core steps in forming precise optical waveguide structures. However, existing fabrication schemes still face challenges in precisely controlling the etching process. For example, during plasma etching, due to fluctuations in process parameters, changes in equipment status, and the inhomogeneity of the material itself, it is often difficult to precisely control the etching rate and depth, resulting in dimensional deviations in the resulting optical waveguide structure, which in turn affects the performance and yield of the on-chip all-optical switch. This imprecise control not only increases manufacturing costs but also limits further improvements in device performance.

[0004] Therefore, an optimized fabrication scheme for on-chip all-optical switches is desired. Summary of the Invention

[0005] In order to solve the above technical problems, this application is proposed.

[0006] According to one aspect of the present application, a method for preparing an on-chip all-optical switch is provided, comprising:

[0007] Providing an SOI wafer, the SOI wafer comprising a silicon substrate, a buried oxide layer located above the silicon substrate, and a top silicon layer located above the buried oxide layer;

[0008] Chemically cleaning the SOI wafer to obtain a chemically cleaned SOI wafer;

[0009] Performing electron beam lithography on the chemically cleaned SOI wafer to form a photoresist pattern on the chemically cleaned SOI wafer, comprising: performing a photoresist spin coating process on the chemically cleaned SOI wafer, then performing a pre-baking process and an electron beam exposure process on the photoresist-spin-coated wafer, and immersing the exposed wafer in a specific developer to obtain the photoresist pattern;

[0010] performing plasma etching on the photoresist pattern to obtain an optical waveguide structure;

[0011] Depositing a layer of cladding material on the optical waveguide structure to form an upper cladding layer that completely covers the optical waveguide structure to obtain an on-chip all-optical switch chip;

[0012] Cutting and packaging the on-chip all-optical switch chip to obtain an on-chip all-optical switch array;

[0013] Among them, the wafers that have been spin-coated with photoresist are pre-baked and subjected to electron beam exposure processing, including: extracting the current process status from the laser interference signal, and performing PID control based on the current process status and rate profile recipe to output actuator instructions, and sending them to the hardware for execution.

[0014] In the above-mentioned method for preparing an on-chip all-optical switch, after the chemically cleaned SOI wafer is subjected to a photoresist spin-coating process, the wafer coated with the photoresist is subjected to a pre-bake process and an electron beam exposure process, and the exposed wafer is immersed in a specific developer to obtain the photoresist pattern, including: uniformly spin-coating a layer of electron beam photoresist on the surface of the chemically cleaned SOI wafer to obtain a wafer coated with the photoresist; after the pre-bake process, the wafer coated with the photoresist is sent to an electron beam lithography device for electron beam exposure to obtain an exposed wafer; and immersing the exposed wafer in a specific developer to obtain the photoresist pattern.

[0015] In the above-mentioned preparation method of the on-chip all-optical switch, the current process state is extracted from the laser interference signal, and PID control is performed based on the current process state and the rate profile recipe to output an actuator instruction, and the actuator instruction is sent to the hardware for execution, including: in response to a task request, extracting the rate profile recipe and initial process parameters matching the task request from the recipe database, the initial process parameters including the basic gas flow, power and gain parameters of the PID controller; sending the initial process parameters to the ICP-RIE hardware through the driver layer; obtaining a real-time data stream through a high-frequency data acquisition module; stripping the laser interference signal from the real-time data stream, and calculating the current etching rate and cumulative etching depth based on the laser interference signal to obtain the current process state; performing PID control based on the current process state and the rate profile recipe to obtain a control output signal; passing the control output signal through a conversion function to obtain a new power value; encapsulating the new power value into an actuator instruction that can be recognized by the ICP-RIE hardware, and sending the actuator instruction to the hardware for execution through the driver layer.

[0016] In the above-mentioned method for preparing an on-chip all-optical switch, the laser interference signal is stripped from the real-time data stream, and the current etching rate and cumulative etching depth are calculated based on the laser interference signal to obtain the current process state, including: obtaining a key parameter, wherein the key parameter is the actual etching depth corresponding to each interference cycle; counting the cycles of the laser interference signal to obtain the total number of cycles and the fraction of the current uncompleted cycle; multiplying the sum of the total number of cycles and the fraction of the current uncompleted cycle by the key parameter to obtain the cumulative etching depth; performing a fast Fourier transform on the laser interference signal to obtain a peak frequency; multiplying the peak frequency by the key parameter to obtain the current etching rate; and assembling the cumulative etching depth and the current etching rate into the current process state.

[0017] In the above-mentioned method for preparing an on-chip all-optical switch, PID control is performed based on the current process state and the rate profile recipe to obtain a control output signal, including: based on the cumulative etching depth in the current process state, searching for a target rate that matches the accumulated etching depth from the rate profile recipe; calculating the difference between the target rate and the current etching rate in the current process state to obtain a rate error; and inputting the rate error into a PID controller to obtain the control output signal.

[0018] In the above-mentioned method for preparing an on-chip all-optical switch, based on the cumulative etching depth in the current process state, searching for a target rate that matches the current etching depth from the rate profile recipe, the method includes: extracting the current etching rate from the current process state; extracting the initial proportional gain coefficient, the initial integral gain coefficient, and the initial differential gain coefficient from the PID controller; performing structured embedded coding on the current etching rate, the initial proportional gain coefficient, the initial integral gain coefficient, and the initial differential gain coefficient to obtain a structured embedded coding vector of the current etching rate, a structured embedded coding vector of the initial proportional gain coefficient, a structured embedded coding vector of the initial integral gain coefficient, and a structured embedded coding vector of the initial differential gain coefficient. Embedding a coding vector; using a current etching rate structured embedded coding vector as a query vector, and using an initial proportional gain coefficient structured embedded coding vector, an initial integral gain coefficient structured embedded coding vector, and an initial differential gain coefficient structured embedded coding vector as key vectors, inputting them into a feature query network to obtain a feedback adjustment pre-response coding vector; performing feature decoding on the feedback adjustment pre-response coding vector to obtain an etching depth cumulative correction factor; correcting the cumulative etching depth based on the etching depth cumulative correction factor to obtain a corrected cumulative etching depth; and searching for a target rate that matches the corrected cumulative etching depth from the rate profile recipe.

[0019] In the above-mentioned method for preparing an on-chip all-optical switch, a current etching rate structured embedded coding vector is used as a query vector, and an initial proportional gain coefficient structured embedded coding vector, an initial integral gain coefficient structured embedded coding vector, and an initial differential gain coefficient structured embedded coding vector are used as key vectors, which are input into a feature query network to obtain a feedback adjustment pre-response coding vector, including: calculating a PID control gain correlation coefficient between any two vectors among the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector, and the initial differential gain coefficient structured embedded coding vector to obtain a PID control gain feature intra-correlation optimization embedding matrix; mapping the current etching rate structured embedded coding vector to the feature space of the PID control gain feature intra-correlation optimization embedding matrix to obtain an aligned current etching rate structured embedded coding vector; and based on the PID control gain feature intra-correlation optimization embedding matrix, analyzing the matching degree of the aligned current etching rate structured embedded coding vector with the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector, and the initial differential gain coefficient structured embedded coding vector, and returning the vector corresponding to the largest one as the feedback adjustment pre-response coding vector.

[0020] In the above-mentioned method for preparing an on-chip all-optical switch, based on the PID control gain feature internal correlation optimization embedding matrix, the matching degree between the aligned current etching rate structured embedded coding vector and the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector is analyzed, and the vector corresponding to the largest one is returned as the feedback adjustment pre-response coding vector, including: based on the PID control gain feature internal correlation optimization embedding matrix, the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector are feature-adaptively fine-tuned to obtain the optimized initial proportional gain coefficient structured embedded coding vector, the optimized initial integral gain coefficient structured embedded coding vector and the optimized initial differential gain coefficient structured embedded coding vector; calculating the matching degree between the aligned current etching rate structured embedded coding vector and the optimized initial proportional gain coefficient structured embedded coding vector, the optimized initial integral gain coefficient structured embedded coding vector and the optimized initial differential gain coefficient structured embedded coding vector; and taking the vector corresponding to the largest matching degree as the feedback adjustment pre-response coding vector.

[0021] According to another aspect of the present application, an on-chip all-optical switch is provided. The on-chip all-optical switch is manufactured by the above-mentioned on-chip all-optical switch manufacturing method.

[0022] Compared with the prior art, the present application provides an on-chip all-optical switch and its preparation method. Based on the conventional steps of providing SOI wafers and performing electron beam lithography to form photoresist patterns, the core is to transform the plasma etching link. First, the current etching rate and cumulative depth are obtained by real-time monitoring of the laser interference signal, and real-time process state feedback is established. Subsequently, the real-time state is sent to a PID control loop based on a rate profile recipe. By comparing with the target rate, the etching power is dynamically adjusted. This is the first layer of guarantee to solve the problem of inaccurate control. In order to eradicate the deep uncertainty caused by process fluctuations and measurement errors, dynamic feature query analysis is further introduced to intelligently analyze the complex intrinsic relationship between the current etching rate and the PID gain parameter before PID control, and generate a feedback adjustment pre-response encoding vector, and then decode the correction factor for the cumulative etching depth. This pre-emptive intelligent correction ensures that the PID controller always makes decisions based on the most accurate state information and the most optimized target, thereby achieving unprecedented control accuracy. Ultimately, the ideal optical waveguide structure is obtained through this high-precision etching, and the subsequent cladding deposition and chip cutting and packaging are completed, thereby systematically solving the problems of poor device performance and low yield caused by insufficient etching accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other purposes, features, and advantages of the present application will become more apparent through a more detailed description of the embodiments of the present application in conjunction with the accompanying drawings. The accompanying drawings are intended to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the drawings, the same reference numerals generally represent the same components or steps.

[0024] Figure 1 is a flow chart of a method for preparing an on-chip all-optical switch according to an embodiment of the present application;

[0025] Figure 2 A flowchart of a method for fabricating an on-chip all-optical switch according to an embodiment of the present application, for extracting the current process state from a laser interference signal, performing PID control based on the current process state and a rate profile recipe to output an actuator instruction, and sending the instruction to hardware for execution;

[0026] Figure 3 A flowchart of a method for fabricating an on-chip all-optical switch according to an embodiment of the present application for stripping a laser interference signal from the real-time data stream, and calculating a current etching rate and a cumulative etching depth based on the laser interference signal to obtain a current process state;

[0027] Figure 4This is a flow chart of searching for a matching target rate from the rate profile recipe based on the accumulated etching depth in the current process state in the method for fabricating an on-chip all-optical switch according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] Below, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described herein.

[0029] As used in this application and the claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not intended to refer to the singular but may include the plural. Generally speaking, the terms "comprises" and "include" only indicate the inclusion of the steps and elements specifically identified, and these steps and elements do not constitute an exclusive list. A method or apparatus may also include other steps or elements.

[0030] Although the present application makes various references to certain modules in the system according to embodiments of the present application, any number of different modules can be used and run on the user terminal and / or server. The modules are illustrative only, and different aspects of the system and method can use different modules.

[0031] Flowcharts are used in this application to illustrate the operations performed by the systems according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, the various steps may be processed in reverse order or simultaneously, as needed. Furthermore, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0032] Below, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described herein.

[0033] In response to the problem that it is difficult to accurately control the etching rate and depth during the plasma etching process of the on-chip all-optical switch preparation process, a method for preparing an on-chip all-optical switch is proposed in the technical solution of this application. Based on the conventional steps of providing an SOI wafer and performing electron beam lithography to form a photoresist pattern, the core of this solution is to transform the plasma etching process, transforming it from an open and uncertain process into a precise and predictable closed-loop intelligent control process. To achieve this goal, this solution obtains the laser interference signal in real time through a high-frequency data acquisition module, and extracts key information from it to calculate the current etching rate and cumulative etching depth, thereby forming real-time process status feedback. On this basis, an advanced PID control strategy is introduced to compare the real-time process status with the preset rate profile recipe, calculate the rate error, and use this as the input of the PID controller to dynamically generate a control output signal, thereby adjusting the initial process parameters such as the power of the ICP-RIE hardware to achieve precise tracking and control of the etching rate.

[0034] Furthermore, to enhance the adaptability and robustness of PID control, dynamic feature analysis is introduced to structuredly embed the current etching rate and the initial gain parameters (proportional, integral, and differential coefficients) of the PID controller. By calculating the matching degree between these encoding vectors, a feedback-adjusted pre-response encoding vector is dynamically generated. After feature decoding, this response encoding vector yields a cumulative etching depth correction factor, which is used to correct the cumulative etching depth, thereby finding a more accurate target rate within the rate profile recipe. This intelligent gain parameter optimization mechanism enables the PID controller to adaptively adjust the control strategy based on the inherent correlation between the real-time process state and the gain parameters, effectively suppressing process fluctuations and external interference, and ensuring the stability and accuracy of the etching process. This approach significantly improves the dimensional accuracy and surface quality of the optical waveguide structure during the fabrication of on-chip all-optical switches, thereby enhancing device performance and yield, and effectively resolving the challenge of inaccurate etching control.

[0035] In the technical solution of the present application, a method for preparing an on-chip all-optical switch is proposed. Figure 1 FIG. 1 is a flow chart of a method for preparing an on-chip all-optical switch according to an embodiment of the present application. Figure 1As shown, the method for preparing an on-chip all-optical switch according to an embodiment of the present application includes the following steps: S100, providing an SOI wafer, wherein the SOI wafer includes a silicon substrate, a buried oxide layer located above the silicon substrate, and a top silicon layer located above the buried oxide layer; S200, chemically cleaning the SOI wafer to obtain a chemically cleaned SOI wafer; S300, performing electron beam lithography on the chemically cleaned SOI wafer to form a photoresist pattern on the chemically cleaned SOI wafer; S400, performing plasma etching on the photoresist pattern to obtain an optical waveguide structure; S500, depositing a layer of cladding material on the optical waveguide structure to form an upper cladding layer that completely covers the optical waveguide structure to obtain an on-chip all-optical switch chip; S600, chip dicing and packaging the on-chip all-optical switch chip to obtain an array of on-chip all-optical switches.

[0036] Specifically, in steps S100 and S200, an SOI wafer is provided and chemically cleaned to obtain a chemically cleaned SOI wafer. It is worth noting that the SOI wafer comprises a silicon substrate, a buried oxide layer located above the silicon substrate, and a top layer of silicon located above the buried oxide layer. It should be understood that the SOI wafer, or silicon-on-insulator wafer, with its unique three-layer structure of silicon substrate, buried oxide layer, and top layer of silicon, provides an ideal platform for building high-performance photonic devices. The silicon substrate provides mechanical support, while the buried oxide layer acts as a low-refractive-index isolation layer, effectively confining light transmission in the top layer of silicon waveguides, reducing optical loss and enabling efficient guidance of optical signals. The top layer of silicon is the core material for forming the optical waveguide structure. Therefore, the SOI wafer is chosen as the substrate because it provides excellent optical isolation and a high refractive index contrast, forming the foundation for realizing on-chip optical waveguide structures. After the SOI wafer is prepared, chemical cleaning helps remove organic matter, metal ions, particulate contaminants, and the native oxide layer that may be present on the wafer surface. Even tiny residues of these contaminants can become sources of defects in subsequent high-precision processes such as electron beam lithography and plasma etching, leading to problems such as poor photoresist adhesion, uneven etching, rough waveguide sidewalls, and even short circuits. These problems severely impact the dimensional accuracy and surface quality of the optical waveguide, directly affecting the performance and reliability of on-chip all-optical switches. For example, organic residues can cause uneven photoresist exposure, metal ions can diffuse at high temperatures and form impurity centers, and particles can cause etching shadows or localized defects.

[0037] Specifically, in step S300, electron beam lithography is performed on the chemically cleaned SOI wafer to form a photoresist pattern on the chemically cleaned SOI wafer. Specifically, electron beam lithography is performed on the chemically cleaned SOI wafer to form a photoresist pattern on the chemically cleaned SOI wafer, including: performing a photoresist spin-coating process on the chemically cleaned SOI wafer, then performing a pre-bake process and an electron beam exposure process on the wafer spun with photoresist, and immersing the exposed wafer in a specific developer to obtain the photoresist pattern. It should be understood that the core functional component of the on-chip all-optical switch is the optical waveguide. The size of these waveguides is usually in the submicron to nanometer range and requires extremely high precision and complex geometric shapes to effectively guide and control optical signals. Traditional ultraviolet lithography technology is limited by the diffraction limit and cannot meet such fine processing requirements. However, electron beam lithography, with its extremely high resolution, can break through this limitation and accurately carve the required nanoscale pattern on the wafer surface. Therefore, the chemically cleaned SOI wafer is further subjected to electron beam lithography to form a photoresist pattern on the chemically cleaned SOI wafer. This allows the designed optical waveguide structure pattern to be transferred to the photoresist layer with high precision and fidelity, forming a photoresist pattern that is completely consistent with the design drawings. This process serves as a template for subsequent plasma etching, and the quality of the photoresist pattern directly determines the geometry, dimensional accuracy, sidewall perpendicularity, and surface roughness of the final etched optical waveguide. For example, a precise photoresist pattern ensures that the waveguide width, spacing, and bend radius meet design requirements, thereby ensuring low-loss transmission and efficient modulation of optical signals in the waveguide.

[0038] Specifically, in an embodiment of the present application, after the chemically cleaned SOI wafer is subjected to a photoresist spin-coating process, the wafer coated with the photoresist is subjected to a pre-bake process and an electron beam exposure process, and the exposed wafer is immersed in a specific developer to obtain the photoresist pattern, including: uniformly spin-coating a layer of electron beam photoresist on the surface of the SOI wafer after the chemical cleaning to obtain a wafer coated with the photoresist; after the pre-bake process is performed on the wafer coated with the photoresist, it is sent into an electron beam lithography device for electron beam exposure to obtain an exposed wafer; and the exposed wafer is immersed in a specific developer to obtain the photoresist pattern.

[0039] Specifically, after the chemical cleaning, a layer of electron beam photoresist is evenly spin-coated on the surface of the SOI wafer to obtain a wafer with a good photoresist coating. It should be understood that electron beam lithography is an indispensable means for preparing nanoscale optical waveguide structures, and photoresist is the photosensitive medium for electron beam exposure, which plays a bridging role in converting the design pattern from a digital blueprint to a physical form. Only by forming a uniform, dense, and thickness-controlled photoresist film on the wafer surface can the accuracy of subsequent electron beam exposure and the uniformity of etching be ensured. Specifically, in a specific example of the present application, a photoresist solution is dripped onto the surface of a high-speed rotating wafer, and the centrifugal force causes the photoresist to spread evenly and form a thin film. If the spin coating is uneven, the photoresist film thickness will vary. During the subsequent electron beam exposure process, different thickness areas will have different sensitivities to the electron beam, and the required exposure dose will also vary, resulting in underexposure or overexposure, causing image distortion, uneven line thickness, and even breakage or adhesion. Furthermore, film unevenness can affect the subsequent plasma etching rate and selectivity, resulting in dimensional deviations and rough sidewalls in the resulting optical waveguide structure, severely impacting the device's optical performance. By uniformly spin-coating a layer of electron beam photoresist on the chemically cleaned SOI wafer surface, a highly uniform, flat, and precisely controlled thickness photoresist film is obtained. This provides an ideal photosensitive medium for subsequent electron beam exposure, ensuring that the electron beam precisely impacts the photoresist at a preset dose, thereby forming a high-resolution, high-fidelity latent image in the photoresist layer.

[0040] Specifically, after the wafer coated with photoresist undergoes a pre-baking treatment, it is fed into an electron beam lithography system for electron beam exposure to produce an exposed wafer. It should be understood that electron beam lithography can achieve nanometer-level pattern resolution, far exceeding traditional photolithography. This is crucial for fabricating the submicron and even nanometer-scale optical waveguide structures required for on-chip all-optical switching. As the photosensitive material for electron beam exposure, the performance of photoresist directly determines the accuracy of the pattern. Pre-baking the wafer coated with photoresist before feeding it into the electron beam lithography system for exposure is a key step in forming precise optical waveguide structures. The purpose of the pre-baking treatment is to remove residual solvents from the photoresist. The photoresist contains a certain amount of solvent during the spin-coating process. If this solvent is not fully evaporated, the subsequent electron beam exposure process can cause uneven photoresist film thickness, inaccurate exposure dose, and even bubbles or cracks, thereby affecting the clarity and accuracy of the exposed pattern. By precisely controlling the temperature and time of pre-bake, the photoresist film layer can be made denser and more stable, improving its sensitivity and resolution to the electron beam, thus preparing for subsequent precise exposure.

[0041] After pre-baking, the wafer is then fed into an electron-beam lithography system for electron beam exposure, which precisely transfers the designed optical waveguide pattern onto the photoresist layer. Specifically, the electron-beam lithography system scans the photoresist surface with a high-energy electron beam, causing chemical changes in the photoresist in the exposed areas (for example, the solubility of positive-tone photoresist increases after exposure, while the solubility of negative-tone photoresist decreases after exposure), thus forming a latent image. The precision of this process directly determines the final optical waveguide geometry and morphology.

[0042] Therefore, the pre-bake and electron-beam lithography steps complement each other. The pre-bake ensures the uniformity and stability of the photoresist film, providing an ideal medium for electron-beam lithography. Electron-beam lithography, with its nanometer-scale resolution, precisely carves complex optical waveguide structures into the photoresist, resulting in an exposed wafer. Successful execution of this step is a prerequisite for subsequent plasma etching to form high-precision optical waveguide structures, which directly impacts the optical performance of the on-chip all-optical switch, such as transmission loss, coupling efficiency, and switching speed. This lays a solid foundation for the ultimate realization of high-performance on-chip all-optical switches.

[0043] Figure 2 The present invention is a flowchart of extracting the current process state from the laser interference signal, performing PID control based on the current process state and the rate profile recipe to output the actuator instruction, and sending it to the hardware for execution. Figure 2 As shown, the current process state is extracted from the laser interference signal, and PID control is performed based on the current process state and the rate profile recipe to output an actuator instruction, and the actuator instruction is sent to the hardware for execution, including: S310, in response to a task request, extracting a rate profile recipe and initial process parameters that match the task request from a recipe database, the initial process parameters including basic gas flow, power and gain parameters of the PID controller; S320, sending the initial process parameters to the ICP-RIE hardware through the driver layer; S330, acquiring a real-time data stream through a high-frequency data acquisition module; S340, stripping the laser interference signal from the real-time data stream, and calculating the current etching rate and cumulative etching depth based on the laser interference signal to obtain the current process state; S350, performing PID control based on the current process state and the rate profile recipe to obtain a control output signal; S360, passing the control output signal through a conversion function to obtain a new power value; S370, encapsulating the new power value into an actuator instruction that can be recognized by the ICP-RIE hardware, and sending the actuator instruction to the hardware for execution through the driver layer.

[0044] Specifically, in steps S310 and S320, in response to a task request, a rate profile recipe and initial process parameters matching the task request are retrieved from the recipe database, and these initial process parameters are sent to the ICP-RIE hardware via the driver layer. It is worth noting that the initial process parameters here include the base gas flow rate, power, and PID controller gain parameters. It should be understood that plasma etching is a highly complex physical and chemical process, and its etching rate and morphology are influenced by a combination of process parameters (such as gas flow rate, power, and pressure). To obtain an ideal optical waveguide structure, these parameters must be precisely set according to different design requirements and material properties. Traditional etching methods often rely on empirical experience or fixed parameters, making them difficult to adapt to diverse fabrication requirements and process fluctuations. In other words, in the fabrication process of an on-chip all-optical switch, particularly during the plasma etching phase, responding to task requests and retrieving matching rate profile recipes and initial process parameters from the recipe database, followed by sending them to the ICP-RIE hardware via the driver layer, is the starting point for achieving intelligent, high-precision etching control. The purpose is to provide a set of customized and optimized etching instructions for ICP-RIE hardware to start and guide the etching process. The task request contains information such as the target depth of this etching and the type of waveguide structure. Based on this information, the system intelligently retrieves the most matching rate profile recipe and initial process parameters from the pre-stored recipe database. The rate profile recipe defines the expected target etching rate at different etching depths, which makes the etching process no longer a single constant rate, but can be segmented or continuously adjusted according to the depth change, thereby optimizing the side wall verticality and surface roughness of the waveguide. The initial process parameters include the basic gas flow rate, RF power, and the gain parameters of the PID controller, which are the initial set points of the etching process. Sending these parameters to the ICP-RIE hardware through the driver layer is equivalent to setting the working mode and initial state for the etching equipment, ensuring that the etching process can be started according to the preset optimization path.

[0045] Specifically, in steps S330 and S340, a high-frequency data acquisition module acquires a real-time data stream, strips the laser interference signal from the real-time data stream, and calculates the current etching rate and cumulative etching depth based on the laser interference signal to obtain the current process status. It should be understood that the etching process is a complex and dynamically changing system. Traditional offline detection or endpoint detection methods cannot provide real-time information during the process, making it difficult to precisely control the etching process and prone to over- or under-etching, which affects the waveguide dimensional accuracy and surface quality. In the plasma etching process of an on-chip all-optical switch, real-time and accurate acquisition of the etching status is the key to achieving high-precision control. Therefore, acquiring the real-time data stream through a high-frequency data acquisition module, stripping the laser interference signal from it, and then calculating the current etching rate and cumulative etching depth to obtain the current process status are the key to solving the problem of insufficient etching accuracy in the background art. The purpose is to establish a high-precision, real-time etching state sensing system. The high-frequency data acquisition module can capture instantaneous changes within the etching chamber, particularly the laser interference signal, which is the most direct and sensitive physical quantity reflecting the etching depth and rate. When laser light strikes the wafer surface, some of the light is reflected by the etched surface, while another portion penetrates the etched layer and reflects at the buried oxide layer or silicon substrate interface, causing the two beams to interfere with each other. As the etching depth continues to change, the interference optical path difference varies, generating a periodic light intensity fluctuation signal. By extracting and analyzing these laser interference signals, the real-time etching status can be accurately inferred.

[0046] Figure 3 The present invention is a flowchart of a method for preparing an on-chip all-optical switch according to an embodiment of the present application, which involves stripping the laser interference signal from the real-time data stream and calculating the current etching rate and cumulative etching depth based on the laser interference signal to obtain the current process status. Figure 3 As shown, step S340 includes: S341, obtaining a key parameter, wherein the key parameter is the actual etching depth corresponding to each interference cycle; S342, counting the cycles of the laser interference signal to obtain the total number of cycles and the fraction of the current unfinished cycle; S343, multiplying the sum of the total number of cycles and the fraction of the current unfinished cycle by the key parameter to obtain the cumulative etching depth; S344, performing a fast Fourier transform on the laser interference signal to obtain a peak frequency; S345, multiplying the peak frequency by the key parameter to obtain the current etching rate; S346, assembling the cumulative etching depth and the current etching rate into the current process state.

[0047] Specifically, in step S350, PID control is performed based on the current process state and the rate profile recipe to obtain a control output signal. It should be understood that traditional etching control methods often use fixed parameters or simple endpoint detection, which is difficult to deal with various disturbances and nonlinear behaviors that may occur during the etching process, resulting in difficulty in accurately controlling the etching rate and depth, thereby affecting the final performance of the optical waveguide. Moreover, in the plasma etching process of the on-chip all-optical switch, it is not enough to simply obtain the real-time process state. What is more critical is how to use this information to accurately control the etching process. Therefore, performing PID control based on the current process state and the rate profile recipe to obtain a control output signal is the core control strategy for solving the problem of insufficient etching accuracy. In this way, dynamic and precise closed-loop control of the etching rate can be achieved, ensuring that the etching process can be carried out strictly in accordance with the preset optimization path.

[0048] More specifically, in an embodiment of the present application, PID control based on the current process state and the rate profile recipe to obtain a control output signal includes: searching for a matching target rate from the rate profile recipe based on the cumulative etch depth in the current process state; calculating the difference between the target rate and the current etch rate in the current process state to obtain a rate error; and inputting the rate error into a PID controller to obtain the control output signal. Specifically, the system first searches for a matching target rate from a pre-set rate profile recipe based on the cumulative etch depth monitored in real time during the current process state. A rate profile recipe is an etch rate curve pre-optimized based on different waveguide structures and material properties. It allows for dynamic adjustment of the etch rate at different depth stages to optimize key parameters such as waveguide sidewall verticality and surface roughness. This search process ensures that etching always progresses toward the optimal target. Next, the found target rate is compared with the current etch rate calculated in real time during the current process state, and the difference between the two, i.e., the rate error, is calculated. This rate error is a quantitative indicator of how far the current etching process deviates from the ideal state. Finally, this rate error is input into a PID (proportional-integral-derivative) controller. A mature and widely used feedback control algorithm, the PID controller calculates and outputs a control signal based on a weighted combination of the proportional term (current error), the integral term (accumulated error), and the derivative term (rate of change of error). This control output signal is used to adjust actuator parameters such as power in the ICP-RIE hardware to reduce the rate error and bring the current etching rate closer to the target rate.

[0049] Figure 4 The present invention is a flowchart of searching for a target rate that matches the rate profile recipe based on the cumulative etching depth in the current process state according to the method for preparing an on-chip all-optical switch according to an embodiment of the present application. Figure 4As shown, based on the cumulative etching depth in the current process state, searching for a target rate that matches the current etching depth from the rate profile recipe, including: S351, extracting the current etching rate from the current process state; S352, extracting the initial proportional gain coefficient, the initial integral gain coefficient, and the initial differential gain coefficient from the PID controller; S353, performing structured embedded coding on the current etching rate, the initial proportional gain coefficient, the initial integral gain coefficient, and the initial differential gain coefficient to obtain a current etching rate structured embedded coding vector, an initial proportional gain coefficient structured embedded coding vector, an initial integral gain coefficient structured embedded coding vector, and an initial differential gain coefficient structured embedded coding vector; S3 54. Using the current etching rate structured embedded coding vector as the query vector, and using the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector as the key vectors, input them into the feature query network to obtain the feedback adjustment pre-response coding vector; S355. Feature decoding is performed on the feedback adjustment pre-response coding vector to obtain an etching depth cumulative correction factor; S356. Based on the etching depth cumulative correction factor, the cumulative etching depth is corrected to obtain a corrected cumulative etching depth; S357. A target rate that matches the corrected cumulative etching depth is found from the rate profile recipe.

[0050] Specifically, in steps S351 and S352, the current etching rate is extracted from the current process state, and the initial proportional gain coefficient, initial integral gain coefficient, and initial differential gain coefficient are extracted from the PID controller. It should be understood that the performance of a PID controller is highly dependent on the settings of its gain parameters. In complex etching environments, process conditions (such as wafer conditions, chamber contamination, and slight variations in gas composition) may undergo subtle changes, causing the preset fixed gain parameters to no longer be optimal, thereby affecting control accuracy and system stability. This is one of the underlying reasons why further improvements in etching accuracy are difficult. To achieve deeper levels of intelligent control and optimization, relying solely on traditional PID control is insufficient; dynamic adjustment of the core parameters and gain coefficients of the PID controller is also required. Therefore, the current etching rate is extracted from the current process state, and the initial proportional gain coefficient, initial integral gain coefficient, and initial differential gain coefficient are extracted from the PID controller. This provides the necessary input data for the subsequent intelligent optimization algorithm to adaptively adjust the gain parameters of the PID controller. Extracting the current etching rate from the current process state is intended to obtain real-time dynamic information about the etching process; it is a key indicator for measuring etching progress and the effectiveness of current control. Extracting the initial proportional gain coefficient, initial integral gain coefficient, and initial differential gain coefficient from the PID controller is to obtain the current PID controller's behavior mode or personalized parameters. These initial gain coefficients represent the controller's current response strength to error, its cumulative effect on historical errors, and its ability to predict error trends.

[0051] Specifically, in step S353, the current etching rate, the initial proportional gain coefficient, the initial integral gain coefficient and the initial differential gain coefficient are subjected to structured embedded coding to obtain a current etching rate structured embedded coding vector, an initial proportional gain coefficient structured embedded coding vector, an initial integral gain coefficient structured embedded coding vector and an initial differential gain coefficient structured embedded coding vector. It should be understood that in order to achieve intelligent optimization of PID gain parameters, it is not enough to simply obtain the original etching rate and gain coefficient, because these raw data are usually scalars or simple numerical values, and it is difficult to directly capture the complex nonlinear relationship and potential pattern between them. Therefore, the current etching rate, the initial proportional gain coefficient, the initial integral gain coefficient and the initial differential gain coefficient are subjected to structured embedded coding to obtain the corresponding structured embedded coding vector. Converting these heterogeneous parameters with different physical meanings into a unified, high-dimensional vector representation can better capture the intrinsic correlation between them and provide a basis for efficient similarity matching and pattern recognition in the subsequent feature query network. This helps to overcome the limitations of PID parameter optimization in the background art that relies on experience or trial and error, and improve the robustness and accuracy of control. Mapping raw process and controller parameters into a low- or high-dimensional continuous vector space places semantically similar or functionally related parameters closer together, making them easier for machine learning models to process and analyze. This encoding effectively extracts and represents the deep features of these parameters, providing richer, more abstract information for subsequent intelligent decision-making.

[0052] More specifically, in a specific example of the present application, an embedding layer network can be used: Input layer: Receive the original current etching rate (a scalar value) and three initial PID gain coefficients (three scalar values). Embedding layer: In order to capture the structured information between the parameters, a multi-layer perceptron (MLP) network can be designed. For example, the etching rate can be used as input, and its embedding vector can be obtained through an MLP; the three PID gain coefficients can be concatenated as input to another MLP to obtain an embedding vector containing the correlation information of the three. Output layer: Output four independent structured embedding coding vectors, corresponding to the current etching rate, initial proportional gain coefficient, initial integral gain coefficient, and initial differential gain coefficient. The dimensions of these vectors can be set according to the input requirements of the subsequent feature query network.

[0053] Specifically, in step S354, the current etching rate structured embedded coding vector is used as the query vector, and the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector are used as key vectors, which are input into the feature query network to obtain the feedback regulation pre-response coding vector. It should be understood that the complexity and dynamics of the etching process require the PID controller to be able to intelligently adjust its gain parameters according to the real-time working conditions to maintain optimal control performance and stability. Traditional empirical adjustment or offline optimization is difficult to meet this real-time, high-precision requirement. In order to overcome the limitations of traditional PID control in which gain parameters are fixed or difficult to dynamically optimize, in the technical solution of the present application, the current etching rate structured embedded coding vector is used as the query vector, and the structured embedded coding vectors of the initial proportional gain coefficient, the initial integral gain coefficient and the initial differential gain coefficient are used as key vectors and input into the feature query network to achieve intelligent adaptive adjustment of PID gain parameters. Through the feature query network, the complex relationship between the current etch rate and the existing PID gain parameters is intelligently analyzed, and the PID controller's output should be predicted to achieve optimal etching results under the current operating conditions. Specifically, the current etch rate structured embedded coding vector, used as a query, represents the system's current specific etching state and the need for a control strategy. The structured embedded coding vectors of the three initial PID gain coefficients, used as keys, represent the potential behavior patterns of the controller under different gain combinations. By deeply exploring the intrinsic semantic associations between these key vectors (i.e., different gain combinations), a dynamically optimized feature space is constructed.

[0054] More specifically, in an embodiment of the present application, the current etching rate structured embedded coding vector is used as a query vector, and the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector are used as key vectors, which are input into a feature query network to obtain a feedback adjustment pre-response coding vector, including: calculating the PID control gain correlation coefficient between any two vectors of the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector to obtain a PID control gain feature intra-correlation optimization embedding matrix; mapping the current etching rate structured embedded coding vector to the feature space of the PID control gain feature intra-correlation optimization embedding matrix to obtain an aligned current etching rate structured embedded coding vector; based on the PID control gain feature intra-correlation optimization embedding matrix, analyzing the matching degree of the aligned current etching rate structured embedded coding vector with the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector, and returning the vector corresponding to the largest one as the feedback adjustment pre-response coding vector.

[0055] Specifically, the PID control gain correlation coefficient between any two vectors among the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector, and the initial differential gain coefficient structured embedded coding vector is calculated to obtain a PID control gain feature intra-correlation optimization embedding matrix, which is expressed as:

[0056] ;

[0057] in, and The first of the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector is respectively and vectors, is the semantic association trainable weight matrix, for function, for function, for length, for and The PID control gain correlation coefficient between The embedding matrix is ​​endogenously optimized for PID control gain features.

[0058] It should be understood that to achieve intelligent optimization of PID gain parameters, simply inputting them as independent key vectors into the feature query network is not sufficient; the mutual influences between these gain parameters must be deeply explored. Therefore, the PID control gain correlation coefficient between any two vectors in the initial proportional gain coefficient structured embedding encoding vector, the initial integral gain coefficient structured embedding encoding vector, and the initial differential gain coefficient structured embedding encoding vector is calculated to obtain the PID control gain feature intra-correlation optimization embedding matrix. This intrinsic correlation is a key factor affecting the performance of the PID controller under different etching conditions. Traditional optimization methods often ignore this deep correlation, resulting in poor optimization results and difficulty in coping with the complexity and dynamics of the etching process. Therefore, by constructing a semantic map or relational network that captures the complex interactions between PID gain parameters, that is, calculating the correlation coefficient between any two gain encoding vectors, it is possible to quantify their synergistic or antagonistic relationship in the control strategy. For example, in certain etching stages, increasing the proportional gain may require a corresponding adjustment of the integral gain to avoid oscillation. The matrix composed of these correlation coefficients, namely the correlation optimization embedding matrix within the PID control gain features, is designed to capture the inherent semantic structure and contextual dependencies of the key vector set (i.e., the PID gain parameter set). It is like building a dynamic map depicting the internal relationship of the gain parameter space, allowing each gain parameter to examine each other and quantify each other's semantic influence.

[0059] Specifically, the current etching rate structured embedded coding vector is mapped to the feature space of the PID control gain feature correlation optimization embedding matrix to obtain the aligned current etching rate structured embedded coding vector, which is expressed as follows:

[0060] ;

[0061] ;

[0062] in, The embedding matrix for the endogenous optimization of PID control gain features is: represents transpose, is matrix multiplication, is the matrix binorm, is the logarithmic function value with the natural constant e as the base, To construct a diagonal matrix, is the PID control gain characteristic dynamic semantic matrix, Structured embedded coding vector for the current etching rate, Structured embedding code vector for alignment with current etch rate.

[0063] It should be understood that although both the current etch rate and PID gain parameters are structured embedding encoded, they may initially be mapped into different, independent vector spaces. Direct comparison may result in semantic gaps or dimensionality mismatches, leading to inaccurate matching results. Therefore, the current etch rate structured embedding vector is mapped into the feature space defined by the PID control gain feature-internal correlation optimized embedding matrix to obtain the aligned current etch rate structured embedding vector. This aims to eliminate this potential representation bias and ensure that the query vector and the optimized key vector are expressed on the same semantic dimension. The PID control gain feature-internal correlation optimized embedding matrix not only captures the intrinsic correlations between the PID gain parameters but also defines an optimized, context-aware feature space. This space is constructed based on the characteristics of the PID gain parameters and their role in the control system. Therefore, mapping the current etch rate into this space aligns and fuses the semantic information of the etch rate with that of the PID gain parameters. This enables the system to understand how different PID gain combinations affect the etching process at the current etch rate, laying a solid foundation for subsequent accurate matching.

[0064] More specifically, in an embodiment of the present application, based on the correlation optimization embedding matrix within the PID control gain feature, the matching degree between the aligned current etching rate structured embedded coding vector and the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector is analyzed, and the vector corresponding to the largest one is returned as the feedback adjustment pre-response coding vector, including: based on the correlation optimization embedding matrix within the PID control gain feature, the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector are feature-adaptively fine-tuned to obtain the optimized initial proportional gain coefficient structured embedded coding vector, the optimized initial integral gain coefficient structured embedded coding vector and the optimized initial differential gain coefficient structured embedded coding vector; calculating the matching degree between the aligned current etching rate structured embedded coding vector and the optimized initial proportional gain coefficient structured embedded coding vector, the optimized initial integral gain coefficient structured embedded coding vector and the optimized initial differential gain coefficient structured embedded coding vector; and taking the vector corresponding to the largest matching degree as the feedback adjustment pre-response coding vector.

[0065] Specifically, based on the PID control gain feature internal correlation optimization embedding matrix, the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector are feature-adaptively fine-tuned to obtain an optimized initial proportional gain coefficient structured embedded coding vector, an optimized initial integral gain coefficient structured embedded coding vector and an optimized initial differential gain coefficient structured embedded coding vector, which are expressed as follows:

[0066] ;

[0067] in, is the PID control gain characteristic dynamic semantic matrix, for The corresponding optimization vector.

[0068] It should be understood that while the initial gain parameters provide a starting point, they are not optimal under all etching conditions. Slight changes in the etching environment, differences in material properties, and nonlinear effects can all lead to performance degradation with fixed gain parameters, which is the underlying reason why further improvements in etching precision are difficult. In other words, during the plasma etching process of an on-chip all-optical switch, the gain parameters of the PID controller are not static; they require fine-tuning based on the real-time dynamics and complexity of the etching process. Therefore, based on an embedding matrix optimized by the intra-correlation optimization of the PID control gain features, the structured embedding encoding vectors of the initial proportional gain coefficient, initial integral gain coefficient, and initial differential gain coefficient are feature-adaptively fine-tuned to obtain optimized gain encoding vectors. Each gain encoding vector is refined and enhanced by leveraging the intrinsic correlation and contextual dependencies between the gain parameters captured by the intra-correlation optimization embedding matrix of the PID control gain features. This means that the adjustment of each gain vector is not performed in isolation, but rather fully incorporates its semantic neighborhood information within the context of the current gain set. For example, if adjusting the proportional gain significantly affects the stability of the integral gain, the system will take this correlation into account when fine-tuning the proportional gain, making the optimized gain vector representation more refined, robust, and context-aware. This adaptive fine-tuning ensures that the optimized gain parameter combination achieves optimal performance under the current etching conditions, effectively suppressing fluctuations and interference in the etching process.

[0069] Specifically, the matching degree between the aligned current etching rate structured embedded coding vector and the optimized initial proportional gain coefficient structured embedded coding vector, the optimized initial integral gain coefficient structured embedded coding vector, and the optimized initial differential gain coefficient structured embedded coding vector is calculated, and is expressed as follows:

[0070] ;

[0071] in, To align the current etching rate structured embedded coding vector, To calculate the matching degree between two vectors, is the one-norm of the vector, represents the trace operation of the matrix, are trainable weights.

[0072] It should be understood that although the query vector and key vector have been transformed and aligned into the same semantic space through complex embedded coding and endogenous dynamic optimization, the final decision still requires a quantitative metric to measure the similarity or correlation between them to select the optimal control strategy. In the plasma etching process of an on-chip all-optical switch, to ultimately determine the PID gain parameter combination that best suits the current etching conditions, it is necessary to accurately evaluate the degree of fit between the current etching rate and various optimized PID gain combinations. Therefore, the matching degree between the structured embedded coding vector of the current etching rate and the structured embedded coding vectors of the optimized initial proportional gain coefficient, optimized initial integral gain coefficient, and optimized initial differential gain coefficient is calculated. This accurately quantifies the deep semantic fit between the query intent (i.e., the control requirement represented by the current etching rate) and each potential candidate answer (i.e., the different optimized PID gain combinations). By calculating the matching degree, the system can determine which optimized PID gain parameter combination will produce the best etching effect at the current etching rate. For example, if the current etching rate deviates significantly from the target rate, the system will tend to select gain combinations that can provide stronger correction capabilities; if the etching process is close to stability, it may select gain combinations that can maintain stability and avoid overshoot.

[0073] Specifically, the vector corresponding to the one with the largest matching degree is used as the feedback adjustment pre-response encoding vector, which is expressed as follows:

[0074] ;

[0075] Among them, the above formula means returning the maximum matching degree corresponding to As , n represents the number of Encode the vector for the feed-back conditioning forward response.

[0076] It should be understood that among multiple potential optimized PID gain parameter combinations, the system must select the one that best meets control requirements under the current etching conditions. A matching calculation quantifies the degree of compatibility between the current etching rate and each optimized gain combination. During the plasma etching process of the on-chip all-optical switch, a complex series of intelligent analyses and matching calculations ultimately results in a clear control instruction or recommendation. Therefore, the vector corresponding to the highest matching degree is used as the pre-response encoding vector for feedback control. From multiple optimized PID gain parameter combinations, the one that best suits the current etching conditions is intelligently selected. This selected vector serves as the pre-response signal for feedback control of the PID controller. It is not a direct gain parameter value, but rather a high-dimensional encoding vector representing how the PID controller should adjust its output to achieve optimal control at the current etching rate. By selecting the vector with the highest matching degree, the system ensures that the selected control strategy best matches the current operating conditions, thereby maximizing control accuracy and response speed.

[0077] Preferably, in the calculation process of the PID control gain correlation coefficient between any two vectors among the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector, firstly and As the two ends of the path of the network topology, through the path coding item To characterize the path structure, and use the hyperbolic tangent function To capture complex structural patterns, and then divide by the spatial distance , thus retaining only its pure phase information.

[0078] Thus, in the calculation process of the correlation optimization embedding matrix within the PID control gain feature, Phase context dependency can be captured in an inherent phase mode through the aggregation and exchange of phase information. For example, the appearance of a wave peak often indicates the arrival of a subsequent zero-crossing point. This inherent rhythm is the phase context dependency. In order to ensure that the capture of this context dependency is still accurate and reliable under various complex field interferences, that is, to improve the versatility of phase context dependency under topological group relationships, that is, to improve the robustness of PID control gain against local topological relationship disturbances, the hyperbolic tangent function can be further calculated. The differential gradient of , that is:

[0079] ;

[0080] in, To calculate the differential gradient.

[0081] And it is weighted with a predetermined weighting coefficient and then input into the calculation of the PID control gain correlation coefficient, that is:

[0082] ;

[0083] in, is the predetermined weighting coefficient. In this way, the hyperbolic tangent function can be used The gradient saturation characteristic, that is, the gradient is close to zero when the input value is too large or too small, is used to suppress the deviation of the PID control gain topology dependence, and the calculation of the PID control gain correlation coefficient is further substituted into the topological structure of the dynamic correlation within the feature space of the PID control gain feature endogenous optimization embedding matrix.

[0084] At the same time, the differential gradient is weighted by the coefficient as the geometric phase information that characterizes the path topology, and after phase exchange, it is applied to The statistical characteristics of , the structural stability can be ensured by phase accumulation exchange, thereby improving the characterization ability of the spatial internal dynamic relationship of the PID control gain feature endogenous optimization embedding matrix.

[0085] Specifically, in step S355, the feed-back adjustment pre-response coded vector is feature-decoded to obtain a cumulative etching depth correction factor. It should be understood that controlling the etching process requires specific, actionable numerical values, such as the amount of fine-tuning for the cumulative etching depth. However, the feed-back adjustment pre-response coded vector itself is a high-dimensional, abstract representation that cannot be directly used to adjust the etching depth. Therefore, the feed-back adjustment pre-response coded vector is feature-decoded to obtain a cumulative etching depth correction factor. This decoding process bridges the gap between abstract intelligent decision-making and concrete physical control, enabling intelligent optimization to be truly implemented. This converts the feed-back adjustment pre-response coded vector into a correction factor with clear physical meaning that can be directly applied to the cumulative etching depth. This correction factor is used to fine-tune the cumulative etching depth, thereby indirectly influencing the PID controller's benchmark for finding the target rate, ultimately achieving more precise control of the etching rate. Through decoding, the system can convert the complex control strategy learned by the intelligent network into a simple and effective numerical value, ensuring that the etching process can accurately follow the preset rate profile and compensate for real-time deviations. More specifically, in a specific example of the present application, a commonly used decoding method is a fully connected neural network, which uses a feed-back regulated forward response encoding vector as input, and gradually maps high-dimensional abstract features to low-dimensional specific numerical values ​​through one or more fully connected layers to obtain an etching depth cumulative correction factor.

[0086] Specifically, in step S356 and step S357, the cumulative etching depth is corrected based on the etching depth cumulative correction factor to obtain a corrected cumulative etching depth, and a target rate that matches the corrected cumulative etching depth is searched from the rate profile recipe. It should be understood that the etching depth cumulative correction factor is the basis for fine-tuning the real-time cumulative etching depth, aiming to compensate for the deviations that may exist in traditional measurement and control, so that the control system can more accurately approach the ideal etching path. Although the cumulative etching depth can be monitored in real time, due to factors such as process fluctuations, equipment drift or model errors, this real-time monitoring value may not be the most ideal control benchmark. In order to ensure that the PID controller can find the target rate based on the most accurate depth information that best reflects the current optimal control strategy, the cumulative etching depth is corrected based on the etching depth cumulative correction factor to provide an intelligently optimized and more accurate cumulative etching depth value as the input for the PID controller to find the target rate. By combining the real-time monitored cumulative etch depth with an intelligently generated correction factor, the accumulated errors caused by various uncertainties can be effectively eliminated or reduced, allowing the PID controller to find a target rate from the rate profile recipe that better meets current actual needs and optimization goals. This correction mechanism is a key step in achieving high-precision closed-loop control of the etching process, ensuring that the control decision-making basis is intelligently corrected rather than relying solely on raw measurement data.

[0087] Specifically, in steps S360 and S370, the control output signal is passed through a conversion function to obtain a new power value. This new power value is then encapsulated into an actuator instruction recognizable by the ICP-RIE hardware, and this actuator instruction is sent to the hardware for execution via the driver layer. It should be understood that there is a physical gap between the output of the PID controller and the actual hardware actuator, requiring a bridge to convert the abstract control signal into a specific physical operation instruction. Specifically, the control output signal is a general control variable, such as voltage, current, or a dimensionless proportional value, and cannot directly drive the RF power supply in the ICP-RIE (Inductively Coupled Plasma Etching - Reactive Ion Etching) hardware. The ICP-RIE hardware requires a specific power value instruction that complies with its interface specification for operation. Therefore, the control output signal is passed through a conversion function to obtain a new power value, and this new power value is encapsulated into an actuator instruction recognizable by the ICP-RIE hardware. This actuator instruction is then sent to the hardware for execution via the driver layer. The abstract control signal generated by the PID controller is converted into an RF power value that the ICP-RIE hardware can directly understand and execute, ensuring that this power value is transmitted to the hardware in the correct format and through the correct channel. A conversion function maps the PID controller output to the actual operating range of RF power. For example, a control signal of 0 to 100 watts is converted into an RF power of 0 to 1000 watts. This conversion is necessary to account for the physical limitations and response characteristics of the hardware. Subsequently, this new power value is encapsulated into an actuator instruction that the ICP-RIE hardware can understand. This ensures that the instruction format, protocol, and timing meet the hardware requirements, avoiding instruction recognition failure or execution errors due to format mismatches. Finally, the instruction is sent to the hardware for execution through the driver layer. This ensures that the instruction is reliably and promptly transmitted to the ICP-RIE device, leveraging the stable and efficient communication interface provided by the underlying driver, thereby achieving real-time and precise control of the plasma etching process.

[0088] Specifically, the exposed wafer is immersed in a specific developer to produce the photoresist pattern. It should be understood that electron beam exposure alters the chemical properties of the photoresist (for example, increasing the solubility of exposed areas of positive-tone resist and decreasing the solubility of exposed areas of negative-tone resist), forming a latent image corresponding to the design pattern in the photoresist layer. This latent image requires chemical dissolution to be revealed, forming a photoresist mask with highly precise edges and a specific thickness. In other words, electron beam lithography forms latent, invisible photoresist patterns on the SOI wafer spun with photoresist. These patterns are the foundation of future optical waveguide structures, but at this point, they still exist in a chemically altered form within the photoresist. To transform these latent patterns into actual three-dimensional structures, the exposed wafer is immersed in a specific developer to produce the photoresist pattern. By selectively removing unexposed or exposed portions of the photoresist layer, a photoresist pattern that is precisely consistent with the design drawing is formed on the wafer surface. This photoresist pattern will serve as a mask for subsequent plasma etching. Its precision and quality directly determine the size, morphology, and performance of the final optical waveguide structure. By using a specific developer, high selectivity and high contrast can be ensured during the development process. This means that only the photoresist in the target areas is dissolved, while other areas are preserved, resulting in clear, sharp photoresist pattern edges. The developer's composition, temperature, and development time all require precise control to avoid over-development or under-development, both of which can lead to pattern distortion or defects.

[0089] Specifically, the developer's "specificity" is reflected in its chemical formula, which allows it to react selectively with exposed or unexposed photoresist. For example, for positive photoresist, the developer dissolves the areas exposed by the electron beam, leaving the unexposed photoresist as the pattern; for negative photoresist, the developer dissolves the unexposed areas, leaving the exposed and cured photoresist as the pattern. After the wafer is immersed in the developer, the developer molecules diffuse into the photoresist layer, reacting with the chemically changed areas, dissolving them and detaching them from the wafer surface. After development is completed, rinsing and drying are usually required to remove residual developer and impurities to ensure the cleanliness and integrity of the photoresist pattern.

[0090] Specifically, in step S400, the photoresist pattern is plasma etched to obtain an optical waveguide structure. It should be understood that during the fabrication of the on-chip all-optical switch, a precise photoresist pattern is formed on the surface of the SOI wafer through electron beam lithography and development steps. This photoresist pattern acts as a mask, but it is not the final optical waveguide structure itself. The actual waveguide must be formed from the top silicon material. In other words, the photoresist pattern is merely a temporary mask; it needs to transfer the pattern information to the underlying top silicon material to form a silicon structure with a specific depth and sidewall morphology. Only then can these silicon structures serve as waveguides for optical signal transmission. Therefore, the photoresist pattern is plasma etched to obtain the optical waveguide structure. This utilizes the chemical and physical effects of the plasma to selectively remove the top silicon material in areas not covered by the photoresist pattern, thereby precisely forming the desired optical waveguide structure on the SOI wafer. Plasma etching technology is highly directional (anisotropic), capable of achieving vertical or near-vertical sidewalls, which are crucial for building high-performance optical waveguides. Vertical sidewalls effectively confine light transmission within the waveguide, reducing losses. Plasma etching also offers high selectivity, meaning that while etching the silicon material, it minimizes damage to the photoresist mask and the underlying buried oxide layer (BOX layer), ensuring the accuracy of the etching process and the integrity of the structure.

[0091] Specifically, in step S500, a layer of cladding material is deposited on the optical waveguide structure to form an upper cladding layer that completely covers the optical waveguide structure, thereby obtaining an on-chip all-optical switch chip. It should be understood that the proper operation of an optical waveguide requires a stable optical environment, namely, a high-refractive-index core layer (silicon waveguide) completely encased by a low-refractive-index cladding material. This core-cladding structure is the fundamental principle of optical waveguides, utilizing total internal reflection to confine light within the core layer. During the fabrication of the on-chip all-optical switch, exposed optical waveguide structures are formed on the SOI wafer through plasma etching. These waveguides are composed of high-refractive-index silicon material, but the refractive index of the surrounding environment (typically air) is lower. While this refractive index difference enables optical waveguides, exposed waveguides are susceptible to environmental contamination and mechanical damage, and their optical performance (such as loss and mode confinement) may not be optimal. To protect the waveguide and optimize its optical performance, a cladding material is deposited on the optical waveguide structure to form an upper cladding layer that completely covers the structure, ultimately creating an on-chip all-optical switch. By depositing a cladding material with an appropriate refractive index, the waveguide's mode confinement capability can be precisely controlled, reducing scattering and bending losses during light transmission. A suitable cladding material provides a more uniform refractive index environment, thereby improving optical signal transmission efficiency and overall device performance.

[0092] Specifically, in step S600, the on-chip all-optical switch chips are diced and packaged to form an array of on-chip all-optical switches. It should be understood that semiconductor manufacturing typically utilizes wafer-level batch production to improve efficiency and reduce costs. After all process steps are completed on the wafer, the individual chips must be separated from the wafer and properly protected and connected before they can become a usable product. The on-chip all-optical switch fabrication process undergoes a series of complex micro-nanofabrication steps, ultimately resulting in multiple independent on-chip all-optical switch chips formed on a single SOI wafer. However, these chips are still integrated on the same wafer and cannot be directly tested, integrated, or sold as independent devices. Therefore, the on-chip all-optical switch chips are diced and packaged to form an array of on-chip all-optical switches. This process separates the individual on-chip all-optical switch chips on the wafer into independent units, and provides these units with the necessary physical protection, electrical connections, and optical interfaces to facilitate testing and integration into larger optical communication systems, ultimately resulting in a commercially available product array. The purpose of dicing is to precisely separate the neatly arranged chips on the wafer, while the purpose of packaging is to provide a sturdy shell for the chip to protect it from environmental influences and provide an interface for connecting to external circuits and optical fibers.

[0093] In summary, the preparation method of the on-chip all-optical switch according to the embodiment of the present application is explained. On the basis of conventional steps such as providing an SOI wafer and performing electron beam lithography to form a photoresist pattern, the core is to transform the plasma etching link. First, the current etching rate and cumulative depth are obtained by real-time monitoring of the laser interference signal, and real-time process state feedback is established. Subsequently, the real-time state is fed into a PID control loop based on a rate profile recipe. By comparing with the target rate, the etching power is dynamically adjusted. This is the first layer of protection to solve the problem of inaccurate control. In order to eradicate the deep uncertainty caused by process fluctuations and measurement errors, dynamic feature query analysis is further introduced to intelligently analyze the complex intrinsic relationship between the current etching rate and the PID gain parameter before PID control, and generate a feedback adjustment pre-response encoding vector, and then decode the correction factor for the cumulative etching depth. This pre-emptive intelligent correction ensures that the PID controller always makes decisions based on the most accurate state information and the most optimized target, thereby achieving unprecedented control accuracy. Ultimately, the ideal optical waveguide structure is obtained through this high-precision etching, and the subsequent cladding deposition and chip cutting and packaging are completed, thereby systematically solving the problems of poor device performance and low yield caused by insufficient etching accuracy.

[0094] Furthermore, an on-chip all-optical switch is provided, and the on-chip all-optical switch is manufactured by the above-mentioned method for manufacturing an on-chip all-optical switch.

[0095] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for preparing an on-chip all-optical switch, characterized in that: include: Providing an SOI wafer, the SOI wafer comprising a silicon substrate, a buried oxide layer located above the silicon substrate, and a top silicon layer located above the buried oxide layer; Chemically cleaning the SOI wafer to obtain a chemically cleaned SOI wafer; Performing electron beam lithography on the chemically cleaned SOI wafer to form a photoresist pattern on the chemically cleaned SOI wafer, comprising: performing a photoresist spin coating process on the chemically cleaned SOI wafer, then performing a pre-baking process and an electron beam exposure process on the photoresist-spin-coated wafer, and immersing the exposed wafer in a specific developer to obtain the photoresist pattern; performing plasma etching on the photoresist pattern to obtain an optical waveguide structure; Depositing a layer of cladding material on the optical waveguide structure to form an upper cladding layer that completely covers the optical waveguide structure to obtain an on-chip all-optical switch chip; Cutting and packaging the on-chip all-optical switch chip to obtain an on-chip all-optical switch array; Among them, the wafers that have been spin-coated with photoresist are pre-baked and subjected to electron beam exposure processing, including: extracting the current process status from the laser interference signal, and performing PID control based on the current process status and rate profile recipe to output actuator instructions, and sending them to the hardware for execution; The method comprises extracting the current process state from the laser interference signal, performing PID control based on the current process state and the rate profile recipe to output an actuator instruction, and sending the actuator instruction to the hardware for execution, including: extracting the rate profile recipe and initial process parameters matching the task request from the recipe database in response to the task request, wherein the initial process parameters include basic gas flow rate, power and gain parameters of the PID controller; sending the initial process parameters to the ICP-RIE hardware through the driver layer; acquiring a real-time data stream through a high-frequency data acquisition module; stripping the laser interference signal from the real-time data stream, and calculating the current etching rate and cumulative etching depth based on the laser interference signal to obtain the current process state; performing PID control based on the current process state and the rate profile recipe to obtain a control output signal; passing the control output signal through a conversion function to obtain a new power value; encapsulating the new power value into an actuator instruction recognizable by the ICP-RIE hardware, and sending the actuator instruction to the hardware for execution through the driver layer; Among them, the laser interference signal is stripped from the real-time data stream, and the current etching rate and cumulative etching depth are calculated based on the laser interference signal to obtain the current process state, including: obtaining key parameters, the key parameters being the actual etching depth corresponding to each interference cycle; counting the cycles of the laser interference signal to obtain the total number of cycles and the fraction of the current unfinished cycle; multiplying the sum of the total number of cycles and the fraction of the current unfinished cycle by the key parameter to obtain the cumulative etching depth; performing fast Fourier transform on the laser interference signal to obtain the peak frequency; multiplying the peak frequency by the key parameter to obtain the current etching rate; and assembling the cumulative etching depth and the current etching rate into the current process state.

2. The method for preparing an on-chip all-optical switch according to claim 1, wherein: After the chemically cleaned SOI wafer is subjected to a photoresist spin coating process, the wafer on which the photoresist has been spin-coated is subjected to a pre-baking process and an electron beam exposure process, and the exposed wafer is immersed in a specific developer to obtain the photoresist pattern, including: Evenly spin-coating a layer of electron beam photoresist on the surface of the SOI wafer after chemical cleaning to obtain a wafer with spin-coated photoresist; After pre-baking the wafer on which the photoresist has been spin-coated, the wafer is sent to an electron beam lithography device for electron beam exposure to obtain an exposed wafer; The exposed wafer is immersed in a specific developer to obtain the photoresist pattern.

3. The method for preparing an on-chip all-optical switch according to claim 2, wherein: Performing PID control based on the current process state and the rate profile recipe to obtain a control output signal includes: Based on the cumulative etching depth in the current process state, searching for a target rate matching the rate profile recipe; calculating a difference between the target rate and a current etching rate in the current process state to obtain a rate error; The velocity error is input into a PID controller to obtain the control output signal.

4. The method for preparing an on-chip all-optical switch according to claim 3, wherein: Based on the cumulative etching depth in the current process state, searching for a target rate matching the rate profile recipe from the rate profile recipe, comprising: extracting a current etch rate from the current process state; Extracting an initial proportional gain coefficient, an initial integral gain coefficient, and an initial differential gain coefficient from the PID controller; Performing structured embedded coding on the current etching rate, the initial proportional gain coefficient, the initial integral gain coefficient, and the initial differential gain coefficient to obtain a current etching rate structured embedded coding vector, an initial proportional gain coefficient structured embedded coding vector, an initial integral gain coefficient structured embedded coding vector, and an initial differential gain coefficient structured embedded coding vector; The current etching rate structured embedded coding vector is used as a query vector, and the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector are used as key vectors, and are input into a feature query network to obtain a feedback adjustment pre-response coding vector; Performing feature decoding on the feed-back adjustment pre-response coding vector to obtain an etching depth accumulation correction factor; Correcting the cumulative etching depth based on the etching depth cumulative correction factor to obtain a corrected cumulative etching depth; A target rate that matches the corrected cumulative etch depth is found from the rate profile recipe.

5. The method for preparing an on-chip all-optical switch according to claim 4, wherein: The current etching rate structured embedded coding vector is used as a query vector, and the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector, and the initial differential gain coefficient structured embedded coding vector are used as key vectors, which are input into the feature query network to obtain the feedback adjustment pre-response coding vector, including: Calculating a PID control gain correlation coefficient between any two vectors of the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector, and the initial differential gain coefficient structured embedded coding vector to obtain a PID control gain feature intra-correlation optimization embedding matrix; Mapping the current etching rate structured embedded coding vector to the feature space of the correlation optimization embedding matrix within the PID control gain feature to obtain an aligned current etching rate structured embedded coding vector; Based on the correlation optimization embedding matrix within the PID control gain feature, the matching degree of the aligned current etching rate structured embedded coding vector and the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector and the initial differential gain coefficient structured embedded coding vector is analyzed, and the vector corresponding to the largest one is returned as the feedback adjustment pre-response coding vector.

6. The method for preparing an on-chip all-optical switch according to claim 5, wherein: Based on the PID control gain feature internal correlation optimization embedding matrix, analyzing the matching degree of the aligned current etching rate structured embedded coding vector and the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector, and the initial differential gain coefficient structured embedded coding vector, and returning the vector corresponding to the largest one as the feedback adjustment pre-response coding vector, including: Based on the PID control gain feature internal correlation optimization embedding matrix, the initial proportional gain coefficient structured embedded coding vector, the initial integral gain coefficient structured embedded coding vector, and the initial differential gain coefficient structured embedded coding vector are feature-adaptively fine-tuned to obtain an optimized initial proportional gain coefficient structured embedded coding vector, an optimized initial integral gain coefficient structured embedded coding vector, and an optimized initial differential gain coefficient structured embedded coding vector; Calculating the matching degree between the aligned current etching rate structured embedded coding vector and the optimized initial proportional gain coefficient structured embedded coding vector, the optimized initial integral gain coefficient structured embedded coding vector and the optimized initial differential gain coefficient structured embedded coding vector respectively; The vector corresponding to the one with the largest matching degree is used as the feed-back adjustment pre-response coding vector.

7. An on-chip all-optical switch, characterized in that: The on-chip all-optical switch is manufactured by the on-chip all-optical switch manufacturing method according to any one of claims 1-6.

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