Processor precision test method and device, equipment, storage medium and program product

Abstract

The invention relates to a processor precision test method and device, equipment, a storage medium and a program product. The method comprises the following steps: in an environment initialization stage, generating a test case according to test parameters; in a test execution stage, respectively inputting the test case into a floating point instruction calculation function and a floating point operation simulation function of a to-be-tested processor for operation to obtain a first operation result of the floating point instruction calculation function and a second operation result of the floating point operation simulation function; wherein the floating point instruction calculation function of the to-be-tested processor is constructed by adopting a C-embedded assembly mode, and the floating point operation simulation function is obtained by fusing floating point operation functions of a plurality of to-be-tested platforms; and comparing the first operation result with the second operation result to obtain a precision test result of the to-be-tested processor. The method can be used for testing the FPU precision of the domestic processor.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a processor accuracy testing method, apparatus, device, storage medium, and program product. Background Art

[0002] With the rapid development of artificial intelligence (AI), particularly breakthroughs in deep learning and machine learning, modern processors face unprecedented challenges in terms of computing power, energy efficiency, and algorithm accuracy. This trend is directly driving the increasing demand for processor floating-point accuracy. To meet the complex demands of AI algorithms, domestic processor architectures are constantly evolving, with the emergence of a wider range of floating-point data formats, such as BF16 (Brain Floating Point 16-bit, half-precision) and FP8 (8-bit Floating Point, low-precision). This places higher demands on the comprehensiveness and compatibility of test systems. During performance optimization, hardware designers often employ various techniques to increase computational speed, which can compromise computational accuracy in extreme cases. Therefore, more detailed verification of the processor's FPU (Floating Point Unit) performance under various edge conditions is necessary. Furthermore, the demands for floating-point computation are becoming increasingly diverse and complex. This means that test systems must be able to simulate these complex computational scenarios and accurately identify potential abnormal computational issues. This process requires not only covering a wider range of test cases but also ensuring the effectiveness and efficiency of test methods.

[0003] To test the design correctness and calculation accuracy of a processor's FPU, targeted floating-point instruction test cases are typically used. Typically, each instruction corresponds to a specific test case, resulting in numerous test procedures and a cumbersome testing process. Existing floating-point arithmetic test suites can test the floating-point data formats specified by the IEEE (Institute of Electrical and Electronics Engineers) standard. However, the floating-point data formats of domestic processors include non-IEEE floating-point data formats, making them ineffective for directly testing the accuracy of domestic processor FPUs. Summary of the Invention

[0004] Based on this, it is necessary to provide a processor accuracy testing method, device, equipment, storage medium and program product that can be used for domestic processor FPU accuracy testing to address the above technical problems.

[0005] In a first aspect, the present application provides a processor accuracy testing method, comprising:

[0006] During the environment initialization phase, test cases are generated based on test parameters;

[0007] During the test execution phase, the test case is input into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested for operation, thereby obtaining a first operation result of the floating-point instruction calculation function and a second operation result of the floating-point operation simulation function; wherein the floating-point instruction calculation function of the processor to be tested is constructed in C embedded assembly, and the floating-point operation simulation function is obtained by integrating the floating-point operation functions of multiple platforms to be tested;

[0008] The first operation result and the second operation result are compared to obtain the accuracy test result of the processor to be tested.

[0009] In one embodiment, generating a test case according to the test parameters includes:

[0010] Select the platform to be tested according to the test parameters and initialize the environment;

[0011] Determine the test target according to the test parameters. The test target includes the floating-point operation type and the floating-point data format. The floating-point data format includes a high-precision data format and a low-precision data format.

[0012] Setting state control parameters of the floating-point instruction calculation function and floating-point operation simulation function of the processor to be tested according to the test parameters;

[0013] Generate test cases based on test objectives.

[0014] In one embodiment, generating a test case according to a test objective includes:

[0015] Set the test case space required for the test target based on the floating-point operation type and floating-point data format;

[0016] Corresponding test cases are generated in the test case space according to the floating-point data format. The test cases include random floating-point numbers, boundary floating-point numbers, special floating-point numbers and combined floating-point numbers.

[0017] In one embodiment, the test case is input into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested for operation, and the first operation result of the floating-point instruction calculation function and the second operation result of the floating-point operation simulation function are obtained, which include:

[0018] Input the test cases into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested respectively;

[0019] The test cases are operated respectively by the state control parameters of the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested, and the first operation result of the floating-point instruction calculation function and the second operation result of the floating-point operation simulation function are output.

[0020] In one embodiment, comparing the first operation result and the second operation result to obtain the accuracy test result of the processor to be tested includes:

[0021] Comparing a first operation result with a second operation result, the first operation result including a first floating-point operation result and a first abnormality triggering result, and the second operation result including a second floating-point operation result and a second abnormality triggering result;

[0022] When the first operation result and the second operation result are consistent, it is determined that the test case has passed the test;

[0023] When the first operation result is inconsistent with the second operation result, the test case is marked as an error and the error information is recorded.

[0024] In one embodiment, the method further includes:

[0025] Classify error messages according to error types and count the distribution of error messages in floating-point operation types or floating-point data formats;

[0026] Count the number of test cases that pass the test and determine the test pass rate based on the number of test cases that pass the test;

[0027] Count the floating-point arithmetic functions covered by the test cases, and determine the test coverage rate based on the floating-point arithmetic functions covered by the test cases.

[0028] In a second aspect, the present application further provides a processor accuracy testing device, comprising:

[0029] The initialization module is used to generate test cases according to test parameters during the environment initialization phase;

[0030] The test execution module is used to input the test case into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested for operation in the test execution phase, and obtain the first operation result of the floating-point instruction calculation function and the second operation result of the floating-point operation simulation function; wherein, the floating-point instruction calculation function of the processor to be tested is constructed in C embedded assembly, and the floating-point simulation instruction calculation function is obtained by integrating the floating-point operation functions of multiple platforms to be tested; the first operation result and the second operation result are compared to obtain the accuracy test result of the processor to be tested.

[0031] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0032] During the environment initialization phase, test cases are generated based on test parameters;

[0033] During the test execution phase, the test case is input into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested for operation, thereby obtaining a first operation result of the floating-point instruction calculation function and a second operation result of the floating-point operation simulation function; wherein the floating-point instruction calculation function of the processor to be tested is constructed in C embedded assembly, and the floating-point operation simulation function is obtained by integrating the floating-point operation functions of multiple platforms to be tested;

[0034] The first operation result and the second operation result are compared to obtain the accuracy test result of the processor to be tested.

[0035] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the following steps:

[0036] During the environment initialization phase, test cases are generated based on test parameters;

[0037] During the test execution phase, the test case is input into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested for operation, thereby obtaining a first operation result of the floating-point instruction calculation function and a second operation result of the floating-point operation simulation function; wherein the floating-point instruction calculation function of the processor to be tested is constructed in C embedded assembly, and the floating-point operation simulation function is obtained by integrating the floating-point operation functions of multiple platforms to be tested;

[0038] The first operation result and the second operation result are compared to obtain the accuracy test result of the processor to be tested.

[0039] In a fifth aspect, the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the following steps:

[0040] During the environment initialization phase, test cases are generated based on test parameters;

[0041] During the test execution phase, the test case is input into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested for operation, thereby obtaining a first operation result of the floating-point instruction calculation function and a second operation result of the floating-point operation simulation function; wherein the floating-point instruction calculation function of the processor to be tested is constructed in C embedded assembly, and the floating-point operation simulation function is obtained by integrating the floating-point operation functions of multiple platforms to be tested;

[0042] The first operation result and the second operation result are compared to obtain the accuracy test result of the processor to be tested.

[0043] The aforementioned processor accuracy testing method, apparatus, device, storage medium, and program product construct the floating-point instruction calculation function of the processor FPU under test through C embedded assembly, integrating the floating-point instruction calculation units of multiple domestic processors. This not only addresses the problem that traditional floating-point arithmetic test suites cannot effectively test domestic processors, but also improves the comprehensiveness of the calculation accuracy verification of domestic processor FPUs. This high degree of integration of calculation accuracy verification for multiple processors makes FPU testing simpler and faster, simplifies the complexity of manual testing, and greatly improves testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 1 is a flow chart of a method for testing processor accuracy in one embodiment;

[0046] Figure 2 A schematic diagram of a process for generating test cases based on test parameters in one embodiment;

[0047] Figure 3 A schematic diagram of a flow chart of comparing a first operation result and a second operation result to obtain an accuracy test result of a processor to be tested in one embodiment;

[0048] Figure 4 is a structural block diagram of a processor accuracy testing device in one embodiment;

[0049] Figure 5 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0051] In order to test the design correctness and calculation accuracy of the processor's FPU, targeted floating-point instruction test cases are usually used. Generally, one instruction corresponds to one test case, and the test procedures are numerous and the test process is cumbersome. The existing Berkeleytestfloat (can be referred to as testfloat) floating-point operation test suite relies on Berkeley softfloat and can only test the floating-point data format specified by the IEEE standard. It has the following shortcomings for floating-point testing of domestic processors: First, Berkeley testfloat is mainly used to verify the correctness of floating-point operations of common ISA (Instruction Set Architecture) such as IA-32 (Intel Architecture 32-bit), AMD64 (Advanced Micro Devices 64-bit), PowerPC (Performance Optimization With Enhanced RISC–Performance Computing, a central processing unit with a reduced instruction set architecture), and SPARC (Scalable Processor ARChitecture). However, the ISA of domestic processors is different from the ISA verified in Berkeley testfloat, and therefore cannot be effectively used directly for precision testing of the FPU of domestic processors. Second, Berkeley testfloat primarily addresses the high-precision requirements of scientific and high-performance computing, including single-precision (32-bit), double-precision (64-bit), and high-precision (128-bit) floating-point formats. It lacks lower-precision formats such as half-precision (BF16) and lower-precision (FP8). Third, the floating-point units of domestic processors differ significantly from the existing Berkeley softfloat floating-point library (e.g., differences in rounding mode handling and exception handling), making the Berkeley softfloat floating-point library unsuitable for direct testing and verification of floating-point units in domestic processors.

[0052] Therefore, to address the above problems, a processor accuracy testing method based on a test suite is proposed.

[0053] In one embodiment, Figure 1As shown, a processor accuracy test method is provided. This embodiment uses the method applied to a terminal as an example for illustration. It is understandable that the method can also be applied to a server, or to a system including a terminal and a server, and implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0054] Step 102: During the environment initialization phase, test cases are generated according to test parameters.

[0055] Test parameters refer to variables used to control test behavior or input during the test process, and test cases refer to descriptive documents or code units used to perform precision testing on the processor FPU.

[0056] Optionally, the accuracy test of the processor FPU is divided into two stages: environment initialization and test execution. The environment initialization stage generates test cases after performing necessary test parameter analysis, and the test execution stage is the core of FPU calculation accuracy verification.

[0057] During the environment initialization phase, the test parameters entered by the user are parsed and processed. Specifically, the test parameters are divided into four categories: the platform to be tested and the environment configuration, floating-point operation type, floating-point data format, and state control parameters. Each parameter category is then configured. Test cases are then generated based on the configured test parameters.

[0058] Step 104: During the test execution phase, the test case is input into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested for operation, to obtain a first operation result of the floating-point instruction calculation function and a second operation result of the floating-point operation simulation function; wherein, the floating-point instruction calculation function of the processor to be tested is constructed in C embedded assembly, and the floating-point simulation instruction calculation function is obtained by integrating the floating-point operation functions of multiple platforms to be tested.

[0059] Optionally, during the test execution phase, the floating-point instruction calculation function for the FPU of the processor under test is written in C embedded assembly (embedded assembly in the C language). This allows the floating-point instruction calculation function to implement floating-point instruction calculations for various domestic processors, enabling verification of the FPU hardware functions of various domestic processors. This not only addresses the issue of testfloat being unable to effectively test domestic processors, but also ensures comprehensive floating-point unit verification, effectively testing the FPU calculation accuracy of various domestic processors. The floating-point instruction calculation function is the embedded assembly function for domestic multi-core processors in the subj-C subdirectory of the testfloat floating-point arithmetic test suite, capable of directly testing the FPU hardware functions of various domestic processors. subj-C is a directory for testing floating-point arithmetic modules implemented in C as the test subject. Using the test case generated during the environment initialization phase as input, the floating-point instruction calculation function for the corresponding FPU of the processor under test is called according to the test parameters set during the environment initialization phase. The test case is calculated to obtain the first calculation result of the FPU of the processor under test.

[0060] During the test execution phase, the floating-point arithmetic functions required by multiple platforms under test are integrated, and corresponding C functions simulating these functions are written in strict accordance with the floating-point instruction requirements of each platform. This is known as the floating-point arithmetic simulation function. Using the same test case as the floating-point instruction calculation function of the processor under test's FPU as input, the floating-point arithmetic simulation function is called to perform calculations on the test case, generating a second result. The floating-point arithmetic simulation function is a softfloat library function written based on the characteristics of floating-point instructions from various domestic multi-core processors.

[0061] Step 106 : Compare the first operation result and the second operation result to obtain an accuracy test result of the processor to be tested.

[0062] During the test execution phase, the first operation result calculated by the FPU of the processor under test is compared with the second operation result calculated by the floating-point operation simulation function. If the first operation result and the second operation result are inconsistent, the test case is marked as an error and fails the test. If the first operation result and the second operation result are consistent, the test case is determined to have passed the test. The result of whether the test case passes or fails the test is used as the accuracy test result of the FPU of the processor under test.

[0063] The aforementioned processor accuracy testing method constructs the floating-point instruction calculation function for the processor's FPU under test using C embedded assembly. This method integrates the floating-point instruction calculation units of various domestic processors. This not only addresses the inability of testfloat to effectively test domestic processors, but also improves the comprehensiveness of FPU accuracy verification for domestic processors. This highly integrated verification of FPU accuracy across multiple processors makes FPU testing simpler and faster, simplifies manual testing, and significantly improves testing efficiency.

[0064] In an exemplary embodiment, Figure 2 As shown, in step 102, generating a test case according to the test parameters includes:

[0065] Step 202: Select a platform to be tested according to the test parameters and initialize the environment.

[0066] Step 204 : determining a test target according to the test parameters. The test target includes a floating-point operation type and a floating-point data format. The floating-point data format includes a high-precision data format and a low-precision data format.

[0067] Step 206: setting state control parameters of the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested according to the test parameters.

[0068] Step 208: Generate test cases according to the test objectives.

[0069] Optionally, first, select the platform to be tested based on the test parameters and initialize the environment. Second, determine the test target, namely the floating-point operation type and floating-point data format. The floating-point operation type refers to the basic floating-point operation type, including basic operation types such as floating-point addition, subtraction, multiplication, and division. Floating-point data formats include high-precision data formats and low-precision data formats. High-precision data formats include double precision (64 bits) and single precision (32 bits). Low-precision data formats include half precision (including two 16-bit formats, HP 754 standard and non-standard BF16), low precision (8 bits), and other data formats. Then, set the state control parameters of the floating-point instruction calculation function and floating-point operation simulation function of the processor to be tested. The state control parameters are the hardware processing modes, such as rounding mode, exception handling mode, and denormalized number processing mode. By flexibly utilizing test parameters to set corresponding state control parameters, such as rounding mode, exception handling and other key parameters, testers can quickly configure the FPU's working state. This solves the problem that the FPU of domestic processors has significant differences with the existing Berkeley softfloat floating-point arithmetic function library (such as different rounding mode processing and exception handling), which makes the Berkeley softfloat floating-point arithmetic function library unable to be directly used in the test and verification of domestic processor FPUs.

[0070] Generate test cases based on floating-point operation types and floating-point data formats. During the test case generation process, write the corresponding test data based on the floating-point data format, and add floating-point instruction calculation functions and floating-point operation simulation functions corresponding to the floating-point data format. Since floating-point data formats include high-precision data formats and low-precision data formats, by adding multiple low-precision floating-point data operations, the floating-point operation data format can be expanded, so that all floating-point operations can support high-precision and low-precision data formats, meeting the coverage requirements of floating-point operation function verification of domestic processors.

[0071] In an optional method of the above embodiment, generating test cases according to the test target includes: setting the test case space required for the test target according to the floating-point operation type and the floating-point data format; generating corresponding test cases in the test case space according to the floating-point data format, and the test cases include random floating-point numbers, boundary floating-point numbers, special floating-point numbers and combined floating-point numbers.

[0072] Optionally, based on the floating-point operation type and floating-point data format in the test target, the test case space size is set to the number of operands required by the test target. Appropriate test cases are then generated based on the floating-point data format. These test cases can include random floating-point numbers covering a wide range of values, floating-point numbers approaching the limits of the floating-point format, special floating-point numbers, and complex test cases with different combinations of random floating-point numbers, boundary floating-point numbers, and special floating-point numbers. Finally, the generated test cases are saved for subsequent use in other tests. Operands refer to the data values or variables involved in the operation, the parts of an expression that are operated on. The test case space size refers to the number of possible operand combinations, or the number of possible cases generated when exhaustively enumerating all possible inputs. Random floating-point numbers can simulate a variety of common inputs in real-world applications, verifying the robustness and universality of the overall logic and computational correctness. Boundary floating-point numbers can test the system's correct handling of extreme values, such as overflow, underflow, and signed zero, for accurate calculation of special boundary points. Special floating-point numbers, including infinity, not-a-number (NaN), denormalized numbers, maximum finite number (MAX), minimum non-zero number (MIN), and zero, are used to verify that processors and algorithms adhere to the IEEE 754 standard and correctly handle invalid or abnormal input. Combined floating-point numbers are used to verify the correctness, fault tolerance, and consistency of calculations involving combinations of boundary values and special values, and to identify underlying logical errors.

[0073] In this embodiment, the test case space required for the test target is set based on the floating-point operation type and the floating-point data format, accurately determining the scope of test case generation. Based on the floating-point data format, various test cases, such as random floating-point numbers, boundary floating-point numbers, special floating-point numbers, and combined floating-point numbers, are generated in the test case space, comprehensively covering all potential issues with floating-point operations from multiple perspectives.

[0074] In an optional manner of the above embodiment, the test case is input into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested respectively for operation, and the first operation result of the floating-point instruction calculation function and the second operation result of the floating-point operation simulation function are obtained, including: inputting the test case into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested respectively; using the state control parameters of the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested, the test case is respectively operated, and the first operation result of the floating-point instruction calculation function and the second operation result of the floating-point operation simulation function are output.

[0075] During the environment initialization phase, the state control parameters for the floating-point instruction calculation function and the floating-point operation simulation function are set based on the test parameters. State control parameters refer to hardware processing modes, such as rounding mode, exception handling mode, and denormalized number processing mode. The floating-point instruction calculation function uses these state control parameters to calculate test cases, and similarly, the floating-point operation simulation function uses these state control parameters to calculate test cases.

[0076] In this embodiment, the floating-point instruction calculation function and the floating-point operation simulation function operate on the test case through the state control parameters, and can determine the reliability and consistency of the floating-point operation.

[0077] In an exemplary embodiment, Figure 3 As shown, step 106, comparing the first operation result and the second operation result to obtain the accuracy test result of the processor to be tested, includes steps 302 to 306.

[0078] Step 302 compares the first calculation result with the second calculation result. The first calculation result includes the first floating-point calculation result, the first exception trigger result, and the first execution state. The second calculation result includes the second floating-point calculation result, the second exception trigger result, and the second execution state. If the first and second calculation results match, step 304 is executed. If the first and second calculation results do not match, step 306 is executed.

[0079] Step 304: Determine whether the test case passes the test.

[0080] Step 306: Mark the test case as an error and record the error information.

[0081] Optionally, a comparison is performed between the results of the FPU calculation of the processor under test and the results of the floating-point operation simulation function calculation. The first operation result includes a first floating-point operation result, a first exception triggering result, and a first execution state; the second operation result includes a second floating-point operation result, a second exception triggering result, and a second execution state. First, the floating-point operation results are compared to verify whether the first floating-point operation result and the second floating-point operation result are consistent. In the floating-point operation result comparison, Not a Number (NaN) is verified to check whether it meets the standard not-a-number requirement of the processor instruction. Not a Number refers to a number that is not a valid real number and is typically used to represent an undefined or illegal mathematical operation result. Second, the first exception triggering result is compared with the second exception triggering result to verify whether the FPU calculation of the processor under test and the floating-point operation simulation function calculation triggered the same floating-point exception. Exemplarily, floating-point exceptions may include invalid operation, division by zero, overflow, underflow, inexact result, integer overflow, and denormalized number exceptions. If the first floating-point operation result is inconsistent with the second floating-point operation result, and / or the first exception trigger result is inconsistent with the second exception trigger result, the test case is marked as an error, and the error test case, state control parameters, test result, reference result, and differences are recorded. If the first floating-point operation result is consistent with the second floating-point operation result, and the first exception trigger result is consistent with the second exception trigger result, the test case is determined to have passed the test.

[0082] Finally, check whether the FPU calculation of the processor under test is correctly executed according to the state control parameters configured in the environment initialization phase, such as dynamic rounding mode, denormalized number processing mode, exception handling mode, etc., to ensure the reliability and consistency of its functions.

[0083] In this embodiment, by verifying whether the floating-point operation results are consistent and whether the FPU calculation of the processor to be tested and the floating-point operation simulation function calculation trigger the same floating-point exception, it is possible to accurately determine whether the calculation accuracy of the FPU passes the test.

[0084] In an exemplary embodiment, the above method further includes: a step of test information statistics and test result analysis, which includes:

[0085] Classify error information according to error type, and count the distribution of error information in floating-point operation type or floating-point data format; count the number of test cases that pass the test, and determine the test pass rate based on the number of test cases that pass the test; count the floating-point operation functions covered by the test cases, and determine the test coverage based on the floating-point operation functions covered by the test cases.

[0086] Specifically, the error information recorded in the test results is categorized by error type, such as operation type, data format, result error, exception error, and state control parameter error. The distribution of error information across different floating-point operation types or floating-point data formats is analyzed. The number of test cases that passed the test is counted to calculate the pass rate. The floating-point instruction operation functions covered by the test cases are counted to calculate the test coverage.

[0087] In this embodiment, by statistically analyzing the distribution of error information, we can optimize or repair frequently occurring floating-point operation types or data formats. By counting the number of test cases that pass the test, we can quickly assess the quality of the test suite. By calculating test coverage, we can ensure that all floating-point operation functions are fully tested, avoiding missing important operations or data format verification, and improving the comprehensiveness and effectiveness of the test.

[0088] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0089] Based on the same inventive concept, the present application also provides a processor accuracy testing device for implementing the aforementioned processor accuracy testing method. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations in one or more processor accuracy testing device embodiments provided below can be found in the aforementioned limitations on the processor accuracy testing method, and will not be further elaborated here.

[0090] In an exemplary embodiment, Figure 4 As shown, a processor accuracy testing device is provided, comprising: an initialization module 402 and a test execution module 404. Initialization module 402 includes a parameter parsing module and a test case generation module. The parameter parsing module includes a test platform analysis module, an operation type analysis module, a data format analysis module, and an execution status analysis module. Test execution module 404 includes a processor FPU calculation module, a floating-point operation simulation module, an operation comparison module, an exception triggering module, an execution status check module, and a result analysis module.

[0091] The initialization module 402 is used to generate test cases according to test parameters during the environment initialization phase.

[0092] The test execution module 404 is used to input the test case into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested for calculation during the test execution phase, so as to obtain a first calculation result of the floating-point instruction calculation function and a second calculation result of the floating-point operation simulation function; wherein, the floating-point instruction calculation function of the processor to be tested is constructed in C embedded assembly, and the floating-point simulation instruction calculation function is obtained by integrating the floating-point operation functions of multiple platforms to be tested; the first calculation result and the second calculation result are compared to obtain the accuracy test result of the processor to be tested.

[0093] In an exemplary embodiment, the test platform analysis module is used to select a platform to be tested according to test parameters and perform environment initialization.

[0094] The operation type analysis module is used to determine the floating-point operation type according to the test parameters.

[0095] The data format analysis module is used to determine the floating-point data format according to the test parameters. The floating-point data format includes a high-precision data format and a low-precision data format.

[0096] The execution state analysis module is used to set the state control parameters of the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested according to the test parameters.

[0097] The test case generation module is used to generate test cases according to the test objectives.

[0098] In an exemplary embodiment, a test case generation module is used to set the test case space required for the test target according to the floating-point operation type and the floating-point data format; and generate corresponding test cases in the test case space according to the floating-point data format, and the test cases include random floating-point numbers, boundary floating-point numbers, special floating-point numbers and combined floating-point numbers.

[0099] In an exemplary embodiment,

[0100] The FPU calculation module of the processor to be tested is used to input the test cases into the floating-point instruction calculation function of the processor to be tested respectively; calculate the test cases through the state control parameters of the floating-point instruction calculation function of the processor to be tested, and output the first calculation result of the floating-point instruction calculation function.

[0101] The floating-point operation simulation module is used to input the test cases into the floating-point operation simulation function respectively; operate the test cases through the state control parameters of the floating-point operation simulation function, and output the second operation result of the floating-point operation simulation function.

[0102] In an exemplary embodiment, the operation comparison module is configured to compare a first floating-point operation result in the first operation result with a second floating-point operation result in the second operation result.

[0103] The abnormality triggering module is used to compare the first abnormality triggering result in the first operation result with the second abnormality triggering result in the second operation result.

[0104] The execution status check module is used to check whether the FPU calculation of the processor to be tested is correctly executed according to the state control parameters configured in the environment initialization stage.

[0105] In an exemplary embodiment, the result analysis module is used to determine that the test case has passed the test when the first operation result and the second operation result are consistent; when the first operation result and the second operation result are inconsistent, mark the test case as an error and record the error information.

[0106] In an exemplary embodiment, the result analysis module is also used to classify error information according to error type, and count the distribution of error information in floating-point operation type or floating-point data format; count the number of test cases that pass the test, and determine the test pass rate based on the number of test cases that pass the test; count the floating-point operation functions covered by the test cases, and determine the test coverage based on the floating-point operation functions covered by the test cases.

[0107] Each module in the processor accuracy testing device described above can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a computer device memory in software form, so that the processor can call and execute the corresponding operations of each module.

[0108] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 5As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store data such as test parameters and test cases. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a processor accuracy testing method is implemented.

[0109] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0110] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0111] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0112] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0113] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0114] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), data processing logic devices based on quantum computing, and the like.

[0115] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A processor accuracy testing method, characterized in that: Applied to a test suite, the method comprises: During the environment initialization phase, test cases are generated based on test parameters; During the test execution phase, the test case is input into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested for operation, thereby obtaining a first operation result of the floating-point instruction calculation function and a second operation result of the floating-point operation simulation function; wherein the floating-point instruction calculation function of the processor to be tested is constructed in a C embedded assembly manner, and the floating-point operation simulation function is obtained by integrating the floating-point operation functions of multiple platforms to be tested; The first operation result and the second operation result are compared to obtain an accuracy test result of the processor to be tested.

2. The method according to claim 1, characterized in that Generating a test case according to the test parameters includes: Select a platform to be tested according to the test parameters and initialize the environment; Determine a test target according to the test parameters, wherein the test target includes a floating-point operation type and a floating-point data format, and the floating-point data format includes a high-precision data format and a low-precision data format; Setting state control parameters of a floating-point instruction calculation function and a floating-point operation simulation function of the processor to be tested according to the test parameters; Generate test cases according to the test objectives.

3. The method according to claim 2, characterized in that Generating a test case according to the test target includes: Setting the test case space required for the test target according to the floating-point operation type and the floating-point data format; Corresponding test cases are generated in the test case space according to the floating-point data format, wherein the test cases include random floating-point numbers, boundary floating-point numbers, special floating-point numbers and combined floating-point numbers.

4. The method according to claim 2, characterized in that Inputting the test case into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested for operation, respectively, to obtain a first operation result of the floating-point instruction calculation function and a second operation result of the floating-point operation simulation function includes: Inputting the test cases into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested respectively; The test case is operated respectively by using the state control parameters of the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested, and a first operation result of the floating-point instruction calculation function and a second operation result of the floating-point operation simulation function are output.

5. The method according to claim 2, characterized in that Comparing the first operation result with the second operation result to obtain the accuracy test result of the processor to be tested includes: comparing the first operation result and the second operation result, wherein the first operation result includes a first floating-point operation result and a first exception triggering result, and the second operation result includes a second floating-point operation result and a second exception triggering result; When the first operation result and the second operation result are consistent, determining that the test case passes the test; When the first operation result and the second operation result are inconsistent, the test case is marked as an error and error information is recorded.

6. The method according to claim 5, characterized in that The method further comprises: Classifying the error information according to error types, and collecting statistics on the distribution of the error information in the floating-point operation type or the floating-point data format; Counting the number of test cases that passed the test, and determining the test pass rate based on the number of test cases that passed the test; Count the floating-point arithmetic functions covered by the test cases, and determine the test coverage rate according to the floating-point arithmetic functions covered by the test cases.

7. A processor accuracy testing device, characterized in that: The device comprises: The initialization module is used to generate test cases according to test parameters during the environment initialization phase; A test execution module is used to input the test case into the floating-point instruction calculation function and the floating-point operation simulation function of the processor to be tested respectively for operation during the test execution phase, so as to obtain a first operation result of the floating-point instruction calculation function and a second operation result of the floating-point operation simulation function; wherein, the floating-point instruction calculation function of the processor to be tested is constructed in C embedded assembly, and the floating-point simulation instruction calculation function is obtained by integrating the floating-point operation functions of multiple platforms to be tested; the first operation result and the second operation result are compared to obtain the accuracy test result of the processor to be tested.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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