Pre-fetch termination and recovery in instruction cache

Abstract

A system includes a CPU core (102), a first memory cache (130) and a second memory cache (155), and a memory controller subsystem (101). The storage controller subsystem (101) speculatively determines a hit or miss condition of a virtual address in the first memory cache (130), and speculatively translates the virtual address to a physical address. The storage controller subsystem (101) configures the state to a valid state in association with a hit or miss condition and a physical address. In response to receiving a first indication from the CPU core (102) that a program instruction associated with the virtual address is not required, the storage controller subsystem (101) reconfigures the state to an invalid state, and in response to receiving a second indication from the CPU core (102) that a program instruction associated with the virtual address is required, the storage controller subsystem (101) reconfigures the state to an invalid state. The storage controller subsystem (101) reconfigures the state back to the active state.

Description

[0001] This application is a divisional application of the Chinese patent application with an application date of August 14, 2019, an entry date of the Chinese national phase on April 13, 2021, and an application number of 201980067439.7 ("Prefetch termination and recovery in instruction cache"). Background Art

[0002] Some memory systems include a multi-level cache system. When a memory controller receives a request for a specific memory address from a processor core, the memory controller determines whether the data associated with the memory address exists in the first-level cache (L1). If the data exists in the L1 cache, the data is returned from the L1 cache. If the data associated with the memory address does not exist in the L1 cache, the memory controller accesses the second-level cache (L2), which may be larger and therefore hold more data than the L1 cache. If the data exists in the L2 cache, the data is returned from the L2 cache to the processor core, and if the same data is requested again, a copy is also stored in the L1 cache. Additional levels of the memory hierarchy are possible. Summary of the Invention

[0003] In one example, a system includes a processor having a CPU core, a first memory cache and a second memory cache, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively converts the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a state to a valid state. In response to receiving a first indication from the CPU core that a program instruction associated with the virtual address is not required, the memory controller subsystem reconfigures the state to an invalid state, and in response to receiving a second indication from the CPU core that a program instruction associated with the first virtual address is required, the memory controller subsystem reconfigures the state back to a valid state without requiring additional access to TAGRAM or address translation logic. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 A processor according to an example is described.

[0005] Figure 2 Promoting an L1 memory cache access to a full L2 cache line access according to an example is described.

[0006] Figure 3 is a flowchart illustrating performance improvements based on examples.

[0007] Figure 4 is another flow chart illustrating another performance improvement according to an example.

[0008] Figure 5 Shown include Figure 1 processor system. DETAILED DESCRIPTION

[0009] Figure 1 An example of a processor 100 including a hierarchical cache subsystem is shown. The processor 100 in this example includes a central processing unit (CPU) core 102, a memory controller subsystem 101, an L1 data cache (L1D) 115, an L1 program cache (L1P) 130, and an L2 memory cache 155. In this example, the memory controller subsystem 101 includes a data storage controller (DMC) 110, a program memory controller (PMC) 120, and a unified memory controller (UMC) 150. In this example, at the L1 cache level, data and program instructions are separated into separate caches. Instructions executed by the CPU core 102 are stored in the L1P 130 and then provided to the CPU core 102 for execution. Data, on the other hand, is stored in the L1D 115. The CPU core 102 can read data from and write data to the L1D 115, but has read access to the L1P 130 (no write access). L2 memory cache 155 may store both data instructions and program instructions.

[0010] Although the sizes of L1D 115, L1P 130, and L2 memory cache 155 may vary depending on the implementation, in one example, the size of L2 memory cache 155 is larger than the size of L1D 115 or L1P 130. For example, L1D 115 is 32 KB and L1P is also 32 KB, while the size of L2 memory cache may be between 64 KB and 4 MB. Furthermore, the cache line size of L1D 115 is the same as the cache line size of L2 memory cache 155 (e.g., 128 bytes), and the cache line size of L1P 130 is smaller (e.g., 64 bytes).

[0011] When CPU core 102 needs data, DMC 110 receives an access request for the target data from CPU core 102. This access request may include an address (e.g., a virtual address) from CPU core 102. DMC 110 determines whether the target data exists in L1D 115. If the data exists in L1D 115, the data is returned to CPU core 102. However, if the data requested by CPU core 102 does not exist in L1D 115, DMC 110 provides an access request to UMC 150. This access request may include a physical address generated by DMC 110 based on the virtual address (VA) provided by CPU core 102. UMC 150 determines whether the physical address provided by DMC 110 exists in L2 memory cache 155. If the data exists in L2 memory cache 155, the data is returned from L2 memory cache 155 to CPU core 102, where a copy is stored in L1D 115. Additional cache subsystem hierarchies may also exist. For example, L3 memory cache or system memory may be accessible. Thus, if the data requested by CPU core 102 is not present in either L1D 115 or L2 memory cache 155, the data may be accessed in an additional cache level.

[0012] Regarding program instructions, when CPU core 102 requires additional instructions to execute, CPU core 102 provides VA 103 to PMC 120. PMC responds to VA 103 provided by CPU core 102 by initiating a workflow to return a prefetch data packet 105 of program instructions to CPU core 102 for execution. While the size of the prefetch data packet may vary depending on the implementation, in one example, the size of the prefetch data packet is equal to the size of a cache line of L1P 130. If the L1P cache line size is, for example, 64 bytes, then the prefetch data packet returned to CPU core 102 will also contain 64 bytes of program instructions.

[0013] The CPU core 102 also provides a prefetch count 104 to the PMC 120. In some embodiments, the prefetch count 104 is provided to the PMC 120 after the CPU core 102 provides the VA 103. The prefetch count 104 indicates the number of prefetch units for program instructions following the prefetch unit starting at VA 103. For example, the CPU core 102 may provide a VA of 200h. This VA is associated with a 64-byte prefetch unit starting at virtual address 200h. If the CPU core 102 wants the memory controller subsystem 101 to send additional instructions for execution after the prefetch unit associated with virtual address 200h, the CPU core 102 submits a prefetch count value greater than 0. A prefetch count of 0 indicates that the CPU core 102 no longer requires any prefetch units. For example, a prefetch count of 6 indicates that the CPU core 102 requests that instructions for an additional 6 prefetch units be obtained and sent back to the CPU core 102 for execution. Returning prefetch units at Figure 1 Shown in FIG. 1 is a pre-fetched data packet 105 .

[0014] Still refer to Figure 1 In the example of FIG, PMC 120 includes TAGRAM (Tagged Random Access Memory) 121, address translator 122, and registers 123. TAGRAM 121 contains a list of virtual addresses, whose contents (program instructions) have been cached in L1P 130. Address translator 122 converts virtual addresses into physical addresses (PA). In one example, address translator 122 generates physical addresses directly from virtual addresses. For example, the lower 12 bits of VA can be used as the least significant 12 bits of PA, with the most significant bits of PA (above the lower 12 bits) generated based on a set of tables configured in main memory before program execution. In this example, physical addresses, rather than virtual addresses, can be used to address L2 memory cache 155. Register 123 stores a hit / miss indicator 124 from a lookup in TAGRAM 121, a physical address 125 generated by address translator 122, and a valid bit 126 (also referred to herein as a status bit) to indicate whether the corresponding hit / miss indicator 124 and physical address 125 are valid or invalid.

[0015] After receiving VA 103 from CPU 102, PMC 120 performs a TAGRAM 121 lookup to determine whether L1P 130 includes the program instruction associated with the virtual address. The result of the TAGRAM lookup is a hit or miss indicator 124. A hit means that the VA is present in L1P 130, while a miss means that the VA is not present in L1P 130. For an L1P 130 hit, PMC 120 retrieves the target prefetch unit from L1P 130 and returns it to CPU core 102 as a prefetch packet 105.

[0016] For an L1P 130 miss, the PA (generated based on the VA) is provided by the PMC 120 to the UMC 150, as shown at 142. A byte count 140 is also provided from the PMC 120 to the UMC 150. The byte count indicates the number of bytes from the L2 memory cache 155 to be retrieved (if present) starting from the PA 142. In one example, the byte count 140 is a multi-bit signal that encodes the number of bytes required from the L2 memory cache 155. In this example, the L2 memory cache line size is 128 bytes, and each line is divided into an upper half (64 bytes) and a lower half (64 bytes). The byte count 140 can therefore encode the number 64 (if only the upper or lower 64 bytes of a given L2 memory cache line are required) or 128 (if the entire L2 memory cache line is required). In another example, the byte count may be a single bit signal where one state (eg, 1) implicitly encodes an entire L2 memory cache line, while another state (eg, 0) implicitly encodes half of an L2 memory cache line.

[0017] The UMC 150 also includes a TAGRAM 152. The PA 142 received by the UMC 150 from the PMC 120 is used to perform a lookup in the TAGRAM 152 to determine whether the target PA is a hit or a miss in the L2 memory cache 155. If there is a hit in the L2 memory cache 155, the target information may be half a cache line or a full cache line, depending on the byte count 140. This target information is returned to the CPU core 102, a copy is stored in the L1P 130, and the next time the CPU core 102 attempts to fetch the same program instruction, the same program instruction will be provided to the CPU core 102 from the L1P 130.

[0018] exist Figure 1 In the example of FIG, CPU core 102 provides VA 103 and prefetch count 104 to PMC 120. As described above, PMC 120 initiates a workflow to retrieve prefetch packets from L1P 130 or L2 memory cache 155. Using prefetch count 104 and original VA 103, PMC 120 calculates additional virtual addresses and continues to retrieve prefetch packets corresponding to those calculated VAs from L1P 130 or L2 memory cache 155. For example, if the prefetch count is 2 and VA 103 from CPU core 102 is 200h, PMC 120 calculates the next two VAs as 240h and 280h, rather than CPU core 102 providing each such VA to PMC 120.

[0019] Figure 2Specific examples are described where optimization results in improved performance of the processor 100. As described above, the line width of the L2 memory cache 155 is greater than the line width of the L1P. In one example, Figure 2 As shown, the width of the L1P is 64 bytes and the line width of the L2 memory cache 155 is 128 bytes. The L2 memory cache 155 is organized into an upper half 220 and a lower half 225. The UMC 150 can read an entire 128-byte cache line from the L2 memory cache 155, or read only half of the L2 memory cache line (the upper half 220 or the lower half 225).

[0020] A given VA can be translated into a specific PA, which, if present in the L2 memory cache 155, is mapped to either the lower half 225 or the upper half 220 of a given line of the L2 memory cache. Based on the addressing scheme used to represent the VA and PA, the PMC 120 can determine whether a given VA will be mapped to the lower half 225 or the upper half 220. For example, a specific bit within the VA (e.g., bit 6) can be used to determine whether the corresponding PA will be mapped to the upper or lower half of the L2 memory cache line. For example, a bit 6 of 0 can indicate the lower half, while a bit 6 of 1 can indicate the upper half.

[0021] Reference numeral 202 illustrates an example where the VA provided by the CPU core 102 to the PMC 120 is 200h and the corresponding prefetch count is 6. Reference numeral 210 illustrates that the VA list passing through the cache pipe includes 200h (received from the CPU core 102) and the next six consecutive virtual addresses 240h, 280h, 2c0h, 300h, 340h, and 380h (calculated by the PMC 120).

[0022] As described above, each address from 200h to 380h is processed. Any or all VAs may miss in L1P 130. PMC 120 may bundle two consecutive VAs that miss in L1P 130 into a single L2 cache line access attempt. Thus, if both 200h and 240h miss in L1P 130, and the physical address corresponding to 200h corresponds to the lower half 225 of a particular cache line of L2 memory cache 155, and the physical address corresponding to 240h corresponds to the upper half 220 of the same cache line of L2 memory cache, then PMC 120 may issue a single PA 142 to UMC 150 along with a byte count 140 specifying the entire cache line from the L2 memory cache. Thus, two consecutive VA misses in L1P 130 may be promoted to a single full-line L2 memory cache lookup.

[0023] If the last VA in a series of VAs initiated by CPU core 102 (e.g., VA 380h in series of VAs 210) maps to the lower half 225 of a cache line in L2 memory cache 155, then according to the described example, the entire cache line in L2 memory cache 155 is retrieved, even though only lower half 225 is needed. The same response occurs if the CPU presents VA 103 to PMC 120 with a prefetch count of 0, meaning that CPU 102 only requires a single prefetch unit. Any additional overhead, time, or power consumption (if any) in retrieving and presenting the entire cache line to L1P 130 is minimal. Since program instructions are typically executed in linear order, there is generally a high probability that program instructions in upper half 220 will be executed after instructions in lower half 225. Therefore, the next set of instructions is received at minimal cost, even though such instructions are likely needed anyway.

[0024] Figure 2 The mapping of VA 380h to the lower half 225 of cache line 260 in L2 memory cache 155 is illustrated by arrow 213. PMC 120 determines this mapping by, for example, examining one or more bits of the VA or its corresponding physical address after translation by address translator 122. PMC 120 elevates the lookup process of UMC 150 to a full cache line read by submitting the PA associated with VA 380h and the byte count 140 specifying the entire cache line. The entire 128-byte cache line is then retrieved (if present in L2 memory cache 155) and written to L1P 130 in two separate 64-byte cache lines, as indicated by 265.

[0025] However, if the last VA in the series of VAs (or only one VA if the prefetch count is 0) maps to the upper half 220 of a cache line in the L2 memory cache 155, the PMC 120 requests the UMC 150 to look in its TAGRAM 152 and return only the upper half of the cache line to the CPU core 102 and L1P 130. The next PA will be located in the lower half 225 of the next cache line in the L2 memory cache 155, and additional time, overhead, and power will be spent speculatively retrieving the next cache line, with no certainty that the CPU core 102 will need to execute those instructions.

[0026] Figure 3An example of a flow chart 300 for the above method is shown. The operations may be performed in the order shown or in a different order. In addition, the operations may be performed sequentially, or two or more operations may be performed simultaneously.

[0027] At 302, the method includes receiving, by the memory controller subsystem 101, a request for access to N prefetch units for program instructions. In one embodiment, this operation is performed by the CPU core 102 providing an address and a count value to the PMC 120. The address may be a virtual address or a physical address, and the count value may indicate the number of additional prefetch units that the CPU core 102 requires.

[0028] At 304, index value I is initialized to a value of 1. This index value is used to determine when PMC 120 is about to process the last virtual address in a series of consecutive virtual addresses. At 306, the method determines whether prefetch unit I is a hit or a miss for L1P 130. In some examples, this determination is made by determining whether the virtual address is present in TAGRAM 121 of the PMC. Determination 306 can have two possible outcomes: a hit or a miss.

[0029] If the virtual address is a hit into the L1P 130, then at 308, the corresponding line of the L1P 130 containing the desired prefetch unit is returned from the L1P 130 and provided to the CPU core 102 as a prefetch data packet 105. The index is then incremented (I = I + 1) at 310. If I has not yet reached N + 1 (as determined at decision operation 312), then the last VA of the prefetch unit has not been evaluated for a hit / miss determination, and control loops back to 306 to evaluate the next I-th prefetch unit for a hit or miss in the L1P 130. If I has reached N + 1, then all N prefetch units have been evaluated and the corresponding program instructions have been provided to the CPU core 102, and the process stops.

[0030] For a given prefetch unit (i), if the PMC 120 determines at 306 that there is a miss in the L1P 130, then at 314, it is determined whether I has reached the value of N. If I is not equal to N (indicating that the last VA in the series of VAs has not yet been reached), then at 316, the method includes the memory controller subsystem 101 obtaining the program instruction from the L2 memory cache 155 (if present, or from the third level cache or system memory if not present). The index value I is then incremented at 318, and control loops back to the determination 306.

[0031] If, at 314, I has reached N (indicating that the last VA in the series has been reached), then at 320, the method includes determining whether the VA of the first prefetch unit is mapped to the lower half or the upper half of a cache line of the L2 memory cache 155. An example of how this determination is made is described above. If the VA of the first prefetch unit is mapped to the upper half, then at 322, the method includes obtaining program instructions only from the upper half of a cache line of the L2 memory cache.

[0032] However, if the VA of the Ith prefetch unit maps to the lower half, then at 324, the method includes promoting the L2 memory cache access to a full cache line access, and at 326, obtaining the program instruction from the full cache line of the L2 memory cache.

[0033] Return Reference Figure 1 As described above, after submitting VA 103 from CPU core 102 to PMC 120, CPU core 102 may also provide prefetch count 104 to PMC 120. The prefetch count may be 0, meaning that CPU core 102 does not require any instructions other than those contained in the prefetch units starting from VA 103. However, between receiving VA 103 and the subsequent prefetch count, PMC 120 performs some work as described below.

[0034] Upon receiving VA 103, PMC 120 performs a lookup in TAGRAM 121 to determine whether the first VA (provided by CPU core 102) is a hit or miss in the L1P, and also performs a VA-to-PA translation using address translator 122. Prior to receiving prefetch count 104, PMC 120 also calculates a second VA (the next consecutive VA after the VA provided by the CPU core). PMC 120 speculatively accesses TAGRAM 121 and uses address translator 122 to determine the hit / miss status of the second VA, populating register 123 with a hit / miss indication 124 and a PA 125. Valid bit 126 in register 123 is set to a valid state, thereby allowing further processing of the second VA as described above (e.g., retrieving the corresponding cache line from L1P 130, if present, or from L2 memory cache 155, if necessary).

[0035] However, before any further processing of the second VA occurs, CPU core 102 may send a prefetch count of zero to PMC 120, meaning that the CPU core does not require any prefetch units other than the prefetch units starting from original VA 103. At this point, a prefetch count of zero is provided to PMC 120, so no prefetch units associated with the second VA are required. However, the PMC has also determined the hit / miss status of the second VA and has generated a corresponding PA. When PMC 120 has received a prefetch count of zero, both hit / miss indicator 124 and PA 125 have been stored in register 123. PMC 120 changes the state of valid bit 126 to indicate an invalid state, thereby precluding any further processing of the second VA. This condition (setting the valid bit to an invalid state) is called a "kill," and thus PMC 120 terminates processing of the second VA.

[0036] However, in some cases, despite the previous termination, CPU core 102 may determine that the prefetch unit associated with the second VA should indeed be obtained from L1P 130 or L2 memory cache 155, as described above. For example, if CPU core 102 has no further internal prediction information to indicate the next required instruction address, CPU core 102 will signal PMC 120 that it should continue prefetching linearly from the last requested address. This situation may occur, for example, due to a misprediction in branch prediction logic within CPU core 102. Therefore, CPU core 102 issues a resume signal 106 to PMC 120 for this purpose. PMC 120 responds to the resume signal by returning valid bit 126 to a valid state, thereby allowing continued processing of the second VA through the memory subsystem pipeline, as described above. In this way, CPU 102 does not need to submit the second VA directly to PMC 120. Instead, the PMC 120 retains the second VA and its hit / miss indicator 124 in, for example, the register 123, thereby avoiding the power consumption and time spent in re-determining the hit / miss status of the second VA and converting the second VA to a PA.

[0037] Figure 4 An example of a flow chart 400 is shown for initiating, then terminating, and then resuming a memory address lookup. The operations may be performed in the order shown or in a different order. Furthermore, the operations may be performed sequentially, or two or more operations may be performed simultaneously.

[0038] At 402, the method includes receiving an access request at a first VA by the memory controller subsystem 101. In one embodiment, this operation is performed by the CPU core 102 providing the first VA to the PMC 120. At 404, the method includes determining whether the first VA is a hit or a miss in the L1P 130. In one example, this operation is performed by accessing the TAGRAM 121 of the PMC to determine the hit / miss status of the first VA. At 406, the first VA is converted to a first PA using, for example, the address translator 122.

[0039] At 408, the method includes calculating a second VA based on the first VA. The second VA can be calculated by incrementing the first VA by a value to generate an address of a byte 64 bytes after the byte associated with the first VA. At 410, the method includes determining whether the second VA is a hit or a miss in L1P 130. In one example, this operation is performed by accessing TAGRAM 121 of the PMC to determine the hit / miss status of the second VA. As described above, at 412, the second VA is converted to a second address position using address translator 122. At 414, the method includes updating a register (e.g., register 123) with the hit / miss indicator 124 and the second address position. In addition, valid bit 126 is configured to a valid state.

[0040] Then, at 416, the PMC 120 receives the prefetch count. Then, at 418, if the prefetch count is greater than zero, then at 420, program instructions are retrieved from the L1P 130 or L2 memory cache 155 (or one or more additional levels), as described above. However, if the prefetch count is zero, then at 422, the valid bit 126 is changed to an invalid state. Despite having provided the zero prefetch count to the PMC 120, the CPU core 102 may then provide a resume indication to the PMC 120 (at 424). At 426, the PMC 120 changes the valid bit 126 back to a valid state, and the memory controller subsystem 101 then retrieves the program instructions associated with the second PA from the L1P, L2 memory cache, etc., as appropriate.

[0041] Figure 5An example use of the processor 100 described herein is shown. In this example, the processor 100 is part of a system-on-chip (SoC) 500, which includes the processor 100 and one or more peripheral ports or devices. In this example, the peripheral devices include a universal asynchronous receiver transmitter (UART) 502, a universal serial bus (USB) port 504, and an Ethernet controller 506. The SoC 500 can perform any of a variety of functions, such as those implemented by program instructions executed by the processor 100. More than one processor 100 may be provided, and within a given processor 100, more than one CPU core 102 may be included.

[0042] Throughout this specification, the term "coupled" refers to an indirect or direct connection, whether wired or wireless. Thus, if a first device is coupled to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. Additionally, throughout this specification, the phrase "based on" means "based at least in part on." Thus, if X is based on Y, then X may be a function of Y and any number of other factors.

[0043] Modifications may be made in the described embodiments, as well as in other embodiments, within the scope of the claims.

Claims

1. A data processing device, comprising: Memory; as well as a memory controller coupled to the memory and configured to: receiving a first address and a prefetch count value; calculating a second address based on the first address; determining a hit / miss status of the second address; Setting the state of the second address to a valid state; After setting the state of the second address to a valid state, determining whether the prefetch count value is zero; as well as When the prefetch count value is zero, the state of the second address is changed to an invalid state.

2. The data processing apparatus according to claim 1, wherein: The memory controller includes a register, and setting the state of the second address to valid includes storing a first value corresponding to a valid state to a first field of the register.

3. The data processing apparatus according to claim 2, wherein: The first field is a single bit of the register.

4. The data processing apparatus according to claim 2, wherein: The memory controller is configured to store a hit / miss status of the second address in a second field of the register and to store a translated address corresponding to the second address in a third field of the register.

5. The data processing apparatus according to claim 4, wherein: The second address is a virtual address, and the translated address corresponding to the second address is a physical address. The data processing apparatus according to claim 5 , wherein: The memory is a first memory, the memory controller is a first memory controller, and the data processing device includes a second memory and a second memory controller coupled to the second memory, and wherein, when the hit / miss status of the second address indicates a miss, the first memory controller is configured to provide the translated address to the second memory controller, and the second memory controller is configured to determine the hit / miss status of the translated address.

7. The data processing apparatus according to claim 6, wherein: The first memory is a first level "L1" cache and the second memory is a second level "L2" cache.

8. The data processing apparatus according to claim 7, wherein: The L1 cache has a first line width and the L2 cache has a second line width greater than the first line width.

9. The data processing apparatus according to claim 1, wherein: The prefetch count value is received by the memory controller after setting the state of the second address to a valid state.

10. The data processing apparatus according to claim 1, wherein: When the prefetch count value is zero, the memory controller changes the state of the second address from an invalid state back to a valid state in response to a resume signal.

11. The data processing apparatus according to claim 10, wherein: The data processing apparatus includes a branch prediction unit, and wherein a restore signal is received by the memory controller in response to a misprediction by the branch prediction unit.

12. The data processing apparatus according to claim 1, wherein: The second address is consecutive with respect to the first address.

13. A method comprising: receiving a first address; calculating a second address based on the first address; Setting the state of the second address to a valid state; receiving a prefetch count value; as well as When the prefetch count value is zero, the state of the second address is changed to an invalid state.

14. The method according to claim 13, wherein Both the first address and the second address are virtual addresses.

15. The method according to claim 13, wherein: The prefetch count value is received after the state of the second address is set to a valid state.

16. The method according to claim 13, wherein: The second address is consecutive with respect to the first address.

17. A method comprising: receiving, by a memory controller associated with the memory, a first address corresponding to a first memory request; In response to receiving the first address, speculatively determining, using the memory controller, a hit / miss condition of a second address and setting a state of the second address to valid; After setting the state of the second address to valid, receiving a prefetch count value by the memory controller; as well as If the prefetch count value is equal to zero, the state of the second address is changed to invalid.

18. The method according to claim 17, wherein: The second address is generated by the memory controller based on the received first address.

19. The method according to claim 17, further comprising: After changing the state of the second address to invalid, receiving, by the memory controller, a resume signal associated with the second address; as well as In response to the resume signal, the state of the second address is changed from invalid to valid.

20. The method according to claim 19, further comprising: After changing the state of the second address from invalid to valid, data associated with the second address is retrieved.

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