Method for detecting performance parameters of chip and performance simulation method of chip

Abstract

The invention provides a method for detecting performance parameters of a chip and a performance simulation method of the chip, and the method comprises the steps: obtaining the operation parameters of the chip when a test program operates on the chip, and enabling the test program to be used for measuring the parameter values of the to-be-tested performance parameters of the chip; and determining the parameter value of the to-be-tested performance parameter of the chip based on the operation parameter, so that the parameter value of the performance parameter can be measured, the accurate configuration of the performance simulation model can be realized, and the hardware performance of the chip can be accurately represented.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a method for detecting chip performance parameters and a chip performance simulation method. Background Art

[0002] During the development of real-time system hardware and software, off-bench debugging is often employed due to the unavailability or inconvenience of bench debugging. This involves debugging using software tools and simulation environments instead of real hardware. Performance simulators are widely used in off-bench debugging, used to predict the runtime of a given workload on a given piece of hardware (e.g., a chip). However, when using existing performance simulators to simulate chip performance, the manufacturer's numerous microarchitectural parameters are not disclosed, making it difficult to accurately set the corresponding performance simulator parameters. Consequently, these simulators are unable to accurately represent the performance of the original hardware. Furthermore, existing performance simulators run extremely slowly, typically at a speed of 0.1 MIPS (million instructions per second), which is more than three orders of magnitude slower than real hardware execution. This results in a long simulation execution time and low efficiency. Summary of the Invention

[0003] In response to the above-mentioned problems, the embodiments of the present application provide a method for detecting chip performance parameters and a chip performance simulation method to solve the problem of difficulty in accurately setting chip performance parameters.

[0004] In a first aspect, an embodiment of the present application provides a method for detecting chip performance parameters, comprising:

[0005] Obtaining operating parameters of the chip when a test program is run on the chip, wherein the test program is used to measure parameter values of performance parameters to be tested of the chip;

[0006] A parameter value of a performance parameter to be measured of the chip is determined based on the operating parameter.

[0007] In some embodiments, the performance parameter to be measured includes instruction execution delay, the operating parameter includes runtime, the test program is used to cause the chip to execute cyclically based on dependent instructions, and determining the parameter value of the performance parameter to be measured of the chip based on the operating parameter includes:

[0008] Determining an instruction time of a single instruction based on the running time and the number of instructions of the cyclically executed dependent instructions;

[0009] Obtaining the number of clock cycles according to the instruction time and the main frequency of the chip;

[0010] Obtaining the number of cycles occupied by a single instruction by dividing the number of instructions and the number of clock cycles;

[0011] The parameter value of the instruction execution delay is determined according to the inverse of the number of cycles occupied by the single instruction.

[0012] In some embodiments, the performance parameter to be measured includes: the number of instruction execution units; the operating parameter includes: running time; the test program is used to cause the chip to execute cyclically based on independent instructions; and determining the parameter value of the performance parameter to be measured of the chip based on the operating parameter includes:

[0013] Determining the instruction time of a single instruction based on the running time and the number of instructions of the cyclic execution instruction;

[0014] Obtaining the number of clock cycles according to the instruction time and the main frequency of the chip;

[0015] Obtaining the number of cycles occupied by a single instruction according to the number of instructions and the number of clock cycles;

[0016] The parameter value of the number of instruction execution units is determined according to the number of cycles occupied by a single instruction.

[0017] In some embodiments, the performance parameters to be tested include: memory access delay of cache at each level, the operating parameters include: running time, the test program is used to make the chip repeatedly read the value of a specific memory address to simulate the operation of accessing the cache, and the parameter value of the memory access delay of the cache at each level is obtained by dividing the running time by the number of cache access operations.

[0018] In some embodiments, the performance parameters to be tested include: associativity and capacity parameters of caches at all levels; the operating parameters include: access latency mutation time; the test program is used to cause the chip to access the cache in multiple memory access sequences, wherein the access distances of access instructions corresponding to any two memory access sequences are different, and there is a fixed access distance offset between two adjacent memory access instructions in the same memory access sequence; and determining parameter values of the performance parameters to be tested of the chip based on the operating parameters includes:

[0019] Establishing a corresponding calculation function based on the access delay mutation time corresponding to the plurality of memory access sequences, wherein the calculation function includes: a calculation relationship between the associativity, the capacity parameter, the access distance and the access delay mutation time;

[0020] The parameter values of the associativity and the capacity parameters of the caches at each level are calculated based on the multiple calculation functions.

[0021] In some embodiments, the method further comprises:

[0022] obtaining the test program;

[0023] The test program is uploaded to the chip, so that the chip runs based on the test program.

[0024] In a second aspect, an embodiment of the present application provides a chip performance simulation method, comprising:

[0025] Obtain parameter values and performance test cases of chip performance parameters;

[0026] Configuring a performance simulation model of the chip based on parameter values of the performance parameters to obtain a target performance simulation model;

[0027] A performance prediction result of the chip is determined based on the performance test case and the target performance simulation model.

[0028] In some embodiments, the performance parameters include: performance parameters measured by the method for detecting chip performance parameters described in the first aspect.

[0029] In some embodiments, the performance prediction results include: running time, the target performance simulation model is used to traverse each target instruction in the performance test case, determine the earliest available time of the occupied component corresponding to each target instruction, and output the running time of running the performance test case based on the earliest available time of the occupied component corresponding to the last target instruction in the performance test case. The earliest available time of the occupied component corresponding to each target instruction is determined based on the execution time and delay of the occupied component executing the previous target instruction.

[0030] In a third aspect, an embodiment of the present application provides a device for detecting chip performance parameters, comprising:

[0031] A first acquisition module is configured to acquire operating parameters of the chip when a test program is executed on the chip, wherein the test program is configured to measure parameter values of performance parameters to be tested of the chip;

[0032] A determination module is used to determine parameters of the performance parameters to be measured of the chip based on the operating parameters.

[0033] In a fourth aspect, an embodiment of the present application provides a chip performance simulation device, comprising:

[0034] The second acquisition module is used to obtain parameter values and performance test cases of the chip performance parameters;

[0035] A configuration module, configured to configure a performance simulation model for the chip based on parameter values of the performance parameters to obtain a target performance simulation model;

[0036] A performance prediction module is used to determine a performance prediction result of the chip based on the performance test case and the target performance simulation model.

[0037] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method provided in the first aspect when executing the computer program.

[0038] In a sixth aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method provided in the second aspect when executing the computer program.

[0039] In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the method provided in the first aspect above.

[0040] In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the method provided in the second aspect above.

[0041] In a ninth aspect, an embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it is used to implement at least the method of any one of the first aspect and / or the second aspect.

[0042] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0043] The method for detecting chip performance parameters provided in an embodiment of the present application obtains the operating parameters of the chip when a test program is run on the chip, wherein the test program is used to measure the parameter values of the performance parameters to be measured of the chip; and the parameter values of the performance parameters to be measured of the chip are determined based on the operating parameters, so that the parameter values of the performance parameters can be measured, thereby enabling accurate configuration of the performance simulation model, and further accurately characterizing the performance of the chip hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 A schematic diagram of a process for detecting chip performance parameters provided by the present application;

[0046] Figure 2A schematic diagram of a chip performance simulation method provided by the present application;

[0047] Figure 3 A schematic diagram of the implementation flow of a chip performance simulation method provided in an embodiment of the present application;

[0048] Figure 4 A schematic diagram of the structure of a device for detecting chip performance parameters provided in an embodiment of the present application;

[0049] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0051] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0052] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0053] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if it is detected" can be interpreted as meaning "upon determining" or "in response to determining" or "upon detecting" or "in response to detecting," depending on the context.

[0054] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0055] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized.

[0056] Based on the technical problems of the related art, the embodiment of the present application provides a method for detecting chip performance parameters that can be applied to electronic devices. Electronic devices may include: mobile phones, tablet computers, wearable devices, augmented reality (AR) / virtual reality (VR) devices, laptop computers, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs). The embodiment of the present application does not impose any restrictions on the specific type of electronic device. The electronic device can be a processor of a system for detecting chip performance parameters.

[0057] The present invention provides a method for detecting chip performance parameters. Figure 1 The present application provides a flow chart of a method for detecting chip performance parameters, as shown in FIG. Figure 1 As shown, the method includes:

[0058] Step S101 : obtaining operating parameters of the chip when a test program is run on the chip, wherein the test program is used to measure parameter values of performance parameters to be tested of the chip.

[0059] In embodiments of the present application, the performance parameters to be measured may include: instruction execution latency, the number of instruction execution units, memory access latency of each cache level, associativity of each cache level, and one of the capacity parameters. A test program is software code specifically written to measure the parameter values of specific chip performance parameters. The test program contains a series of instructions whose execution can trigger different functional units and cache levels within the chip, thereby indirectly measuring the chip's performance parameters by monitoring the execution of these instructions.

[0060] In a possible embodiment of the present application, each performance parameter to be measured corresponds to a test program. That is, if multiple performance parameters to be measured of a chip are to be measured, a test program corresponding to each performance parameter to be measured can be written on the chip.

[0061] In other embodiments, the test program on the chip can also be edited based on multiple performance parameters to be measured, that is, the test programs written based on each performance parameter to be measured are integrated together. For example, the test program includes multiple sub-test programs, and each sub-test program is edited by one performance parameter to be measured. However, when performing the test, the sub-test program corresponding to each performance parameter to be measured is run in sequence. For example, when it is necessary to determine the parameter value of the performance parameter A to be measured corresponding to the performance parameter A to be measured of the chip, the sub-test program corresponding to the performance parameter A to be measured in the test program can be run, and then the operating parameters of the sub-test program corresponding to the performance parameter A to be measured when it is running. When it is necessary to determine the parameter value of the performance parameter B to be measured corresponding to the performance parameter B to be measured of the chip, the sub-test program corresponding to the performance parameter B to be measured in the test program can be run. Then the operating parameters of the sub-test program corresponding to the performance parameter B to be measured when it is running are obtained.

[0062] In the embodiments of the present application, the test program is typically written in assembly language or a low-level programming language (such as C, but compiler optimization should be avoided to prevent interference with the measurement results) to ensure precise control of the chip behavior. The program may contain loop structures, memory access patterns, etc. to simulate the workload in real applications. The chip can be: a microcontroller unit (MCU).

[0063] In an embodiment of the present application, the user can clearly specify the performance parameters of the chip that he wants to measure, such as instruction execution delay, cache access delay, cache associativity and capacity parameters. These parameters will guide the design and writing of the test program. The user also needs to understand the chip architecture and instruction set, and then design the test program based on the performance parameters to be measured and the chip architecture. The test program should contain a series of instructions, the execution of which can trigger different functional units and cache levels inside the chip, thereby allowing the performance parameters of the chip to be indirectly measured by monitoring the execution of these instructions. After clarifying the design of the test program, the user begins to write the test program and uploads the test program to the chip, so that the chip runs the test program.

[0064] In the embodiment of the present application, the electronic device can monitor the serial port of the chip, thereby obtaining the operating parameters of the chip when the test program is running on the chip through the serial port of the chip.

[0065] In the embodiment of the present application, a serial port (serial communication interface) is an interface standard for data communication. It allows data to be transmitted between a chip and an electronic device (such as a computer). During the test process, the serial port is often used to read operating parameters or status information from the chip. Monitoring the serial port refers to capturing the operating parameters generated when the chip runs a test program through the serial communication interface (such as UART) of the chip. Operating parameters typically include run time, error codes or other status information for subsequent performance parameter calculations.

[0066] In the embodiment of the present application, before running the test program on the chip, it is necessary to configure the serial port settings of the chip (such as baud rate, data bits, etc.) to ensure that the data can be transmitted correctly. Then, the serial port communication software of the electronic device is used to receive and record these operating data.

[0067] Step S102: determining a parameter value of a performance parameter to be measured of the chip based on the operating parameter.

[0068] In the embodiment of the present application, after the operating parameters are collected, the operating parameters can be processed and analyzed to obtain parameter values of the performance parameters to be measured.

[0069] The method for detecting chip performance parameters provided in an embodiment of the present application obtains the operating parameters of the chip when a test program is run on the chip, wherein the test program is used to measure the parameter values of the performance parameters to be measured of the chip; and the parameter values of the performance parameters to be measured of the chip are determined based on the operating parameters, so that the parameter values of the performance parameters can be measured, thereby enabling accurate configuration of the performance simulation model, and further accurately characterizing the performance of the chip hardware.

[0070] In some embodiments, the performance parameter to be measured includes: instruction execution delay.

[0071] In this embodiment of the present application, instruction execution latency refers to the time required from the chip receiving an instruction to the completion of that instruction execution and the generation of a result. The operational parameters include: runtime. The runtime refers to the total time required for a test program to run on the chip. The test program is used to cause the chip to execute cyclically based on dependent instructions.

[0072] In an embodiment of the present application, dependent instructions are compiled into the test program, where the source register of the dependent instructions is the target register of the previous instruction. Dependent instructions refer to instructions with data dependencies, meaning that the execution result of one instruction needs to be used as input for the next instruction. This dependency prevents instructions from being executed in parallel and requires them to be executed in a specific order. Using dependent instructions in the test program can simulate instruction execution scenarios in actual work and more accurately measure instruction execution delays.

[0073] In the embodiment of the present application, step S102, determining the parameter value of the performance parameter to be measured of the chip based on the operating parameter, includes:

[0074] Step S1021 , determining the instruction time of a single instruction based on the running time and the number of instructions of the cyclically executed dependent instructions.

[0075] In the embodiment of the present application, the execution time can be divided by the number of instructions in the loop that executes dependent instructions to obtain the instruction time of a single instruction. The instruction time can be the average execution time of a single instruction. The instruction time of a single instruction is used to reflect the time required for the chip to execute a dependent instruction under test conditions.

[0076] Step S1022: Obtain the number of clock cycles according to the instruction time and the main frequency of the chip.

[0077] In the embodiment of the present application, the main frequency can be the number of clock cycles executed per unit time. The number of clock cycles reflects how many clock cycles are required to execute a dependent instruction within one clock cycle of the chip. The number of clock cycles can be obtained by multiplying the instruction time by the main frequency of the chip.

[0078] Step S1023: Obtain the number of cycles occupied by a single instruction by dividing the number of instructions and the number of clock cycles.

[0079] In an embodiment of the present application, the number of instructions may be divided by the number of clock cycles to obtain the number of cycles occupied by a single instruction.

[0080] Step S1024: determining a parameter value of the instruction execution delay according to the inverse of the number of cycles occupied by the single instruction.

[0081] In an embodiment of the present application, the inverse of the number of cycles occupied by the single instruction can be determined as the parameter value of the instruction execution delay.

[0082] In the embodiment of the present application, the reciprocal of the number of cycles occupied by a single instruction (i.e., 1 divided by the number of cycles) can be determined as the instruction execution delay. This value indicates how many clock cycles are required on average for each instruction to be executed.

[0083] The method provided in the embodiment of the present application determines the instruction time of a single instruction based on the running time and the number of instructions of the dependent instructions executed cyclically; obtains the number of clock cycles based on the instruction time and the main frequency of the chip; obtains the number of cycles occupied by a single instruction by dividing the number of instructions and the number of clock cycles; and determines the parameter value of the instruction execution delay based on the inverse of the number of cycles occupied by the single instruction, so as to accurately measure the instruction execution delay.

[0084] In some embodiments, the performance parameter to be tested includes: the number of instruction execution units, the operating parameter includes: operating time, and the test program is used to enable the chip to perform cyclic execution based on non-dependent instructions.

[0085] In an embodiment of the present application, non-dependent test instructions are compiled into the test program, and the source register of the non-dependent test instructions is not the target register of any previous instruction. Non-dependent instructions are those that do not need to wait for the result of the previous instruction when executing. Non-dependent instructions can be executed in parallel or in any order without affecting each other. In the test program, the use of non-dependent instructions can simplify the measurement process and reduce performance fluctuations caused by dependencies between instructions.

[0086] In some embodiments, determining the parameter value of the performance parameter to be measured of the chip based on the operating parameter in step S102 can be achieved by the following steps:

[0087] Step S1025 : determining the instruction time of a single instruction according to the running time and the number of instructions of the cyclically executed instruction.

[0088] In the embodiment of the present application, the running time can be divided by the number of instructions of the cyclic execution instruction to obtain the instruction time of a single instruction.

[0089] Step S1026: Obtain the number of clock cycles according to the instruction time and the main frequency of the chip.

[0090] In the embodiment of the present application, the instruction time may be multiplied by the main frequency of the chip to obtain the number of clock cycles.

[0091] Step S1027: Obtain the number of cycles occupied by a single instruction according to the number of instructions and the number of clock cycles.

[0092] In an embodiment of the present application, the number of instructions may be divided by the number of clock cycles to obtain the number of cycles occupied by a single instruction.

[0093] Step S1028: Determine a parameter value of the number of instruction execution units according to the number of cycles occupied by a single instruction.

[0094] In the embodiment of the present application, the smaller the number of instruction execution units, the better the performance of the instruction execution units.

[0095] The method provided by the implementation of the present application determines the instruction time of a single instruction based on the running time and the number of instructions of the cyclically executed instructions; obtains the number of clock cycles based on the instruction time and the main frequency of the chip; obtains the number of cycles occupied by a single instruction based on the number of instructions and the number of clock cycles; and determines the parameter value of the number of instruction execution units based on the number of cycles occupied by a single instruction, thereby accurately measuring the parameter value of the number of instruction execution units.

[0096] In some embodiments, the performance parameters to be tested include: memory access delay of each level of cache, the operating parameters include: operating time, and the test program is used to make the chip repeatedly read the value of a specific memory address to simulate the operation of accessing the cache.

[0097] In the embodiment of the present application, memory access latency refers to the time interval from the issuance of a memory access request to the actual availability of data. For cache, different levels of cache (such as L1, L2, L3 cache) may have different memory access latencies because of their different physical locations, sizes, and speeds. The test program is used to simulate the operation of the chip accessing the cache, which is achieved by repeatedly reading the value of a specific memory address. The test program is used to cause the chip to set the value of a memory address to the address itself, set the value of a register to the address, and then repeatedly read the address pointed to by the register, and write the read value to the register.

[0098] In an embodiment of the present application, the parameter value of the memory access delay of each level of cache is obtained by dividing the running time by the number of operations to access the cache.

[0099] In the embodiment of the present application, step S102 can be implemented by the following steps:

[0100] Step S1029: Divide the running time by the number of cache access operations to obtain the memory access delay of each level of cache.

[0101] In the embodiment of the present application, to determine the memory access latency of each cache level, the running time (i.e., the total time required to complete all cache access operations) can be recorded and the number of cache access operations can be calculated. Then, the average latency per access is obtained by dividing the running time by the number of accesses, and the memory access latency of each cache level can be obtained.

[0102] In some embodiments, the performance parameters to be tested include: the associativity and capacity parameters of each level of cache, the operating parameters include: the mutation time of the access delay, and the test program is used to enable the chip to access the cache in multiple memory access sequences, wherein the access distances of the access instructions corresponding to any two memory access sequences are different, and there is a fixed access distance offset between two adjacent memory access instructions in the same memory access sequence.

[0103] In the embodiments of the present application, the relevance of each level of cache refers to the number of different rows in the cache that can be used to store data, and the ability of these rows to be searched simultaneously to match a given address. In a direct-mapped cache, each memory block can only be mapped to a specific location in the cache; in a fully associative cache, any memory block can be mapped to any location in the cache; and in a set-associative cache, a memory block can be mapped to any location in a group of rows in the cache. Associativity usually refers to the number of rows in each group of a set-associative cache. The capacity of a cache refers to the amount of data that the cache can store, usually expressed in bytes, and determines how many memory blocks the cache can accommodate. The mutation time of memory access latency refers to the time from when memory access always hits to when memory access always misses. The memory access sequence can be expressed as: [m, m+offset, m+2*offset, ..., m+N*offset], where m is the memory access instruction, offset is the offset, and there is 1 offset between two adjacent memory access instructions in the same memory access sequence.

[0104] In the embodiment of the present application, step S102 can be implemented by the following steps:

[0105] Step S1030 : establishing a corresponding calculation function based on the access delay mutation time corresponding to the plurality of memory access sequences, wherein the calculation function includes: a calculation relationship between associativity, a capacity parameter, an access distance, and the access delay mutation time.

[0106] In an embodiment of the present application, the mutation time of the memory access delay may be recorded, and then a corresponding calculation function may be established based on the mutation time of the access delay.

[0107] For example, the calculation relationship can be expressed as: Different memory access sequences can construct a calculation relationship, where the cache capacity is C, the associativity is A, and the mutation time is n, where To round up.

[0108] Step S1051 : Calculate the associativity and capacity parameters of caches at all levels based on the plurality of calculation functions.

[0109] In the embodiment of the present application, a system of equations can be constructed by using multiple calculation functions, thereby obtaining the associativity and capacity parameters of each level of cache. Continuing with the above example, the cache capacity can be obtained as C and the associativity as A through the system of equations.

[0110] The method provided in the embodiment of the present application realizes automated chip measurement and analysis by writing a preset test program, automatically uploading the test program to the chip using a script file, and recording the start and end time of each test program by monitoring the serial port.

[0111] In some embodiments, before step S101, the method further includes:

[0112] Step S1011, obtaining the test program;

[0113] Step S1012: Upload the test program to the chip, so that the chip runs based on the test program.

[0114] In the embodiment of the present application, it can be determined that the type (such as MCU, FPGA, ASIC etc.) and programming interface (such as JTAG, ISP, SWD etc.) of the clear chip to be tested need to be clearly identified. Suitable programmer or download tool are selected according to chip type. Electronic equipment is connected to chip using the interface line of programmer or download tool, and then test program is uploaded to chip, and chip can be run based on test program after obtaining test program.

[0115] The present invention provides a chip performance simulation method that can be applied to electronic devices. The electronic devices may include: mobile phones, tablet computers, wearable devices, augmented reality (AR) / virtual reality (VR) devices, laptop computers, ultra-mobile personal computers (UMPCs), netbooks, and personal digital assistants (PDAs). The present invention does not impose any restrictions on the specific types of electronic devices.

[0116] The present invention provides a chip performance simulation method. Figure 2 The present application provides a flow chart of a chip performance simulation method, as shown in FIG. Figure 2 As shown, the method includes:

[0117] Step S201: Obtain parameter values and performance test cases of chip performance parameters.

[0118] In the embodiment of the present application, performance parameters may include: clock speed, cache size, memory bandwidth, power consumption, latency, throughput, etc.

[0119] In some embodiments, the performance parameters may also include: performance parameters measured by the method for detecting chip performance parameters provided in the above embodiments. Such as: instruction execution delay, the number of instruction execution units, memory access delay of caches at all levels, associativity and capacity parameters of caches at all levels, etc. Performance test cases are a series of test scenarios or tasks designed to evaluate chip performance. These test cases usually simulate various loads and operations that the chip may encounter in actual applications in order to comprehensively evaluate its performance. Performance test cases may include computationally intensive tasks, memory access intensive tasks, I / O intensive tasks, etc.

[0120] In an embodiment of the present application, users can design customized performance test cases based on the application scenarios and performance requirements of the chip, and can use professional testing tools and software (such as oscilloscopes, logic analyzers, IC testers, circuit simulation software, etc.) to generate and execute performance test cases.

[0121] In an embodiment of the present application, a user interface may be provided, through which a user may input parameter values of performance parameters of a chip, thereby enabling an electronic device to obtain parameter values of the performance parameters of the chip.

[0122] Step S202 : configuring a performance simulation model of the chip based on the parameter values of the performance parameters to obtain a target performance simulation model.

[0123] In an embodiment of the present application, a performance simulation model is a digital representation used to simulate the behavior and performance of a chip during actual operation. The performance simulation model is based on the design parameters and actual working conditions of the chip, and uses algorithms and mathematical formulas to predict the performance of the chip under different test cases. In an embodiment of the present application, the performance simulation model can be configured according to the parameter values of the performance parameters of the chip, and configuration refers to the process of adjusting and setting the performance simulation model according to the performance parameters of the chip. Configuring the performance simulation model includes setting the parameter values, initialization states, etc. of the performance parameters in the performance simulation model to ensure that the model can accurately reflect the actual performance of the chip, for example, setting the parameter values of the instruction execution delay, the number of instruction execution units, the memory access delay of caches at all levels, the associativity of caches at all levels, and the capacity parameters.

[0124] Step S203 : determining a performance prediction result of the chip based on the performance test case and the target performance simulation model.

[0125] In the embodiment of the present application, the performance prediction result may include: running time.

[0126] In an embodiment of the present application, the QEMU functional emulator can be used to run the performance test case of the software, export the trace file required by the emulator, and enter the trace file into the target performance simulation model to obtain the performance prediction result of the chip.

[0127] In the embodiment of the present application, the designed performance test case can be input into the target performance simulation model. The target performance simulation model will simulate the behavior and performance of the chip during actual operation and perform corresponding operations according to the requirements of the performance test case.

[0128] The method provided in the embodiment of the present application obtains the parameter values of the required performance parameters, configures the performance simulation model, and obtains a target performance simulation model for a specific chip, so that the configured target performance simulation model can more accurately characterize the performance of the original chip, so that testing can be performed based on the target performance simulation model, making the performance simulation results more accurate.

[0129] In the embodiment of the present application, the electronic device for executing the chip performance simulation method and the electronic device for executing the method for detecting chip performance parameters can be the same electronic device or different electronic devices, and the embodiment of the present application is not limited to this.

[0130] If the electronic device that performs the method for detecting chip performance parameters and the electronic device that performs the chip performance simulation method are the same electronic device, then for Figure 1 In the embodiment shown, the method provided in the embodiment of the present application may further include steps 201 to 203 after steps S101 to S102.

[0131] If the electronic device that performs the method for detecting chip performance parameters and the electronic device that performs the chip performance simulation method are not the same electronic device, for example, the electronic device that performs the method for detecting chip performance parameters is electronic device 1, and the electronic device that performs the chip performance simulation method is electronic device 2, then for Figure 1 In the embodiment shown, the method provided in the embodiment of the present application may further include the electronic device 1 sending parameter values of the chip's performance parameters to another electronic device 2 after the step of chip performance simulation.

[0132] In some embodiments, the performance prediction results include: running time, the target performance simulation model is used to traverse each target instruction in the performance test case, determine the earliest available time of the occupied component corresponding to each target instruction, and output the running time of running the performance test case based on the earliest available time of the occupied component corresponding to the last target instruction in the performance test case. The earliest available time of the occupied component corresponding to each target instruction is determined based on the execution time and delay of the occupied component executing the previous target instruction.

[0133] Taking the MCU as an example, the specific working principle of the performance simulation model is as follows: the MCU is abstracted into an out-of-order multi-issue CPU (O3 CPU) and a hierarchical memory system. The input trace file contains the executed instruction sequence and all memory access address sequences. The performance simulation model does not model the complete state information of the CPU at a certain time slice, but rather models the earliest available time of each component. During simulation, the performance simulation model obtains instructions from the instruction sequence one by one and calculates the end time of each pipeline segment of the instruction at one time, while updating the earliest available time of the components used. The earliest available time of a component is the time it was last occupied by the instruction. After the simulation ends, the maximum value of the earliest available time of all components is taken as the final running time. In the embodiment of the present application, if the instruction is a memory access instruction, the address of this memory access is obtained from the memory access address sequence, and the memory access delay is calculated using the hierarchical memory model and added to the end time of the memory access stage. Information such as instruction delay and memory access delay used to calculate the instruction execution time is provided by the performance analysis file generated by the automated analysis script. When executing an instruction, the earliest available time for the components occupied by the instruction is calculated by adding the time it starts that phase to the latency of that phase. This principle significantly reduces the amount of state information required to store in the CPU model. Furthermore, for any instruction, only the components involved need to be calculated once, rather than simulating the entire system every cycle in the main simulation loop and tracking its distribution, emission, execution, memory access, writeback, and commit behavior. This significantly reduces the computational complexity of the performance model. This ultimately significantly improves the simulation speed of the performance model, reaching approximately 100 MIPS.

[0134] Based on the above embodiments, the present application further provides a chip performance simulation method. The following takes the MCU as an example: Figure 3 A schematic diagram of the implementation flow of a chip performance simulation method provided in an embodiment of the present application is shown in FIG. Figure 3 Shown, including:

[0135] Step S301: given MCU platform.

[0136] Step S302: The automated MCU analyzes performance parameters.

[0137] In an embodiment of the present application, the performance parameters include: instruction execution delay, performance parameters of the instruction execution unit, memory access delay of each level of cache, associativity and capacity parameters of each level of cache, or one or more of the following:

[0138] Step S303: providing a configurable fast MCU performance model (same as the performance simulation model in the above embodiment).

[0139] Step S304: a performance simulation model specialized for a given MCU platform.

[0140] In the embodiment of the present application, the fast MCU performance model can be configured based on the parameter values of the performance parameters, thereby obtaining a performance simulation model specialized for a given MCU platform.

[0141] Step S305: Run the test case using the functional simulator.

[0142] In the embodiment of the present application, a trace file can be obtained by running the test case using a functional simulator.

[0143] Step S306: obtaining a performance simulation result of a given MCU simulation model running a given performance test case.

[0144] The method provided in the embodiments of this application addresses the issue of slow simulation speed. This embodiment of the application provides a performance simulation model. This performance simulation model is based on an instruction-driven approach, avoiding cycle-by-cycle simulation of underlying hardware behavior. While maintaining a relative error in performance estimation of no more than 20%, it significantly improves the performance simulation speed to 200 MIPS. To address the difficulty in obtaining real hardware parameters, the embodiments of this application provide an automated MCU performance parameter analysis method that measures the microarchitecture parameters required by the MCU and configures the performance model.

[0145] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0146] According to the aforementioned embodiments, the embodiments of the present application provide a device for detecting chip performance parameters. The modules included in the device, and the units included in each module, can be implemented by a processor in a computer device; of course, they can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0147] The present invention provides a device for detecting chip performance parameters. Figure 4 A schematic diagram of a device for detecting chip performance parameters provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the device 400 for detecting chip performance parameters includes:

[0148] A first acquisition module 401 is configured to acquire operating parameters of the chip when a test program is executed on the chip, wherein the test program is configured to measure parameter values of performance parameters to be tested of the chip;

[0149] The determination module 402 is configured to determine parameters of the performance parameters to be measured of the chip based on the operating parameters.

[0150] In some embodiments, the performance parameter to be tested includes instruction execution delay, the operating parameter includes operating time, and the test program is used to cause the chip to execute cyclically based on dependent instructions. The determination module 402 includes:

[0151] a first calculation unit, configured to determine an instruction time of a single instruction based on the running time and the number of instructions of the cyclically executed dependent instructions;

[0152] a second calculation unit, configured to obtain a number of clock cycles according to the instruction time and the main frequency of the chip;

[0153] a third calculating unit, configured to obtain a cycle occupied by a single instruction by dividing the number of instructions and the number of clock cycles;

[0154] The first determining unit is configured to determine a parameter value of the instruction execution delay according to the inverse of the number of cycles occupied by the single instruction.

[0155] In some embodiments, the performance parameters to be tested include performance parameters of an instruction execution unit, the operating parameters include operating time, and the test program is used to cause the chip to execute cyclically based on independent instructions. The determination module 402 includes:

[0156] a fourth calculation unit, configured to determine an instruction time of a single instruction based on the running time and the number of instructions of the cyclically executed instruction;

[0157] a fifth calculation unit, configured to obtain a number of clock cycles according to the instruction time and the main frequency of the chip;

[0158] a sixth calculating unit, configured to obtain the number of cycles occupied by a single instruction according to the number of instructions and the number of clock cycles;

[0159] The second determining unit is configured to determine a parameter value of the number of instruction execution units according to the number of cycles occupied by a single instruction.

[0160] In some embodiments, the performance parameter to be tested includes: memory access latency of each level of cache; the operating parameter includes: operating time; the test program is used to cause the chip to repeatedly read the value of a specific memory address to simulate the operation of accessing the cache; and the determination module 402 includes:

[0161] The seventh calculation unit is used to divide the running time by the number of operations of accessing the cache to obtain the memory access delay of each level of cache.

[0162] In some embodiments, the performance parameters to be tested include: associativity and capacity parameters of caches at all levels; the operating parameters include: access latency mutation time; the test program is used to cause the chip to access the cache using multiple memory access sequences, wherein the access distances of access instructions corresponding to any two memory access sequences are different, and there is a fixed access distance offset between two adjacent memory access instructions in the same memory access sequence. The determination module 404 includes:

[0163] An establishing unit, configured to establish a corresponding calculation function based on the access delay mutation time corresponding to a plurality of memory access sequences, wherein the calculation function includes: a calculation relationship between the associativity, the capacity parameter, the access distance, and the access delay mutation time;

[0164] An eighth calculation unit is used to calculate the associativity and capacity parameters of caches at each level based on a plurality of the calculation functions.

[0165] In some embodiments, the device 400 for detecting chip performance parameters further includes:

[0166] A third acquisition module is used to acquire the test program;

[0167] The uploading module is used to upload the test program to the chip so that the chip runs based on the test program.

[0168] The present application further provides a chip performance simulation device, comprising:

[0169] The second acquisition module is used to obtain parameter values and performance test cases of the chip performance parameters;

[0170] A configuration module, configured to configure a performance simulation model of the chip based on parameter values of the performance parameters to obtain a target performance simulation model;

[0171] A performance prediction module is used to determine a performance prediction result of the chip based on the performance test case and the target performance simulation model.

[0172] In some embodiments, the performance parameters include: performance parameters measured by the above-mentioned method for detecting chip performance parameters.

[0173] In some embodiments, the performance prediction results include: running time, the target performance simulation model is used to traverse each target instruction in the performance test case, determine the earliest available time of the occupied component corresponding to each target instruction, and output the running time of running the performance test case based on the earliest available time of the occupied component corresponding to the last target instruction in the performance test case. The earliest available time of the occupied component corresponding to each target instruction is determined based on the execution time and delay of the occupied component executing the previous target instruction.

[0174] In addition, the above-mentioned device for detecting chip performance parameters and chip performance simulation device can be a software unit, hardware unit, or a combination of software and hardware units built into existing electronic devices, or can be integrated into electronic devices as independent accessories, or can exist as independent terminal devices.

[0175] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment section and will not be repeated here.

[0176] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0177] Figure 5 This is a schematic diagram of the structure of the electronic device provided in the embodiment of the present application. Figure 5 As shown, the electronic device 3 of this embodiment may include: at least one processor 30 ( Figure 5 Only one processor 30 is shown in the figure), a memory 31, and a computer program 32 stored in the memory 31 and executable on at least one processor 30. When the processor 30 executes the computer program 32, the steps of any of the above-mentioned method embodiments are implemented, or when the processor 30 executes the computer program 32, the functions of the modules / units in the above-mentioned device embodiments are implemented.

[0178] Exemplarily, the computer program 32 may be divided into one or more modules / units, one or more of which are stored in the memory 31 and executed by the processor 30 to implement the present application. The one or more modules / units may be a series of computer program 32 instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of the computer program 32 in the electronic device 3.

[0179] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program 32. When the computer program 32 is executed by the processor 30, the steps in the above-mentioned method embodiments can be implemented.

[0180] An embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0181] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application can implement all or part of the processes in the above-mentioned embodiment method by instructing the relevant hardware through a computer program 32. The computer program 32 can be stored in a computer-readable storage medium. When the computer program 32 is executed by the processor 30, it can implement the steps of the above-mentioned various method embodiments. Among them, the computer program 32 includes computer program code, which can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying the computer program code to the terminal, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunication signal and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, a computer-readable medium cannot be an electric carrier signal or a telecommunication signal.

[0182] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0183] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0184] In the embodiments provided in this application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0185] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0186] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

[0187] The relevant user personal information that may be involved in the various embodiments of this application is strictly in accordance with the requirements of laws and regulations, following the principles of legality, legitimacy and necessity, and based on the reasonable purposes of business scenarios, to process the personal information that users actively provide during the use of products / services or generated due to the use of products / services, as well as the personal information obtained with the user's authorization.

[0188] The personal information processed by the Applicant will vary depending on the specific product / service scenario and will be based on the specific scenario in which the user uses the product / service. This may involve the user's account information, device information, driving information, vehicle information, or other related information. The Applicant will treat the user's personal information and its processing with a high degree of diligence.

[0189] The Applicant attaches great importance to the security of user personal information and has taken reasonable and feasible security measures that comply with industry standards to protect user information and prevent personal information from being accessed, disclosed, used, modified, damaged or lost without authorization.

Claims

1. A method for detecting chip performance parameters, characterized in that: include: Obtaining operating parameters of the chip when a test program is run on the chip, wherein the test program is used to measure parameter values of performance parameters to be measured of the chip; the test program is written based on at least the performance parameters to be measured; A parameter value of a performance parameter to be measured of the chip is determined based on the operating parameter.

2. The method according to claim 1, characterized in that The performance parameter to be tested includes instruction execution delay, the operating parameter includes running time, the test program is used to cause the chip to execute cyclically based on dependent instructions, and determining the parameter value of the performance parameter to be tested of the chip based on the operating parameter includes: Determining an instruction time of a single instruction based on the running time and the number of instructions of the cyclically executed dependent instructions; Obtaining the number of clock cycles according to the instruction time and the main frequency of the chip; Obtaining the number of cycles occupied by a single instruction by dividing the number of instructions and the number of clock cycles; The parameter value of the instruction execution delay is determined according to the inverse of the number of cycles occupied by the single instruction.

3. The method according to claim 1, characterized in that The performance parameter to be tested includes: the number of instruction execution units; the operating parameter includes: running time; the test program is used to cause the chip to execute cyclically based on independent instructions; and determining the parameter value of the performance parameter to be tested of the chip based on the operating parameter includes: Determining the instruction time of a single instruction based on the running time and the number of instructions of the cyclic execution instruction; Obtaining the number of clock cycles according to the instruction time and the main frequency of the chip; Obtaining the number of cycles occupied by a single instruction according to the number of instructions and the number of clock cycles; The parameter value of the number of instruction execution units is determined according to the number of cycles occupied by a single instruction.

4. The method according to claim 1, wherein The performance parameters to be tested include: memory access delay of each level of cache; the operating parameters include: running time; the test program is used to make the chip repeatedly read the value of a specific memory address to simulate the operation of accessing the cache; the parameter value of the memory access delay of each level of cache is obtained by dividing the running time by the number of operations of accessing the cache.

5. The method according to claim 1, wherein The performance parameters to be tested include: associativity and capacity parameters of caches at all levels; the operating parameters include: access delay mutation time; the test program is used to cause the chip to access the cache in multiple memory access sequences, wherein the access distances of access instructions corresponding to any two memory access sequences are different, and there is a fixed access distance offset between two adjacent memory access instructions in the same memory access sequence; and determining parameter values of the performance parameters to be tested of the chip based on the operating parameters includes: Establishing a corresponding calculation function based on the access delay mutation time corresponding to the plurality of memory access sequences, wherein the calculation function includes: a calculation relationship between the associativity, the capacity parameter, the access distance and the access delay mutation time; The parameter values of the associativity and the capacity parameters of the caches at each level are calculated based on the multiple calculation functions.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: obtaining the test program; The test program is uploaded to the chip, so that the chip runs based on the test program.

7. A chip performance simulation method, characterized in that: include: Obtain parameter values and performance test cases of chip performance parameters; Configuring a performance simulation model of the chip based on parameter values of the performance parameters to obtain a target performance simulation model; A performance prediction result of the chip is determined based on the performance test case and the target performance simulation model.

8. The method according to claim 7, characterized in that The performance parameters include: performance parameters measured by the method for detecting chip performance parameters according to any one of claims 1 to 6.

9. The method according to claim 7, characterized in that The performance prediction result includes: running time, the target performance simulation model is used to traverse each target instruction in the performance test case, determine the earliest available time of the occupied component corresponding to each target instruction, and output the running time of running the performance test case based on the earliest available time of the occupied component corresponding to the last target instruction in the performance test case. The earliest available time of the occupied component corresponding to each target instruction is determined based on the execution time and delay of the occupied component executing the previous target instruction.

10. A device for detecting chip performance parameters, characterized in that: include: A first acquisition module is configured to acquire operating parameters of the chip when a test program is executed on the chip, wherein the test program is configured to measure parameter values of performance parameters to be tested of the chip; A determination module is used to determine parameters of the performance parameters to be measured of the chip based on the operating parameters.

11. A chip performance simulation device, characterized in that: include: The second acquisition module is used to obtain parameter values and performance test cases of the chip performance parameters; A configuration module, configured to configure a performance simulation model of the chip based on parameter values of the performance parameters to obtain a target performance simulation model; A performance prediction module is used to determine a performance prediction result of the chip based on the performance test case and the target performance simulation model.

12. An electronic device, characterized in that: include: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 6 and / or 7 to 9 when executing the computer program.

13. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 and / or 7 to 9 is implemented.

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