Capacitor library construction method, electronic equipment and storage medium

Abstract

The invention relates to a capacitor library construction method, electronic equipment and a storage medium. The method comprises the following steps: determining a device graph type according to a process technology file; determining a basic graph corresponding to the device structure according to the device graph type; determining the sampling size of the basic pattern corresponding to each device structure according to a device design rule; establishing a device sampling graph according to the basic graph corresponding to the device structure and the sampling size corresponding to the basic graph; and solving the parasitic capacitance corresponding to each device sampling graph, and forming a capacitor library constructed by the device sampling graphs and the corresponding parasitic capacitance values. According to the technical scheme, different device pattern types and corresponding parasitic capacitance values are calculated and stored in advance, so that the accuracy and efficiency of constructing the capacitor library are improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method for constructing a capacitor bank, an electronic device, and a storage medium. Background Art

[0002] FinFET (Fin Field-Effect Transistor) is an advanced field-effect transistor technology. In the FinFET process, the channel of the transistor is designed to be shaped like a fin, perpendicular to the silicon substrate. Compared with the early processes in which designers can freely choose the size of the transistor within a certain range (i.e., continuous size), the FinFET process has stricter control over the physical size of electronic components such as transistors on the chip, which is limited to a combination of several fixed discrete value sizes (i.e., discrete sizes). In the process of extracting parasitic capacitance, the parasitic capacitance of discrete-size devices may need to be calculated through the capacitance library node interpolation method, which limits the accuracy of the capacitance calculation results. Summary of the Invention

[0003] In response to the above technical problems, the present application provides a method for constructing a capacitor library, an electronic device, and a storage medium, which improves the accuracy and efficiency of constructing the capacitor library by pre-calculating and storing different device graphics types and their corresponding parasitic capacitance values.

[0004] To solve the above technical problems, the present application provides a method for constructing a capacitor bank, comprising the following steps:

[0005] Determine the device pattern type based on process technology documents;

[0006] Determine the basic graphics corresponding to the device structure according to the device graphics type;

[0007] Determine the sampling size of the basic graphics corresponding to each device structure according to the device design rules;

[0008] According to the basic graphics corresponding to the device structure and the sampling size corresponding to the basic graphics, the device sampling graphics are constructed;

[0009] Solve the parasitic capacitance corresponding to each device sampling pattern to form a capacitance library constructed by the device sampling patterns and their corresponding parasitic capacitance values.

[0010] In some embodiments, the sampling size consists of a graphic width and a graphic interval. The graphic width refers to the width of the graphic corresponding to each device graphic type in the basic graphic, and the graphic interval refers to the interval between the graphics corresponding to each device graphic type in the basic graphic.

[0011] In some embodiments, the type of the sampling size includes a discrete size, a plurality of pairs of first widths and first intervals are determined according to the discrete size, and a value of the first width is a value consisting of discrete values determined according to design rules.

[0012] In some embodiments, constructing a device sampling pattern according to a basic pattern corresponding to a device pattern type and a sampling size corresponding to the basic pattern includes:

[0013] Based on fixed combinations of values of the first width and the first interval, a device sampling pattern corresponding to each combination is determined.

[0014] In some embodiments, the sampling size type further includes a continuous size, and a plurality of second widths and second intervals appearing in pairs are determined based on the continuous size, and the value of the second width is a value in a preset continuous interval determined according to the design rules.

[0015] In some embodiments, the preset value of the first width is smaller than the preset value range of the second width, and the first interval is smaller than the second interval.

[0016] In some embodiments, forming a device sampling pattern according to a basic pattern corresponding to the device pattern type and a sampling size corresponding to the basic pattern further includes:

[0017] Adjusting the sampling sizes corresponding to the continuous sizes to obtain a plurality of second widths and a plurality of second intervals;

[0018] A plurality of second widths and a plurality of second intervals are combined to determine a device sampling pattern corresponding to each combination.

[0019] In some embodiments, adjusting the sampling size corresponding to the continuous size includes:

[0020] The continuous dimensions are scaled proportionally so that the second widths in at least two combinations are in a preset multiple relationship, and the second intervals in at least two combinations are in a preset multiple relationship.

[0021] The present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the method for constructing a capacitor bank as described above are implemented.

[0022] The present application also provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method for constructing a capacitor library as described above are implemented.

[0023] The present invention discloses a method for constructing a capacitor library, an electronic device, and a storage medium. The method includes: determining the type of device graphics based on process technology documents; determining the basic graphics corresponding to the device structure based on the device graphics type; determining the sampling size of the basic graphics corresponding to each device structure based on device design rules; constructing device sampling graphics based on the basic graphics corresponding to the device structure and the sampling size corresponding to the basic graphics; and solving the parasitic capacitance corresponding to each device sampling graphic to form a capacitor library constructed from the device sampling graphics and their corresponding parasitic capacitance values. The technical solution of the present invention improves the accuracy and efficiency of constructing the capacitor library by precalculating and storing different device graphics types and their corresponding parasitic capacitance values. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is one of the flow charts of the method for constructing a capacitor library provided in an embodiment of the present application.

[0025] Figure 2 A schematic structural diagram of a device provided in an embodiment of the present application.

[0026] Figure 3 The embodiments of this application provide Figure 2 Schematic diagram of the structure of the basic graphics corresponding to the device.

[0027] Figure 4 This is a second flow chart of the method for constructing a capacitor library provided in an embodiment of the present application.

[0028] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0030] It should be noted that, in this document, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0031] It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the term "if" as used herein may be interpreted as "at the time of," "when," or "in response to a determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms "comprising" and "including" indicate the presence of the described features, steps, operations, elements, components, items, types, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, types, and / or groups. The terms "or" and "and / or" as used herein are to be interpreted as inclusive, meaning any one or any combination. Thus, “A, B, or C” or “A, B, and / or C” means “any of: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition occurs only when a combination of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0032] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless clearly stated herein, the execution of these steps is not strictly limited in order, and they can be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of other steps or sub-steps or stages of other steps.

[0033] It should be noted that in this article, step codes such as S1 and S2 are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial restriction on the order. When implementing the step, those skilled in the art may execute S2 first and then S1, etc., but these should all be within the scope of protection of this application.

[0034] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0035] In the subsequent description, the use of suffixes such as "module", "component" or "unit" to represent elements is only for the purpose of facilitating the description of the present application and has no specific meaning. Therefore, "module", "component" or "unit" can be used interchangeably.

[0036] Parasitic parameter extraction is a crucial step in the back-end design and signoff process for integrated circuits. This process involves describing the parasitic effects in the layout, extracting the parasitic resistance and capacitance caused by device interconnects on the layout, and then creating an accurate circuit simulation model. This is crucial for ensuring that circuit performance standards such as data delay, signal integrity, and power consumption are met.

[0037] See Figure 1 The present application provides a method for constructing a capacitor library. The method can be implemented in software and / or hardware, for example, using a computing device such as a computer or server. The method for constructing a capacitor library provided in this embodiment includes:

[0038] S1, determine the device pattern type according to the process technology file.

[0039] In this embodiment, the process technology file is used to provide the process information required for integrated circuit design and manufacturing at a specific process node. By reading the chip's process technology file, the chip's process characteristics can be analyzed to determine the types of device graphics that can be used to form different devices under that process. In other words, the device graphic type refers to a general graphic category determined based on the device type and structural characteristics under specific process conditions, which is used to form the basic graphics corresponding to different devices. Different device graphic types represent the structures of different parts of different devices and can be located in different positions within the device, thereby allowing them to be used to form different devices.

[0040] In some embodiments, for a device implemented by a process, there are some specific types of device graphics used to constitute the device. For example, the device graphic types include gate layer (GATE) graphics, field polysilicon layer (FIELD_POLY graphics), diffusion layer (DIFFUSION) graphics, connection trench (TRENCH_CONTACT) graphics, metal layer (METAL) graphics, and connection hole (VIA) graphics, etc.

[0041] S2, determining a basic graphic corresponding to the device structure according to the device graphic type.

[0042] In some embodiments, a device can be a complete device that realizes a complete function, or it can be a partial device that constitutes a complete device. Accordingly, the device structure can be a complete device structure that realizes a complete function, or it can be a partial device structure that constitutes a complete device. Among them, by combining the types of device graphics, it can be used to determine the basic graphics corresponding to the structures of different parts of different devices, for example, the basic graphics corresponding to the device structures of devices such as SVT-MOS and SGT-MOS. The basic graphics corresponding to the device structure are used to indicate the layout of each component in the device, that is, the position and shape characteristics of the graphics corresponding to different device graphic types in the device. Specifically, according to the structure of the target device, the required device graphic types are combined to form a basic graphic that matches the target device. For simple target devices, the device graphic types can be searched to determine the corresponding basic graphics. For target devices with complex shapes, they can be decomposed into a combination of multiple partial device structures that constitute the device, and the device graphic types of the multiple partial device structures are searched separately to determine the multiple corresponding basic graphics.

[0043] like Figure 2 FIG. 1 is a schematic diagram of a structure of a specific device shown in this embodiment. Figure 2 (a) is a top view of the device. Figure 2(b) is a cross-sectional view of the device. The device includes a gate 21 (GATE), a field polysilicon layer 22 (FIELD_POLY), a diffusion layer 26 (DIFFUSION), a connection trench 24 (TRENCH_CONTACT), a metal layer 25 (METAL), and a connection hole (VIA). According to the type and shape of each component in the device, the basic pattern corresponding to the device is determined. Figure 3 As shown, based on Figure 2 The corresponding basic graphics are determined by the device. Figure 3 (a) is the top view of the basic figure. Figure 3 (b) is a cross-sectional view of the basic figure. Figure 3 The basic pattern shown in the figure includes the device's gate 21, field polysilicon layer 22, connection trench 24, and diffusion layer 36. Specifically, the basic pattern includes a gate pattern 27, a field polysilicon layer pattern 28, a connection trench pattern 29, and a diffusion layer pattern 30. This means that the basic pattern simplifies the metal layer 25 and connection hole 26 relative to the device, and can serve as a universal template for partial device structures with the same semiconductor structure in other devices, accelerating the extraction of parasitic parameters and the construction of a capacitance library.

[0044] S3, determining a sampling size of a basic pattern corresponding to each device structure according to device design rules.

[0045] The basic graphics of each device structure are defined by the geometric parameters of each graphic type (such as length, width, and height), which are used to indicate the structural characteristics and layout of the device. Therefore, different dimensional data corresponding to the device graphic types that make up the device will form different device structures and layouts.

[0046] Device design rules describe the design and layout of a device or its components, specifically the various device graphic types that comprise the device, as well as the available sizes and positions within the device corresponding to each device graphic type. Sampling dimensions refer to the specific geometric dimensions of the underlying graphics corresponding to the target device, serving as parameters for simulating and calculating the parasitic capacitance of the target device. These dimensions include, but are not limited to, the length, width, height (or thickness), and spacing between sampling points. The sampling dimensions of the underlying graphics corresponding to each device include both the dimensional data of the device graphic type and the positional data between the graphics. Different device graphic types have different sampling dimensions, and accordingly, the underlying graphics corresponding to the component device structures also have different sampling dimensions. Some device graphic types or underlying graphics have discrete sampling dimensions, while others have continuous sampling dimensions. Alternatively, some have discrete sampling dimensions within a certain range, while others can have continuous sampling dimensions within a certain range. The sampling dimensions corresponding to each underlying graphic are determined by analyzing the device design rule specifications for sampling dimensions within the device, such as the range of values and minimum and maximum size limits.

[0047] S4, constructing a device sampling pattern according to the basic pattern corresponding to the device structure and the sampling size corresponding to the basic pattern.

[0048] The basic patterns determined based on the device and their corresponding sampling dimensions are combined to obtain one or more specific device sampling patterns for the device. The sampling dimensions can consist of a set of data describing different locations in the basic pattern. For example, the length, width, and height of the pattern corresponding to the device pattern type in the basic pattern constitute a set of sampling dimensions. Basic patterns can be combined with fixed combinations of sampling dimensions to obtain device sampling patterns. For example, a gate basic pattern and its corresponding Group A sampling dimensions (length 10 μm, width 5 μm, height 0.5 μm) are combined to obtain a device sampling pattern for a device pattern type corresponding to one target device. A gate basic pattern and its corresponding Group B sampling dimensions (length 8 μm, width 3 μm, height 0.3 μm) are combined to obtain a device sampling pattern for a device pattern type corresponding to another target device. Basic patterns can also be combined with freely combined sampling dimensions to obtain device sampling patterns. In other words, the individual dimensional parameters in Groups A and B can be freely combined to form new sampling dimensions. For example, Group C sampling dimensions (length 8 μm, width 5 μm, height 0.5 μm) are combined to obtain a sampling pattern for a device pattern type corresponding to another target device.

[0049] like Figure 2As shown, the basic graphics corresponding to the device can be determined according to the types of components in the device. The basic graphics can be represented by data indicating the shape and structural features of the gate 21 (GATE), field polysilicon layer 22 (FIELD_POLY), diffusion layer 26 (DIFFUSION), connection trench 24 (TRENCH_CONTACT), metal layer 25 (METAL1) and connection hole (VIA0), such as the length, width and height corresponding to the gate 21 (GATE), field polysilicon layer 22 (FIELD_POLY), diffusion layer 26 (DIFFUSION), connection trench 24 (TRENCH_CONTACT), metal layer 25 (METAL1) and connection hole (VIA0), namely, the gate graphics, field polysilicon layer graphics, connection trench graphics, diffusion layer graphics, connection trench (TRENCH_CONTACT), metal layer graphics and connection hole graphics. Figure 3 As shown, the device pattern types of this part of the device structure only cover the gate 21, field polysilicon layer 22, connection trench 24 and diffusion layer 36 of the device, and the corresponding basic patterns include gate pattern 27, field polysilicon layer pattern 28, connection trench pattern 29 and diffusion layer pattern 30, etc.

[0050] S5, solving the parasitic capacitance corresponding to each device sampling pattern to form a capacitance library constructed by the device sampling patterns and their corresponding parasitic capacitance values.

[0051] Calculate the parasitic capacitance of the device sample pattern. Optionally, use the parasitic parameter extraction function in the tool to calculate and record the parasitic capacitance between different nodes in the device sample pattern. Based on the calculated parasitic capacitance, build a capacitance library containing the device sample patterns and their associated parasitic capacitance values.

[0052] It should be noted that in order to improve the extraction efficiency while ensuring the accuracy of parasitic parameter extraction, the embodiment of the present application adopts an algorithm based on pattern matching to extract parasitic capacitance. The method first establishes a set of basic graphic libraries based on the critical dimensions of the process layer specified in the process file (such as the minimum line width of the graphics corresponding to each device graphic type in the basic graphics specified by the device design rules and the sampling spacing between the graphics, etc.), and pre-calculates the coupling capacitance values of each part between these basic graphics to form a capacitance library file under specific process conditions. In the actual parasitic capacitance extraction process, the basic graphics closest to the actual graphics are selected by comparing the design layout with the known basic graphic library, and then the parasitic capacitance value in the actual design is calculated, so as to efficiently and accurately complete the extraction of parasitic capacitance.

[0053] In some embodiments, the sampling size consists of a graphic width and a graphic interval. The graphic width refers to the width of the graphic corresponding to each device graphic type in the basic graphic, and the graphic interval refers to the interval between the graphics corresponding to each device graphic type in the basic graphic.

[0054] In this embodiment, a set of sampling sizes can be composed of a graphic width and a graphic interval. Based on the graphic width and the graphic interval, the number and position of sampling points corresponding to the basic graphic corresponding to the device structure can be determined, and then the parasitic capacitance of the device basic graphic can be solved. It should be noted that the sampling point refers to a specific position or area selected during the sampling process. Sampling refers to the selection of a set of discrete data points from a continuous physical entity (such as a section of wire or a plane) for analysis and calculation. In parasitic parameter extraction, a specific position or area can be selected by sampling to measure or estimate the parasitic effect. In this way, the amount of calculation can be reduced while ensuring sufficient calculation accuracy to represent the parasitic effect of the device as a whole.

[0055] In some embodiments, the type of the sampling size includes a discrete size, a plurality of pairs of first widths and first intervals are determined according to the discrete size, and a value of the first width is a value consisting of discrete values determined according to design rules.

[0056] As an implementation method of this embodiment, discrete dimensions refer to the provisions in the device design rules, and the device dimensions are represented by specific, discontinuous numerical values to reflect the width and mutual spacing of each part. The discrete dimensions include a plurality of first widths and first spacings that appear in pairs, and the first width can be selected from a set of predefined discrete values. These discrete values are usually set according to the capabilities and design rules of the manufacturing process. For example, at a specific process node, the device design rules stipulate that the gate width of the transistor, which is what those skilled in the art call the line width, can be discrete values such as 20nm, 30nm, 40nm, etc., that is, the device has discrete dimensions. Correspondingly, the value of the first spacing is obtained from the discrete discrete dimensions specified in the device design rules. For example, the spacing between the transistor gates can be discrete values such as 50nm, 60nm, 80nm, etc. In some embodiments, the width and spacing exist in a preset fixed combination.

[0057] When dealing with discrete-size devices, parasitic capacitance calculations and storage are only required for a limited number of preset sizes. This simplifies the construction of the capacitance library, reduces the number of base graphics and sampling points, and reduces the size of the capacitance library, making it more compact and easier to manage.

[0058] In some embodiments, constructing a device sampling pattern according to a basic pattern corresponding to a device pattern type and a sampling size corresponding to the basic pattern includes:

[0059] Based on fixed combinations of values of the first width and the first interval, a device sampling pattern corresponding to each combination is determined.

[0060] Different sampling size compositions form different base pattern sizes, so each sampling size corresponds to a sampling pattern for a device. As an implementation of this embodiment, for example, in a certain process, the design rules allow device gate size width and spacing combinations of 20nm / 50nm, 30nm / 60nm, and 40nm / 80nm. In other words, the discrete sizes only include three fixed combinations: 20nm line width and 50nm spacing, 30nm line width and 60nm spacing, and 40nm line width and 80nm spacing.

[0061] By fixing the width and spacing to a specific combination and forming a device sampling pattern, the fixed combination of width and spacing determined from the device design rules is a commonly used size in the device. Therefore, including this combination in the sampling process can more quickly extract the corresponding parasitic parameters in subsequent applications. Selecting from a limited and fixed number of predefined combinations can more accurately predict and control the parasitic effects of devices that meet this size combination, avoiding the loss of capacitance accuracy caused by the interpolation algorithm.

[0062] In some embodiments, the sampling size type further includes a continuous size, and a plurality of second widths and second intervals appearing in pairs are determined based on the continuous size, and the value of the second width is a value in a preset continuous interval determined according to the design rules.

[0063] As an implementation method of this embodiment, the continuous dimension is that the dimension of the device specified in the device design rules can be continuously changed within a certain range of values. For example, at a specific process node, the device design rules specify that the value range of the gate width of the transistor can be any value within a continuous value range between 90nm and 300nm to meet a variety of different design requirements. The second interval can be the spacing between the gates obtained from the continuous dimension specified in the device design rules. The device design rules specify that the distance between the gates of the transistors can be any value within a continuous value range between 100nm and 800nm.

[0064] Based on the continuous dimensions, multiple second widths and second intervals that appear in pairs are determined, and the second widths have a range of values. One or more values can be selected from the range of the second widths to generate one or more groups of sampling dimensions, each group of sampling dimensions including a second width and a second interval that appear in pairs. For example, the width of the continuous dimension is between 100nm and 500nm, and the interval is between 200nm and 1000nm. Based on the range of the width and interval, a width value can be selected every 100nm, and an interval value can be selected every 200nm. In this way, the width values are 100nm, 200nm, 300nm, 400nm, and 500nm respectively; the interval values are 200nm, 400nm, 600nm, 800nm, and 1000nm respectively. For each combination of width and sampling point interval, a group of sampling dimensions is generated.

[0065] In some embodiments, the preset value of the first width is smaller than the preset value range of the second width, and the first interval is smaller than the second interval.

[0066] As one implementation of this embodiment, since the values of discrete dimensions are discrete and typically smaller than those of continuous dimensions, a device sampling pattern can be determined for each discrete dimension to obtain accurate parasitic capacitance. The parasitic capacitance values for the device sampling pattern corresponding to each discrete dimension are pre-calculated and stored. In this way, in actual design, these values can be directly retrieved and used from the capacitance library without the need for repeated complex calculations.

[0067] Larger values for consecutive dimensions are typically used for larger devices, such as long traces or larger resistors and capacitors. Sampling and interpolating values across a larger dimension range simplifies the calculation process and allows for faster parasitic calculations, ensuring accuracy while conserving computing resources.

[0068] In this way, the capacitance library constructed using the method of the present application can comprehensively cover the parasitic parameter extraction of various devices from micro-sized to large-sized.

[0069] In some embodiments, forming a device sampling pattern according to a basic pattern corresponding to the device pattern type and a sampling size corresponding to the basic pattern further includes:

[0070] Adjusting the sampling sizes corresponding to the continuous sizes to obtain a plurality of second widths and a plurality of second intervals;

[0071] A plurality of second widths and a plurality of second intervals are combined to determine a device sampling pattern corresponding to each combination.

[0072] As one implementation of this embodiment, after determining multiple pairs of second widths and second intervals based on continuous dimensions, the multiple second widths and multiple second intervals are freely combined. That is, each second width can be combined with each second interval to generate multiple groups of sampling dimensions, and a corresponding device sampling pattern is generated for each group. Constructing a capacitance library based on the device sampling patterns generated based on continuous dimensions is adaptable to the different needs of devices and improves the accuracy of capacitance calculations.

[0073] In some embodiments, adjusting the continuous dimensions includes:

[0074] The continuous dimensions are scaled proportionally so that the second widths in at least two combinations are in a preset multiple relationship, and the second intervals in at least two combinations are in a preset multiple relationship.

[0075] As one implementation of this embodiment, within a continuous range of sizes, the sizes are adjusted using a preset multiple relationship to generate multiple sets of different sampling sizes. The preset multiple relationships between each combination ensure that the entire size range is covered, thereby accurately calculating the parasitic capacitance values at the required size points and constructing a capacitance library. This ensures both calculation accuracy and improved applicability and flexibility of the capacitance library.

[0076] For example, the width of a continuous dimension ranges from 90nm to 300nm, with intervals of no less than 100nm. Based on the maximum and minimum values within this dimension range, the dimensions and number of sampling points can be set according to a certain multiple relationship. For example, widths of 90nm, 108nm, 135nm, 180nm, 225nm, and 300nm represent the base dimension, 1.2 times, 1.5 times, 2 times, 2.5 times, and the maximum value allowed, respectively. At the same time, intervals can be 100nm, 120nm, 150nm, 200nm, 250nm, 300nm, 400nm, 500nm, 800nm, 1μm, etc., ensuring that there are sufficient data points within the entire dimension range for subsequent analysis and calculations. This ensures that the entire dimension range is covered while maintaining the logical association between sampling points, improving accuracy and efficiency during the design process.

[0077] Figure 4 This is a specific example provided in the embodiment of this application. Figure 4As shown, first read in the process technology file and process design rule information respectively. Read the relevant process technology file to obtain information about the characteristics and requirements of the process. Then, analyze the read process technology file to identify the various characteristics involved in the process, such as process hierarchy information, basic dimensions, process effect information, etc. Based on the analysis results, determine the type of device graphics. Taking MOS devices as an example, the basic layer types that make up MOS devices are gate (GATE), diffusion layer (DIFFUSION), connection trench (TRENCH_CONTACT) and bottom metal and corresponding connection holes. The bottom metal and connection holes do not need to be specially defined in the layer type.

[0078] At the same time, the tool reads the process design rule information, analyzes the device design rules, and distinguishes the discrete size part and the continuous size part in the device size list. For example, when reading the process technology file, the tool can obtain the following information:

[0079] The conductor layer named gate is of type GATE, the gate in a MOS device. It has a thickness of 0.08 μm, a minimum width of 0.02 μm, and a minimum spacing of 0.05 μm. The device type is SVT_MOS, indicating that this layer is an SVT_MOS (Standard Vt, SVT, standard threshold voltage MOS, metal oxide semiconductor transistor). In digital back-end design, process libraries typically provide three types of devices: HVT (high threshold voltage metal oxide semiconductor transistor), SVT (standard threshold voltage metal oxide semiconductor transistor), and LVT (low threshold voltage metal oxide semiconductor transistor). Designers can select the appropriate device based on specific timing and power consumption requirements.

[0080] Therefore, based on the analysis results of the process technology file, determine the types of basic graphics that need to be included in the process capacitor library. For example, the device structure of svt_mos needs to be included in the example.

[0081] In addition, the device design rules stipulate that the basic dimensions of the gate definition are a minimum line width of 20nm and a minimum spacing of 50nm. The design rules also stipulate the allowable device gate dimensions, including separation dimensions and continuous dimensions. The width and spacing of the separation dimensions are 20nm / 50nm, 30nm / 60nm, and 40nm / 80nm respectively. The continuous dimensions are allowed to have a width of 90nm to 100nm, and the spacing must be no less than 100nm.

[0082] For the discrete size part, fixed sampling points are set according to the above design rules. Specifically, the discrete value combinations allowed by the design rules are used as sampling points. The gate sizes allowed by the design rules are 20nm / 50nm, 30nm / 60nm, and 40nm / 80nm. These fixed combinations are directly used as the sampling sizes of the basic graphics without the need for interpolation calculations. For the continuous size part, sampling points are set according to the multiple relationship within the value range of the size. Specifically, sampling points can be set within the value range according to a preset multiple relationship (such as 1.2 times, 1.5 times). For a line width range of 90 to 300nm, 90nm, 108nm (1.2 times), 135nm (1.5 times), 180nm (2 times), and 300nm (maximum value) can be selected as sampling points. In this way, the basic graphics corresponding to each device and the sampling points associated with it can be determined. Finally, the collected basic graphics, sampling points, and capacitance values are used to create a process capacitance library. Specifically, for discrete size parts, a fixed combination of sampling sizes (such as 20nm / 50nm) is combined with the base pattern to generate a device sampling pattern. For continuous size parts, the width and spacing of continuous sizes are freely combined (such as 90nm line width + 100nm spacing) to form multiple sampling patterns. Parasitic capacitance is extracted for each sampling pattern, and each sampling pattern and its corresponding capacitance value are stored in the capacitance library to form a structured data table.

[0083] In this way, this application combines a fixed combination of discrete sizes with a multiple scaling strategy of continuous sizes, which not only ensures the high precision of small-size devices, but also covers the diverse needs of large-size devices. At the same time, it simplifies the calculation process through the basic graphics library to achieve a balance between accuracy and efficiency.

[0084] The method for constructing a capacitor library of the present application includes: determining the device pattern type based on process technology documents; determining the basic pattern corresponding to the device structure based on the device pattern type; determining the sampling size of the basic pattern corresponding to each device structure based on device design rules; constructing the device sampling pattern based on the basic pattern corresponding to the device structure and the sampling size corresponding to the basic pattern; solving the parasitic capacitance corresponding to each device sampling pattern to form a capacitor library constructed from the device sampling patterns and their corresponding parasitic capacitance values. The technical solution of the present application improves the accuracy and efficiency of constructing the capacitor library by precalculating and storing different device pattern types and their corresponding parasitic capacitance values.

[0085] Based on the same inventive concept as the above embodiments, an embodiment of the present invention provides an electronic device, such as Figure 5 As shown, the electronic device includes: a processor 310 and a memory 311 storing a computer program; wherein, Figure 5The processor 310 shown in the figure is not used to indicate that the number of processors 310 is one, but is only used to indicate the positional relationship of the processor 310 relative to other devices. In actual applications, the number of processors 310 may be one or more; similarly, Figure 5 The memory 311 shown in the figure has the same meaning, that is, it is only used to refer to the position relationship of the memory 311 relative to other components. In actual application, the number of memories 311 can be one or more. When the processor 310 runs the computer program, the method for constructing the capacitor library applied to the above-mentioned electronic device is implemented.

[0086] The electronic device may also include: at least one network interface 312. The various components in the electronic device are coupled together via a bus system 313. It is understood that the bus system 313 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 5 Various buses are labeled as bus system 313.

[0087] Memory 311 may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disk, or compact disc read-only memory (CD-ROM); magnetic surface memory may include magnetic disk memory or magnetic tape memory. Volatile memory may include random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus random access memory (DRRAM).The memory 311 described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memories.

[0088] The memory 311 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic device. Examples of these data include: any computer program used to operate on the electronic device, such as an operating system and an application; contact data; phone book data; messages; pictures; videos, etc. Among them, the operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., which are used to implement various basic services and process hardware-based tasks. The application program can include various applications, such as a media player (Media Player), a browser (Browser), etc., which are used to implement various application services. Here, the program that implements the method of the embodiment of the present invention can be included in the application program.

[0089] Based on the same inventive concept as the above embodiment, this embodiment further provides a storage medium, wherein a computer program is stored in the storage medium. The storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a read-only optical disc (CD-ROM). It may also be various devices including one or any combination of the above memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc. When the computer program stored in the storage medium is executed by the processor, the method for constructing the above-mentioned capacitor library is implemented. For the specific steps implemented when the computer program is executed by the processor, please refer to the description of the above embodiment and will not be repeated here.

[0090] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion of elements other than the listed elements and may also include additional elements not specifically listed.

[0092] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for constructing a capacitor library, characterized in that: The method comprises the following steps: Determine the device pattern type based on process technology documents; Determining a basic graphic corresponding to a device structure according to the device graphic type; Determining a sampling size of the basic graphics corresponding to each of the device structures according to device design rules; assembling a device sampling pattern according to a basic pattern corresponding to the device structure and a sampling size corresponding to the basic pattern; The parasitic capacitance corresponding to each of the device sampling patterns is solved to form a capacitance library constructed by the device sampling patterns and their corresponding parasitic capacitance values.

2. The method according to claim 1, characterized in that The sampling size consists of a graphic width and a graphic interval. The graphic width refers to the width of a graphic corresponding to each device graphic type in the basic graphic. The graphic interval refers to the interval between graphics corresponding to each device graphic type in the basic graphic.

3. The method according to claim 2, characterized in that The type of the sampling size includes a discrete size, and a plurality of first widths and first intervals appearing in pairs are determined according to the discrete size. The value of the first width is a value consisting of discrete values determined according to design rules.

4. The method according to claim 3, characterized in that The step of forming a device sampling pattern according to a basic pattern corresponding to the device pattern type and a sampling size corresponding to the basic pattern includes: Based on fixed combinations of values of the first width and the first interval, the device sampling pattern corresponding to each combination is determined.

5. The method according to claim 3, characterized in that The sampling size type also includes a continuous size, and a plurality of second widths and second intervals appearing in pairs are determined according to the continuous size, and the value of the second width is a value in a preset continuous interval determined according to the design rule.

6. The method according to claim 5, characterized in that The preset value of the first width is smaller than the preset value range of the second width, and the first interval is smaller than the second interval.

7. The method according to claim 5, characterized in that The step of constructing a device sampling pattern according to a basic pattern corresponding to the device pattern type and a sampling size corresponding to the basic pattern further includes: Adjusting the sampling size corresponding to the continuous size to obtain a plurality of second widths and a plurality of second intervals; The plurality of second widths and the plurality of second intervals are combined to determine the device sampling pattern corresponding to each combination.

8. The method according to claim 7, characterized in that The adjusting the sampling size corresponding to the continuous size includes: The continuous dimensions are scaled proportionally so that the second widths in at least two combinations are in a preset multiple relationship, and the second intervals in at least two combinations are in a preset multiple relationship.

9. An electronic device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 8 when executing the computer program.

10. A storage medium, characterized in that: The storage medium stores a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 8.

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