Semiconductor device and method of manufacturing the same

Abstract

According to one embodiment, a semiconductor device includes a first insulating film, a first plug provided in the first insulating film, and a first wiring layer provided on the first insulating film. The device further includes a second insulating film including a first region provided on the first insulating film and having a first upper surface, and a second region provided on the first wiring layer and having a second upper surface higher than the first upper surface. The device further includes a second wiring layer including a first portion disposed on the first insulating film and the first plug, a second portion disposed on the first region, and a third portion disposed on the second region, and including a bond pad.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] When a wiring layer including bonding pads is disposed on a plug, defects may occur on the plug after the wiring layer is formed. For example, when a probe contacts the bonding pad, the plug may be damaged. Summary of the Invention

[0003] According to one embodiment, a semiconductor device includes a first insulating film, a first plug provided within the first insulating film, and a first wiring layer provided on the first insulating film. The device further includes a second insulating film including a first region provided on the first insulating film and having a first upper surface, and a second region provided on the first wiring layer and having a second upper surface higher than the first upper surface. The device further includes a second wiring layer including a first portion provided on the first insulating film and the first plug, a second portion provided on the first region, and a third portion provided on the second region, and including a bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0005] Figure 2 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0006] Figures 3 to 6 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0007] Figure 7 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0008] Figures 8 to 10 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0009] Figure 11 and Figure 12 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first comparative example of the first embodiment.

[0010] Figure 13 and Figure 14 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first modification of the first embodiment.

[0011] Figure 15 It is a plan view showing the structure of the semiconductor device according to the first embodiment.

[0012] Figures 16 to 18 These are plan views showing various examples of the structure of the semiconductor device according to the first embodiment.

[0013] Figures 19 to 22 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0014] Figure 23 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first comparative example of the first embodiment.

[0015] Figure 24 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Figure 25 and Figure 26 This is a cross-sectional view showing a first example of the method for manufacturing the semiconductor device according to the first embodiment.

[0017] Figure 27 and Figure 28 This is a cross-sectional view showing a second example of the method for manufacturing the semiconductor device according to the first embodiment.

[0018] Figure 29 This is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the first embodiment.

[0019] Figure 30 This is a cross-sectional view showing the structure of a semiconductor device according to a third modification of the first embodiment.

[0020] Figure 31 This is a cross-sectional view showing the structure of a semiconductor device according to a fourth modification of the first embodiment.

[0021] Figure 32 This is a cross-sectional view showing the structure of a semiconductor device according to a fifth modification of the first embodiment.

[0022] Figure 33 This is a cross-sectional view showing the structure of a semiconductor device according to a sixth modification of the first embodiment.

[0023] Figure 34 This is a cross-sectional view showing the structure of a semiconductor device according to a seventh modification of the first embodiment.

[0024] Figure 35 This is a cross-sectional view showing the structure of a semiconductor device according to an eighth modification of the first embodiment.

[0025] Figure 36 This is a cross-sectional view showing the structure of a semiconductor device according to a ninth modification of the first embodiment.

[0026] Figure 37 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.

[0027] Figure 38 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a first comparative example of the second embodiment.

[0028] Figure 39 This is a cross-sectional view for comparing the semiconductor device according to the second embodiment with the semiconductor device according to the first comparative example of the second embodiment.

[0029] Figure 40 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a first modification of the second embodiment.

[0030] Figure 41 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a second modification of the second embodiment.

[0031] Figure 42 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a third modification of the second embodiment.

[0032] Figure 43 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a fourth modification of the second embodiment.

[0033] Figure 44 sectional views showing the configurations of semiconductor devices according to fifth and sixth modifications of the second embodiment.

[0034] Figure 45 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a seventh modification of the second embodiment.

[0035] Figure 46 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to an eighth modification of the second embodiment.

[0036] Figure 47 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a ninth modification of the second embodiment.

[0037] Figure 48 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a tenth modification of the second embodiment.

[0038] Figure 49 1 and 2 are cross-sectional views illustrating the configurations of semiconductor devices according to the eleventh and twelfth modified examples of the second embodiment. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1 to 49In the drawings, the same components are given the same reference numerals and repeated descriptions are omitted.

[0040] (First embodiment)

[0041] Figure 1 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0042] The semiconductor device of this embodiment includes, for example, a three-dimensional semiconductor memory. As described later, the semiconductor device of this embodiment is manufactured by bonding an array wafer including an array chip 1 and a circuit wafer including a circuit chip 2 together.

[0043] Array chip 1 includes a memory cell array 11 including a plurality of memory cells, and an interlayer insulating film 12 below memory cell array 11. Interlayer insulating film 12 is, for example, a stacked film including a SiO2 film (silicon oxide film) and other insulating films. Interlayer insulating film 12 is an example of a first insulating film.

[0044] The circuit chip 2 is disposed under the array chip 1 . Figure 1 The bonding surface S between array chip 1 and circuit chip 2 is shown. Circuit chip 2 includes an interlayer insulating film 13 beneath interlayer insulating film 12 and a substrate 14 beneath interlayer insulating film 13. Interlayer insulating film 13 is, for example, a laminated film comprising a SiO2 film and other insulating films. Substrate 14 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Substrate 14 is an example of a first substrate.

[0045] Figure 1 The X and Y directions are parallel to and perpendicular to the surface of substrate 14, and the Z direction is perpendicular to the surface of substrate 14. The X, Y, and Z directions intersect with each other. In this specification, the +Z direction is considered the upward direction, and the -Z direction is considered the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0046] The array chip 1 includes multiple word lines WL, source select lines SGS, and drain select lines SGD as multiple electrode layers within the memory cell array 11. The source select lines SGS are arranged above these word lines WL, while the drain select lines SGD are arranged below these word lines WL. The memory cell array 11 includes multiple pillars CL that penetrate these word lines WL, source select lines SGS, and drain select lines SGD. These pillars CL extend in the Z direction.

[0047] Figure 1The figure shows a stepped structure 21 within the memory cell array 11 and a plurality of beams 22 provided within the stepped structure 21. These beams 22 extend in the Z direction. Each word line WL is electrically connected to the word wiring layer 24 via a contact plug 23. Each columnar portion CL is electrically connected to a bit line BL via a via plug 25 and is also electrically connected to a source line SL. The source line SL is provided above the source-side select line SGS, and the bit line BL is provided below the drain-side select line SGD. The source line SL is provided on each columnar portion CL so as to be in contact with the columnar portion CL. The source line SL forms part of the memory cell array 11.

[0048] The circuit chip 2 further includes a plurality of transistors 31 , a plurality of contact plugs 32 , a wiring layer 33 , a wiring layer 34 , a wiring layer 35 , a plurality of via plugs 36 , and a plurality of metal pads 37 within the interlayer insulating film 13 .

[0049] Each transistor 31 includes a gate insulating film 31a and a gate electrode 31b sequentially arranged on the substrate 14, and a source region and a drain region (not shown) arranged in the substrate 14. Each contact plug 32 is arranged on the gate electrode 31b, source region, or drain region of the corresponding transistor 31. The wiring layer 33 is arranged on the contact plug 32 and includes a plurality of wirings. The wiring layer 34 is arranged on the wiring layer 33 and includes a plurality of wirings. The wiring layer 35 is arranged on the wiring layer 34 and includes a plurality of wirings. The through-hole plug 36 is arranged on the wiring layer 35. The metal pad 37 is arranged on the through-hole plug 36. The metal pad 37 is, for example, a metal layer including a Cu (copper) layer. The circuit chip 2 functions as a circuit for controlling the operation of the array chip 1. The circuit is composed of transistors 31 and the like and is electrically connected to the metal pad 37.

[0050] The array chip 1 further includes a plurality of metal pads 41, a plurality of via plugs 42, a wiring layer 43, a wiring layer 44, and a plurality of via plugs 45 within the interlayer insulating film 12. The via plugs 45 are examples of first plugs and second plugs.

[0051] Metal pad 41 is provided on metal pad 37. Metal pad 41 is, for example, a metal layer including a Cu layer. The aforementioned circuit is electrically connected to memory cell array 11 via metal pads 37, 41, etc., and controls the operation of memory cell array 11 via metal pads 37, 41, etc. A via plug 42 is provided on metal pad 41. A wiring layer 43 is provided on contact plug 42 and includes a plurality of wirings. A wiring layer 44 is provided on wiring layer 43 and includes a plurality of wirings. The aforementioned bit line BL is included in wiring layer 44. A via plug 45 is provided on wiring layer 44. Via plug 45 is, for example, a metal plug including a W (tungsten) layer.

[0052] Array chip 1 further includes wiring layer 51, insulating film 52, insulating film 53, wiring layer 54, passivation insulating film 55, solder 56, and bonding wires 57 on interlayer insulating film 12. Wiring layer 51 is an example of a first wiring layer. Insulating film 53 is an example of a second insulating film. Wiring layer 54 is an example of a second wiring layer.

[0053] Wiring layer 51 is disposed on interlayer insulating film 12 and above source-side select line SGS. Wiring layer 51 is, for example, a metal layer including a W layer. Wiring layer 51 includes multiple wirings, such as wiring 51a. Wiring 51a is disposed on and electrically connected to the aforementioned plurality of columnar portions CL. Wiring 51a represents the aforementioned source line SL. At least a portion of wiring layer 51 may also be a semiconductor layer, such as a polysilicon layer.

[0054] The insulating film 52 is formed on the wiring layer 51. The insulating film 52 is, for example, a laminated film including a plurality of insulating films.

[0055] The insulating film 53 is formed on the interlayer insulating film 12, the wiring layer 51, and the insulating film 52. The insulating film 53 is, for example, a SiO2 film.

[0056] Wiring layer 54 is formed on interlayer insulating film 12 via wiring layer 51, insulating film 52, and insulating film 53. Wiring layer 54 is a metal layer including, for example, an Al (aluminum) layer. Wiring layer 54 includes a plurality of wirings, such as wiring 54a. Wiring 54a is arranged on interlayer insulating film 12, via plug 45, and insulating film 53, and is electrically connected to via plug 45. Parts of wiring 54a function as external connection pads (bonding pads) for the semiconductor device of this embodiment.

[0057] The passivation insulating film 55 is formed on the insulating film 53 and the wiring layer 54 and has an opening P that exposes the surface of the wiring 54a. The portion of the wiring 54a exposed in the opening P functions as the external connection pad described above. The wiring 54a can be connected to the mounting substrate or other devices through the opening P using bonding wires, solder balls, metal bumps, etc. Figure 1 There is shown a bonding wire 57 electrically connected to the wiring 54a (bonding pad) through the solder 56. The passivation insulating film 55 is, for example, a stacked film including a SiO2 film and a SiN film (silicon nitride film).

[0058] Figure 2 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0059] Figure 2 Shown Figure 1The memory cell array 11 shown in FIG. 1 includes a stacked film 61 including a plurality of electrode layers 61a and a plurality of insulating films 61b alternately stacked in the Z direction. These electrode layers 61a are separated from each other in the Z direction. Each electrode layer 61a functions as, for example, the aforementioned word line WL, source side selection line SGS, or drain side selection line SGD. Figure 2 The uppermost electrode layer 61a serves as the source select line SGS, the lowermost electrode layer 61a serves as the drain select line SGD, and the other electrode layers 61a serve as word lines WL. Each electrode layer 61a is, for example, a metal layer including a W layer. Each insulating film 61b is, for example, a SiO2 film.

[0060] Figure 2 Also shown Figure 1 One of the multiple columnar portions CL shown. Each columnar portion CL is provided within the stacked film 61 and has a columnar shape extending in the Z direction. Each columnar portion CL includes a blocking insulating film 62 provided on the side of the stacked film 61, a charge storage layer 63 provided on the side of the blocking insulating film 62, a tunnel insulating film 64 provided on the side of the charge storage layer 63, a channel semiconductor layer 65 provided on the side of the tunnel insulating film 64, and a core insulating film 66 provided on the side of the channel semiconductor layer 65. Each columnar portion CL, together with the word line WL, constitutes a cell transistor (memory cell), together with the source-side select line SGS, constitutes a source-side select transistor, and together with the drain-side select line SGD, constitutes a drain-side select transistor.

[0061] The blocking insulating film 62 is, for example, a SiO2 film. The charge storage layer 63 is, for example, an insulating film such as a SiN film. The charge storage layer 63 may also be a semiconductor layer such as a polysilicon layer. The charge storage layer 63 can store signal charges of the three-dimensional semiconductor memory. The tunnel insulating film 64 is, for example, a SiO2 film or a SiON film (silicon oxynitride film). The channel semiconductor layer 65 is, for example, a polysilicon layer. The channel semiconductor layer 65 functions as a channel of the three-dimensional semiconductor memory. The core insulating film 66 is, for example, a SiO2 film.

[0062] Figures 3 to 6 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0063] Figure 3 An array wafer W1 including a plurality of array chips 1 and a circuit wafer W2 including a plurality of circuit chips 2 are shown. Figure 3 The orientation of the array wafer W1 is Figure 1 The orientation of the array chip 1 is reversed. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. Figure 3 1 shows the array wafer W1 before being reversed for bonding. Figure 1The array chip 1 is shown after being reversed for bonding, bonded, and diced.

[0064] Figure 3 Also shown are the upper surface S1 of the array wafer W1 and the upper surface S2 of the circuit wafer W2. The array wafer W1 includes a substrate 15 below the memory cell array 11. The substrate 15 is, for example, a semiconductor substrate such as a Si substrate.

[0065] In this embodiment, first, Figure 3 As shown, a memory cell array 11, an interlayer insulating film 12, a stepped structure 21, a metal pad 41, a through-hole plug 45, etc. are formed on the substrate 15 of the array wafer W1, and an interlayer insulating film 13, a transistor 31, a contact plug 32, a metal pad 37, etc. are formed on the substrate 14 of the circuit wafer W2. Figure 4 As shown, the array wafer W1 and the circuit wafer W2 are bonded together using mechanical pressure so that the upper surface S1 and the upper surface S2 are opposite each other. As a result, the interlayer insulating film 12 and the interlayer insulating film 13 are bonded. Next, the array wafer W1 and the circuit wafer W2 are annealed. As a result, the metal pad 41 and the metal pad 37 are bonded. In this way, the substrate 15 and the substrate 14 are bonded together with the interlayer insulating films 12 and 13 sandwiched therebetween, and the memory cell array 11, the through-hole plug 45, etc. are formed (configured) above the substrate 14.

[0066] Then, the substrate 15 ( Figure 5 ). As a result, the interlayer insulating film 12, the columnar portion CL, the beam portion 22, the via plug 45, and the like are exposed.

[0067] Next, a wiring layer 51, an insulating film 52, an insulating film 53, a wiring layer 54, and a passivation insulating film 55 are sequentially formed on the interlayer insulating film 12, the columnar portion CL, the beam portion 22, and the via plug 45 ( Figure 6 ). The wiring 51a (source line SL) in the wiring layer 51 is formed on the columnar portion CL and the beam portion 22. The wiring 54a in the wiring layer 54 is formed on the interlayer insulating film 12, the via plug 45 and the insulating film 53, and is exposed in the opening P of the passivation insulating film 55. Next, the substrate 14 is thinned by CMP and / or wet etching, and the array wafer W1 and the circuit wafer W2 are cut into multiple chips. Then, the bonding wire 57 is electrically connected to the wiring 54a (bonding pad) by solder 56 ( Figure 6 ). This creates Figure 1 The semiconductor device shown.

[0068] In addition, although Figure 1The interface between interlayer insulating film 12 and interlayer insulating film 13, and the interface between metal pad 41 and metal pad 37 are shown. However, these interfaces are usually not observed after the annealing. However, the positions of these interfaces can be estimated by, for example, detecting the side surface of metal pad 41, the inclination of the side surface of metal pad 37, or the positional offset between the side surfaces of metal pad 41 and metal pad 37.

[0069] Figure 7 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0070] Figure 7 Zoomed in to show Figure 1 Specifically, Figure 7 The interlayer insulating film 12 , the wiring layer 51 , the insulating film 52 , the insulating film 53 , the wiring layer 54 , the passivation insulating film 55 , the solder 56 , and the bonding wire 57 are shown.

[0071] The wiring layer 51 and the insulating film 52 are sequentially formed on the interlayer insulating film 12. The insulating film 52 includes an insulating film 71 formed on the wiring layer 51, an insulating film 72 formed on the insulating film 71, and an insulating film 73 formed on the insulating film 72.

[0072] Insulating film 53 includes: region A1 formed on wiring layer 51 with insulating film 52 interposed therebetween; region A2 formed on the sides of wiring layer 51 and insulating film 52; and region A3 formed on interlayer insulating film 12. As described later, insulating film 53 is formed on interlayer insulating film 12, wiring layer 51, and insulating film 52 after forming wiring layer 51 and insulating film 52 on interlayer insulating film 12 and removing portions of wiring layer 51 and insulating film 52 by etching. Therefore, insulating film 53 includes not only region A1 but also regions A2 and A3. The upper surface of region A1 is higher than the upper surface of region A3. Region A3 is an example of a first region having a first upper surface. Region A1 is an example of a second region having a second upper surface.

[0073] The wiring layer 54 is formed on the interlayer insulating film 12 via the wiring layer 51, the insulating film 52, and the insulating film 53. As will be described later, the wiring layer 54 is formed on the interlayer insulating film 12, the via plug 45, and the insulating film 53 after the insulating film 53 is formed and a portion of the insulating film 53 is removed by etching. Figure 7 The wiring 54a shown includes a portion formed on the interlayer insulating film 12 and the via plug 45, a portion formed on the region A3 of the insulating film 53, and a portion formed on the region A1 of the insulating film 53. The portion on the interlayer insulating film 12 and the via plug 45 is an example of a first portion. The portion on the region A3 of the insulating film 53 is an example of a second portion. The portion on the region A1 of the insulating film 53 is an example of a third portion. Figure 7 In the embodiment, the upper surface of the second portion is higher than the upper surface of the first portion, and the upper surface of the third portion is higher than the upper surface of the second portion.

[0074] The portion of the wiring 54a on the interlayer insulating film 12 and the via plug 45 includes a portion B1 provided on the interlayer insulating film 12 and a plurality of portions B2 protruding downward from the portion B1. Each portion B2 is provided on a corresponding via plug 45. Figure 7 In FIG, the left portion B2 is provided on the left through-hole plug 45, and the right portion B2 is provided on the right through-hole plug 45, and these portions B2 are separated from each other. The height of the upper end (upper surface) of each through-hole plug 45, that is, the height of the lower surface of each portion B2 is lower than the height of the lower surface of portion B1. Portion B1 is an example of an upper portion. Portion B2 is an example of a lower portion (a first lower portion and a second lower portion). In Figure 7 In the embodiment, each portion B2 is provided on a corresponding via plug 45 and on the interlayer insulating film 12 around the via plug 45 .

[0075] exist Figure 7 In FIG, a probe trace C is formed on the wiring 54a (bonding pad). Figure 7 The illustrated probe mark C is formed at the boundary between the portion of wiring 54a that is on interlayer insulating film 12 (first portion) and the portion that is on area A3 (second portion). As will be described later, probe mark C is formed when a probe is brought into contact with a bonding pad for inspection of the semiconductor device of this embodiment. The first and second portions of wiring 54a may be separated by probe mark C, or they may be connected to each other at a portion other than probe mark C. When the first and second portions are separated by probe mark C, the first and second portions are electrically connected to each other via solder 56.

[0076] In this embodiment, openings are formed in the wiring layer 51 and the insulating film 52 , and a portion of the insulating film 53 is formed in the openings. Figure 7 The area BA where the opening is formed is shown. Since the insulating film 53 has a recessed shape within the area BA, the wiring layer 54 has a recessed shape within the area TV. In this embodiment, an opening is also formed in the insulating film 53, and a portion of the wiring layer 54 is formed within this opening. Figure 7 The area VA where the opening is formed is shown. Area A3 and the like of insulating film 53 are included in area BA, the second portion of wiring layer 54 and the like are included in area TV, and the first portion of wiring layer 54 and the like are included in area VA. Areas BA, TV, and VA will be described in more detail later.

[0077] Figures 8 to 10It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. Figures 8 to 10 Shows the formation Figure 7 The construction process shown.

[0078] First, a wiring layer 51, an insulating film 52, an insulating film 53, a wiring layer 54, and a passivation insulating film 55 are formed on the interlayer insulating film 12 ( Figure 8 ). Next, the probe 74 is brought into contact with the wiring 54a (bonding pad) to inspect the semiconductor device of this embodiment ( Figure 9 As a result, the wiring 54a in the region R is pressed by the probe 74, and a probe mark C is formed on the wiring 54a ( Figure 10 ). After that, the bonding wire 57 is electrically connected to the wiring 54a through the solder 56.

[0079] Figure 9 The width PR of the probe 74 in the X direction is shown. In this embodiment, the width PR of the probe 74 is shorter than the width of the opening P of the passivation insulating film 55 in the X direction. Thus, the probe 74 can be inserted into the opening P. In this embodiment, further, the width PR of the probe 74 is longer than the width of the portions B1 and B2 (first portion) of the wiring 54a in the X direction. Thus, the portions B1 and B2 can be effectively protected from the influence of the probe 74 (details will be described later). Figure 9 In FIG, the width of portions B1 and B2 in the X direction is the width of the upper surface of portion B1 in the X direction.

[0080] The probe 74 has a width PR of, for example, 10 μm or greater. In this embodiment, the width PR is 10 μm to 20 μm, for example, 12 μm to 20 μm. Meanwhile, the width of the portions B1 and B2 of the wiring 54 a in the X direction is, for example, less than 10 μm.

[0081] Next, the semiconductor device according to the first embodiment is compared with the semiconductor device according to the first comparative example of the first embodiment.

[0082] Figure 11 and Figure 12 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first comparative example of the first embodiment. Figure 11 and Figure 12 Corresponding to Figure 8 and Figure 9 .

[0083] First, a wiring layer 51, an insulating film 52, an insulating film 53, a wiring layer 54, and a passivation insulating film 55 are formed on the interlayer insulating film 12 ( Figure 11The insulating film 53 of this comparative example has regions A1 and A2, but does not have region A3. Furthermore, in this comparative example, the wiring 54a has portion B1 but does not have portion B2, and the top end of each via plug 45 is higher than the bottom surface of portion B1. Consequently, the top of each via plug 45 protrudes into the interior of the wiring 54a.

[0084] Next, the semiconductor device of this comparative example is inspected by bringing the probe 74 into contact with the wiring 54a (bonding pad). Figure 12 At this time, the pressure from the probe 74 may damage the via plug 45. For example, a crack may be generated in the via plug 45 as shown by an arrow D1, or the upper portion of the via plug 45 may be chipped as shown by an arrow D2.

[0085] On the other hand, the insulating film 53 of this embodiment has regions A1 to A3 ( Figure 8 ). In addition, in this embodiment, the wiring 54a has parts B1 and B2, and the height of the upper end of each via plug 45 is lower than the height of the lower surface of the part B1 ( Figure 8 ). This can prevent the occurrence of cracks on the via plug 45 or the upper portion of the via plug 45 from being damaged ( Figure 9 The first reason is that the region A3 can prevent the probe 74 from getting too close to the via plug 45. The second reason is that since the upper portion of the via plug 45 does not protrude into the wiring 54a, the upper portion of the via plug 45 is less likely to be damaged.

[0086] As described above, the X-direction width PR of probe 74 in this embodiment is greater than the X-direction widths of portions B1 and B2 of wiring 54a. As a result, when probe 74 approaches via plug 45, the lower surface of probe 74 collides with the upper surface of area A3. Thus, area A3 prevents probe 74 from approaching via plug 45 too closely. By making probe 74's width PR greater than the widths of portions B1 and B2, probe 74 will collide with area A3 even if its position shifts in the X-direction.

[0087] Figure 13 and Figure 14 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first modification of the first embodiment. Figure 11 and Figure 12 Corresponding to Figure 8 and Figure 9 .

[0088] First, a wiring layer 51, an insulating film 52, an insulating film 53, a wiring layer 54, and a passivation insulating film 55 are formed on the interlayer insulating film 12 ( Figure 13The insulating film 53 of this modification has regions A1 to A3. This is the same as the first embodiment. Meanwhile, in this modification, the wiring 54a has portion B1 but not portion B2, and the top end of each via plug 45 is higher than the bottom surface of portion B1. Consequently, the top of each via plug 45 protrudes into the interior of the wiring 54a. This is the same as the first comparative example.

[0089] According to this modification, it is possible to suppress the occurrence of cracks in the via plug 45 or the chipping of the upper portion of the via plug 45 ( Figure 14 The reason is that the region A3 can prevent the probe 74 from excessively approaching the via plug 45. This is the same as the first embodiment.

[0090] On the other hand, according to the first embodiment, it is possible to further suppress the occurrence of cracks in the via plug 45 or the chipping of the upper portion of the via plug 45 ( Figure 9 The reason is that, since the upper portion of the via plug 45 does not protrude into the interior of the wiring 54a, the upper portion of the via plug 45 is less likely to be damaged.

[0091] [Planar Structure of Semiconductor Device According to First Embodiment]

[0092] Figure 15 It is a plan view showing the structure of the semiconductor device according to the first embodiment.

[0093] Figure 15 Shown Figure 7 The illustrated region TV and region VA, as well as a plurality of via plugs 45 disposed beneath region VA, are shown. Region TV is generally square in shape, but may be of other shapes (e.g., rectangular). Similarly, region VA is generally rectangular extending in the Y direction, but may be of other shapes (e.g., square). Figure 15 The area VA is shown to be located within the area TV.

[0094] exist Figure 15 In FIG. 4 , the number of via plugs 45 is 45 (=3×15), but other numbers may be used. Figure 7 yes Figure 15 The XZ cross-sectional view of the top view, so Figure 7 The number of through-hole plugs 45 shown should be exactly 3. However, for the convenience of drawing, Figure 7 Only two via plugs 45 are shown.

[0095] Figures 16 to 18 These are plan views showing various examples of the structure of the semiconductor device according to the first embodiment.

[0096] Figure 16 (a) and Figure 15Similarly, the area TV and the area VA set within the area TV are shown. Figure 16 (a) omits the illustration of the via plug 45 provided under the area VA (the same applies hereinafter).

[0097] Figure 16 (b)~ Figure 16 (d) and Figure 16 (a) similarly shows the area TV and the area VA set within the area TV. However, Figure 16 The area VA of (a) is arranged near the center of the area TV. In contrast, Figure 16 The area VA of (b) is arranged near the end of the area TV. Figure 16 The area VA of (c) is configured outside the area TV. Figure 16 The area VA of (d) is configured to partially overlap with the area TV. Therefore, Figure 16 A portion of the area VA of (d) is arranged in the area TV, Figure 16 The remaining part of the area VA of (d) is arranged outside the area TV.

[0098] Figure 17 (a)~ Figure 17 (d) shows the region TV and a plurality of regions VA arranged in the region TV. Each region VA is arranged in the region TV, outside the region TV, or partially overlapped with the region TV.

[0099] Figure 18 (a)~ Figure 18 (d) shows the region TV and one or more regions VA provided in the region TV. These regions VA have various shapes. For example, Figure 18 The area VA in (c) has a shape formed by combining three rectangles. Figure 18 The region VA in (d) has a shape formed by combining four rectangles and has a ring shape.

[0100] [Method for Manufacturing Semiconductor Device According to First Embodiment]

[0101] Figures 19 to 22 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. Figure 19 (a)~ Figure 22 (b) shows Figure 8 Details of the process shown.

[0102] First, a wiring layer 51 and an insulating film 52 are sequentially formed on the interlayer insulating film 12 and the via plug 45 ( Figure 19(a)). The insulating film 52 is formed by sequentially forming insulating films 71, 72, and 73 on the wiring layer 51. The via plug 45 is formed in the interlayer insulating film 12 before the array wafer W1 and the circuit wafer W2 are bonded together (see Figure 3 ).exist Figure 19 In (a), the height of the upper end of the via plug 45 is higher than the height of the upper surface of the interlayer insulating film 12 (the lower surface of the wiring layer 51 ).

[0103] Next, a recess H1 ( Figure 19 (b)). As a result, the upper end of the via plug 45 is exposed in the recess H1. Furthermore, a wiring 51a (source line SL) is formed in the wiring layer 51. The shape of the area BA is determined by the shape of the recess H1. The recess H1 is an example of a first recess.

[0104] Next, an insulating film 53 is formed on the interlayer insulating film 12, the via plug 45, the wiring layer 51, and the insulating film 52 ( Figure 20 As a result, the upper end of the via plug 45 is covered with the insulating film 53. The insulating film 53 is formed so as to include the regions A1, A2, and A3.

[0105] Next, a recess H2 ( Figure 20 (b)). As a result, the upper end of the via plug 45 is exposed in the recess H2. In addition, the region A3 of the insulating film 53 is partially removed and processed into Figure 7 The shape of the region VA is determined by the shape of the recess H2. The recess H2 is an example of a second recess.

[0106] Next, the exposed portion of the via plug 45 in the recess H2 and the exposed surface of the interlayer insulating film 12 are processed by etching ( Figure 21 (a)). As a result, the height of the upper end of the via plug 45 and the height of the upper surface of the interlayer insulating film 12 within the recess H2 become lower than before etching. In this embodiment, the via plugs 45 outside the interlayer insulating film 12 are removed, and the via plugs 45 within the interlayer insulating film 12 are also partially removed. As a result, recesses H3 are formed in the interlayer insulating film 12 near each via plug 45, and the upper end of each via plug 45 descends toward the bottom of the recess H3. Figure 21 (a) shows the left recess H3 formed on the left via plug 45 and the right recess H3 formed on the right via plug 45. The recess H3 is an example of a third recess. Figure 21 Further details of the step (a) will be described later.

[0107] Next, a wiring layer 54 is formed on the interlayer insulating film 12, the via plug 45, the wiring layer 51, the insulating film 52, and the insulating film 53, and the wiring layer 54 is processed by photolithography and RIE ( Figure 21 As a result, the upper end of the via plug 45 is covered with the wiring layer 54. The wiring layer 54 is formed and processed so as to include the wiring 54a. Figure 21 Wiring 54a shown in (b) includes a portion formed on the interlayer insulating film 12 and the via plug 45 (first portion), a portion formed on region A3 of the insulating film 53 (second portion), and a portion formed on region A1 of the insulating film 53 (third portion). The portion of wiring 54a formed on the interlayer insulating film 12 and the via plug 45 includes a portion B1 provided on the interlayer insulating film 12 and a plurality of portions B2 protruding downward from portion B1. Portion B1 is formed within recess H2, and portion B2 is formed within recess H3.

[0108] Next, a passivation insulating film 55 ( Figure 22 (a)), the passivation insulating film 55 is processed by photolithography and RIE ( Figure 22 As a result, an opening P is formed in the passivation insulating film 55, and a portion of the wiring 54a exposed in the opening P becomes a bonding pad.

[0109] Next, the method for manufacturing the semiconductor device according to the first embodiment is compared with the method for manufacturing the semiconductor device according to the first comparative example of the first embodiment.

[0110] Figure 23 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first comparative example of the first embodiment.

[0111] Figure 23 (a) corresponds to Figure 20 In this comparative example, the exposed portion of the via plug 45 in the recess H2 and the exposed surface of the interlayer insulating film 12 are processed by etching ( Figure 23 As a result, the height of the upper end of the via plug 45 and the height of the upper surface of the interlayer insulating film 12 in the recess H2 become lower than before etching.

[0112] Figure 23 (b) shows the lowering distance of the upper surface of the interlayer insulating film 12 by arrow E1, and shows the lowering distance of the upper end of the via plug 45 by arrow E2. The etching of this comparative example is performed so that the lowering distance E1 of the upper surface of the interlayer insulating film 12 and the lowering distance E2 of the upper end of the via plug 45 are substantially equal. Figure 23 Same as (a), Figure 23The height of the upper end of the via plug 45 in (b) is higher than the height of the upper surface of the interlayer insulating film 12 near the via plug 45. Specifically, the difference between the height of the upper end of the via plug 45 and the height of the upper surface of the interlayer insulating film 12 near the via plug 45 is Figure 23 (a) and Figure 23 The etching in this comparative example is, for example, RIE.

[0113] Figure 24 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0114] Figure 24 (a) corresponds to Figure 20 In this embodiment, the exposed portion of the via plug 45 in the recess H2 and the exposed surface of the interlayer insulating film 12 are processed by etching ( Figure 24 As a result, the height of the upper end of the via plug 45 and the height of the upper surface of the interlayer insulating film 12 in the recess H2 become lower than before etching. Figure 24 (b) corresponds to Figure 21 (a).

[0115] Figure 24 (b) also shows the lowering distance of the upper surface of the interlayer insulating film 12 by arrow E1, and the lowering distance of the upper end of the via plug 45 by arrow E2. The etching of this embodiment is performed so that the lowering distance E2 of the upper end of the via plug 45 is greater than the lowering distance E1 of the upper surface of the interlayer insulating film 12. Therefore, Figure 24 The height of the upper end of the via plug 45 in (b) is lower than the height of the upper surface of the interlayer insulating film 12 near the via plug 45. An example of the etching in this embodiment will be described later.

[0116] Figure 25 and Figure 26 This is a cross-sectional view showing a first example of the method for manufacturing the semiconductor device according to the first embodiment.

[0117] Figure 25 (a) corresponds to Figure 20 In this example, first, a sacrificial film 77 is formed on the interlayer insulating film 12, the via plug 45, the wiring layer 51, the insulating film 52, and the insulating film 53. Figure 25 (b)). The sacrificial film 77 is, for example, a metal film formed by PVD (Physical Vapor Deposition). The sacrificial film 77 is formed to include a portion 77a formed on the surfaces of the interlayer insulating film 12, the wiring layer 51, the insulating film 52, and the insulating film 53, and a portion 77b formed near the upper end of the via plug 45. Figure 25 In (b), a portion of each via plug 45 is exposed between the portion 77a and the portion 77b. The sacrificial film 77 is an example of a first film.

[0118] Next, the sacrificial film 77 and the via plug 45 are processed by isotropic etching ( Figure 25 (b)). The isotropic etching is performed by simultaneously introducing an etchant gas and an ion beam into a chamber that houses the array wafer W1 and the circuit wafer W2. Figure 25 As shown by the arrow in (b), the ion beam is introduced into the chamber in a manner that travels in a direction oblique to the surface (XY plane) of the substrate 14. Therefore, the ion beam is incident on the exposed portion of each via plug 45 from an oblique direction (a direction oblique to the XY plane). As a result, the exposed portion of each via plug 45 is etched laterally from the side of each via plug 45 by the ion beam. At this time, the sacrificial film 77 is also etched by the etchant gas and the ion beam. If any sacrificial film 77 remains after the isotropic etching is completed, the remaining sacrificial film 77 is removed.

[0119] Figure 26 (a) shows the array wafer W1 after the isotropic etching is completed. The above-mentioned isotropic etching is performed in a state where the surface of the interlayer insulating film 12 is covered with the sacrificial film 77. As a result, the isotropic etching can be performed in a manner such that the lowering distance E2 of the upper end of the via plug 45 is greater than the lowering distance E1 of the upper surface of the interlayer insulating film 12 (see Figure 24 As a result, a recess H3 is formed in the interlayer insulating film 12 near each via plug 45 , and the upper end of each via plug 45 descends toward the bottom of the recess H3 . Figure 26 (a) corresponds to Figure 21 (a).

[0120] Next, a wiring layer 54 is formed on the interlayer insulating film 12, the via plug 45, the wiring layer 51, the insulating film 52, and the insulating film 53, and the wiring layer 54 is processed by photolithography and RIE ( Figure 26 As a result, the upper end of the via plug 45 is covered with the wiring layer 54 . Figure 26 (b) corresponds to Figure 21 (b).

[0121] Then, proceed Figure 22 (a) and Figure 22 In addition, Figure 9 and Figure 10 As a result, a product having Figure 7 A semiconductor device having the structure shown.

[0122] Figure 27 and Figure 28This is a cross-sectional view showing a second example of the method for manufacturing the semiconductor device according to the first embodiment.

[0123] Figure 27 (a) corresponds to Figure 20 In this example, first, an insulating film 78 is formed on the interlayer insulating film 12, the via plug 45, the wiring layer 51, the insulating film 52, and the insulating film 53. Figure 27 (b)). The insulating film 78 is, for example, a SiO2 film formed by CVD (Chemical Vapor Deposition). The insulating film 78 is formed so as to cover each via plug 45. Therefore, Figure 27 Each via plug 45 shown in (b) is embedded in the interlayer insulating film 12 and the insulating film 78. The insulating film 78 is an example of a third insulating film.

[0124] Next, the insulating film 78 is processed by RIE etching back ( Figure 28 (a)). As a result, the insulating film 78 is thinned by etching, and the upper end of each via plug 45 is exposed from the insulating film 78. In addition, a recess H3' is formed in the insulating film 78 near each via plug 45, and the upper end of each via plug 45 descends toward the bottom of the recess H3'. Figure 28 In (a), the height of the upper end of each via plug 45 is lower than the height of the upper surface of the insulating film 78 outside the recess H3' and higher than the height of the upper surface of the interlayer insulating film 12 near each via plug 45. The recess H3' is an example of a fourth recess.

[0125] Next, a wiring layer 54 is formed on the via plug 45 and the insulating film 78, and the wiring layer 54 is processed by photolithography and RIE ( Figure 28 As a result, the upper end of the via plug 45 is covered with the wiring layer 54. The wiring layer 54 is formed and processed so as to include the wiring 54a. Figure 28 The wiring 54a shown in (b) is formed on the interlayer insulating film 12 via the insulating film 78, and includes: a portion formed on the via plug 45 (first portion), a portion formed on the region A3 of the insulating film 53 via the insulating film 78 (second portion), and a portion formed on the region A1 of the insulating film 53 via the insulating film 78 (third portion). The first portion includes: a portion B1 provided on the interlayer insulating film 12 via the insulating film 78, and a plurality of portions B2 protruding downward from the portion B1. Figure 28 In (b), the portion B1 is formed in the recess H2, and the portion B2 is formed in the recess H3'.

[0126] Then, proceed Figure 22 (a) and Figure 22 In addition, Figure 9 and Figure 10 As a result, a product having Figure 7 The semiconductor device has an insulating film 78 added to the structure shown.

[0127] [Semiconductor Device According to Modification of First Embodiment]

[0128] Figure 29 This is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the first embodiment.

[0129] The semiconductor device of this modification has Figure 7 However, the upper end of the via plug 45 in this modification is higher than the lower surface of the portion B1 of the wiring 54a. Therefore, the wiring 54a in this modification does not include the portion B2.

[0130] Furthermore, the wiring layer 54 of this modified example includes a metal layer 75 formed on the interlayer insulating film 12, the via plug 45, the wiring layer 51, the insulating film 52, and the insulating film 53, and a metal layer 76 formed on the metal layer 75. The metal layer 76 is formed of a material different from that of the metal layer 75. The metal layer 75 is, for example, a stacked film including a W layer, a TiN (titanium nitride) layer, and a Ti (titanium) layer. The metal layer 76 is, for example, an Al layer. The metal layers 75 and 76 are examples of the first layer and the second layer, respectively.

[0131] According to this modification, it is possible to suppress the occurrence of cracks in the via plug 45 or the upper portion of the via plug 45 from being damaged. The first reason is that the region A3 can block the probe 74 (see Figure 9 ) too close to the via plug 45. The second reason is that the upper portion of the via plug 45 is less likely to be damaged because the upper portion of the via plug 45 is protected by the metal layer 75. When the metal layer 75 includes a W layer, the W layer has a high Young's modulus, so the upper portion of the via plug 45 can be effectively protected by the metal layer 75.

[0132] The semiconductor device of this modification can be used, for example, Figure 13 and Figure 14 The method shown is used for manufacturing. Figure 13 In the process shown, the wiring layer 54 is formed in a state where the upper end of the via plug 45 is higher than the bottom surface of the recess H2 (the upper surface of the interlayer insulating film 12 near the via plug 45). At this time, the wiring layer 54 of this modification is formed by sequentially forming the metal layers 75 and 76. Figure 29 The structure shown.

[0133] Figure 30 This is a cross-sectional view showing the structure of a semiconductor device according to a third modification of the first embodiment.

[0134] The semiconductor device of this modification has Figure 29 However, the width of the portion B1 of the wiring 54a in the second modification example in the X direction is larger than the width PR of the probe 74 in the X direction (see FIG. Figure 9 ) is shorter, the width of portion B1 of wiring 54a in the present modification example in the X direction is longer than the width PR in the X direction of probe 74. Region A3 of the second modification example is arranged at a position partially overlapping with opening P in plan view, but region A3 of the present modification example is arranged at a position not overlapping with opening P in plan view.

[0135] According to the second modification, due to the first and second reasons described above, it is possible to suppress the occurrence of cracks in the via plug 45 or the chipping of the upper portion of the via plug 45. On the other hand, according to this modification, due to the second reason described above, it is possible to suppress the occurrence of cracks in the via plug 45 or the chipping of the upper portion of the via plug 45.

[0136] Figure 31 This is a cross-sectional view showing the structure of a semiconductor device according to a fourth modification of the first embodiment.

[0137] The semiconductor device of this modification has Figure 7 However, the wiring 54a of this modification has one portion B2 on the plurality of via plugs 45. In other words, Figure 31 The portion B2 shown is shared by the left through-hole plug 45 and the right through-hole plug 45. According to the portion B2 of this modification, the same Figure 7 The same effect is shown in part B2.

[0138] Figure 32 This is a cross-sectional view showing the structure of a semiconductor device according to a fifth modification of the first embodiment.

[0139] The semiconductor device of this modification has Figure 29 The structure of the semiconductor device of the second modification shown in FIG. However, compared with the second modification where the metal layer 75 covers the upper portions of the plurality of via plugs 45 separately, the metal layer 75 of this modification covers the upper portions of the plurality of via plugs 45 collectively. Therefore, Figure 29 Two protruding portions of the metal layer 75 are shown, and Figure 32 1 shows a protruding portion of the metal layer 75. According to the wiring 54a of this modification, the same effects as those of the wiring 54a of the second modification can be obtained.

[0140] Figure 33 This is a cross-sectional view showing the structure of a semiconductor device according to a sixth modification of the first embodiment.

[0141] Figure 33 The array region R1 and pad region R2 included in the semiconductor device of this modification are shown. The array region R1 includes a memory cell array 11 (see Figure 1 ), the pad region R2 includes wiring 54a that functions as a bonding pad. Figure 33 The pad region R2 shown has Figure 7 However, in this modification, the wiring 51a (source line SL) is not arranged near the wiring 54a but is arranged within the array region R1. Figure 33 A plurality of columnar portions CL arranged under the wiring 51 a in the array region R1 are shown.

[0142] The wiring layer 54 of this modified example includes wiring 54a included in pad region R2, and wirings 54b and 54c included in array region R1. Wiring 54b is formed on interlayer insulating film 12, via plug 45, and insulating film 53, and is electrically connected to via plug 45. Wiring 54c is formed on wiring 51a, insulating film 52, and insulating film 53, and is electrically connected to wiring 51a.

[0143] Wiring 54b includes a portion B3 having the same shape as portion B1 of wiring 54a and a portion B4 having the same shape as portion B2 of wiring 54a. Portion B3 is provided on interlayer insulating film 12. Portion B4 protrudes downward from portion B3 and is provided on via plug 45. However, wiring 54b is not exposed in opening P of passivation insulating film 55 and does not function as a pad.

[0144] According to the wiring 54a in the pad region R2 of this modification, it is possible to obtain Figure 7 The same effect is achieved as shown in the wiring 54a.

[0145] Figure 34 This is a cross-sectional view showing the structure of a semiconductor device according to a seventh modification of the first embodiment.

[0146] The semiconductor device of this modification has Figure 33 The structure of the semiconductor device of the sixth modification shown in FIG. However, the wiring 54b of this modification has a structure including the portion B3 but not including the portion B4. In other words, the wiring 54b of this modification has a structure including the portion B1 but not including the portion B2. Figure 13 The wiring 54a shown has the same structure.

[0147] In this modification, the wiring 54a functions as a bonding pad, but the wiring 54b does not function as a bonding pad. Therefore, the wiring 54b is not subjected to bonding. Figure 9Therefore, the wiring 54b may be formed so as not to include the portion B4 as in this modification.

[0148] Figure 35 This is a cross-sectional view showing the structure of a semiconductor device according to an eighth modification of the first embodiment.

[0149] The semiconductor device of this modification has Figure 33 The structure is the same as that of the semiconductor device of the sixth modification shown in FIG. However, the wiring layer 54 of this modification includes metal layers 75 and 76. In this modification, the wiring 54a includes the portion B1 but does not include the portion B2, and the wiring 54b includes the portion B3 but does not include the portion B4. In other words, the wirings 54a and 54b of this modification have the same Figure 29 The wiring 54a shown has the same structure.

[0150] According to the wiring 54a in the pad region R2 of this modification, it is possible to obtain Figure 29 The same effect is achieved as shown in the wiring 54a.

[0151] Figure 36 This is a cross-sectional view showing the structure of a semiconductor device according to a ninth modification of the first embodiment.

[0152] The semiconductor device of this modification has Figure 35 The structure of the semiconductor device of the eighth modification shown in FIG. However, in this modification, wiring layer 54 includes metal layers 75 and 76 in pad region R2 and only metal layer 76 in array region R1. Therefore, in this modification, wiring 54a includes metal layers 75 and 76, while wirings 54b and 54c only include metal layer 76.

[0153] In this modification, the wiring 54a functions as a bonding pad, but the wiring 54b does not function as a bonding pad. Therefore, the wiring 54b is not subjected to bonding. Figure 9 Therefore, the wiring 54b may be formed without including the metal layer 75 as in this modification.

[0154] As described above, the semiconductor device of this embodiment includes an insulating film 53 having regions A1 to A3, and a wiring layer 54 provided on the insulating film 53 and the via plug 45 and including a bonding pad. Therefore, according to this embodiment, it is possible to form a suitable via plug 45. For example, it is possible to prevent the via plug 45 from being damaged when the probe 74 contacts the bonding pad.

[0155] (Second embodiment)

[0156] Figure 37 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.

[0157] The semiconductor device of this embodiment has Figure 7 The semiconductor device shown is constructed similarly. Figure 37 (a) shows a planar structure of the semiconductor device of this embodiment. Figure 37 (b) shows the Figure 37 The XZ cross section of the line XX' shown in (a). Figure 37 (c) shows the Figure 37 YZ cross section along the line YY' shown in (a).

[0158] like Figure 37 (b) and Figure 37 As shown in (c) of FIG. 1 , the semiconductor device of this embodiment includes an interlayer insulating film 12, a plurality of via plugs 45, a wiring layer 51, an insulating film 52, an insulating film 53, a wiring layer 54, a passivation insulating film 55, solder 56, and bonding wires 57. The passivation insulating film 55 includes insulating films 81, 82, and 83 formed on the insulating film 53 and the wiring layer 54 in this order.

[0159] exist Figure 37 (b) and Figure 37 In (c), wiring layer 54 includes wiring 54a including a bonding pad, and wiring layer 51 includes wiring 51b different from wiring 51a (source line SL). Wiring 51b is provided below wiring 54a via insulating films 53 and 52 and does not contact wiring 54a. Figure 37 (a) shows the planar shapes of the region TV, the region VA, the wiring 51a, and the wiring 54b.

[0160] like Figure 37 (a)~ Figure 37 As shown in (c), the semiconductor device of this embodiment further includes a plurality of dummy plugs 45' arranged at the same height as the through-hole plugs 45. Each through-hole plug 45 functions as a plug for controlling the semiconductor device of this embodiment, whereas each dummy plug 45' does not function as a plug for controlling the semiconductor device of this embodiment. For example, each through-hole plug 45 is used to connect the memory cell array 11 or the transistor 31 (see Figure 1 ) or the like, or is used as a plug to which a signal voltage is supplied from the device, but each dummy plug 45' is not used as such a plug. Figure 37 (a)~ Figure 37 In (c), each dummy plug 45 ′ is not electrically connected to a device or a bonding pad in the semiconductor device of this embodiment. Figure 37 (a)~ Figure 37(c) In order to distinguish the via plug 45 from the dummy plug 45', the via plug 45 is shown with sparse hatching and the dummy plug 45' is shown with dense hatching. The dummy plug 45' is an example of a third plug.

[0161] exist Figure 37 (b) and Figure 37 In (c), the dummy plug 45' is provided on the lower surface of the wiring 51b in the interlayer insulating film 12 and is electrically connected to the wiring 51b. The wiring 51b is not electrically connected to the device or bonding pad in the semiconductor device of this embodiment, similarly to the dummy plug 45'. Figure 3 In the illustrated process, the dummy plugs 45 are formed simultaneously with the via plugs 45 using the same material as the via plugs 45. Therefore, the dummy plugs 45' are metal plugs including a W layer, for example, similarly to the via plugs 45. In this embodiment, each via plug 45 is disposed on the wiring layer 44, while each dummy plug 45' is not disposed on the wiring layer 44.

[0162] Figure 37 (a) shows the planar shape of the via plug 45 and the dummy plug 45'. The planar shape of the via plug 45 of the first embodiment is a circle (see Figure 15 ), in contrast, the planar shape of the via plug 45 and the dummy plug 45' of this embodiment is a rectangle extending in the X direction. However, the via plug 45 and the dummy plug 45' of this embodiment may have other planar shapes.

[0163] Figure 38 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a first comparative example of the second embodiment.

[0164] Figure 38 (a) shows the planar structure of the semiconductor device of this comparative example. Figure 38 (b) shows the Figure 38 The XZ cross section of the line XX' shown in (a). Figure 38 (c) shows the Figure 38 YZ cross section along the line YY' shown in (a).

[0165] The semiconductor device of this comparative example has the same structure as the semiconductor device of the second embodiment. However, the semiconductor device of this comparative example does not include the dummy plug 45' and the wiring 54b. In addition, the planar shape of the via plug 45 of this comparative example is a circle.

[0166] Figure 39 This is a cross-sectional view for comparing the semiconductor device according to the second embodiment with the semiconductor device according to the first comparative example of the second embodiment.

[0167] Figure 39 (a) and Figure 38 (b) similarly shows an XZ cross section of a semiconductor device according to a first comparative example of the second embodiment. Figure 39 (a) shows the stress F1 applied to the wiring 54a in the area TV and the stress F2 applied to the wiring 54a outside the area TV. The stress applied to the wiring 54a tends to concentrate in the area where the hard layer exists under the wiring 54a. The wiring 54a in the area TV is arranged on the through-hole plug 45 which is the hard layer. Therefore, in Figure 39 In (a), a large stress F1 is easily applied to the wiring 54a in the region TV. As a result, there is a possibility of damage to the via plug 45. When the probe 74 is brought into contact with the wiring 54a or when the bonding wire 57 is arranged on the wiring 54a, a large stress is easily applied to the wiring 54a.

[0168] on the other hand, Figure 39 (b) and Figure 37 (b) similarly shows an XZ cross section of the semiconductor device according to the second embodiment. Figure 39 (b) shows the stress F3 applied to the wiring 54a within the region TV and the stress F4 applied to the wiring 54a outside the region TV. Figure 39 In (b), the wiring 54a in the area TV is arranged on the through-hole plug 45 as the hard layer, and the wiring 54a outside the area TV is arranged above the wiring 51b as the hard layer and the dummy plug 45'. Figure 39 In (b), the wiring 54a in the region TV is less likely to be subjected to the large stress F3. This is because the stress applied to the wiring 54a is dispersed into the stress F3 and the stress F4. This can suppress damage to the via plug 45.

[0169] [Semiconductor Device According to Modification of Second Embodiment]

[0170] Figure 40 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a first modification of the second embodiment. Figure 40 (a) shows a planar structure of a semiconductor device according to this modification. Figure 40 (b) shows the Figure 40 YZ cross section along the line YY' shown in (a).

[0171] The semiconductor device of this variation has the same structure as the semiconductor device of the second embodiment. However, the wiring layer 51 of this variation includes wiring 51b and wiring 51c provided on the lower surface of wiring 54a. Wirings 51b and 51c of this variation are in contact with wiring 54a and are electrically connected to wiring 54a. Figure 40FIG. 5( b ) shows a dummy plug 45 ′ provided on the lower surface of the wiring 51 b and a dummy plug 45 ′ provided on the lower surface of the wiring 51 c .

[0172] Each dummy plug 45' of the second embodiment is not electrically connected to a device or bonding pad within the semiconductor device. On the other hand, each dummy plug 45' of this variant is electrically connected to a device or bonding pad within the semiconductor device. This is because each dummy plug 45' of this variant is electrically connected to the wiring 54a (bonding pad) via wiring 51b, 51c, and is electrically connected to devices such as the memory cell array 11 and the transistor 31 via the through-hole plug 45. However, each dummy plug 45' of this variant does not function as a plug for controlling the semiconductor device of this variant. This is because the power supply voltage or signal voltage supplied from the wiring 54a to the device is not supplied to the device via the dummy plug 45', but is supplied to the device via the through-hole plug 45. The same applies to the signal voltage supplied from the device to the wiring 54a.

[0173] The wirings 51b, 51c, and dummy plugs 45' of this variation can achieve the same effects as the wirings 51b and dummy plugs 45' of the second embodiment. Furthermore, as long as the wirings 54a are not electrically connected to the device via the dummy plugs 45', the dummy plugs 45' of this variation can also be placed on the wiring layer 44. This also applies to the variations described below. For the same reason, the dummy plugs 45' of the second embodiment can also be placed on the wiring layer 44.

[0174] Figure 41 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a second modification of the second embodiment. Figure 41 (a) shows a planar structure of a semiconductor device according to this modification. Figure 41 (b) shows the Figure 41 YZ cross section along the line YY' shown in (a).

[0175] The semiconductor device of this modification has the same structure as the semiconductor device of Embodiment 2. However, the wiring layer 51 of this modification does not include the wiring 51 b. Figure 41 (b) shows multiple dummy plugs 45' provided on the lower surface of wiring 54a. These dummy plugs 45' are in contact with wiring 54a and are electrically connected to wiring 54a. The dummy plugs 45' of this modification can achieve the same effects as the wiring 51b and dummy plugs 45' of the second embodiment.

[0176] Figure 42 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a third modification of the second embodiment. Figure 42(a) shows a planar structure of a semiconductor device according to this modification. Figure 42 (b) shows the Figure 42 The XZ cross section of the line XX' shown in (a).

[0177] The semiconductor device of this variation has the same structure as the semiconductor device of the second embodiment. However, the wiring layer 51 of this variation includes wiring 51b that is extensively provided below wiring 54a. Wiring 51b of this variation is in contact with wiring 54a and is electrically connected to wiring 54a. Figure 42 (b) shows a plurality of dummy plugs 45' provided on the lower surface of the wiring 51b. According to the wiring 51b and the dummy plugs 45' of this modification, the same effects as those of the wiring 51b and the dummy plugs 45' of the second embodiment can be obtained.

[0178] Figure 43 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a fourth modification of the second embodiment. Figure 43 (a) shows a planar structure of a semiconductor device according to this modification. Figure 43 (b) shows the Figure 43 The XZ cross section of the line XX' shown in (a).

[0179] The semiconductor device of this modification has the same structure as the semiconductor device of the second embodiment. However, the wiring 54a of this modification includes a portion P1 having a flat plate shape and a plurality of portions P2 protruding downward from the portion P1. Figure 43 (a) and Figure 43 As shown in (b), each portion P2 extends in the Y direction and is arranged on a plurality of via plugs 45. The wiring 51b and dummy plug 45' of this modification can achieve the same effects as those of the wiring 51b and dummy plug 45' of the second embodiment.

[0180] Figure 44 sectional views showing the configurations of semiconductor devices according to fifth and sixth modifications of the second embodiment.

[0181] Figure 44 (a) shows an XZ cross section of a semiconductor device according to a fifth modification of the second embodiment. The semiconductor device according to this modification has the same structure as the semiconductor device according to the second embodiment. However, the wiring 54a of this modification is Figure 7 The wiring 54a shown in the figure also has the parts B1 and B2. Therefore, the effects of the first embodiment can be obtained in this modification as well.

[0182] Figure 44(b) shows an XZ cross section of a semiconductor device according to a sixth modification of the second embodiment. The semiconductor device according to this modification has the same structure as the semiconductor device according to the second embodiment. However, the wiring 54a of this modification is Figure 29 The wiring 54a shown similarly includes metal layers 75 and 76. Thus, the effects of the first embodiment can also be obtained in this modification.

[0183] Figure 45 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a seventh modification of the second embodiment. Figure 45 (a) shows a planar structure of a semiconductor device according to this modification. Figure 45 (b) shows the Figure 45 YZ cross section along the line YY' shown in (a).

[0184] The semiconductor device of this modification has the same structure as the semiconductor device of the first modification of the second embodiment. However, the planar shapes of the via plugs 45 and dummy plugs 45' in this modification are circular. This modification can achieve the same effects as the first modification.

[0185] Figure 46 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to an eighth modification of the second embodiment. Figure 46 (a) shows a planar structure of a semiconductor device according to this modification. Figure 46 (b) shows the Figure 46 YZ cross section along the line YY' shown in (a).

[0186] The semiconductor device of this modification has the same structure as the semiconductor device of the second modification of the second embodiment. However, the planar shapes of the via plugs 45 and dummy plugs 45' in this modification are circular. This modification can achieve the same effects as the second modification.

[0187] Figure 47 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a ninth modification of the second embodiment. Figure 47 (a) shows a planar structure of a semiconductor device according to this modification. Figure 47 (b) shows the Figure 47 The XZ cross section of the line XX' shown in (a).

[0188] The semiconductor device of this modification has the same structure as the semiconductor device of the third modification of the second embodiment. However, the planar shapes of the via plugs 45 and dummy plugs 45' in this modification are circular. This modification can achieve the same effects as the third modification.

[0189] Figure 48 1 and 2 are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a tenth modification of the second embodiment. Figure 48 (a) shows a planar structure of a semiconductor device according to this modification. Figure 48 (b) shows the Figure 48 The XZ cross section of the line XX' shown in (a).

[0190] The semiconductor device of this modification has the same structure as the semiconductor device of the fourth modification of the second embodiment. However, the planar shapes of the via plugs 45 and dummy plugs 45' in this modification are circular. This modification can achieve the same effects as the fourth modification.

[0191] Figure 49 1 and 2 are cross-sectional views illustrating the configurations of semiconductor devices according to the eleventh and twelfth modified examples of the second embodiment.

[0192] Figure 49 (a) shows an XZ cross-section of a semiconductor device according to the eleventh modification of the second embodiment. The semiconductor device of this modification has the same structure as the semiconductor device of the fifth modification of the second embodiment. However, the planar shapes of the via plug 45 and the dummy plug 45' in this modification are circular. This modification achieves the same effects as the fifth modification.

[0193] Figure 49 (b) shows an XZ cross section of a semiconductor device according to a twelfth modification of the second embodiment.

[0194] The semiconductor device of this modification has the same structure as the semiconductor device of the sixth modification of the second embodiment. However, the planar shapes of the via plugs 45 and dummy plugs 45' in this modification are circular. This modification can achieve the same effects as the sixth modification.

[0195] As described above, the semiconductor device of this embodiment includes a dummy plug 45' below the bonding pad (wiring 54a). Therefore, according to this embodiment, a suitable via plug 45 can be formed. For example, damage to the via plug 45 when the probe 74 is brought into contact with the wiring 54a or when the bonding wire 57 is arranged on the wiring 54a can be suppressed.

[0196] As described above, the planar shape of the via plug 45 may be circular, rectangular, or other shapes. A rectangular planar shape of the via plug 45 has the advantage of easily preventing damage to the via plug 45, compared to a circular planar shape.

[0197] Although several embodiments have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. The new devices and methods described in this specification can be implemented in various other ways. In addition, various omissions, substitutions, and changes can be made to the methods of the devices and methods described in this specification without departing from the scope of the invention. The scope of the attached claims and their equivalents is intended to cover such methods and variations that fall within the scope and spirit of the invention.

Claims

1. A semiconductor device comprising: a first insulating film; a first plug disposed in the first insulating film; a first wiring layer provided on the first insulating film; a second insulating film including a first region provided on the first insulating film and having a first upper surface, and a second region provided on the first wiring layer and having a second upper surface higher than the first upper surface; as well as A second wiring layer includes a first portion provided on the first insulating film and the first plug, a second portion provided on the first region, and a third portion provided on the second region, and includes a bonding pad.

2. The semiconductor device according to claim 1, wherein The first portion includes an upper portion provided on the first insulating film and a lower portion protruding downward from the upper portion and provided on at least the first plug.

3. The semiconductor device according to claim 2, wherein The height of the upper end of the first plug is lower than the height of the lower surface of the upper portion.

4. The semiconductor device according to claim 1, wherein The height of the upper end of the first plug is higher than the height of the lower surface of the first portion.

5. The semiconductor device according to claim 4, wherein The second wiring layer includes a first layer provided on the first insulating film and the first plug, and a second layer provided on the first layer. The semiconductor device according to claim 1 , wherein: further comprising a second plug provided in the first insulating film, The first portion is provided on the first insulating film, the first plug, and the second plug.

7. The semiconductor device according to claim 6, wherein The first portion includes an upper portion provided on the first insulating film, a first lower portion protruding downward from the upper portion and provided at least on the first plug, and a second lower portion protruding downward from the upper portion and provided at least on the second plug.

8. The semiconductor device according to claim 6, wherein The first portion includes an upper portion provided on the first insulating film and a lower portion protruding downward from the upper portion and provided on at least the first plug and the second plug.

9. The semiconductor device according to claim 1, wherein further comprising a third insulating film provided on the first insulating film and the second insulating film and provided below the second wiring layer, The first plug is provided in the first insulating film and the third insulating film, The first portion is provided on the first insulating film and on the first plug via the third insulating film, the second portion is provided on the first region via the third insulating film, and the third portion is provided on the second region via the third insulating film. The first portion includes an upper portion provided on the first insulating film via the third insulating film, and a lower portion protruding downward from the upper portion and provided on at least the first plug.

10. The semiconductor device according to claim 1, wherein A third plug is further provided below the bonding pad and on the lower surface of the first wiring layer or the second wiring layer, and does not function as a plug for controlling the semiconductor device.

11. A method for manufacturing a semiconductor device, comprising the following steps: forming a first insulating film; forming a first plug in the first insulating film; forming a first wiring layer on the first insulating film; forming a second insulating film including a first region provided on the first insulating film and having a first upper surface, and a second region provided on the first wiring layer and having a second upper surface higher than the first upper surface; A second wiring layer is formed, the second wiring layer including a first portion disposed on the first insulating film and the first plug, a second portion disposed on the first region, and a third portion disposed on the second region, and including a bonding pad.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The method further includes forming a first recess in the first wiring layer so that the upper end of the first plug is exposed in the first recess, The second insulating film is formed after the first recess is formed.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The method further includes forming a second recess in the second insulating film so that the upper end of the first plug is exposed in the second recess, The second wiring layer is formed after the second recess is formed.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: After the second recess is formed, the exposed portion of the first plug is processed, and a third recess is formed in the first insulating film so that the upper end of the first plug descends toward the bottom of the third recess. The second wiring layer is formed after the third recess is formed.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The exposed portion of the first plug is processed by isotropic etching.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The isotropic etching is performed using an etchant gas and an ion beam after forming a first film on the first insulating film, the second insulating film, and the first plug.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The ion beam is incident on the first plug at an angle relative to a surface of the first substrate provided with the first insulating film.

18. The method for manufacturing a semiconductor device according to claim 13, wherein: The following processing is also included: After forming the second recess, forming a third insulating film on the first insulating film, the second insulating film, and the first plug; and forming a fourth recess in the third insulating film so that the upper end of the first plug is exposed at the bottom of the fourth recess; The second wiring layer is formed after the fourth recess is formed.

19. The method for manufacturing a semiconductor device according to claim 13, wherein: The second wiring layer is formed in a state in which the upper end of the first plug is higher than the bottom surface of the second recess.

20. The method for manufacturing a semiconductor device according to claim 11, wherein: The method further comprises the following steps: contacting a probe with the bonding pad; The width of the probe is greater than the width of the first portion.

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