A high-reliability communication interface circuit, communication chip and communication equipment thereof

Abstract

The present invention belongs to the field of integrated circuit technology, and particularly relates to a highly reliable communication interface circuit, communication chip, and communication device thereof. The present invention comprises: a TX transmission module, connected between the TX port and the BUS_O port, serving as a data transmission path; comprising: resistors R0 to R4, transistor N1, and transistor N3; an RX reception module, connected between the RX port and the BUS_I port, serving as a data reception path; comprising: resistors R6 to R9 and transistors N4 to N5; and a current limiting unit, comprising: transistor N2 and resistors R3 to R4. The present invention can reduce the area of ​​a PCB or lower the design cost of a PCB, significantly saving the cost of peripheral components; and can enable a single chip to achieve dual-wire communication or single-wire communication functions through different packaging and wiring forms, allowing a single chip to multiplex multiple functions.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-reliability communication interface circuit, a communication chip and a communication device thereof. Background Art

[0002] With the continuous evolution of electronic technology, the functional integration of consumer appliances continues to increase. The performance of their internal signal transmission and reception modules has become a key factor in determining the overall performance of the device. As the core circuit unit of the signal interface, the communication method of the level conversion circuit directly affects the signal integrity of data transmission. If its performance is inaccurate, it will lead to level misjudgment or timing deviation, which in turn will cause system-level communication failures, ultimately hindering the reliable implementation of the entire circuit function.

[0003] Currently, the single-channel unidirectional level conversion circuit design on the market, such as the single-channel unidirectional level conversion circuit with patent publication number CN201797505U, is a simple level conversion solution based on NPN digital transistors. It mainly solves the unidirectional signal compatibility problem between chips with different voltage domains (such as 1.8V and 3.3V systems). The working principle of the single-channel unidirectional level conversion circuit is: when the input is low level, that is, the signal input terminal is a "0" signal, the transistor base-emitter voltage V BE When the voltage is >0.7V, the transistor conducts, and the collector-emitter voltage is 0, effectively a short circuit. The signal output terminal is pulled down to 0V by the conducting transistor, completing the low-level conversion. When the input is high, meaning the signal input terminal is a "1," the base-emitter voltage of the transistor is 0, placing the transistor in the off state. The signal output terminal is pulled up to a high level by the collector pull-up resistor, achieving the high-level conversion. However, a single level conversion circuit typically only supports a one-way communication link from the transmitter to the receiver. In this architecture, after the receiver successfully receives the level signal, it lacks an effective reverse feedback path and cannot send a receipt confirmation or status response to the transmitter. This prevents the transmitter from determining whether the data has been successfully received in real time, resulting in a loss of data transmission validity. As a direct consequence, the receiver may be unable to correctly execute intended operations due to doubts about data integrity.

[0004] In view of the above situation, the existing technical solutions have the following significant limitations:

[0005] 1) The data exchange mode between signal receiving devices is single. The circuit only supports one-way signal transmission from the low-voltage domain to the high-voltage domain, and cannot achieve receiving-end feedback or two-way communication. Due to the lack of a receiving-end feedback mechanism, data transmission accuracy cannot be guaranteed.

[0006] 2) Most of them are discrete devices, which are costly;

[0007] 3) In a normal application solution, there will be multiple groups of such circuits on the PCB board. The discrete solution occupies a very large area of ​​the PCB board, which is not convenient for routing;

[0008] 4) Poor reliability, requires additional protection, high cost, large area occupied, and complex solution. Summary of the Invention

[0009] The purpose of the present invention is to provide a highly reliable communication interface circuit, communication chip and communication equipment thereof, which not only solve the limitation of unidirectional transmission of traditional structures, but also can be integrated into the chip, use a small amount of or even avoid the use of discrete components to reduce the layout of the PCB board, save a lot of costs, and even further reduce costs by sealing with the MCU chip, so that the area of ​​the PCB board is further reduced and the wiring is simpler. At the same time, the built-in current and voltage limiting structure improves its reliability, and the dual power supply and dual communication port structure makes it compatible with various usage scenarios. At the same time, combined with simple peripherals, its reliability can be further improved to meet a variety of usage scenarios.

[0010] To solve the above technical problems, the present invention provides a highly reliable communication interface circuit, comprising:

[0011] The TX transmission module is connected between the TX port and the BUS_O port as a data transmission path; it includes: resistors R0 to R4, transistor N1, and transistor N3; one end of the resistor R0 is connected to the power supply VDD, and the other end is connected to one end of the resistor R1 and the TX port; the other end of the resistor R1 is connected to the base of the transistor N1, the emitter of the transistor N1 is grounded, the collector of the transistor N1 is connected to one end of the resistor R2 and the base of the transistor N3, and the other end of the resistor R2 is connected to the power supply VCC; the emitter of the transistor N3 is grounded, and the collector of the transistor N3 is connected to the BUS_O port;

[0012] The RX receiving module is connected between the RX port and the BUS_I port as a data receiving path; it includes: resistors R6~R9 and transistors N4~N5; one end of the resistor R6 is connected to the RX port and the collector of the transistor N4, and the other end of the resistor R6 is connected to the power supply VDD; the emitter of the transistor N4 is grounded, the base of the transistor N4 is connected to the collector of the transistor N5 and one end of the resistor R7, the other end of the resistor R7 is connected to the power supply VCC, and the emitter of the transistor N5 is grounded; the base of the transistor N5 is connected to the resistor R8 and one end of the resistor R9, the other end of the resistor R9 is grounded, and the other end of the resistor R8 is connected to the BUS_I port.

[0013] Preferably, a current limiting unit is further included, which includes: a transistor N2 and resistors R3~R4; the collector of the transistor N2 is connected to the base of the transistor N3, the base of the transistor N2 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to one end of the resistor R4 and the emitter of the transistor N3; the other end of the resistor R4 is connected to the emitter of the transistor N2 and is grounded.

[0014] Preferably, four ESD protection units are further included, each of which is composed of a grounded diode, and the four ESD protection units are respectively connected to the TX port, the BUS_O port, the RX port and the BUS_I port.

[0015] Preferably, two overvoltage protection units are further included, one end of the two overvoltage protection units is commonly connected to the base of the transistor N1, and the other end is respectively connected to the BUS_O port and the BUS_I port.

[0016] Preferably, the overvoltage protection unit is composed of two diodes and a resistor connected in series.

[0017] Preferably, one of the diodes is a voltage regulator diode and is connected to the base of the transistor N1 as the input end of the overvoltage protection unit.

[0018] The present invention also provides a communication chip, comprising a high-reliability communication interface circuit and an MCU chip as described above; the TX port and the RX port are respectively connected to the transmitting interface and the receiving interface of the MCU chip, and the power supply end of the MCU chip is connected to the power supply VDD.

[0019] Preferably, a bus interface circuit is further included, wherein the bus interface circuit includes: a resistor Rx, a fuse resistor Rs, a diode Dx, a diode D TVS One end of the resistor Rx is connected to the power supply VCC, the other end of the resistor Rx is connected to one end of the diode Dx, and the other end of the diode Dx is connected to the fuse resistor Rs, the diode Ds and the diode D TVS One end, and BUS_O port and BUS_I port; the diode D TVS The other end of the fuse resistor Rs is connected to the communication bus interface.

[0020] Preferably, a bus interface circuit is further included, which includes: resistors R11~R14, transistor N7 and diodes D8~D9; one end of the resistor R11 and the resistor R12 is connected to the power supply VCC, the other end of the resistor R11 is connected to the base of the transistor N7, the emitter of the transistor N7 is connected to the BUS_O port, the collector of the transistor N7 is connected to one end of the diodes D8~D9 and the communication bus interface, the other end of the diode D8 is connected to the other end of the resistor R12; the other end of the diode D9 is connected to one end of the resistor R13, the other end of the R13 is connected to one end of the resistor R14 and the BUS_I port, and the other end of the resistor R14 is grounded.

[0021] The present invention also provides a communication device, comprising the high-reliability communication interface circuit as described above.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The present invention integrates a solution that could be implemented with discrete components into a single chip, reducing PCB wiring, thereby reducing PCB area or PCB design costs, and significantly saving the cost of peripheral components. Different packaging and wiring formats allow a single chip to implement dual-wire and single-wire communication functions, allowing for multiple functions on a single chip and reducing R&D costs. Built-in overvoltage protection and current limiting protection improve the reliability of the communication bus interface without increasing the area of ​​the driver transistors. The dual communication port design improves the reliability of the communication bus interface by adding an external e' unit (bus interface circuit), reducing the chip design process. The dual power supply design not only better protects the components on the MCU port and enhances the driving capability of the communication bus interface, but also prevents backflow from the communication bus interface to the power supply, improving chip reliability. Specifically, when an external communication module is plugged into the communication bus interface, if the user mistakenly connects a power supply to the communication bus interface, the chip's overvoltage protection unit b' and current limiting protection unit a' will trigger the corresponding protection mechanism, otherwise the chip will be easily damaged, even if a TVS diode and fuse are added to the external port. Compared with the conventional solution of increasing the area of ​​N3 tube to improve reliability, these protection measures can reduce the chip area and reduce the cost while ensuring reliability. If used in situations with higher reliability, it can also be combined with Figure 4There are two solutions: one is to use N7 tube for isolation, and the other is to use overvoltage protection unit c' and current limiting protection unit a' to further improve the reliability of the chip; when the user correctly connects the external communication module, the MCU sends communication information to the external communication module through the TX port, and can also receive information through the RX port whether the external communication module has received the sent information; at the same time, the dual power supply design can ensure that the highest potential of the MCU chip remains consistent with the MCU power supply voltage when the TX and RX ports are connected, and the high-voltage power supply of the external communication module will not be backflowed to the power supply or even the MCU chip through the port, thereby damaging the power supply or MCU chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The present invention provides a circuit diagram of a high-reliability communication interface circuit.

[0025] Figure 2 This is a circuit diagram of a communication chip applied to an MCU chip provided by the present invention.

[0026] Figure 3 The present invention provides a circuit diagram of a communication chip applied to a bus interface circuit.

[0027] Figure 4 This is a circuit diagram of a communication chip applied to another bus interface circuit provided by the present invention. DETAILED DESCRIPTION

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention. Example

[0029] like Figure 1 As shown, the embodiment of the present invention specifically provides a high reliability communication interface circuit, namely Figure 2 The d' unit in includes:

[0030] The TX transmission module is connected between the TX port and the BUS_O port as a data transmission path; it includes: resistors R0 to R4, transistor N1, and transistor N3; one end of the resistor R0 is connected to the power supply VDD, and the other end is connected to one end of the resistor R1 and the TX port; the other end of the resistor R1 is connected to the base of the transistor N1, the emitter of the transistor N1 is grounded, the collector of the transistor N1 is connected to one end of the resistor R2 and the base of the transistor N3, and the other end of the resistor R2 is connected to the power supply VCC; the emitter of the transistor N3 is grounded, and the collector of the transistor N3 is connected to the BUS_O port;

[0031] The RX receiving module is connected between the RX port and the BUS_I port as a data receiving path; it includes: resistors R6~R9 and transistors N4~N5; one end of the resistor R6 is connected to the RX port and the collector of the transistor N4, and the other end of the resistor R6 is connected to the power supply VDD; the emitter of the transistor N4 is grounded, the base of the transistor N4 is connected to the collector of the transistor N5 and one end of the resistor R7, the other end of the resistor R7 is connected to the power supply VCC, and the emitter of the transistor N5 is grounded; the base of the transistor N5 is connected to the resistor R8 and one end of the resistor R9, the other end of the resistor R9 is grounded, and the other end of the resistor R8 is connected to the BUS_I port.

[0032] It also includes a current limiting unit, which includes: a transistor N2 and resistors R3~R4; the collector of the transistor N2 is connected to the base of the transistor N3, the base of the transistor N2 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to one end of the resistor R4 and the emitter of the transistor N3; the other end of the resistor R4 is connected to the emitter of the transistor N2 and is grounded.

[0033] It also includes four ESD protection units, each of which is composed of a grounded diode, and the four ESD protection units are respectively connected to the TX port, the BUS_O port, the RX port and the BUS_I port.

[0034] It also includes two overvoltage protection units, one end of the two overvoltage protection units is commonly connected to the base of the transistor N1, and the other end is respectively connected to the BUS_O port and the BUS_I port.

[0035] The overvoltage protection unit is composed of two diodes and a resistor connected in series.

[0036] One of the diodes is a voltage regulator and is connected to the base of the transistor N1 as the input end of the overvoltage protection unit. Example

[0037] like Figure 2 As shown, based on the above-mentioned embodiment 1, the present invention also provides a communication chip, including a high-reliability communication interface circuit and an MCU chip as described above; the TX port and the RX port are respectively connected to the transmitting interface and the receiving interface of the MCU chip, and the power supply end of the MCU chip is connected to the power supply VDD.

[0038] It should be noted that the TX to BUS_O path is for the MCU chip to send communications to other interface modules, and the BUS_I to RX path is for the MCU chip to receive communications from the interface module, enabling two-way communication. The application scenarios of this embodiment are due to the design of dual communication interfaces, and the single chip can achieve the function of two-line communication, making the chip more flexible in use and more applicable. Example

[0039] like Figure 3 As shown, based on the above embodiment 2, a bus interface circuit is further included, and the bus interface circuit includes: a resistor Rx, a fuse resistor Rs, a diode Dx, a diode D TVS One end of the resistor Rx is connected to the power supply VCC, the other end of the resistor Rx is connected to one end of the diode Dx, and the other end of the diode Dx is connected to the fuse resistor Rs, the diode Ds and the diode D TVS One end, and BUS_O port and BUS_I port; the diode D TVS The other end of the fuse resistor Rs is connected to the communication bus interface.

[0040] It should be noted that BUS_I and BUS_O are connected as a single-line communication port, which can realize the function of MCU communicating with the communication bus through TX and can also judge whether the communication is normal through RX feedback. At the same time, the MCU can also receive information sent from the communication bus, realizing the sending and receiving functions of communication through a single line.

[0041] The above D0, D3, D4, and D5 are ESD tubes of the port, R0 is the pull-up resistor of the TX port, and the MCU port only needs to provide an open-drain output function. The electrical levels are all TTL standards. The R1 resistor is the input resistor, and N1 and R2 are the pre-stage driver units of the open-drain output driver tube N3. The a' unit is a current limiting unit that can protect the output current of the N3 open-drain driver within a certain standard. The b' unit is a port overvoltage protection unit. When the BUS port is mistakenly connected to a high voltage, the voltage regulator tube D1 breaks down, turns on the N1 tube, turns off the open-drain driver tube, and protects the N3 open-drain driver tube. Together with the a' unit, they protect the N3 tube. R5 is a current limiting resistor, and D2 is to prevent the TX signal from entering the BUS port during normal operation; R8 is the BUS port input resistor, and R9 is Pull-down resistor, N5 and R7 are the pre-stage driver unit of driver tube N4, R6 is the RX output pull-up resistor, N4 is the RX output low-level driver tube, and c' unit is the same as b' unit in this application; at the same time, the dual power supply design makes it more flexible in application. When the power supply of the communication bus interface is much greater than the MCU power supply voltage, VDD can be connected to the MCU power supply and VCC to the communication bus pull-up power supply. This not only improves the driving capability of the N3 driver tube, but also is compatible with the power supply design of the MCU port, so as not to damage the MCU chip; in order to protect the MCU port, the existing design will connect VCC and VDD to the MCU power supply together, but the voltage of the BUS port will be fed back to the MCU power supply through the N5 tube, damaging the MCU chip or even the MCU power supply. Example

[0042] like Figure 4 As shown, based on the above-mentioned embodiment 2, a bus interface circuit is further included, which includes: resistors R11~R14, transistor N7 and diodes D8~D9; one end of the resistors R11 and R12 is connected to the power supply VCC, the other end of the resistor R11 is connected to the base of the transistor N7, the emitter of the transistor N7 is connected to the BUS_O port, the collector of the transistor N7 is connected to one end of the diodes D8~D9 and the communication bus interface, the other end of the diode D8 is connected to the other end of the resistor R12; the other end of the diode D9 is connected to one end of the resistor R13, the other end of R13 is connected to one end of the resistor R14 and the BUS_I port, and the other end of the resistor R14 is grounded.

[0043] Because of the dual-port design, this embodiment allows for the addition of an e' unit (bus interface circuit) to the periphery, primarily to further enhance reliability. By adding only a small number of peripheral components, chip reliability is significantly improved, further reducing the chip's process voltage requirements and significantly reducing the chip's design cost. This allows the communication bus port to be used in high-reliability scenarios, such as when it is mistakenly connected to a 100V voltage. In this case, the chip effectively protects the internal BUS_O port due to isolation provided by the added N7 transistor. Furthermore, the reasonable allocation of the R13 and R14 resistor values ​​ensures the reliability of the BUS_I port. Furthermore, in this application, the c' unit can more quickly shut down the N3 transistor before BUS_O reaches the protection level of the b' unit, thus implementing a multiple protection mechanism. Example

[0044] The present invention also provides a communication device, including a high-reliability communication interface circuit as described above. The dual power supply and dual communication port structure makes it compatible with various usage scenarios. At the same time, it can be further improved with simple peripherals to meet a variety of usage scenarios, such as the communication interface of electric bicycle chargers, the communication interface of home appliances and other equipment, etc.

[0045] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A communication interface circuit, characterized in that: include: The TX transmission module is connected between the TX port and the BUS_O port as a data transmission path; it includes: resistors R0 to R4, transistor N1, and transistor N3; one end of the resistor R0 is connected to the power supply VDD, and the other end is connected to one end of the resistor R1 and the TX port; the other end of the resistor R1 is connected to the base of the transistor N1, the emitter of the transistor N1 is grounded, the collector of the transistor N1 is connected to one end of the resistor R2 and the base of the transistor N3, and the other end of the resistor R2 is connected to the power supply VCC; the emitter of the transistor N3 is grounded, and the collector of the transistor N3 is connected to the BUS_O port; The RX receiving module is connected between the RX port and the BUS_I port as a data receiving path; it includes: resistors R6~R9 and transistors N4~N5; one end of the resistor R6 is connected to the RX port and the collector of the transistor N4, and the other end of the resistor R6 is connected to the power supply VDD; the emitter of the transistor N4 is grounded, the base of the transistor N4 is connected to the collector of the transistor N5 and one end of the resistor R7, the other end of the resistor R7 is connected to the power supply VCC, and the emitter of the transistor N5 is grounded; the base of the transistor N5 is connected to the resistor R8 and one end of the resistor R9, the other end of the resistor R9 is grounded, and the other end of the resistor R8 is connected to the BUS_I port; The device further includes a current limiting unit, which includes: a transistor N2 and resistors R3 and R4; the collector of the transistor N2 is connected to the base of the transistor N3, the base of the transistor N2 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to one end of the resistor R4 and the emitter of the transistor N3; the other end of the resistor R4 is connected to the emitter of the transistor N2 and is grounded; It also includes two overvoltage protection units, one end of the two overvoltage protection units is commonly connected to the base of the transistor N1, and the other end is respectively connected to the BUS_O port and the BUS_I port; The overvoltage protection unit is composed of two diodes and a resistor connected in series. One of the diodes is a voltage regulator and is connected to the base of the transistor N1 as the input end of the overvoltage protection unit.

2. A communication interface circuit according to claim 1, characterized in that: It also includes four ESD protection units, each of which is composed of a grounded diode, and the four ESD protection units are respectively connected to the TX port, the BUS_O port, the RX port and the BUS_I port.

3. A communication chip, characterized in that: It comprises a communication interface circuit and an MCU chip according to any one of claims 1 to 2; the TX port and the RX port are respectively connected to the transmitting interface and the receiving interface of the MCU chip, and the power supply end of the MCU chip is connected to the power supply VDD.

4. A communication chip as claimed in claim 3, characterized in that: It also includes a bus interface circuit, which includes: a resistor Rx, a fuse resistor Rs, a diode Dx, a diode D TVS One end of the resistor Rx is connected to the power supply VCC, the other end of the resistor Rx is connected to one end of the diode Dx, and the other end of the diode Dx is connected to the fuse resistor Rs, the diode Ds and the diode D TVS One end, and BUS_O port and BUS_I port; the diode D TVS The other end of the fuse resistor Rs is connected to the communication bus interface.

5. A communication chip as claimed in claim 3, characterized in that: It also includes a bus interface circuit, which includes: resistors R11~R14, transistor N7 and diodes D8~D9; one end of the resistors R11 and R12 is connected to the power supply VCC, the other end of the resistor R11 is connected to the base of the transistor N7, the emitter of the transistor N7 is connected to the BUS_O port, the collector of the transistor N7 is connected to one end of the diodes D8~D9 and the communication bus interface, the other end of the diode D8 is connected to the other end of the resistor R12; the other end of the diode D9 is connected to one end of the resistor R13, the other end of R13 is connected to one end of the resistor R14 and the BUS_I port, and the other end of the resistor R14 is grounded.

6. A communication device, characterized in that: It comprises a communication interface circuit as described in any one of claims 1 to 2.

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