Measuring circuit, working method thereof and layout measuring circuit
By connecting the standard unit to be tested in the ring oscillation circuit, using the change of the effect capacitance value, the problem of inaccurate evaluation of the frequency and power consumption of the standard unit is solved, and the layout optimization speed and performance are improved.
Patent Information
- Application Number
- CN202410186188.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-19
- Publication Date
- 2025-08-19
AI Technical Summary
In the prior art, the frequency and power consumption evaluation verification of standard units is not accurate enough, resulting in large deviations in layout design verification, which reduces layout optimization speed and working performance.
It provides a measurement circuit, which connects to the standard unit to be tested through a ring oscillation circuit, uses the change of the effect capacitance value under different loads to accurately measure the effect capacitance value and optimize the layout design.
It improves the layout optimization speed and working performance, expands the application range of measurement circuits, and enhances the measurement accuracy of the effect capacitance value.
Smart Images
Figure CN120507631A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of testing technology, and in particular to a measurement circuit and a working method thereof, and a layout measurement circuit. Background Art
[0002] In semiconductor design, a standard cell is a method for designing application-specific integrated circuits (ASICs) with primarily digital logic features. A standard cell is a group of transistors and interconnects that provide a Boolean logic function (e.g., AND, OR, XOR, XNOR, inverter) or a memory function (flip-flop or latch).
[0003] The key performance indicators of standard cell design are frequency and power consumption, and these two parameters also affect the frequency and power consumption results of the final chip. Improving the accuracy of standard cell frequency and power consumption evaluation and verification, so that they are closer to actual manufacturing test values, can improve the accuracy of subsequent chip design, reduce design verification deviations, and improve chip quality from design to final manufacturing.
[0004] However, the typical parameters of existing digital units are generally obtained by extracting RC parasitic parameters, and additional computing tools are required to perform complex calculations to obtain the input and output capacitance or resistance values. This is not conducive to directly evaluating the pros and cons of layout design and guiding layout optimization, and reduces the speed of layout optimization and the working performance of the layout. Summary of the Invention
[0005] The technical problem solved by the present invention is to provide a measurement circuit and a working method thereof, and a layout measurement circuit, so as to improve the speed of layout optimization and the working performance of the layout.
[0006] To solve the above technical problems, an embodiment of the present invention provides a measurement circuit for measuring the effective capacitance of a standard cell, comprising: a ring oscillator circuit, comprising an odd number of digital cells connected in series, each of the digital cells comprising an input and an output, the output of each digital cell being connected to the input of a subsequent digital cell, and the output of the last digital cell being connected to the input of the first digital cell; and a plurality of load circuits being connected between two adjacent digital cells, wherein the load circuits comprise a plurality of standard cells to be measured.
[0007] Optionally, the plurality of standard units to be tested are connected in parallel.
[0008] Optionally, the standard cell to be tested is a combination of one or more of an AND gate circuit standard cell, an OR gate circuit standard cell, a NOT gate circuit standard cell, and a multiplexer standard cell.
[0009] Optionally, each of the standard units to be tested includes: a first type of transistor and a second type of transistor, and both the first type of transistor and the second type of transistor include a first end, a second end, and a control end.
[0010] Optionally, the load circuit also includes: a selector, the selector including an input end, a first output end and a second output end, the input end of the selector is connected between two adjacent levels of digital units, the first output end of the selector is connected to the first end or the second end of the first type of transistor, and the second output end of the selector is connected to the first end or the second end of the second type of transistor.
[0011] Optionally, the measurement circuit also includes: a test module, which is connected to the control ends of the first and second type transistors and the standard unit to be tested; the test module is used to apply a first level to N standard units to be tested, so that the first type transistor or the second type transistor in the standard unit to be tested is turned on and connected to the ring oscillation circuit, and the electrical parameters of the standard unit to be tested are obtained after the first type transistor or the second type transistor is connected to the ring oscillation circuit, where N is the number of standard units to be tested connected to the ring oscillation circuit.
[0012] Optionally, the electrical parameters include a delay time t delay , first frequency F, output resistance value R and parasitic capacitance value C2.
[0013] Optionally, the testing module is further used to: obtain a first frequency F in the ring oscillation circuit.
[0014] Optionally, the test module is further configured to: obtain a delay time t according to the first frequency F delay =1 / F*2N=N*R*C1+R*C2; According to the formula t delay =N*R*C1+R*C2, and the slope in the formula is K=R*C1, that is, the effective capacitance value is C1=K / R, where C2 is the parasitic capacitance value in the ring oscillation circuit.
[0015] Correspondingly, the technical solution of the present invention also provides a working method of a measurement circuit, including: applying a first level to N standard units to be tested, so that the first type transistor or the second type transistor in the standard unit to be tested is turned on and connected to the ring oscillation circuit, and obtaining the electrical parameters of the standard unit to be tested after the first type transistor or the second type transistor is connected to the ring oscillation circuit, where N is the number of standard units to be tested connected to the ring oscillation circuit.
[0016] Optionally, the electrical parameters include a delay time t delay , first frequency F, output resistance value R, effective capacitance value C1 and parasitic capacitance value C2.
[0017] Optionally, obtaining the electrical parameters of the standard unit to be tested further includes: obtaining a first frequency F in the ring oscillation circuit.
[0018] Optionally, the step of obtaining the electrical parameters of the standard unit to be tested further includes: obtaining a delay time t according to the first frequency F. delay =1 / F*2N=N*R*C1+R*C2; According to the formula t delay =N*R*C1+R*C2, and the slope in the formula is K=R*C1, that is, the effective capacitance value is C1=K / R, where C2 is the parasitic capacitance value in the ring oscillation circuit.
[0019] Correspondingly, the technical solution of the present invention also provides a layout measurement circuit, including: a ring oscillation circuit, including an odd number of digital unit layouts connected in series, each of the digital unit layouts including an input end and an output end, the output end of each digital unit layout is connected to the input end of the next level of digital unit, and the output end of the last level of digital unit layout is connected to the input end of the first level of digital unit layout; a number of load circuits are connected between two adjacent levels of digital unit layouts, and the load circuits include a number of standard unit layouts to be tested.
[0020] Optionally, the layout measurement circuit includes: the plurality of standard unit layouts to be tested are connected in parallel.
[0021] Optionally, the layout measurement circuit includes: the standard cell layout to be tested is one or more combinations of an AND gate circuit standard cell layout, an OR gate circuit standard cell layout, a NOT gate circuit standard cell layout, and a multiplexer standard cell layout.
[0022] Optionally, the layout measurement circuit includes: each of the standard cell layouts to be tested includes: a first type of transistor and a second type of transistor, and the first type of transistor and the second type of transistor both include a first end, a second end, and a control end.
[0023] Optionally, the layout measurement circuit includes: the load circuit also includes: a selector, the selector includes an input end, a first output end and a second output end, the input end of the selector is connected between two adjacent levels of digital unit layouts, the first output end of the selector is connected to the first end or the second end of the first type of transistor, and the second output end of the selector is connected to the first end or the second end of the second type of transistor.
[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0025] The measurement circuit provided by the technical solution of the present invention connects the standard unit to be measured in the ring oscillation loop. Since the effect capacitance values under loads of different sizes are also different, the loads of different sizes can be changed by controlling the control signal of the standard unit to be measured, thereby achieving accurate measurement of the effect capacitance value in the standard unit to be measured. The optimization is performed according to the effect capacitance value, thereby improving the optimization speed and working performance. The parasitic capacitance affecting the effect capacitance value in the technical solution of the present invention is completely caused by the digital unit, eliminating the influence of other factors, thereby improving the accuracy of the measurement of the effect capacitance value. In addition, the measurement circuit in the technical solution of the present invention is suitable for measuring the architecture of all digital units, as well as the effect capacitance changes caused by connecting the standard unit to be measured, thereby expanding the application range of the measurement circuit.
[0026] Furthermore, the number of the standard cells to be tested in the technical solution of the present invention can be flexibly selected according to test requirements, thereby realizing the measurement of the capacitance changes in different structural layers in the standard cells to be tested.
[0027] Furthermore, in the technical solution of the present invention, it is only necessary to measure the frequency of the ring oscillator and calculate based on the frequency to obtain the value of the effect capacitance, which facilitates simulation and manufacturing implementation as well as data comparison between manufacturing and simulation.
[0028] The working method of the measuring circuit provided by the technical solution of the present invention obtains the electrical parameter to be measured during the oscillation of the ring oscillation circuit, wherein the delay time t is obtained by delay , the first frequency F and the parasitic capacitance value C2, to obtain the output resistance value R and the effective capacitance value C1, thereby achieving performance testing of the standard cell and optimization of the standard cell. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 This is a schematic diagram of the structure of the measurement circuit in one embodiment of the present invention. Figure 1 ;
[0030] Figure 2 This is a schematic diagram of the structure of the measurement circuit in one embodiment of the present invention. Figure 2 ;
[0031] Figure 3 Schematic diagram of the linear relationship between the delay time of the ring oscillator circuit in the measurement circuit and the number of standard units connected to be measured in one embodiment of the present invention. DETAILED DESCRIPTION
[0032] As mentioned in the background technology, the optimization speed and working performance of the current digital unit layout need to be further improved.
[0033] Typical parameters in existing digital units are generally obtained by extracting RC parasitic parameters. Additional computing tools are required to perform complex calculations to obtain input and output capacitance or resistance values. This is not conducive to directly evaluating the pros and cons of layout design and guiding layout optimization, and reduces the speed of layout optimization and the working performance of the layout.
[0034] In order to solve the above technical problems, the technical solution of the present invention provides a measurement circuit and its working method, and a layout measurement circuit. A standard unit to be measured is connected to a ring oscillation circuit. Since the effect capacitance values under loads of different sizes are also different, the control signal of the standard unit to be measured can be controlled to change the loads of different sizes, thereby achieving accurate measurement of the effect capacitance value in the unit to be measured. The optimization is performed according to the effect capacitance value, thereby improving the optimization speed and working performance. The parasitic capacitance affecting the effect capacitance value in the technical solution of the present invention is completely caused by the digital unit, eliminating the influence of other factors, and improving the accuracy of the measurement of the effect capacitance value. In addition, the measurement circuit in the technical solution of the present invention is suitable for measuring the architecture of all digital units, as well as the effect capacitance changes caused by connecting the standard unit to be measured, thereby expanding the application range of the measurement circuit.
[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0036] Figure 1 This is a schematic diagram of the structure of the measurement circuit in one embodiment of the present invention. Figure 1 .
[0037] Please refer to Figure 1 The technical solution of the present invention provides a measurement circuit, comprising: a ring oscillator circuit 1, comprising an odd number of digital units 101 connected in series, each of the digital units 101 comprising an input end and an output end, the output end of each digital unit 101 being connected to the input end of the next digital unit 101, and the output end of the last digital unit 101 being connected to the input end of the first digital unit 101; and a plurality of load circuits 2 being connected between two adjacent digital units 101.
[0038] In the above scheme, by connecting the standard unit 201 to be tested in the ring oscillation circuit 1, since the effect capacitance values under loads of different sizes are also different, the control signal of the standard unit 201 to be tested can be controlled to change the loads of different sizes, thereby achieving accurate measurement of the effect capacitance value in the standard unit 201 to be tested, and optimizing according to the effect capacitance value, thereby improving the optimization speed and working performance. Moreover, the parasitic capacitance affecting the effect capacitance value in the technical scheme of the present invention is completely caused by the digital unit 101, eliminating the influence of other factors, and improving the accuracy of the measurement of the effect capacitance value; in addition, the measurement circuit in the technical scheme of the present invention is suitable for measuring the architecture of all digital units 101, as well as the effect capacitance changes caused by connecting the standard unit 201 to be tested, thereby expanding the application range of the measurement circuit.
[0039] Figure 2 This is a schematic diagram of the structure of the measurement circuit in one embodiment of the present invention. Figure 2 .
[0040] Please refer to Figure 2 The load circuit 2 includes a plurality of standard units 201 to be tested, and the plurality of standard units 201 to be tested are connected in parallel.
[0041] Specifically, the number of the standard units 201 to be tested in each load circuit 2 is the same.
[0042] The standard cell to be tested 201 is one or a combination of an AND gate circuit standard cell, an OR gate circuit standard cell, a NOT gate circuit standard cell, and a multiplexer 202 standard cell.
[0043] Each of the standard cells to be tested 201 includes: a first type of transistor and a second type of transistor, and both the first type of transistor and the second type of transistor include a first terminal, a second terminal, and a control terminal.
[0044] The load circuit 2 also includes: a selector 202, which includes an input end, a first output end, and a second output end. The input end of the selector 202 is connected between two adjacent levels of digital units 101, the first output end of the selector 202 is connected to the first end or the second end of the first type of transistor, and the second output end of the selector 202 is connected to the first end or the second end of the second type of transistor.
[0045] The measurement circuit also includes: a test module 203, which is connected to the control terminals of the first and second type transistors, the standard unit to be tested 201, and the power supply voltage terminal of the digital unit 101; the test module 203 is used to apply a first voltage V1 to the standard unit to be tested 201 and the power supply voltage terminal of the digital unit 101, so that an oscillation signal is generated in the ring oscillation circuit 1, and apply a first electrical level to N standard units to be tested 201, so that the first type transistor or the second type transistor in the standard unit to be tested 201 is turned on and connected to the ring oscillation circuit 1, and obtain the electrical parameters of the standard unit to be tested 201 after the first type transistor or the second type transistor is connected to the ring oscillation circuit 1, where N is the number of standard units to be tested 201 connected to the ring oscillation circuit 1.
[0046] The type of the first transistor M1 is opposite to that of the second transistor M2.
[0047] The types of the first transistor M1 and the second transistor M2 include PMOS transistors and NMOS transistors.
[0048] In this embodiment, the first transistor M1 is a PMOS transistor, and the second transistor M2 is an NMOS transistor.
[0049] The control terminal level states of the first transistor M1 and the second transistor M2 in each standard unit 201 to be tested in the measurement circuit are shown in Table 1:
[0050]
[0051] Table 1
[0052] The values in each column in Table 1 represent the level states of the same control terminal in different measurement orders, and the values in each row represent the level states of different control terminals in the same standard unit 201 to be tested in the same measurement order.
[0053] In a specific embodiment, in a first measurement sequence, the selector 202 selects the first transistor M1 as the standard unit to be tested 201 to be connected to the ring oscillator circuit 1. The test module 203 applies a low level to the control terminal A1 of the first transistor M1 and the second transistor M2 of the first-level standard unit to be tested 201. Since the first transistor M1 is a PMOS transistor and the second transistor M2 is an NMOS transistor, in the first-level standard unit to be tested 201, the first transistor M1 is turned on and the second transistor M2 is turned off; a high level is applied to the control terminals (i.e., A2, A3, etc. in the table) of the first transistor M1 and the second transistor M2 in other standard units to be tested 201, turning off the first transistor M1 in the other standard units to be tested 201, and turning off the second transistor M2 in the other standard units to be tested 201 through the selector 202, so that only the first transistor M1 of the first-level standard unit to be tested 201 in the current load circuit 2 is connected to the ring oscillator circuit 1.
[0054] In the second measurement sequence, the selector 202 selects the first transistor M1 as the standard cell to be tested 201 to be connected to the ring oscillator circuit 1. The test module 203 applies a low level to the control terminals (A1, A2) of the first transistor M1 and the second transistor M2 of the first-stage standard cell to be tested 201 and the second-stage standard cell to be tested 201. Since the first transistor M1 is a PMOS transistor and the second transistor M2 is an NMOS transistor, in the first-stage standard cell to be tested 201 and the second-stage standard cell to be tested 201, the first transistor M1 is turned on and the second transistor M2 is turned off. A high level is applied to the control terminals (i.e., A3, etc. in the table) of the first transistor M1 and the second transistor M2 in the other standard cells to be tested 201 to turn off the first transistor M1 in the other standard cells to be tested 201, and the second transistor M2 in the other standard cells to be tested 201 is turned off through the selector 202, so that only the first transistor M1 of the first-stage standard cell to be tested 201 and the second-stage standard cell to be tested 201 in the current load circuit 2 is connected to the ring oscillator circuit 1.
[0055] In the third measurement sequence, the selector 202 selects the first transistor M1 as the standard unit to be tested 201 to be connected to the ring oscillation circuit 1, and the test module 203 applies a low level to the control terminals (A1, A2, A3) of the first transistor M1 and the second transistor M2 of the first-level standard unit to be tested 201, the second-level standard unit to be tested 201, and the third-level standard unit to be tested 201. Since the first transistor M1 is a PMOS tube and the second transistor M2 is an NMOS tube, the first-level standard unit to be tested 201, the second-level standard unit to be tested 201, and the third-level standard unit to be tested In the quasi-unit 201, the first transistor M1 is turned on and the second transistor M2 is turned off; a high level is applied to the control ends of the first transistor M1 and the second transistor M2 in other standard units to be tested 201 (i.e., the part omitted in the table), turning off the first transistor M1 in other standard units to be tested 201, and turning off the second transistor M2 in other standard units to be tested 201 through the selector 202, so that only the first transistors M1 of the first-level standard unit to be tested 201, the second-level standard unit to be tested 201, and the third-level standard unit to be tested 201 in the current load circuit 2 are connected to the ring oscillation circuit 1.
[0056] In the above scheme, the selector 202 selects and the test module 203 controls the level state of the control terminal of the first transistor M1 and the second transistor M2 in each standard unit 201 to be tested, and different numbers of first transistors M1 are connected to the ring oscillation circuit 1 in different orders. By linearly increasing the number of connected transistors, the delay of the ring oscillation circuit 1 is linearly increased. That is, the connection of different numbers of transistors results in different delay times of the ring oscillation circuit 1, and the size of the measured capacitance is thereby measured.
[0057] Figure 3 Schematic diagram of the linear relationship between the delay time of the ring oscillator circuit in the measurement circuit and the number of standard units connected to be measured in one embodiment of the present invention.
[0058] Please refer to Figure 3 , Figure 3 The X-axis represents the number of the standard cells 201 to be tested connected to the ring oscillation circuit, and the Y-axis represents the delay time of the ring oscillation circuit corresponding to different numbers of the standard cells 201 to be tested.
[0059] The number N of standard units to be tested in the above linear diagram and the delay time t of the ring oscillator circuit delay The linearity is 0.999, which is close to 1. It can be seen that the linear relationship between the number of standard units 201 to be tested connected to the ring oscillation circuit and the delay time of the ring oscillation circuit is positively correlated, thereby improving the accuracy of the measurement of the effect capacitance value.
[0060] In this embodiment, the electrical parameters include the delay time tdelay , first frequency F, output resistance value R and parasitic capacitance value C2.
[0061] The testing module 203 is further configured to obtain a first frequency F in the ring oscillation circuit 1 .
[0062] The test module 203 is further configured to obtain a delay time t according to the first frequency F. delay =1 / F*2N=N*R*C1+R*C2; According to the formula t delay =N*R*C1+R*C2, the slope in the formula is K=R*C1, that is, the effective capacitance value is C1=K / R, where C2 is the parasitic capacitance value in the ring oscillation circuit 1.
[0063] Among them, the delay time t delay =1 / F*2N is the delay time of each digital unit, and the total delay time of all digital units is t delay *2N.
[0064] Among them, the output resistance value R is the on-resistance of the transistor in the digital unit. According to the formula t delay =N*R*C1+R*C2, the slope in the formula is K=R*C1, that is, the output resistance R=K / C2.
[0065] The number of the standard cells 201 to be tested in the above solution can be flexibly selected according to the test requirements, thereby achieving the measurement of the capacitance changes in different structural layers of the standard cells 201 to be tested.
[0066] In addition, the technical solution of the present invention only needs to measure the frequency of the ring oscillator and calculate according to the frequency to obtain the value of the effect capacitance, which facilitates simulation and manufacturing implementation as well as data comparison between manufacturing and simulation.
[0067] Correspondingly, the technical solution of the present invention also provides a working method of a measuring circuit, including: applying a first voltage V1 to the power supply voltage terminal of the standard unit to be tested and the digital unit, so that an oscillation signal is generated in the ring oscillation loop, applying a first level to N standard units to be tested, so that the first type of transistor or the second type of transistor in the standard unit to be tested is turned on and connected to the ring oscillation loop, and obtaining the electrical parameters of the standard unit to be tested after the first type of transistor or the second type of transistor is connected to the ring oscillation loop, where N is the number of standard units to be tested connected to the ring oscillation loop.
[0068] In this embodiment, the electrical parameters include the delay time t delay , first frequency F, output resistance value R, effective capacitance value C1 and parasitic capacitance value C2.
[0069] In this embodiment, the step of obtaining the electrical parameters of the standard unit to be tested further includes: obtaining a first frequency F in the ring oscillation loop.
[0070] In this embodiment, the step of obtaining the electrical parameters of the standard unit to be tested further includes: obtaining the delay time t according to the first frequency F. delay =1 / F*2N=N*R*C1+R*C2; According to the formula t delay =N*R*C1+R*C2, and the slope in the formula is K=R*C1, that is, the effective capacitance value is C1=K / R, where C2 is the parasitic capacitance value in the ring oscillation loop.
[0071] In the above solution, the electrical parameter to be measured is obtained during the oscillation of the ring oscillation circuit, wherein the delay time t is obtained. delay , the first frequency F and the parasitic capacitance value C2, to obtain the output resistance value R and the effective capacitance value C1, thereby achieving performance testing of the standard cell and optimization of the standard cell.
[0072] Correspondingly, the technical solution of the present invention also provides a layout measurement circuit, including: a ring oscillation circuit, including an odd number of digital unit layouts connected in series, each of the digital unit layouts including an input end and an output end, the output end of each digital unit layout is connected to the input end of the next level of digital unit, and the output end of the last level of digital unit layout is connected to the input end of the first level of digital unit layout; a number of load circuits are connected between two adjacent levels of digital unit layouts, and the load circuits include a number of standard unit layouts to be tested.
[0073] In this embodiment, the plurality of standard cell layouts to be tested are connected in parallel.
[0074] In this embodiment, the standard cell layout to be tested is one or more of an AND gate circuit standard cell layout, an OR gate circuit standard cell layout, a NOT gate circuit standard cell layout, and a multiplexer standard cell layout.
[0075] In this embodiment, each of the standard cell layouts to be tested includes: a first type of transistor and a second type of transistor, and both the first type of transistor and the second type of transistor include a first end, a second end, and a control end.
[0076] In this embodiment, the load circuit also includes: a selector, the selector including an input end, a first output end, and a second output end, the input end of the selector is connected between two adjacent levels of digital unit layouts, the first output end of the selector is connected to the first end or the second end of the first type of transistor, and the second output end of the selector is connected to the first end or the second end of the second type of transistor.
[0077] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A measurement circuit for measuring the effect capacitance of a standard cell, characterized in that: include: A ring oscillator circuit includes an odd number of digital units connected in series, each of the digital units including an input and an output, the output of each digital unit connected to the input of a subsequent digital unit, and the output of the last digital unit connected to the input of the first digital unit; A plurality of load circuits are connected between two adjacent digital units, and the load circuits include a plurality of standard units to be tested.
2. The measuring circuit according to claim 1, wherein: The plurality of standard units to be tested are connected in parallel.
3. The measuring circuit according to claim 2, wherein: The standard cell to be tested is one or a combination of an AND gate circuit standard cell, an OR gate circuit standard cell, a NOT gate circuit standard cell, and a multiplexer standard cell.
4. The measuring circuit according to claim 3, wherein: Each of the standard units to be tested includes: a first type of transistor and a second type of transistor, and both the first type of transistor and the second type of transistor include a first end, a second end, and a control end.
5. The measuring circuit according to claim 4, wherein: The load circuit also includes: a selector, which includes an input end, a first output end, and a second output end. The input end of the selector is connected between two adjacent levels of digital units, the first output end of the selector is connected to the first end or the second end of the first type of transistor, and the second output end of the selector is connected to the first end or the second end of the second type of transistor.
6. The measuring circuit according to claim 5, wherein: Also includes: A test module connected to the control terminals of the first and second type transistors and the standard cell to be tested; the test module is configured to apply a first electrical level to N standard cells to be tested, so that the first or second type transistors within the standard cells to be tested are turned on and connected to the ring oscillation circuit, and obtain electrical parameters of the standard cells to be tested after the first or second type transistors are connected to the ring oscillation circuit, where N is the number of standard cells to be tested connected to the ring oscillation circuit.
7. The measuring circuit according to claim 6, wherein: The electrical parameters include the delay time t delay , first frequency F, output resistance value R and parasitic capacitance value C2.
8. The measuring circuit according to claim 7, wherein: The testing module is further configured to obtain a first frequency F in the ring oscillation circuit.
9. The measuring circuit according to claim 8, wherein: The test module is further configured to obtain a delay time t according to the first frequency F. delay =1 / F*2N=N*R*C1+R*C2; According to the formula t delay =N*R*C1+R*C2, and the slope in the formula is K=R*C1, that is, the effective capacitance value is C1=K / R, where C2 is the parasitic capacitance value in the ring oscillation circuit.
10. A method for operating a measuring circuit, characterized in that: include: A first electrical level is applied to N standard cells to be tested, so that the first type transistor or the second type transistor in the standard cell to be tested is turned on and connected to a ring oscillation circuit. After the first type transistor or the second type transistor is connected to the ring oscillation circuit, electrical parameters of the standard cell to be tested are obtained, where N is the number of standard cells to be tested connected to the ring oscillation circuit.
11. The operating method of the measuring circuit according to claim 10, characterized in that: The electrical parameters include the delay time t delay , first frequency F, output resistance value R, effective capacitance value C1 and parasitic capacitance value C2.
12. The operating method of the measuring circuit according to claim 11, characterized in that: The obtaining of the electrical parameters of the standard unit to be tested further includes: obtaining a first frequency F in the ring oscillation circuit.
13. The operating method of the measuring circuit according to claim 12, characterized in that: The step of obtaining the electrical parameters of the standard unit to be tested further includes: obtaining the delay time t according to the first frequency F. delay =1 / F*2N=N*R*C1+R*C2; According to the formula t delay =N*R*C1+R*C2, and the slope in the formula is K=R*C1, that is, the effective capacitance value is C1=K / R, where C2 is the parasitic capacitance value in the ring oscillation circuit.
14. A layout measurement circuit, characterized in that: include: A ring oscillator circuit includes an odd number of digital unit layouts connected in series, each of the digital unit layouts including an input and an output, the output of each digital unit layout being connected to the input of the next digital unit, and the output of the last digital unit layout being connected to the input of the first digital unit layout; A plurality of load circuits are connected between two adjacent levels of digital unit layouts, and the load circuits include a plurality of standard unit layouts to be tested.
15. The layout measurement circuit according to claim 14, wherein: include: The plurality of standard cells to be tested are connected in parallel.
16. The layout measurement circuit according to claim 15, wherein: include: The standard cell layout to be tested is one or more of an AND gate circuit standard cell layout, an OR gate circuit standard cell layout, a NOT gate circuit standard cell layout, and a multiplexer standard cell layout.
17. The layout measurement circuit according to claim 16, wherein: include: Each of the standard cell layouts to be tested includes: a first type of transistor and a second type of transistor, and both the first type of transistor and the second type of transistor include a first end, a second end, and a control end.
18. The layout measurement circuit according to claim 17, wherein: include: The load circuit also includes: a selector, which includes an input end, a first output end, and a second output end. The input end of the selector is connected between two adjacent levels of digital unit layouts, the first output end of the selector is connected to the first end or the second end of the first type of transistor, and the second output end of the selector is connected to the first end or the second end of the second type of transistor.