Regulator and power device

Abstract

A regulator includes a reference potential generation circuit that generates a reference potential serving as a reference for an intermediate potential and an intermediate potential lower than the intermediate potential, a differential amplifier supplied with the intermediate potential as a low-potential-side power supply, and a transistor connected to the differential amplifier as a low-potential-side power supply. And a transistor having a gate to which the amplified differential voltage is input, a drain connected to a ground potential via a constant current source or a resistor, and a source generating the intermediate potential, and amplifying a differential voltage between a feedback potential corresponding to the intermediate potential and a reference potential.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2024-021989 filed on February 16, 2024 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a regulator and a power device. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Laid-Open Patent Application No. 2020-014356

[0006] Patent Document 1 discloses a technique for generating an intermediate potential using a Zener diode. Summary of the Invention

[0007] Patent Document 1 discloses setting the current flowing through the Zener diode according to the maximum current of a circuit to which the intermediate potential is supplied (eg, an internal circuit of a power device). Therefore, there is a problem that a large current is required to generate the intermediate potential.

[0008] The present disclosure is to solve such problems and aims to realize a regulator and a power device that can be controlled with a small current.

[0009] Other issues and novel features will become clear from the description of this specification and the accompanying drawings.

[0010] According to one embodiment, a regulator includes a reference potential generating circuit, a differential amplifier, and a first transistor. The reference potential generating circuit generates a reference potential used as a reference for a first intermediate potential and a second intermediate potential lower than the first intermediate potential. The differential amplifier is supplied with the second intermediate potential as a low-potential side power supply and amplifies a differential voltage between a feedback potential corresponding to the first intermediate potential and the reference potential. The first transistor has a gate to which the amplified differential voltage is input, a drain connected to a ground potential via a constant current source or a resistor, and a source that generates the first intermediate potential.

[0011] According to one embodiment, a power device includes a reference potential generating circuit, a differential amplifier, a first transistor, and a control circuit, wherein the reference potential generating circuit generates a reference potential used as a reference for a first intermediate potential and a second intermediate potential lower than the first intermediate potential, the differential amplifier is supplied with the second intermediate potential as a low-potential side power supply and amplifies a differential voltage between a feedback potential corresponding to the first intermediate potential and the reference potential, the first transistor has a gate to which the amplified differential voltage is input, a drain connected to a ground potential via a constant current source or a resistor, and a source to which the first intermediate potential is generated, and the control circuit is supplied with the first intermediate potential as a low-potential side power supply and controls the power transistor.

[0012] According to the embodiment, a regulator and a power device that can be controlled with a small current can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a circuit diagram illustrating a configuration of a regulator according to a first embodiment;

[0014] Figure 2 is a circuit diagram illustrating a configuration of a regulator according to a first modification of the first embodiment;

[0015] Figure 3 is a circuit diagram illustrating a configuration of a regulator according to a second modification of the first embodiment;

[0016] Figure 4 is a circuit diagram illustrating a configuration of a regulator according to a second embodiment; and

[0017] Figure 5 is a schematic circuit diagram illustrating the configuration of a power device according to a third embodiment. DETAILED DESCRIPTION

[0018] For the sake of clarity, the following description and drawings are omitted and simplified appropriately. In each figure, the same elements are given the same reference numerals, and repeated descriptions are omitted when necessary.

[0019] First embodiment

[0020] Figure 11 is a circuit diagram illustrating the configuration of a regulator 1 according to a first embodiment. The regulator 1 uses a power supply voltage VCC as an input voltage and generates an intermediate potential VFGND as an output voltage. The intermediate potential VFGND is also referred to as a first intermediate potential. The intermediate potential VFGND is supplied to the internal circuit 2 as a low-potential side power supply voltage. Although the internal circuit 2 specifically refers to an internal circuit of an intelligent power device (IPD), such as a control circuit, the internal circuit 2 can be any arbitrary circuit. The intermediate potential VFGND is preferably a voltage that is approximately 5 to 8 V lower than the power supply voltage VCC so that the internal circuit 2 can be formed by low-voltage components.

[0021] The regulator 1 includes a reference potential generating circuit 11, a differential amplifier 12, and a p-channel metal oxide semiconductor (MOS) transistor Tr1. The reference potential generating circuit 11 generates a reference potential Vref and an intermediate potential VFGNDL. The reference potential Vref and the intermediate potential VFGNDL are also referred to as the first reference potential and the second reference potential, respectively. The intermediate potential VFGNDL is lower than the intermediate potential VFGND. The intermediate potential VFGNDL is also referred to as the second intermediate potential. The intermediate potentials VFGND and VFGNDL are potentials between the power supply potential VCC and the ground potential GND. Note that a metal oxide semiconductor field effect transistor (MOSFET) can also be used for the p-channel MOS transistor Tr1. To drive the p-channel MOS transistor Tr1, the intermediate potential VFGNDL is preferably a voltage approximately 1V lower than the intermediate potential VFGND.

[0022] The regulator 1 also includes n-channel MOS transistors Tr2 to Tr4 and p-channel MOS transistors Tr5 to Tr6. The sources of the MOS transistors Tr2, Tr3, and Tr4 are connected to the ground potential GND. A bias voltage BIAS is supplied to the gates of the MOS transistors Tr2, Tr3, and Tr4. The MOS transistors Tr2, Tr3, and Tr4 each function as a constant current source. The MOS transistor Tr5 is connected in series with the MOS transistor Tr2, and the MOS transistor Tr4 is connected in series with the MOS transistor Tr1. The MOS transistor Tr6 is provided in the path for supplying the power supply potential VCC to the differential amplifier 12 and functions as a constant current source to ensure stable operation of the differential amplifier 12. The gates of the MOS transistors Tr5 and Tr6 are connected to the drain of the MOS transistor Tr5.

[0023] Reference potential generating circuit 11 includes a Zener diode ZD1 and a p-channel MOS transistor Tr7. Zener diode ZD1 is also referred to as a second Zener diode. Zener diode ZD1 and MOS transistor Tr7 are connected in series and positioned in the path between power supply potential VCC and MOS transistor Tr3. The cathode of Zener diode ZD1 is connected to power supply potential VCC. The gate and drain of MOS transistor Tr7 are connected, and MOS transistor Tr7 functions as a diode. The anode of the diode is connected to the anode of Zener diode ZD1.

[0024] The reference potential Vref used as a reference for the intermediate potential VFGND is generated at the anode of the Zener diode ZD1. When the Zener voltage of the Zener diode ZD1 is expressed as Vz, the reference potential Vref is given by VCC-Vz. The intermediate potential VFGNDL is generated at the cathode of the diode formed by the MOS transistor Tr7.

[0025] The intermediate potential VFGNDL is supplied to the differential amplifier 12 as a low-potential power supply voltage. A reference potential Vref is input to a first input terminal of the differential amplifier 12. A potential corresponding to the intermediate potential VFGND is supplied as a feedback potential to a second input terminal of the differential amplifier 12. Specifically, the source voltage of the MOS transistor Tr1 is supplied as a feedback potential to the second input terminal of the differential amplifier 12. The differential amplifier 12 amplifies the differential voltage between the reference potential Vref and the feedback potential and outputs the amplified differential signal.

[0026] The gate of the MOS transistor Tr1 is connected to the output of the differential amplifier 12. That is, the amplified differential voltage is input to the gate of the MOS transistor Tr1. The drain of the MOS transistor Tr1 is connected to the ground potential GND via the MOS transistor Tr4 forming a constant current source. In addition, the drain of the MOS transistor Tr1 can be connected to the ground potential GND via a resistor instead of the MOS transistor Tr4. The resistor can be a resistor for limiting the current in the internal circuit 2. The source of the MOS transistor Tr1 is the output of the regulator 1. That is, the source voltage of the MOS transistor Tr1 is the output voltage of the regulator 1, that is, the intermediate potential VFGND. The MOS transistors Tr1 and Tr4 form a source follower circuit.

[0027] The current flowing through MOS transistors Tr2 and Tr5 is IR0, the current flowing through MOS transistor Tr3 is IR1, the current flowing through MOS transistor Tr6 is IR2, and the current flowing through MOS transistor Tr4 is IR3. MOS transistor Tr6 is configured so that current IR2 is a replica of current IR0 at a predetermined mirror ratio. Current IR2 flows to differential amplifier 12. MOS transistor Tr3 is configured so that current IR1 is greater than current IR2. The difference between current IR1 and current IR2 flows through reference potential generating circuit 11. Current IR3 is N times current IR1 and is set based on the maximum current flowing through internal circuit 2. In idle mode, currents IR0 and IR1 can be controlled to be small.

[0028] The operation of the regulator 1 according to the first embodiment will be described. As described above, the regulator 1 receives the power supply voltage VCC as input and outputs the intermediate potential VFGND. The intermediate potential VFGND is the source voltage of the MOS transistor Tr1. The MOS transistor Tr1 is controlled by the output of the differential amplifier 12.

[0029] The differential amplifier 12 controls the MOS transistor Tr1 based on the differential voltage between the reference voltage Vref and the source voltage of the MOS transistor Tr1 (serving as a feedback potential). Specifically, the differential amplifier 12 controls the MOS transistor Tr1 in response to fluctuations in the potential of the intermediate potential VFGND. For example, when the potential of the intermediate potential VFGND falls below the reference potential Vref due to load fluctuations in the internal circuit 2, the differential amplifier 12 controls the voltage at the gate of the MOS transistor Tr1 to increase. Because the MOS transistor Tr1 functions as a source follower, its source voltage follows the increase in the gate voltage of the MOS transistor Tr1. This causes the intermediate potential VFGND to rise. On the other hand, when the potential of the intermediate potential VFGND rises above the reference potential Vref due to load fluctuations in the internal circuit 2, the differential amplifier 12 controls the gate voltage of the MOS transistor Tr1 to decrease. As a result, the voltage at the source of the MOS transistor Tr1 follows the decrease in the gate voltage of the MOS transistor Tr1. Through this operation, the intermediate potential VFGND stabilizes at a value equal to the reference voltage Vref.

[0030] In the regulator 1 according to the first embodiment, the intermediate potential VFGNDL is supplied to the differential amplifier 12 as a low-potential power supply. Since the differential amplifier 12 only needs to control the MOS transistor Tr1, the intermediate potential VFGNDL, which serves as the low-potential power supply voltage, can be approximately 1V lower than the intermediate potential VFGND (VCC - VFGNDL = 6 to 9V). As a result, the differential amplifier 12 can be formed using low-voltage components and a low-voltage circuit, thereby reducing the current flowing through the differential amplifier 12. Furthermore, the currents IR1 and IR2 of the reference potential generating circuit 11 and the differential amplifier 12 can be set regardless of the current supplied to the internal circuit 2. Therefore, the current flowing through the reference potential generating circuit 11 can also be reduced.

[0031] Therefore, the regulator 1 according to the first embodiment can be controlled with a small current. In addition, since the differential amplifier 12 can be formed of low-voltage elements, the circuit scale is small and control is easy.

[0032] Since the output of the differential amplifier 12 is always at approximately the intermediate potential VFGND-Vtp, the response speed of the MOS transistor Tr1 is fast and the risk of oscillation is low. Vtp represents the threshold voltage of the p-channel MOS transistor Tr1.

[0033] First Modification of the First Embodiment

[0034] Figure 2 : is a circuit diagram illustrating the configuration of a regulator 1a according to a first modification. Figure 1 and Figure 2 In comparison, the regulator 1a according to the first modification further includes a feedback circuit F. The feedback circuit F includes a diode D1. The cathode of the diode D1 is connected to the source of the MOS transistor Tr1. The anode of the diode D1 serves as the output of the regulator 1a.

[0035] When the Zener voltage of the Zener diode ZD1 is Vz and the forward voltage of the diode D1 is VF, the regulator 1a controls the MOS transistor Tr1 to satisfy VFGND-VF=VCC-Vz. Therefore, the intermediate potential VFGND is stabilized at (VCC-Vz)+VF.

[0036] The regulator 1 a according to the first modification generates an intermediate potential VFGND different from the reference voltage Vref of the differential amplifier 12 by using the feedback circuit F.

[0037] Second Modification of the First Embodiment

[0038] Figure 3 : is a circuit diagram illustrating the configuration of a regulator 1b according to the second modification. Figure 1 and Figure 3In comparison, the Zener diode ZD1 forming the reference potential generating circuit 11 is replaced by a plurality of diodes D2 connected in series. The diode may be a MOS transistor whose gate and drain are connected to each other. In addition, circuit elements such as resistors may be used instead of diodes.

[0039] As in the reference potential generating circuit 11 according to the second modification, the reference potential may be generated using a diode or a resistor without being limited to the Zener diode.

[0040] Second embodiment

[0041] Figure 4 is a circuit diagram illustrating the configuration of a regulator 10 according to the second embodiment.

[0042] Will Figure 1 and Figure 4 In comparison, the regulator 10 further includes a Zener diode ZD2 , a capacitor C, and n-channel MOS transistors Tr8 to Tr10 .

[0043] The cathode of the Zener diode ZD2 is connected to the power supply potential VCC, and the anode of the Zener diode ZD2 is connected to the output of the regulator 10. The Zener diode ZD2 is also called a first Zener diode. A capacitor C is connected in parallel to the Zener diode ZD2.

[0044] The sources of the MOS transistors Tr8 and Tr9 are connected to the ground potential GND. The gates of the MOS transistors Tr8 and Tr9 are connected to the drain of the MOS transistor Tr8. The MOS transistor Tr9 copies the current flowing through the MOS transistor Tr8 and supplies the current to the Zener diode ZD2.

[0045] MOS transistor Tr10 is provided in the path between Zener diode ZD2 and MOS transistor Tr9. MOS transistor Tr10 is also referred to as a second transistor. A control signal IDLE_DIS is input to the gate of MOS transistor Tr10. The control signal IDLE_DIS indicates whether internal circuit 2 is in idle mode or normal mode. In the second embodiment, when the idle mode of internal circuit 2 is disabled, that is, when internal circuit 2 is in normal mode, the control signal IDLE_DIS is at an H level. Thus, MOS transistor Tr10 functions as a switch that uses the control signal IDLE_DIS to switch the connection state between Zener diode ZD2 and MOS transistor Tr9.

[0046] The current flowing through MOS transistor Tr9 is represented as IR4. MOS transistor Tr9 is configured so that current IR4 is greater than the maximum current of internal circuit 2 in normal mode. Current IR4 is set to N times (N is an integer equal to or greater than 1) the current IR1 flowing through MOS transistor Tr3. Furthermore, MOS transistor Tr4 is configured so that current IR3 flowing through MOS transistor Tr4 is greater than the maximum current of internal circuit 2 in idle mode. Current IR3 is set to M times (M is an integer equal to or greater than 1) the current IR1. Current IR4 is greater than current IR3. In other words, N is greater than M.

[0047] Similar to the first embodiment, the source voltage of MOS transistor Tr1 is the intermediate potential VFGND supplied to internal circuit 2. When internal circuit 2 is in idle mode, control signal IDLE_DIS indicates an L level, turning off MOS transistor Tr10. Therefore, when internal circuit 2 is in idle mode, the current flowing through internal circuit 2 flows through the path in which MOS transistors Tr1 and Tr4 are provided. Internal circuit 2 is supplied with the intermediate potential VFGND generated by MOS transistor Tr1.

[0048] When the internal circuit 2 is in normal mode, the control signal IDLE_DIS indicates an H level, causing the MOS transistor Tr10 to be controlled to be in the on state. Therefore, when the internal circuit 2 is in normal mode, the current flowing through the internal circuit 2 primarily flows through the path in which the MOS transistor Tr9 is provided. The difference between the current IR4 and the current flowing through the internal circuit 2 then flows through the Zener diode ZD2, generating an intermediate potential VFGND at the anode of the Zener diode ZD2. The internal circuit 2 is supplied with the intermediate potential VFGND generated by the Zener diode ZD2. When the internal circuit 2 is in normal mode, to suppress fluctuations in the intermediate potential VFGND, the current IR4 flowing through the MOS transistor Tr9 is made greater than the current flowing through the internal circuit 2 in normal mode.

[0049] The differential amplifier 12 may include a function for adjusting an offset. For example, the offset of the differential amplifier 12 may be adjusted so that the intermediate potential VFGND generated by the MOS transistor Tr1 is higher than the intermediate potential VFGND generated by the Zener diode ZD2.

[0050] Furthermore, the differential amplifier 12 includes an offset adjustment function, thereby reducing the effects of characteristic variations of the Zener diodes ZD1 and ZD2. For example, consider the case in the second embodiment where the characteristics of the Zener diodes ZD1 and ZD2 vary. The output of the regulator 10 (i.e., the source voltage of the MOS transistor Tr1) is controlled by the differential amplifier 12 to become the voltage of the Zener diode ZD1. Due to the difference between the voltage generated by the Zener diodes ZD2 and ZD1, unnecessary current may flow. However, by adjusting the offset of the differential amplifier 12, this unnecessary current can be reduced.

[0051] When the internal circuit 2 is in normal mode, the current IR4 flowing through the MOS transistor Tr9 must be greater than the current flowing through the internal circuit 2 during normal mode in order to stably supply the intermediate potential VFGND. On the other hand, when the internal circuit 2 is in idle mode, the current flowing through the internal circuit 2 is smaller than when the internal circuit 2 is in normal mode. Therefore, in the second embodiment, the power consumption of the regulator 10 when the internal circuit 2 is in idle mode is smaller than when the internal circuit 2 is in normal mode.

[0052] In the second embodiment, MOS transistors Tr1 and Tr4 are configured so that current IR3 flows therethrough, which is the estimated maximum current when the internal circuit 2 is in idle mode. Therefore, MOS transistors Tr1 and Tr4 can be formed to be smaller in size than MOS transistor Tr9. Furthermore, differential amplifier 12 can be formed using low-voltage components as described in the first embodiment. Consequently, the circuit scale of differential amplifier 12 can also be reduced.

[0053] When the internal circuit 2 is in the idle mode, the regulator 10 of the second embodiment can reduce the current flowing through the regulator 10 .

[0054] Furthermore, an n-channel MOS transistor (not shown) may be further provided in the path between the MOS transistor Tr1 and the MOS transistor Tr4. An inverted signal of the control signal IDLE_DIS may be input to the gate of the MOS transistor. Consequently, when the internal circuit 2 is in normal mode, no current flows through the MOS transistors Tr1 and Tr4, and the intermediate potential VFGND may be supplied only by the Zener diode ZD2.

[0055] Third embodiment

[0056] Figure 5 1 is a schematic circuit diagram illustrating a configuration of an intelligent power device (IPD) 100 according to a third embodiment. The IPD 100 includes the regulator 10 according to the second embodiment. It should be noted that the IPD 100 may also include the regulator 1 according to the first embodiment.

[0057] IPD 100 includes n-channel power MOS transistor Tr11, regulator 1, level shifter 101, control circuit 102, charge pump 103, level shifter 104, driver 105, n-channel sense MOS transistor Tr12, and current detection circuit 106. Control circuit 102 and charge pump 103 correspond to internal circuit 2 described above.

[0058] The power MOS transistor Tr11 is provided in a path for supplying a power supply potential VCC to the load circuit 3, which may include an inductor, a resistor, a capacitor, etc. The power supply potential VCC may be generated by a battery. A drive signal from the driver 105 is input to the gate of the power MOS transistor Tr11. The potential at the source of the power MOS transistor Tr11 is output as the output potential OUT.

[0059] The regulator 10 has a configuration similar to that of the regulator 10 in the second embodiment and generates an intermediate potential VFGND. The intermediate potential VFGND is supplied to the control circuit 102, the charge pump 103, and the level shifter 104. Furthermore, the regulator 10 receives a detection result from the current detection circuit 106. Based on the detection result, the regulator 10 can identify whether the control circuit 102 is set to normal mode or idle mode. In other words, the detection result of the current detection circuit 106 corresponds to the control signal IDLE_DIS in the second embodiment.

[0060] The level shifter 101 converts a control signal that transitions with a predetermined amplitude from ground potential GND as a low level into a signal that transitions with a predetermined amplitude from power supply potential VCC as a high level. The control circuit 102 controls the charge pump 103 based on the level-shifted control signal and transmits the control signal to the driver 105 via the level shifter 104. Under the control of the control circuit 102, the charge pump 103 generates a boosted potential CPOUT that is higher than the power supply potential VCC. The level shifter 104 converts the control signal from the control circuit 102 into a signal that transitions with a predetermined amplitude from boosted potential CPOUT as a high level. The driver 105 generates a drive signal for driving the gate of the power MOS transistor Tr11 based on the level-shifted control signal. The drive signal is also input to the gate of the sense MOS transistor Tr12. A small current flows through the sense MOS transistor Tr12. This small current is a replica of the current flowing through the power MOS transistor Tr11 with a low mirror ratio. The current flowing through the sense MOS transistor Tr12 is represented as current Is.

[0061] The current detection circuit 106 detects whether the minute current Is flowing through the sense MOS transistor Tr12 is equal to or less than a specific current value. For example, the current detection circuit 106 can use a comparator to compare the voltage generated across the resistor through which the minute current Is flows with a threshold voltage. In addition, the voltage generated across the resistor can be digitized by an analog-to-digital converter (ADC), and the digitized voltage value can be compared with a threshold voltage.

[0062] When the current detection circuit 106 detects that the current Is is lower than a specific current value, it is determined that the load circuit 3 has entered the idle state. Therefore, the detection result of the current detection circuit 106 is transmitted to the control circuit 102 via the level shifter 101, and the control circuit 102 is set to the idle mode. Otherwise, the control circuit 102 is set to the normal mode. For example, when the current Is is equal to or lower than a specific current value, the regulator 10 can use the differential amplifier 12 and the MOS transistor Tr1 to generate the intermediate potential VFGND, and when the current Is is not equal to or lower than a certain current value. The regulator 10 can use the Zener diode ZD2 to generate the intermediate potential VFGND. Specifically, the detection signal output by the current detection circuit 106 corresponds to the control signal IDLE_DIS in the second embodiment.

[0063] In the IPD 100 of the third embodiment, since the intermediate potential VFGND is supplied to the control circuit 102 and the like, the control circuit 102 and the like can be formed of low-voltage components. In addition, when the load circuit 3 is in an idle state, the IPD 100 can reduce the current consumption of the IPD 100 by reducing the current required to generate the intermediate potential VFGND.

[0064] Furthermore, in the third embodiment, the regulator 10 may be replaced with the regulator 1 of the first embodiment. In this case, the regulator 1 of the first embodiment can generate the intermediate potential VFGND regardless of the detection result of the current detection circuit 106, that is, regardless of the operating state of the load circuit 3.

[0065] In the third embodiment, the regulator 10 can be replaced with a configuration similar to that of the regulator 1 in the first embodiment, and the current flowing through the regulator 1 can also be switched based on the detection result of the current detection circuit 106. For example, the MOS transistors Tr1 and Tr4 can be configured so that the amount of current allowed to flow through the path of the MOS transistors Tr1 and Tr4 can be switched based on the detection result of the current detection circuit 106. That is, when the control circuit 102 is set to idle mode based on the detection result of the current detection circuit 106, the amount of current flowing through the path of the MOS transistors Tr1 and Tr4 is less than the current flowing through the path of the MOS transistors Tr1 and Tr4 when the control circuit 102 is set to normal mode. As a result, when the load circuit 3 is in the idle state, the intermediate potential VFGND can be supplied with lower power consumption. In addition, to ensure a stable supply of the intermediate potential VFGND, the amount of current supplied to the differential amplifier 12 can be switched based on the detection result of the current detection circuit 106.

[0066] In the above, the invention made by the inventors of this application has been specifically described based on the embodiment. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications and changes can be made within the scope of the present invention.

[0067] For example, in the regulator according to the above-described embodiment, the conductivity type (p-type or n-type) of elements such as the semiconductor substrate, semiconductor layer, and diffusion layer (diffusion region) can be reversed in configuration. Thus, when one of n-type and p-type conductivity types is designated as the first conductivity type and the other conductivity type is designated as the second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

Claims

1. A regulator, comprising: a reference potential generating circuit that generates a reference potential used as a reference for a first intermediate potential and a second intermediate potential lower than the first intermediate potential; a differential amplifier supplied with the second intermediate potential as a low-potential-side power supply and amplifying a differential voltage between a feedback potential corresponding to the first intermediate potential and the reference potential; as well as The first transistor has a gate to which the amplified differential voltage is input, a drain connected to a ground potential via a constant current source or a resistor, and a source generating the first intermediate potential.

2. The regulator according to claim 1, further comprising: a second transistor that is controlled to be in an off state when the circuit supplied with the first intermediate potential as a low-potential-side power supply is in an idle mode; as well as a first Zener diode connected in series with the second transistor, When the circuit is in a normal mode, the first intermediate potential generated by the first Zener diode is supplied to the circuit.

3. The regulator according to claim 2, wherein the current flowing through the first transistor is set based on the maximum current of the circuit in the idle mode, and The current flowing through the second transistor in the on state is set based on the maximum current of the circuit in the normal mode.

4. The regulator according to claim 1, The diode is provided between the source of the first transistor and a node generating the first intermediate potential.

5. The regulator according to claim 1, wherein the reference potential generating circuit includes a second Zener diode and a diode connected in series, wherein the anode of the Zener diode and the anode of the diode are connected to each other, wherein the reference potential is generated at the anode of the Zener diode, and The second intermediate potential is generated at the cathode of the diode.

6. A power device comprising: a reference potential generating circuit that generates a reference potential used as a reference for a first intermediate potential and a second intermediate potential lower than the first intermediate potential; a differential amplifier supplied with the second intermediate potential as a low-potential-side power supply and amplifying a differential voltage between a feedback potential corresponding to the first intermediate potential and the reference potential; a first transistor having a gate to which the amplified differential voltage is input, a drain connected to a ground potential via a constant current source or a resistor, and a source generating the first intermediate potential; as well as The control circuit is supplied with the first intermediate potential as a low potential side power supply and controls the power transistor.

7. A regulator comprising: a reference potential generating circuit for generating a reference potential which is an intermediate potential between a power supply potential and a ground potential as an input voltage; a differential amplifier that uses the power supply potential as a high-potential-side power supply and amplifies a differential voltage between the output voltage of the regulator and the reference potential; as well as A transistor has a gate connected to the output of the differential amplifier, a drain connected to the ground potential via a constant current source or a resistor, and a source serving as an output of the regulator.

8. The regulator according to claim 7, The transistor is a p-channel MOS transistor.

9. The regulator according to claim 7, wherein the reference potential is a first reference potential, wherein the reference potential generating circuit further generates a second reference potential which is lower than the first reference potential and higher than the ground potential, and The differential amplifier is supplied with the second reference potential as a low potential side power supply.

10. The regulator according to claim 9, wherein the constant current source is a first constant current source, and The regulator further includes a second constant current source connected between a second reference potential output node outputting the second reference potential of the reference potential generating circuit and the ground potential.

11. The regulator according to claim 7, wherein the constant current source is a first constant current source, and The regulator further comprises: a Zener diode connected between a power supply voltage line supplied with the power supply potential and the output of the regulator; as well as switch and a third constant current source, connected in series to the output and the ground potential, The current flowing through the first constant current source or the resistor is smaller than the current flowing through the third constant current source.

12. A power device comprising: The regulator according to claim 7; a power transistor configured to supply a power supply potential to a load circuit; as well as a control circuit, controlling the power transistor, The control circuit is supplied with the power supply potential and operates using the output voltage of the regulator as a low-potential-side power supply.

13. The power plant according to claim 12, further comprising: a current detection unit for detecting a current flowing through the power transistor, Wherein, in the regulator, The constant current source is a first constant current source, a Zener diode connected between the input voltage and the output, and A switch and a third constant current source connected in series to the output and ground potential are included, and The switch is turned on and off according to the detection result of the current detection unit.

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