Data error correction method and device based on low-density parity check, equipment and medium

Abstract

The invention discloses a data error correction method and device based on low-density parity check, equipment and a medium, and relates to the technical field of data error correction, and the method comprises the steps: reading data to be corrected from a data memory, and carrying out the pre-verification of the data to be corrected and a verification matrix of a preset low-density parity check code, and obtaining a pre-verification result; based on the pre-verification result, determining a first error position set in a code word position set; performing bit flipping operation on code words indicated by the first error position set to complete pre-error correction; and inputting the code word after pre-error correction processing into a low density parity check decoder for decoding, outputting data after error correction, pre-detecting the error position of the code word, and performing bit flipping on the code word at the error position, thereby reducing the number of error bits entering LDPC decoding, and improving the decoding efficiency. Therefore, the number of error bits does not exceed the decoding capability limit of hard decoding, the probability that the system enters soft decoding is reduced, and the decoding throughput rate of the system is ensured.

Description

Technical Field

[0001] The present application relates to the field of data error correction technology, and in particular to a data error correction method, apparatus, device and medium based on low-density parity check. Background Art

[0002] As the capacity of Negative-AND Flash (NAND Flash) chips increases, their reliability continues to decline. In order to ensure data reliability, error correction coding is required to correct the code errors caused by the increase in capacity. In related technologies, low-density parity check code (LDPC code) is used as the error correction technology for flash memory master chips. It includes two error correction methods: hard decoding and soft decoding. That is, hard decoding is performed first during decoding, and soft decoding is performed when hard decoding fails.

[0003] When processing high bit error rate scenarios, insufficient hard decoding capabilities increase the probability of entering the soft decoding process. Although the high-performance error correction capability of soft decoding can ensure data reliability, in order to obtain soft information, the NAND needs to be reread multiple times. The delay corresponding to NAND rereading is large, which affects the efficiency of NAND reading. As a result, once the soft decoding process begins, the system's decoding throughput will drop significantly. Summary of the Invention

[0004] The present application provides a data error correction method, apparatus, device and medium based on low-density parity check (LDPC) to at least solve the problem in the related art that soft decoding error correction leads to a decrease in the decoding throughput of the system.

[0005] The present application provides a data error correction method based on a low-density parity-check code, comprising: reading data to be corrected from a data storage device, and performing pre-check processing on the data to be corrected and a check matrix of a preset low-density parity-check code to obtain a pre-check result, wherein the data to be corrected includes a codeword generated by low-density parity-check encoding; based on the pre-check result, determining a first error position set in a codeword position set; performing a bit flip operation on the codeword indicated by the first error position set to complete pre-error correction; inputting the codeword after the pre-error correction processing into a low-density parity-check decoder for decoding, and outputting the error-corrected data.

[0006] The present application also provides a data error correction device based on a low-density parity-check code, comprising: a data verification module, configured to read data to be corrected from a data storage device, and perform pre-verification processing on the data to be corrected and a check matrix of a preset low-density parity-check code to obtain a pre-verification result, wherein the data to be corrected includes a codeword generated by low-density parity-check encoding; an error position determination module, configured to determine a first error position set in a codeword position set based on the pre-verification result; a pre-error correction module, configured to perform a bit flip operation on the codeword indicated by the first error position set to complete pre-error correction; and a data error correction module, configured to input the codeword after pre-error correction processing into a low-density parity check decoder for decoding, and output the corrected data.

[0007] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned data error correction methods based on low-density parity-check codes when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned data error correction methods based on low-density parity-check codes are implemented.

[0009] Through the present application, data to be corrected is read from a data storage device, and a pre-check processing is performed on the data to be corrected and a check matrix of a preset low-density parity-check code to obtain a pre-check result; based on the pre-check result, a first error position set in a codeword position set is determined; a bit flipping operation is performed on the codeword indicated by the first error position set to complete pre-error correction; the codeword after the pre-error correction processing is input into a low-density parity-check decoder for decoding, and the error-corrected data is output. By pre-detecting the error position of the codeword and bit flipping the codeword at the error position, the number of error bits entering the LDPC decoder is reduced, thereby ensuring that the number of error bits does not exceed the decoding capability limit of hard decoding, reducing the probability of the system entering soft decoding, and ensuring the decoding throughput of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 This is an example diagram of the existing LDPC error correction process;

[0012] Figure 2A flowchart of a data error correction method based on low-density parity-check codes provided in an embodiment of the present application;

[0013] Figure 3 A flowchart of another data error correction method based on low-density parity-check codes provided in an embodiment of the present application;

[0014] Figure 4 An example diagram of a matrix including row check values and the number of row check failures provided in an embodiment of the present application;

[0015] Figure 5 An example flow chart of a data error correction method based on low-density parity-check codes provided in an embodiment of the present application;

[0016] Figure 6 A flowchart of another data error correction method based on low-density parity-check codes provided in an embodiment of the present application;

[0017] Figure 7 An example matrix diagram including row check values, number of row check failures, and number of oscillations provided in an embodiment of the present application;

[0018] Figure 8 This is a flowchart illustrating another data error correction method based on low-density parity-check codes provided in an embodiment of the present application;

[0019] Figure 9 A structural block diagram of a data error correction device based on low-density parity-check code provided in an embodiment of the present application;

[0020] Figure 10 This is a structural block diagram of the electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0022] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0023] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0024] With the continuous development of NAND Flash technology, its storage media capacity and performance continue to improve. However, the technological development of capacity and performance has a significant impact on the reliability and durability of storage particles. The bit error rate in the NAND reading and writing process has increased significantly. In order to ensure the reliability of NAND reading and writing data, related technologies have introduced LDPC error correction technology in the data reading and writing channel, such as Figure 1 As shown, it includes a combination of hard decoding and soft decoding, that is, hard decoding is performed first during decoding, and soft decoding is performed when hard decoding fails. However, with the increase in NAND read and write error rates, the error correction capability requirements for LDPC codewords are also constantly increasing, which makes it easy to exceed the decoding capability limit of hard decoding and increase the probability of entering the soft decoding process. The method of implementing soft decoding requires multiple rereading of NAND, and the delay corresponding to NAND rereading is large, which affects the data throughput rate in practical applications. Therefore, the present application proposes a data error correction method based on low-density parity-check code, which first detects some error positions in the codeword data and performs bit flipping of the data, reduces the number of error bits entering the decoder, improves the decoding capability limit of hard decoding, and then reduces the probability of the system entering soft decoding.

[0025] According to an embodiment of the present invention, an embodiment of a data error correction method based on a low-density parity-check code is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0026] In this embodiment, a data error correction method based on low-density parity-check code is provided, which can be used in computer equipment. Figure 2 is a flow chart of a data error correction method based on a low-density parity-check code according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0027] In step S201 , data to be corrected is read from a data memory, and a pre-check process is performed on the data to be corrected and a check matrix of a preset low-density parity-check code to obtain a pre-check result.

[0028] The data to be corrected includes code words generated by low-density parity check coding.

[0029] The data storage device of the embodiment of the present invention may be a NAND Flash. As an example, data to be corrected is read from the data storage device. LDPC encoding encodes the read original data using a specific algorithm to generate a codeword consisting of information bits and check bits, which is denoted as c. The data to be corrected may be pre-checked with a preset LDPC check matrix to obtain a pre-check result. The check matrix defines a check relationship between coding bits, and each row in the matrix corresponds to a check equation. The data to be corrected is multiplied by the check matrix to perform row check processing to obtain a row check result, i.e., chk_rslt = H·c. T , where chk_rslt represents the vector of row check values, and H represents the check matrix. If the row check value chk_rslt corresponding to a row in the pre-check result is 1, it means that the current row check fails.

[0030] In one approach, considering that the amount of data stored in NAND Flash is generally large, in order to improve the efficiency of pre-verification, parallel processing technology can be used. The data to be corrected can be divided into multiple sub-blocks, and pre-verification processing can be performed simultaneously with the corresponding sub-check matrices, thereby significantly shortening the pre-verification time. For example, by utilizing the parallel computing capabilities of multi-threading or a controller (Graphics Processing Unit, GPU), the check matrix and the data to be corrected can be divided according to certain rules. Each thread or GPU core is responsible for processing the check calculation of a portion of the data to obtain the row check result corresponding to each portion. Finally, the row check results of each portion can be merged to obtain a complete row check result. The preset LDPC check matrix can also be dynamically adjusted according to different application scenarios and data characteristics. For example, for data areas stored in NAND Flash that are frequently updated or accessed, a stricter check matrix can be used, and the number of check bits can be increased to improve error correction capability. For some less important or rarely accessed data, the complexity of the check matrix can be reduced to reduce the consumption of computing resources. This is just an example.

[0031] Step S202: Determine a first error position set in the codeword position set based on the pre-check result.

[0032] In an embodiment of the present invention, if the row check value corresponding to a row in the check matrix is determined to be 1, it indicates that there may be an error in the codeword position corresponding to the non-zero element in the row. For example, if the check fails in the c-th row in the check matrix H, and the element in the t-th column of the c-th row is 1, it may indicate that the t-th position of the codeword may be erroneous. As an example only, all possible erroneous positions in the codeword position set can then be obtained to form a first error position set. The number of check failure rows involved in each bit position can also be calculated, and a threshold is set. The bit positions whose number of check failure rows exceeds the threshold are regarded as possible erroneous positions. As an example only.

[0033] In an optional manner, after completing the first round of pre-check processing to obtain the first error position set, a targeted second round of pre-check can be performed on the error positions in the first error position set, such as adjusting the combination or parameters of the check matrix and recalculating the row check values related to these positions. Other algorithms can also be used for two rounds of pre-check, such as using a linear block error correction code (Bose-Chaudhuri-Hocquenghem, BCH) for two rounds of check. The BCH code has advantages in error correction and can further verify the accuracy of the positions in the first error position set, and can supplement and correct some errors that are not discovered by the LDPC pre-check. The combination of the two error correction codes can bring into play their respective advantages and improve the overall error correction capability. For example, if a certain position frequently fails to check in multiple rounds of pre-check, it means that the probability of its real error is higher. If it only appears in some rounds, it may also be accidental noise interference. It can be deleted from the first error position combination, thereby improving the accuracy of error positioning.

[0034] Step S203: Perform a bit flip operation on the codeword indicated by the first error position set to complete pre-error correction.

[0035] The embodiment of the present invention can perform bit flipping on the codewords indicated by all error positions in the first error position set, that is, changing from 0 to 1 and from 1 to 0, thereby completing pre-error correction of the codewords.

[0036] Step S204: input the pre-error-corrected codeword into a low-density parity check decoder for decoding, and output error-corrected data.

[0037] Embodiments of the present invention can use a mix of different LDPC decoding algorithms (such as the Belief Propagation (BP) algorithm, the Minimum Sum (Min-Sum) algorithm, and their improved versions). For example, in the early stages of decoding, a low-complexity algorithm or algorithm can be used for rapid iteration to reduce computational complexity. When nearing convergence, the algorithm can be switched to the more accurate BP algorithm to further improve decoding accuracy. By dynamically switching algorithms, decoding speed and error correction performance can be balanced. As an example, the pre-corrected codeword can be input into a low-density parity check (LDPC) decoder for decoding, and the corrected data can be output. Furthermore, key indicators of the decoding process, such as the verification pass rate or the trend of information bit changes during iterations, can be monitored in real time to establish a decoding failure warning mechanism. When certain indicators are detected to be outside the normal range (e.g., the verification pass rate has not significantly improved after multiple consecutive iterations), a warning is triggered. At this time, measures such as adjusting decoding algorithm parameters, re-performing pre-correction, or introducing other error-correcting codes to assist in decoding can be taken to avoid eventual decoding failure. For example,

[0038] Furthermore, the error-corrected data output by the LDPC decoder can be verified twice, and additional check codes (such as cyclic redundancy check (CRC)) or compared with a backup copy of the original data can be used. If an error is found during the verification, re-decoding is triggered or a redundant data recovery mechanism is started to ensure the accuracy of the output data. At the same time, the error-corrected data can be backed up regularly to prevent data loss due to subsequent system failures. Specifically, a performance monitoring system for the LDPC decoding system can be established to monitor indicators such as decoding time, bit error rate, and resource utilization in real time. Through data analysis and machine learning algorithms, the trend of system performance changes can be predicted. When performance degrades, the decoding algorithm parameters, computing resource allocation, or pre-error correction strategy can be automatically adjusted to achieve dynamic optimization of the system. This is just an example.

[0039] In an embodiment of the present invention, the codeword after pre-error correction processing can be input into the LDPC decoder for multiple rounds of iterative decoding, and the error-corrected data can be output. This method has no special requirements for the LDPC decoding algorithm and is applicable to various LDPC algorithms. It is also applicable to both soft decoding and hard decoding modes. When the hard decoding mode is applied, the data at the corresponding position can be bit-flipped to achieve pre-error correction. When the soft decoding mode is applied, the LLR value corresponding to the data at the corresponding position can be pre-adjusted. The above-mentioned pre-error correction processing can be performed before entering the LDPC decoding, or pre-error correction can be performed during the LDPC decoding process.

[0040] The data error correction method based on low-density parity-check code provided in this embodiment reads the data to be corrected from a data storage device, and pre-checks the data to be corrected with a check matrix of a preset low-density parity-check code to obtain a pre-check result; based on the pre-check result, determines a first error position set in a codeword position set; performs a bit flip operation on the codeword indicated by the first error position set to complete pre-error correction; inputs the codeword after the pre-error correction process into a low-density parity-check decoder for decoding, and outputs the error-corrected data. By pre-detecting the error position of the codeword and bit flipping the codeword at the error position, the number of error bits entering the LDPC decoder is reduced, thereby ensuring that the number of error bits does not exceed the decoding capability limit of hard decoding, reducing the probability of the system entering soft decoding, and ensuring the decoding throughput of the system.

[0041] In this embodiment, a data error correction method based on low-density parity-check code is provided, which can be used in computer equipment. Figure 3 is a flow chart of a data error correction method based on a low-density parity-check code according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0042] Step S301 , reading data to be corrected from a data memory, and performing pre-check processing on the data to be corrected and a check matrix of a preset low-density parity check code to obtain a pre-check result, wherein the data to be corrected includes a codeword generated by low-density parity check coding.

[0043] Specifically, the above step S301 includes:

[0044] Step S3011 , pre-checking the data to be corrected and a check matrix of a preset low-density parity-check code to obtain row check values corresponding to each row sequence in the check matrix.

[0045] The check matrix of the preset low-density parity check code in the embodiment of the present invention defines the check relationship between each bit in the codeword. Each row in the check matrix corresponds to a check equation, and each column corresponds to a bit position in the codeword. The LDPC codeword is multiplied by the check matrix of the preset low-density parity check code to obtain the following: Figure 4 As shown, the row check values corresponding to each row sequence in the check matrix constitute the column vector chk_rslt of the row check.

[0046] Step S3012: Calculate the number of row check failures corresponding to all non-zero bit entries in each column of the check matrix as a pre-check result.

[0047] After obtaining the column vector of the row check, the embodiment of the present invention can count the number of row check failures corresponding to all non-zero bit items in each column of the check matrix H to obtain the number of row check failures for each column, which can be defined as syndrome_fail_num. For example, Figure 4 As shown in the figure, the positions without numbers marked in the figure indicate that the corresponding position values are 0. Taking the first column as an example to count the number of row check failures, there are 5 non-zero bit items in the first column, and the positions are the 2nd, 5th, 7th, 8th and c rows respectively. Among them, the row check values of the 5th and 7th rows are 1, that is, the row check fails. Therefore, the number of row check failures corresponding to the first column can be counted as syndrome_fail_num=2. The number of row check failures of other columns is calculated in the same way as the first column, which will not be repeated here. Then, the number of row check failures corresponding to all non-zero bit items in each column can be used as the pre-check result.

[0048] In an optional approach, embodiments of the present invention may assign a weight to the number of row check failures corresponding to each column, where the weight may be determined based on factors such as the distribution density of non-zero bits in the check matrix and the check importance of the row. For example, if a row bears more check constraints in the entire check matrix, the number of failures corresponding to it will be assigned a higher weight. Ultimately, the weighted number of failures will be used as the pre-check result, allowing subsequent error correction to prioritize error locations that have a greater impact on the overall check. This is just an example.

[0049] The present invention pre-checks the data to be corrected with a check matrix of a preset low-density parity-check code to obtain row check values corresponding to each row sequence in the check matrix. The number of row check failures corresponding to all non-zero bit items in each column of the check matrix is calculated as the check result. The degree of correlation between each bit position and the check failure can be further quantified, greatly narrowing the scope of error location and helping to more accurately screen out codewords that may have errors in complex codewords.

[0050] Step S302: Determine a first error position set in the codeword position set based on the pre-check result.

[0051] Specifically, the above step S302 includes:

[0052] Step S3021: Determine a column index set whose number of row check failures is greater than a preset number threshold as a first error position set.

[0053] The embodiment of the present invention pre-sets a row check failure number threshold based on actual needs. For example, the number threshold can be set to 2. As an example only, after obtaining the number of row check failures corresponding to all non-zero bit items in each column, when it is determined that the number of row check failures in a certain column is greater than the preset number threshold, it indicates that the probability of the codeword data corresponding to the current column being erroneous is extremely high. The current column index position can be defined as the error position, and then the column index set with the number of row check failures greater than the preset number threshold is determined as the first error position set. Furthermore, the threshold of the number of row check failures can be dynamically adjusted according to historical data or real-time channel status. When the number of failures in a certain column exceeds the threshold, not only is the column marked as having a possible error, but the failure of its adjacent columns can also be further analyzed. If multiple adjacent columns have an abnormal number of failures, it can be determined as a local area error, triggering a more comprehensive error location and repair process to avoid single-point misjudgment. This is an example only.

[0054] The present invention determines the column index set with the number of row check failures greater than a preset threshold as the first error position set, and determines the priority of bit flipping according to the number of row check failures in each column, giving priority to flipping codewords associated with more row check failures, which can make the codewords meet the check relationship more quickly, accelerate decoding convergence, reduce the number of iterations, and improve the speed and success rate of error correction.

[0055] In a specific embodiment, Figure 5As shown, in an embodiment of the present invention, the data to be corrected is first pre-checked with a preset LDPC check matrix to obtain a row check value chk_rslt corresponding to each row in the check matrix, the number of row check failures (also referred to as the syndrome check failure number) corresponding to all non-zero bit items in each column of the check matrix is calculated, and is defined as syndrome_fail_num. The number of row check failures is counted to obtain a set of column indexes corresponding to different row check failure values, the number of row check failures corresponding to each column is compared with a preset number threshold, and a set of column indexes whose number of row check failures is greater than the preset number threshold is filtered out and determined as a first error position set; the LDPC codeword data position corresponding to the column index in the first error set is defined as the error position, and error position detection is completed; the corresponding LDPC codeword bits in the first error position set are flipped, that is, the original codeword data is flipped to 1 when it is 0, and the original codeword data is flipped to 0 when it is 1, to complete pre-error correction, and the LDPC codeword after pre-error correction is input into the LDPC decoder for multiple rounds of iterative decoding operations, and the error-corrected data is output. For detailed description, please refer to the above embodiment and will not be repeated here.

[0056] Step S303: Perform a bit flip operation on the codeword indicated by the first error position set to complete pre-error correction. Figure 2 Step S203 of the illustrated embodiment will not be described in detail here.

[0057] Step S304: Input the pre-corrected codeword into a low-density parity check decoder for decoding, and output the corrected data. Figure 2 Step S204 of the illustrated embodiment will not be described in detail here.

[0058] In this embodiment, a data error correction method based on low-density parity-check code is provided, which can be used in computer equipment. Figure 6 is a flow chart of a data error correction method based on a low-density parity-check code according to an embodiment of the present invention. Figure 6 As shown, the process includes the following steps:

[0059] Step S601: Read the data to be corrected from the data memory and perform a pre-check process on the data to be corrected with a check matrix of a preset low-density parity check code to obtain a pre-check result. The data to be corrected includes a codeword generated by the low-density parity check code. Figure 3 Step S301 of the illustrated embodiment will not be described in detail here.

[0060] Step S602: Based on the pre-check result, determine the first error position set in the codeword position set. Figure 3 Step S302 of the illustrated embodiment will not be described in detail here.

[0061] Step S603: Perform a bit flip operation on the codeword indicated by the first error position set to complete pre-error correction. Figure 3 Step S303 of the illustrated embodiment will not be described in detail here.

[0062] Step S604: input the pre-error-corrected codeword into a low-density parity check decoder for decoding, and output error-corrected data.

[0063] Specifically, the above step S604 includes:

[0064] Step S6041 , during the first round of iterative decoding of the codeword after the pre-error correction processing by the LDPC decoder, the flipping condition of each decoded data is detected to obtain the oscillation number of the decoded data corresponding to each column.

[0065] Step S6042 : Determine a second error position set based on the number of oscillations of the decoded data corresponding to each column and the number of row check failures.

[0066] Step S6043: Perform a bit flip operation on the decoded data indicated by the second error position set to obtain updated decoded data.

[0067] Step S6044: input the updated decoded data into a low-density parity check decoder for iterative decoding.

[0068] In the embodiment of the present invention, the codeword after the pre-error correction processing is input into the LDPC decoder for the first round of iterative decoding. During the process of the LDPC decoder performing the first round of iterative decoding on the codeword after the pre-error correction processing, the flip situation of each decoded data can be counted, such as Figure 7 As shown, taking the first column as an example, during the first round of decoding iterations, the decoding data corresponding to the first column is monitored to have flipped twice, so the number of oscillations can be recorded as 2, and the decoding data corresponding to the second column is not flipped during the first round of decoding iterations, so the number of oscillations can be recorded as 0. The statistics of the number of oscillations of other columns are similar, and will not be repeated here. After the first round of decoding is completed, the following can be obtained: Figure 7 The set of oscillation times shown.

[0069] Furthermore, cluster analysis can be performed on the set of oscillation times to identify different oscillation patterns. For example, if the oscillation times of certain columns show periodic variations, this may indicate the presence of a specific interference source or local characteristics of the parity check matrix. Using a clustering algorithm (such as the K-means algorithm), columns with similar oscillation times can be grouped together. Different processing strategies can be adopted for different categories, and the distribution characteristics of the oscillation times, such as the mean and variance, can be analyzed. A large variance indicates significant differences in oscillation between different columns, suggesting that some columns may be subject to more severe interference or errors, necessitating special attention to the decoding results of these columns. Historical decoding data can also be combined to study the correlation between the oscillation times and the final decoding errors. Regression models or decision tree models can be established to predict the probability of decoding errors when the oscillation times reach a certain threshold. For example, when the oscillation times of a column exceed a certain threshold, the probability of decoding errors in that column increases significantly. In this case, additional verification or re-decoding can be performed on that column.

[0070] The embodiment of the present invention can determine the second error position set in combination with the number of oscillations and the number of row check failures of the decoding data corresponding to each column, wherein the method for determining the second error position set is not limited, and it can be to pre-set an oscillation number threshold and a row check failure number threshold, filter out a column index set whose oscillation number is greater than the oscillation number threshold from the codeword position set, and at the same time filter out a column index set whose row check failure number is greater than the preset number threshold from the codeword position set, and perform statistics on the two filtered column index sets, such as selecting the union of the two sets as the second error position set. For example, in an optional implementation, not only can the error position set be determined by the number of oscillations and the number of row check failures, but the confidence information of each bit can also be included in the error. Considerations for position judgment include, for example, calculating the confidence of each codeword bit through the corresponding channel model. When the number of oscillations and the number of row check failures in a certain column meet the conditions and the confidence of the corresponding bit is low, it can be judged as an error position. The status of other columns related to the current column in the check matrix can also be considered. By analyzing the number of oscillations of neighboring columns, the number of row check failures and other information, it is possible to more accurately judge whether the current column index is an error position. The error detection process can also be divided into multiple stages, and different stages use different screening criteria and thresholds. In the first stage, a set of possible error columns is preliminarily screened out based on a relatively loose threshold. In subsequent stages, the set is further screened and refined based on more information (such as bit confidence, etc.) to obtain a more accurate second set of error positions. This is just an example.

[0071] The embodiment of the present invention can perform a bit flip operation on the decoded data indicated by the second error position set to obtain updated decoded data, and input the updated decoded data into the LDPC decoder for subsequent iterative decoding to obtain error-corrected data.

[0072] The present invention detects the number of oscillations of the decoded data and the number of row check failures during the iterative decoding process to screen out the decoded data at the error position. It can more comprehensively consider the different characteristics of the decoded data, thereby locating the error position more accurately and performing bit flipping in advance to improve the efficiency of subsequent decoding.

[0073] Furthermore, based on the number of oscillations and the number of row check failures of the decoding data corresponding to each column, a second error position set is determined, including: determining the column index set with a number of row check failures greater than a preset number threshold as the first error position set; determining the column index set with a number of oscillations greater than a preset number threshold as the third error position set; and performing a set merging operation on the first error position set and the third error position set to obtain a second error position set.

[0074] In the embodiment of the present invention, the column index set whose number of row check failures is greater than a preset number threshold is determined as the first error position set, for example, Figure 7 As shown, the quantity threshold is taken as 1 as an example, the first error position set is {1, 3, 4, 6}, and the oscillation number threshold is taken as 1 as an example. The column index set with the oscillation number greater than 1 is determined as the third error position set. For example, the third error position set is {2, 4, 5, 6}. The first error position set and the third error position set can be merged to obtain the second error position set, that is, the two sets are merged to obtain the second error position set of {4, 6}.

[0075] In an optional manner, different weights may be assigned to the first error location set and the third error location set, and the two sets may be merged based on the weights. For example, if the number of row check failures is considered to more accurately reflect the error location, a higher weight may be assigned to the first error location set; during the merge, for elements that appear in both sets at the same time, a comprehensive judgment is made based on the weights to determine whether to include them in the second error location set. Alternatively, a hierarchical merging strategy may be adopted, where the two sets are initially merged to obtain a temporary set, and then the elements in the temporary set are further screened and verified to remove those that may be misjudged elements, ultimately obtaining a more accurate second error location set. This is just an example.

[0076] The present invention combines the first error position set and the second error position set to obtain the second error position set, thereby combining two types of information reflecting the possibility of errors from different angles, comprehensively capturing the positions where errors exist, and improving the accuracy of error positioning.

[0077] Furthermore, a bit flipping operation is performed on the decoded data indicated by the second error position set, including: comparing the decoded data indicated by the second error set with the codeword at the corresponding position in the data to be corrected; if the decoded data indicated by the current error position is the same as the codeword at the current error position in the data to be corrected, bit flipping is performed on the decoded data at the current error position.

[0078] In an embodiment of the present invention, before bit-flipping the decoded data at the error position, the decoded data indicated by the second error position set needs to be compared with the codeword at the corresponding position in the data to be corrected. If the decoded data indicated by the current error position is the same as the codeword at the current error position in the data to be corrected, it means that the decoded data indicated by the current error position has not changed after decoding. At this time, the decoded data at its position can be bit-flipped according to the error position detection result to obtain updated decoded data, wherein the decoded data indicated by the current error position is different from the codeword at the current error position in the data to be corrected, indicating that it has changed after decoding, and no bit flipping is required. Finally, the updated decoded data can be obtained, and the updated decoded data is then input into the LDPC decoder for subsequent iterative decoding to output the error-corrected data.

[0079] Before performing bit flipping on the decoded data at the error position, the present invention needs to compare the decoded data indicated by the second error position set with the codeword at the corresponding position in the data to be corrected. Only when it is determined that the error position has not changed after decoding is flipped, thereby reducing the occurrence of erroneous error correction and reducing the impact of erroneous operations on the stability of the entire decoding system.

[0080] In a specific embodiment, Figure 8As shown, the error-corrected data is pre-checked to obtain the number of row check failures corresponding to all non-zero bit items in each column of the check matrix, and the column index set with the number of row check failures greater than a preset number threshold is screened out to form a first error position set. The codeword indicated by the first error position set is subjected to a bit flip operation to complete the pre-error correction. The codeword after the pre-error correction is input into a low-density parity check decoder for decoding. In the first round of iterative decoding, the flipping situation of each decoded data can be counted to obtain the number of oscillations of the decoded data corresponding to each column, and the position set with the number of oscillations greater than the preset number threshold is screened out to form a third error position set. and performing a set merging operation on the third error position set and the first error position set to obtain a merged second error position set, and comparing the decoded data indicated by the current error position in the second error position set with the codeword indicated by the current error position in the data to be corrected; if the decoded data indicated by the current error position is the same as the codeword indicated by the current error position in the data to be corrected, bit flipping is performed on the codeword data of the current error position; after the flipping is completed, updated decoded data is obtained, and the updated decoded data is input into the LDPC decoder for decoding processing, and finally the error-corrected data is output. For detailed description, please refer to the above embodiment and will not be repeated here.

[0081] In an optional embodiment, the codeword after pre-error correction processing is input into a low-density parity check decoder for decoding, and the error-corrected data is output. It also includes: in the subsequent rounds of iterative decoding of the codeword after pre-error correction processing by the low-density parity check decoder, repeatedly executing the step of detecting the flipping condition of each decoded data until the iteration is completed, and outputting the error-corrected data.

[0082] In an embodiment of the present invention, the pre-error correction processing method based on the number of decoding oscillations and the number of row check failures can be applied only after the first round of iterative decoding, and the pre-error correction processing may not be performed in subsequent rounds of iterative decoding. Alternatively, the pre-error correction processing method based on the number of decoding oscillations and the number of row check failures can be performed after each round of iterative decoding, thereby improving the error correction capability of hard decoding and reducing the probability of the system entering soft decoding.

[0083] In an optional embodiment, in addition to whether the current number of iterations reaches the preset number of iterations, the method for determining whether to terminate the iteration early can also be based on some intermediate results in the decoding process. For example, when the estimated value of the information bit no longer changes significantly after multiple consecutive iterations, or all rows of the check matrix meet the check conditions, it can be considered that the decoding has converged and the iteration can be terminated early, thereby saving computing time. Additional parameters can also be set, such as the maximum allowable error probability. When the error probability of the decoding result is lower than the threshold, the iteration can also be terminated early. This is just an example.

[0084] The present invention performs pre-error correction of code words after each iterative decoding. As the number of iterations increases, more errors can be corrected, thereby enhancing the error correction capability of the entire decoding system.

[0085] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0086] In this embodiment, a data error correction device based on a low-density parity-check code is also provided. The device is used to implement the above-mentioned embodiments and preferred embodiments, and the details already described are not repeated here. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and contemplated.

[0087] This embodiment provides a data error correction device based on low-density parity-check code, such as Figure 9 As shown, it includes: a data verification module 901, which is used to read the data to be corrected from the data storage device, and pre-check the data to be corrected with the check matrix of the preset low-density parity check code to obtain a pre-check result, and the data to be corrected includes a codeword generated by the low-density parity check encoding; an error position determination module 902, which is used to determine the first error position set in the codeword position set based on the pre-check result; a pre-error correction module 903, which is used to perform a bit flip operation on the codeword indicated by the first error position set to complete pre-error correction; a data error correction module 904, which is used to input the codeword after the pre-error correction processing into the low-density parity check decoder for decoding, and output the corrected data.

[0088] In some optional embodiments, the data verification module 901 includes: a row check value calculation unit, which is used to perform pre-verification processing on the data to be corrected and the check matrix of a preset low-density parity-check code to obtain the row check value corresponding to each row sequence in the check matrix; a failure number statistics unit, which is used to calculate the number of row check failures corresponding to all non-zero bit items in each column of the check matrix as a pre-verification result.

[0089] In some optional implementations, the error location determination module 902 includes: an index set statistics unit, configured to determine a column index set having a number of row check failures greater than a preset number threshold as a first error location set.

[0090] In some optional embodiments, the data error correction module 904 includes: an oscillation number statistics unit, which is used to detect the flipping of each decoded data during the first round of iterative decoding of the codeword after pre-error correction by the low-density parity check decoder, and obtain the oscillation number of the decoded data corresponding to each column; a position determination unit, which is used to determine the second error position set based on the oscillation number of the decoded data corresponding to each column and the number of row check failures; a data update unit, which is used to perform a bit flip operation on the decoded data indicated by the second error position set to obtain updated decoded data; and a data decoding unit, which is used to input the updated decoded data into the low-density parity check decoder for iterative decoding.

[0091] In some optional embodiments, the data update unit includes: a codeword comparison subunit, used to compare the decoded data indicated by the second error set with the codeword at the corresponding position in the data to be corrected; and a bit flipping unit, used to perform bit flipping on the decoded data at the current error position if the decoded data indicated by the current error position is the same as the codeword at the current error position in the data to be corrected.

[0092] In some optional embodiments, the position determination unit includes: a first position set determination subunit, used to determine a column index set whose number of row check failures is greater than a preset number threshold as a first error position set; a third position set determination subunit, used to determine a column index set whose number of oscillations is greater than a preset number threshold as a third error position set; and a set merging operation subunit, used to perform a set merging operation on the first error position set and the third error position set to obtain a second error position set.

[0093] In some optional embodiments, the data error correction module 904 includes: an iterative decoding unit, which is used to repeatedly execute the step of detecting the flipping condition of each decoded data during the subsequent rounds of iterative decoding of the codeword after pre-error correction by the low-density parity check decoder, until the iteration is completed, and output the corrected data.

[0094] The description of the features in the embodiment corresponding to a data error correction device based on low-density parity-check code can refer to the relevant description of the embodiment corresponding to the above-mentioned data error correction method based on low-density parity-check code, and will not be repeated here.

[0095] The embodiment of the present application also provides an electronic device, such as Figure 10 As shown, it includes a memory 10 and a processor 20, wherein the memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any of the above-mentioned embodiments of the data error correction method based on the low-density parity-check code.

[0096] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned embodiments of the data error correction method based on low-density parity-check code when running.

[0097] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0098] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned data error correction method embodiments based on low-density parity-check codes are implemented.

[0099] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps in any of the above-mentioned embodiments of the data error correction method based on low-density parity-check code.

[0100] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0101] The above describes in detail a data error correction method, apparatus, computer device, and storage medium based on low-density parity-check codes provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A data error correction method based on low-density parity-check code, characterized in that: include: Reading data to be corrected from a data memory, and performing a pre-check process on the data to be corrected and a check matrix of a preset low-density parity check code to obtain a pre-check result, wherein the data to be corrected includes a codeword generated by the low-density parity check encoding; Determining a first error position set in the codeword position set based on the pre-check result; Performing a bit flip operation on the codeword indicated by the first error position set to complete pre-error correction; The codeword after the pre-error correction processing is input into the low-density parity check decoder for decoding, and the error-corrected data is output.

2. The data error correction method based on low-density parity-check code according to claim 1, characterized in that: The pre-checking the data to be corrected and a check matrix of a preset low-density parity-check code to obtain a pre-check result includes: Performing a pre-check process on the to-be-corrected error data and a check matrix of a preset low-density parity-check code to obtain a row check value corresponding to each row sequence in the check matrix; The number of row check failures corresponding to all non-zero bit entries in each column of the check matrix is calculated as the pre-check result.

3. The method according to claim 2, characterized in that The determining, based on the pre-check result, a first error position set in the codeword position set includes: A column index set whose number of row check failures is greater than a preset number threshold is determined as a first error position set.

4. The method according to claim 2, characterized in that The step of inputting the codeword after the pre-error correction process into a low-density parity check decoder for decoding comprises: During the first round of iterative decoding of the codeword after the pre-error correction processing by the low-density parity check decoder, detecting the flipping of each decoded data to obtain the number of oscillations of the decoded data corresponding to each column; Determine a second error position set based on the number of oscillations and the number of row check failures of the decoded data corresponding to each column; performing a bit flip operation on the decoded data indicated by the second error position set to obtain updated decoded data; The updated decoded data is input into a low-density parity check decoder for iterative decoding.

5. The method according to claim 4, characterized in that The performing a bit flip operation on the decoded data indicated by the second error position set includes: comparing the decoded data indicated by the second error set with the codeword at the corresponding position in the data to be corrected; If the decoded data indicated by the current error position is the same as the codeword of the current error position in the data to be corrected, bit flipping is performed on the decoded data of the current error position.

6. The method according to claim 4, characterized in that The determining a second error position set by combining the number of oscillations of the decoded data corresponding to each column and the number of row check failures includes: Determine a column index set whose number of row check failures is greater than a preset number threshold as a first error position set; Determine a column index set whose oscillation times are greater than a preset number threshold as a third error position set; A set merging operation is performed on the first error position set and the third error position set to obtain a second error position set.

7. The method according to claim 4, characterized in that The step of inputting the pre-error-corrected codeword into a low-density parity check decoder for decoding and outputting the error-corrected data further comprises: During the subsequent rounds of iterative decoding of the pre-error-corrected codeword by the low-density parity check decoder, the step of detecting the flipping condition of each decoded data is repeatedly performed until the iteration is completed and the error-corrected data is output.

8. A data error correction device based on low-density parity-check code, characterized in that: include: a data verification module, configured to read data to be corrected from a data storage device and perform a pre-verification process on the data to be corrected with a check matrix of a preset low-density parity-check code to obtain a pre-verification result, wherein the data to be corrected includes a codeword generated by the low-density parity-check code; an error position determination module, configured to determine a first error position set in the codeword position set based on the pre-check result; a pre-error correction module, configured to perform a bit flip operation on the codeword indicated by the first error position set to complete pre-error correction; The data error correction module is used to input the codeword after pre-error correction processing into the low-density parity check decoder for decoding, and output the error-corrected data.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data error correction method based on low-density parity-check code according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the data error correction method based on low-density parity-check code are implemented as claimed in any one of claims 1 to 7.

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