Test system, serial port data receiving and sending method and related device

Abstract

The invention discloses a test system, a serial port data receiving and sending method and a related device. The test system comprises an upper computer and an FPGA, wherein the FPGA comprises a clock generation module, a serial port receiving processing module and a serial port sending processing module; the upper computer is used for sending configuration parameters matched with the to-be-tested equipment to the FPGA; the clock generation module is used for sending a first clock signal to the serial port receiving processing module and sending a second clock signal to the serial port sending processing module based on a target baud rate; the serial port receiving and processing module is used for sampling first serial port data from the to-be-tested equipment based on the first clock signal and stopping sampling when the bit width of a target data bit is reached; and the serial port sending processing module is used for sending second serial port data to the to-be-tested equipment based on the second clock signal and stopping sending when the target data bit width is reached. Therefore, the flexibility of configuration parameter adjustment is greatly improved.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a testing system, a method for receiving and sending serial port data, and related devices. Background Art

[0002] Users of ammunition devices usually conduct performance tests on ammunition devices through testing equipment, and evaluate whether the ammunition devices meet the usage requirements by analyzing the test results obtained from the performance tests, and then make decisions such as returning the ammunition devices to the factory for maintenance or scrapping them.

[0003] When testing an ammunition device, the test equipment needs to send serial data to the device and receive serial data from the device. However, the serial communication configuration parameters of the test equipment and the device must match in order for the data to be sent and received between them.

[0004] However, the configuration parameters in the current test equipment are set during initialization. There may be a need to adjust the configuration parameters based on changes in the ammunition device in the future. At this time, the program is usually modified to obtain the new configuration parameters, and then downloaded to the test equipment. The flexibility of adjusting the configuration parameters is insufficient. Summary of the Invention

[0005] In view of this, embodiments of the present application provide a test system, a serial port data receiving and sending method, and related devices, the purpose of which is to improve the flexibility of configuration parameter adjustment.

[0006] In a first aspect, an embodiment of the present application provides a test system, the test system being connected to a device to be tested, the test system comprising a host computer and a field programmable gate array (FPGA), the FPGA comprising a clock generation module, a serial port receiving processing module, and a serial port sending processing module;

[0007] The host computer is used to configure configuration parameters that match the device to be tested and send the configuration parameters to the FPGA; the configuration parameters include a target data bit width of the serial port data and a target baud rate of the serial port data;

[0008] The clock generating module is configured to send a first clock signal to the serial port receiving processing module based on the target baud rate, and send a second clock signal to the serial port sending processing module based on the target baud rate;

[0009] The serial port receiving processing module is configured to sample the first serial port data from the device under test based on the first clock signal, and stop sampling when the data bit width of the sampled first serial port data reaches the target data bit width;

[0010] The serial port sending processing module is configured to send second serial port data to the device under test based on the second clock signal, and stop sending when the data bit width of the sent second serial port data reaches the target data bit width.

[0011] Optionally, the first serial port data includes a plurality of data bits; the serial port receiving processing module includes a first counter;

[0012] The first counter is configured to count based on the first clock signal, and trigger the serial port receiving processing module to sample the next data bit in the first serial port data from the device under test when the count reaches a first value.

[0013] Optionally, the second serial port data includes multiple data bits; the serial port sending processing module includes a second counter;

[0014] The second counter is configured to count based on the second clock signal, and trigger the serial port sending processing module to send the next data bit in the second serial port data when the count reaches a second value.

[0015] Optionally, the configuration parameters further include a target verification type;

[0016] The serial port receiving processing module is further configured to verify the sampled first serial port data according to the target verification type after stopping sampling and when determining that a verification bit signal of the first serial port data is received;

[0017] The serial port sending processing module is further configured to generate a check bit signal of the second serial port data according to the target check type after stopping sending, and send the check bit signal of the second serial port data to the device under test.

[0018] Optionally, the configuration parameters further include a target stop bit width;

[0019] The serial port receiving processing module is further configured to continue sampling the stop bit signal of the first serial port data after stopping sampling, and determine whether the stop bit signal of the first serial port data is valid based on the target stop bit width;

[0020] The serial port sending processing module is further configured to generate a stop bit signal of the second serial port data based on the target stop bit width after stopping sending, and continue to send the stop bit signal of the second serial port data to the device under test.

[0021] Optionally, the system further comprises a processor unit and an Advanced eXtensible Interface (AXI) bus;

[0022] The host computer is used to send the configuration parameters to the processor unit;

[0023] The processor unit is configured to receive the configuration parameters sent by the host computer and send the configuration parameters to the AXI bus;

[0024] The AXI bus is used to send the target baud rate in the configuration parameters to the clock generation module, and to send the target data bit width to both the serial port receiving processing module and the serial port sending processing module.

[0025] In a second aspect, an embodiment of the present application provides a method for receiving and sending serial port data, which is applied to a test system, wherein the test system is connected to a device to be tested, and the test system includes a host computer and a field programmable gate array (FPGA), wherein the FPGA includes a clock generation module, a serial port receiving processing module, and a serial port sending processing module; the method includes:

[0026] The host computer configures configuration parameters that match the device to be tested, and sends the configuration parameters to the FPGA; the configuration parameters include a target data bit width of the serial port data and a target baud rate of the serial port data;

[0027] Sending a first clock signal to the serial port receiving processing module based on the target baud rate through the clock generating module, and sending a second clock signal to the serial port sending processing module based on the target baud rate;

[0028] Sampling the first serial port data from the device under test based on the first clock signal by the serial port receiving processing module, and stopping sampling when the data bit width of the sampled first serial port data reaches the target data bit width;

[0029] The second serial port data is sent to the device under test based on the second clock signal through the serial port sending processing module, and the sending is stopped when the data bit width of the sent second serial port data reaches the target data bit width.

[0030] In a third aspect, an embodiment of the present application provides a serial port data receiving and transmitting device, the device including a memory and a processor:

[0031] The memory is used to store a computer program and transmit the computer program to the processor;

[0032] The processor is used to execute the computer program to enable the device to perform the serial port data receiving and sending method described in the second aspect.

[0033] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed, the device running the computer program implements the serial port data receiving and sending method described in the second aspect above.

[0034] In a fifth aspect, an embodiment of the present application provides a testing device, which includes the testing system described in the first aspect.

[0035] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0036] The present invention provides a test system, a serial port data receiving and sending method, and a related device. The test system is connected to a device under test, and includes a host computer and a field programmable gate array (FPGA). The FPGA includes a clock generation module, a serial port receiving processing module, and a serial port sending processing module. The host computer is configured to send configuration parameters matching the device under test to the FPGA. The configuration parameters include a target data bit width of the serial port data and a target baud rate of the serial port data. The clock generation module is configured to send a first clock signal to the serial port receiving processing module based on the target baud rate, and to send a second clock signal to the serial port sending processing module based on the target baud rate. The serial port receiving processing module is configured to sample first serial port data from the device under test based on the first clock signal, and stop sampling when the data bit width of the sampled first serial port data reaches the target data bit width. The serial port sending processing module is configured to send second serial port data to the device under test based on the second clock signal, and stop sending when the data bit width of the sent second serial port data reaches the target data bit width.

[0037] In this way, the host computer in the test equipment can configure the configuration parameters that match the device to be tested according to its requirements. Each module in the FPGA can receive and send serial port data according to the configuration parameters. The operation is simple and the flexibility of adjusting the configuration parameters is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in this embodiment or the prior art, the following briefly introduces the drawings required for use in the embodiment or the prior art description. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1An application scenario of a test system provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of the structure of a test system provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of the structure of a specific test system provided in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of generating a first clock signal provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of generating a start sampling pulse provided by an embodiment of the present application;

[0044] Figure 6 A schematic diagram of generating an intermediate sampling pulse provided by an embodiment of the present application;

[0045] Figure 7 A schematic diagram of generating a second clock signal provided in an embodiment of the present application;

[0046] Figure 8 A schematic diagram of generating a rising edge pulse and a falling edge pulse provided in an embodiment of the present application;

[0047] Figure 9 A schematic diagram of a serial port receiving processing module receiving first serial port data provided by an embodiment of the present application;

[0048] Figure 10 A schematic diagram of a serial port sending processing module sending second serial port data provided by an embodiment of the present application;

[0049] Figure 11 A flowchart of a method for receiving and sending serial port data provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0051] Currently, the configuration parameters in the test equipment are set during initialization. There may be a need to adjust the configuration parameters based on changes in the ammunition device in the future. In this case, the program is usually modified to obtain the new configuration parameters, which are then downloaded to the test equipment. The flexibility of adjusting the configuration parameters is insufficient.

[0052] Based on this, in order to solve the above problems, the embodiment of the present application provides a test system, a serial port data receiving and sending method and related devices. The test system is connected to the device to be tested, and the test system includes a host computer and a field programmable gate array (FPGA). The FPGA includes a clock generation module, a serial port receiving processing module and a serial port sending processing module. The host computer is used to send configuration parameters matching the device to be tested to the FPGA. The configuration parameters include a target data bit width of the serial port data and a target baud rate of the serial port data. The clock generation module is used to send a first clock signal to the serial port receiving processing module based on the target baud rate, and to send a second clock signal to the serial port sending processing module based on the target baud rate. The serial port receiving processing module is used to sample the first serial port data from the device to be tested based on the first clock signal, and stop sampling when the data bit width of the sampled first serial port data reaches the target data bit width. The serial port sending processing module is used to send second serial port data to the device to be tested based on the second clock signal, and stop sending when the data bit width of the sent second serial port data reaches the target data bit width.

[0053] In this way, the host computer in the test equipment can configure the configuration parameters that match the device to be tested according to its requirements. Each module in the FPGA can receive and send serial port data according to the configuration parameters. The operation is simple and the flexibility of adjusting the configuration parameters is greatly improved.

[0054] For example, the embodiments of the present application can be applied to Figure 1 In the scenario shown, the scenario includes a test device 101 and a device to be tested 102, wherein the device to be tested 102 may be an ammunition device, etc. The test device 101 may include a test system provided in an embodiment of the present application, and the test system is used to test the device to be tested 102.

[0055] The above scenario is only an example scenario provided by an embodiment of the present application. The embodiment of the present application is not limited to this scenario, and other devices to be tested can also be tested.

[0056] The specific implementation of the test system, serial port data receiving and sending method and related devices in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0057] See also Figure 2 , which is a structural diagram of a test system provided in an embodiment of the present application, combined with Figure 2 As shown, the test system may specifically include a host computer and a field programmable gate array FPGA, wherein the FPGA includes a clock generation module, a serial port receiving processing module, and a serial port sending processing module;

[0058] The test system is connected to the device to be tested. Figure 1 As shown in the introduction.

[0059] The host computer is used to configure configuration parameters that match the device to be tested and send the configuration parameters to the FPGA.

[0060] The user can configure the host computer according to the requirements of the device under test. In response to the user's configuration operations, the host computer generates configuration parameters that match the device under test. The device under test uses these configuration parameters to send serial port data, and the test system must also use these configuration parameters to receive serial port data from the device under test. Similarly, the device under test uses these configuration parameters to receive serial port data, and the test system must also use these configuration parameters to send serial port data to the device under test. The host computer can then send the configuration parameters to the FPGA, so that the FPGA can receive data from the first serial port and send data from the second serial port based on these configuration parameters.

[0061] The configuration parameters include a target data bit width of the serial port data and a target baud rate of the serial port data.

[0062] The serial data may include multiple serial data frames. The data bit width refers to the length of valid data bits in each serial data frame. For example, the target data bit width may be 5 bits, 6 bits, etc. This application does not limit this and can be set according to the requirements of the device under test.

[0063] Baud rate refers to the transmission speed when transmitting serial data, which means the number of bits transmitted per second. For example, at a baud rate of 9600, it takes about 1.04 milliseconds to transmit a 10-bit serial data.

[0064] The clock generating module is configured to send a first clock signal to the serial port receiving processing module based on the target baud rate, and send a second clock signal to the serial port sending processing module based on the target baud rate.

[0065] The clock generation module can generate a first clock signal. The sending of the first clock signal can be determined based on the target baud rate, so as to facilitate the subsequent determination of the data bit width of the first serial port data currently received.

[0066] The clock generation module can generate a second clock signal. The sending of the second clock signal can also be determined based on the target baud rate, so as to facilitate the subsequent determination of the data bit width of the second serial port data that has been sent.

[0067] The serial port receiving processing module is configured to sample the first serial port data from the device under test based on the first clock signal, and stop sampling when the data bit width of the sampled first serial port data reaches the target data bit width.

[0068] Based on the correlation between the transmitted first clock signal and the target baud rate, the first serial port data continuously transmitted by the device under test can be sampled. For example, the first clock signal can be used to determine which data bits of the first serial port data are to be sampled. Furthermore, the sampling stop time can be determined based on the target data bit width.

[0069] In some embodiments, the target data bit width may be the length of data bits indicating valid information in a serial data frame. Accordingly, sampling may be stopped after determining that a serial data frame has been received, so as to facilitate corresponding processing of the serial data frame.

[0070] The serial port sending processing module is configured to send second serial port data to the device under test based on the second clock signal, and stop sending when the data bit width of the sent second serial port data reaches the target data bit width.

[0071] Based on the correlation between the transmitted second clock signal and the target baud rate, the second serial port data can be sent to the device under test. For example, the second clock signal can be used to determine which data bits of the second serial port data to send. Furthermore, the transmission stop time can be determined based on the configuration of the target data bit width.

[0072] In some embodiments, the target data bit width may be the length of data bits indicating valid information in a serial data frame. Accordingly, after determining to send a serial data frame, the sending may be stopped to facilitate the device under test to process the serial data frame accordingly.

[0073] In a possible implementation, the test system may further include a processor unit and an Advanced eXtensible Interface (AXI) bus.

[0074] For example, the processor unit may be a processing system (PS) in an FPGA.

[0075] The host computer is used to send the configuration parameters to the processor unit.

[0076] In some embodiments, the host computer may send configuration parameters to the PS via a high-speed Peripheral Component Interconnect Express (PCIE) bus.

[0077] The processor unit is configured to receive the configuration parameters sent by the host computer and send the configuration parameters to the AXI bus.

[0078] The AXI bus is used to send the target baud rate in the configuration parameters to the clock generation module, and to send the target data bit width to both the serial port receiving processing module and the serial port sending processing module.

[0079] The AXI bus can send the target baud rate in the configuration parameters to the clock generation module, so that it can send the first clock signal and the second clock signal; the AXI bus can send the target data bit width in the configuration parameters to the serial port receiving processing module and the serial port sending processing module, so that the serial port receiving processing module can determine when to stop sampling and the serial port sending processing module can determine when to stop sending.

[0080] Next, combine Figure 3 A specific test system is introduced. Figure 3 A schematic diagram of the structure of a specific test system provided in an embodiment of the present application. The test system includes a host computer and an FPGA. Programmable Logic (PL). The PS communicates with the host computer via the PCIE bus, converts data into the AXI bus, and interacts with the logic code of the PL. The PL includes a register control module, a receive first-in first-out (FIFO) module, a transmit FIFO module, a clock generation module, a serial port receive processing module, and a serial port transmit processing module. The serial port receive processing module has a receive end (Receive, referred to as RX), and the serial port transmit processing module has a transmit end (Transmit, referred to as TX).

[0081] The host computer sends configuration parameters to the PS via the PCIE bus. The PS sends the target data bit width, target stop bit width, and target parity type for the serial port data to the register control module via the AXI bus. The register control module then sends these configuration parameters to the serial port receive processing module and the serial port transmit processing module. The PS also sends the target baud rate to the clock generation module via the AXI bus.

[0082] The clock generation module generates a first clock signal (also known as the serial port receive clock, or simply the receive clock) and a second clock signal (also known as the serial port transmit clock, or simply the transmit clock) according to the target baud rate configured for the AXI bus. The serial port receive processing module is responsible for converting the received first serial port data into parallel data (also known as a parallel signal). The first serial port data is sent to the RX by the device under test. The serial port receive processing module writes the parallel signal into the receive FIFO module. The PS sends a read command to the register control module via the AXI bus. The register control module responds to the read command by reading the parallel data from the receive FIFO module. The parallel data is then read by the AXI bus and sent to the PS, so that the PS forwards the parallel data corresponding to the first serial port data to the host computer via the PCIE bus. On the contrary, the host computer sends the parallel data corresponding to the second serial port data to be sent to the PS through the PCIE bus, and the PS sends a read command and parallel data to the register control module through the AXI bus. The register control module writes the parallel data into the transmit FIFO module in response to the read command. The serial port transmit processing module detects that the transmit FIFO module is not empty, that is, it reads the parallel data and converts the parallel data into the second serial port data, and then sends the second serial port data to the device to be tested through TX.

[0083] For example, the first serial port data may be data used to determine whether the device under test and the test system can communicate and interact. Accordingly, the corresponding second serial port data may be response data for the communication interaction. For another example, the first serial port data may be data used to obtain the self-test status of the device under test. Accordingly, the corresponding second serial port data may be the self-test status.

[0084] It should be noted that Figure 3 The device under test is not shown.

[0085] In a possible implementation, the first serial port data includes multiple data bits, and the serial port receiving processing module includes a first counter.

[0086] In some embodiments, based on the above description, the first serial port data may include multiple serial port data frames, each of which includes multiple data bits. For example, the multiple data bits may include a start bit, valid data bits (corresponding to a target data bit width), a stop bit, a check bit, etc. This application does not limit this. The stop bit and the check bit are described in the following embodiments and are not expanded here.

[0087] The first counter is configured to count based on the first clock signal, and trigger the serial port receiving processing module to sample the next data bit in the first serial port data from the device under test when the count reaches a first value.

[0088] In some embodiments, the first value can be set based on a target baud rate. For example, the clock frequency of the first and second clock signals generated by the clock generation module can be a preset multiple of the target baud rate. Generating the preset multiple of the first clock signal can indicate that a data bit has been received, and generating the preset multiple of the second clock signal can indicate that a data bit has been sent. The first value can be the same as the preset multiple.

[0089] For example, the first value may be 64 or 16, and this application does not limit this. When the count of the first counter reaches 64, the next data bit may be sampled. For example, when the count reaches 64 for the first time, the first data bit may be sampled; when the count reaches 64 for the second time, the second data bit may be sampled, and so on.

[0090] As an example, see Figure 4 , which is a schematic diagram of generating a first clock signal provided by an embodiment of the present application. Figure 4 As shown, the clock generation module can be used to generate a first clock signal, which is an oversampling clock required for receiving first serial port data. Its clock frequency can be 64 times the target baud rate. The clock crystal oscillator can be preset to 14.7456MHz. After passing through a phase-locked loop (PLL), it can be multiplied to 117.9648MHz (i.e., the clock frequency for generating the first clock signal). Each rising edge of the first clock signal activates a reset signal (which can be sent from the host computer).

[0091] When the reset signal is asserted, the first counter is initialized. When the reset signal is deasserted, the first counter begins counting based on the first clock signal. If the count value does not reach the first value, the first counter continues counting. When the count value reaches the first value, the generated first clock signal is negated, the first counter is cleared, and the counter continues counting based on the first clock signal. As the first counter repeatedly reaches the first value and then clears, the generated first clock signal continuously fluctuates between 0 and 1. The crystal oscillator clock frequency of 14.7456 MHz is merely an example; other values are possible to meet different target baud rate requirements. The 117.9648 MHz generated by the PLL can be divided by a maximum of 2 to 58.9824 MHz. Therefore, when the input clock crystal oscillator is 14.7456 MHz, 58.9824 divided by the first value, 64, yields a target baud rate of 0.9216 MHz. For other target baud rates, different allocation coefficients can be used. As long as 117.9648 MHz is divisible by 64, the corresponding target baud rate can be obtained.

[0092] When the serial port receiving processing module receives the first serial port data, the first serial port data is sampled using a 64-fold frequency clock, that is, the data is sampled once when the first counter reaches a first value.

[0093] Next, combine Figure 5 and Figure 6 Two sampling methods are introduced.

[0094] See also Figure 5 , this figure is a schematic diagram of generating a start sampling pulse provided by an embodiment of the present application. The serial port receiving processing module includes a wait state and a non-wait state. When it is in the wait state, the first counter is assigned a value of 0; when it is in the non-wait state, the initial value of the first counter is 0, and it can count based on the first clock signal. When the count reaches the first value, the start sampling pulse is set to 1, and the serial port receiving processing module can perform sampling (not shown in the figure); and the first counter is cleared and counted again. When the count reaches the first value, the start sampling pulse is set to 1, and the serial port receiving processing module can perform sampling again (not shown in the figure), and so on. The first counter starts counting with an initial value of 0, so that the generated start sampling pulse is always at the starting position of the data bit in the first serial port data.

[0095] See also Figure 6 , which is a schematic diagram of generating an intermediate sampling pulse provided by an embodiment of the present application.

[0096] The serial port receiving processing module includes a wait state and a non-wait state. When in the wait state, a first counter is assigned a value equal to the middle value of the first value. When in the non-wait state, the first counter is initialized to the middle value of the first value (e.g., if the first value is 64, the initial value is 32). Counting can be performed based on a first clock signal. When the count reaches the first value, an intermediate sampling pulse is set to 1, and the serial port receiving processing module can perform sampling (not shown in the figure). The first counter is then reset and counted again. When the count reaches the first value, an intermediate sampling pulse is set to 1, and the serial port receiving processing module can perform sampling again (not shown in the figure). This cycle repeats. The first counter starts counting with the middle value of the first value, so that the generated intermediate sampling pulse is always located at the middle position of the data bit in the first serial port data.

[0097] In a possible implementation, the second serial port data includes multiple data bits, and the serial port receiving processing module includes a second counter.

[0098] The second counter is configured to count based on the second clock signal, and trigger the serial port sending processing module to send the next data bit in the second serial port data when the count reaches a second value.

[0099] It should be noted that the introduction of the second serial port data can refer to the first serial port data, and the introduction of the second value can refer to the first value, which will not be repeated here.

[0100] As an example, see Figure 7 , which is a schematic diagram of generating a second clock signal provided by an embodiment of the present application. Figure 7 As shown, the clock generation module can be used to generate a second clock signal, which is the clock required for sending the second serial port data. Its clock frequency can be the target baud rate. The clock crystal oscillator can be preset to 50MHz. After passing through the PLL, it can be multiplied to 200MHz (that is, the clock frequency of the second clock signal). Each rising edge of the second clock signal activates the reset signal (which can be sent from the host computer).

[0101] When the reset signal is valid, and when the reset signal is invalid, the second counter counts based on the second clock signal, and the subsequent process when the count reaches the second value can be referred to the first counter counting based on the first clock signal and the subsequent process when the count reaches the first value introduced above, which will not be repeated here.

[0102] The 50MHz crystal oscillator clock is only an example and can be set to other values to meet different target baud rate requirements. If the target baud rate is 0.9216MHz, 200MHz needs to be divided by 217. After division, the serial port transmit baud rate is 0.921658MHz, with an error of 0.006%, which meets the accuracy requirement.

[0103] When the serial port sending processing module receives the first serial port data and the second counter reaches the second value, the data is sent once.

[0104] See also Figure 8 This figure is a schematic diagram of a method for generating rising and falling edge pulses provided by an embodiment of the present application. The serial port transmission processing module can generate the rising and falling edges of the transmission clock signal, using 200MHz as the master clock. When the reset signal is valid, the rising edge pulse is set to 0, and the falling edge pulse is set to 0. When the reset signal is valid, a 4ns pulse can be generated as a rising edge pulse to trigger the output of valid data bits. When the reset signal is valid, a 4ns pulse can be generated as a falling edge pulse to trigger the output of the stop bit.

[0105] In a possible implementation manner of the present application, the configuration parameter further includes a target verification type.

[0106] The target check type refers to the check type of the check method used when checking the serial port data. For example, the target check type can be even check, odd check, and mark check, etc. This application does not limit this.

[0107] The serial port receiving processing module is further configured to verify the sampled first serial port data according to the target verification type after stopping sampling and when determining that the verification bit signal of the first serial port data is received.

[0108] In some embodiments, after sampling of valid data bits in a serial port data frame is completed, sampling may be stopped, and when it is determined that a check bit signal is received, the valid data bits in the serial port data frame may be checked according to a target check type.

[0109] The serial port sending processing module is further configured to generate a check bit signal of the second serial port data according to the target check type after stopping sending, and send the check bit signal of the second serial port data to the device under test.

[0110] In some embodiments, after sending the valid data bits in a serial port data frame, the sending can be stopped, and a check bit signal in the serial port data frame can be generated according to the target check type and sent to the device under test so that the device under test can check the received serial port data frame.

[0111] In a possible implementation manner of the present application, the configuration parameter further includes a target stop bit width.

[0112] The stop bit is used to mark the end of a serial data frame and helps correctly identify the start bit of the next serial data frame. The stop bit can have different bit widths, such as 1 bit, 1.5 bits, 2 bits, etc.

[0113] The serial port receiving processing module is further configured to continue sampling the stop bit signal of the first serial port data after stopping sampling, and determine whether the stop bit signal of the first serial port data is valid based on the target stop bit width.

[0114] In some embodiments, after sampling the stop bit signal, it can be determined whether the stop bit signal of the first serial port data is valid based on the target stop bit width. If it is valid, it means that the serial port data frame is received successfully. Otherwise, there may be a problem with the reception, or the reception may be incomplete.

[0115] The serial port sending processing module is further configured to generate a stop bit signal of the second serial port data based on the target stop bit width after stopping sending, and continue to send the stop bit signal of the second serial port data to the device under test.

[0116] In some embodiments, a corresponding stop bit signal of the second serial port data may be generated based on the target stop bit width, so that the device under test can determine that reception of the serial port data frame is complete.

[0117] Next, combine Figure 9 and Figure 10 The process of receiving data from the first serial port and sending data from the second serial port are described in detail.

[0118] See also Figure 9 This figure is a schematic diagram of a serial port receiving processing module receiving first serial port data, provided in an embodiment of the present application. The serial port receiving processing module can perform different processing based on different configuration parameters. In this example, the 117.9648 MHz generated by the PLL in the clock generation module can be used as the master clock.

[0119] When the reset signal is valid, the registers inside the serial port receiving processing module are initialized, such as the check register and the data buffer register (Drx). When the reset signal is invalid, the serial port receiving processing module enters the wait state. When the serial port input is 0, that is, when there is a serial port start bit, that is, when the start bit of the first serial port data is received, the serial port receiving processing module enters the start state. When the serial port input is 0, it enters the wait state.

[0120] After entering the start state, the byte valid signal is set to 0, and then the d0 state is entered. The byte valid signal indicates that a complete and valid byte data (i.e., a serial port data frame) has been received. After entering the d0 state, while waiting for the intermediate sampling pulse to be valid, the serial port receive signal is assigned to the 0th bit of the buffer Drx, namely D[0] (that is, the first valid data bit collected is assigned to the 0th bit of the buffer Drx), and the current serial port receive data (also known as the valid data bit currently sampled) is XORed with the check register. Then, the d1 state is entered. While waiting for the intermediate sampling pulse to be valid, the serial port receive signal is assigned to the 1st bit of the buffer Drx, namely D[1] (that is, the next valid data bit collected is assigned to the 1st bit of the buffer Drx), and the current serial port receive data is XORed with the check register. Then, the d2 state is entered. While waiting for the intermediate sampling pulse to be valid, the serial port receive signal is assigned to the 2nd bit of the buffer Drx, namely D[2], and the current serial port receive data is XORed with the check register. Then enter the d3 state, wait for the middle sampling pulse to be valid, assign the serial port receiving signal to the third bit of the buffer Drx, that is, D[3], and perform an XOR operation on the current serial port receiving data and the check register. Then enter the d4 state.

[0121] After entering the d4 state, when the intermediate sampling pulse is valid, the serial port receive signal is assigned to the 4th bit of the buffer Drx, namely D[4], and the current serial port receive data is XORed with the check register. Then, the bit width (i.e., the target data bit width, which is 5 bits in this case) and the check parameter (i.e., the target check type) of the register control module input are determined. If the bit width is 5 bits and there is no check (i.e., there is no check bit signal), the 1-bit stop state is entered (i.e., the target stop bit width is 1 bit), and the upper 3 bits of the buffer Drx are set to zero (at this time, the buffer Drx has a total of 8 bits, the lower 5 bits D[0]-D[4] have been assigned, and the remaining upper 3 bits are padded, and the 8 bits are only for example). If the bit width is 5 bits and there is check (i.e., there is a check bit signal), the d8 state is entered, and the upper 3 bits of the buffer Drx are set to zero. If the bit width is not 5 bits (i.e., the target data bit width is not 5 bits), the XOR operation is performed and the d5 state is directly entered.

[0122] After entering the d5 state, when the intermediate sampling pulse is valid, the serial port receive signal is assigned to the 5th bit of the buffer Drx, i.e. D[5], and the current serial port receive data is XORed with the check register. Then, the bit width (6 bits in this case) and check parameters of the register control module input are determined. If the bit width is 6 bits and there is no check, the 1-bit stop state is entered, and the upper 2 bits of the buffer Drx are set to zero; if the bit width is 6 bits and there is a check, the d8 state is entered, and the upper 2 bits of the buffer Drx are set to zero; if the bit width is not 6 bits (that is, the target data bit width is not 6 bits), the XOR operation is performed and the d6 state is directly entered.

[0123] After entering the d6 state, when the intermediate sampling pulse is valid, the serial port receive signal is assigned to the 6th bit of the buffer Drx, i.e. D[6], and the current serial port receive data is XORed with the check register. Then, the bit width (7 bits at this time) and check parameters of the register control module input are determined. If the bit width is 7 bits and there is no check, the 1-bit stop state is entered, and the high 1 bit of the buffer Drx is set to zero; if the bit width is 7 bits and there is a check, the d8 state is entered, and the high 1 bit of the buffer Drx is set to zero; if the bit width is not 7 bits (that is, the target data bit width is not 7 bits), the d7 state is directly entered after the XOR operation.

[0124] After entering the D7 state, the system waits for the intermediate sampling pulse to be valid. The serial port receive signal is assigned to the 7th bit of the buffer Drx, D[7], and the current serial port receive data is XORed with the check register. The register control module then determines the input check parameter. If no check is performed, the system enters the 1-bit stop state; if a check is performed, the system enters the D8 state.

[0125] After entering the d8 state, the received check bit (also known as the check bit signal) is compared with the check register according to the check type (also known as the target check type) input by the register control module. If they are equal, the 1-bit stop state is entered; if they are not equal, the wait state is entered. When the check type is even check, the check register and the check bit are XORed to 0, then the check succeeds, otherwise the check fails; when the check type is odd check, the check register and the check bit are XORed to 1, then the check succeeds, otherwise the check fails; when the check type is Mark check, the check bit is 1, then the check succeeds, otherwise the check fails; when the check type is safe space check, the check bit is 0, then the check succeeds, otherwise the check fails;

[0126] After entering the 1-bit stop state, while waiting for the intermediate sampling pulse to be valid, the process is performed according to the stop bit type (i.e., the target stop bit width) input by the register control module. When the stop bit width (i.e., the target stop bit width) is 1 bit, the value of the serial port receive stop bit (i.e., the received stop bit signal) is determined. If the stop bit is 1, the byte valid signal is 1 (indicating that all valid data bits in a serial port data frame have been received and the serial port data frame is valid). If the stop bit is 0, the byte valid signal is 0 (indicating that the serial port data frame is invalid). This method indicates whether the received serial port data frame is valid, and then enters the wait state, that is, waiting for the next serial port data frame. The above description of entering the 1-bit stop state is only an example. The following describes examples with target stop bit widths of 1.5 bits and 2 bits.

[0127] Process the stop bit type input by the register control module. When the stop bit width is 1.5 bits, it enters the 1.5-bit stop state. Or, when the stop bit width is 2 bits, it enters the 2-bit stop state.

[0128] After entering the 1.5-bit stop state, while waiting for the middle sampling pulse to be valid, the serial port receives the stop bit value, and if the stop bit is 1, the byte valid signal is 1; if the stop bit is 0, the byte valid signal is 0. Alternatively, after entering the 2-bit stop state, while waiting for the middle sampling pulse to be valid, the serial port receives the stop bit value, and if the stop bit is 1, the byte valid signal is 1; if the stop bit is 0, the byte valid signal is 0.

[0129] See also Figure 10 This figure is a schematic diagram of a serial port transmission processing module sending second serial port data provided by an embodiment of the present application. The serial port transmission processing module can perform different processing based on different configuration parameters. In this example, the 200MHz generated by the PLL in the clock generation module can be used as the main clock.

[0130] When the reset signal is valid, the registers inside the serial port sending processing module are initialized; when the reset signal is invalid, the serial port sending processing module enters the wait state. When the send enable is 0 (for example, the host computer enables it), no state transition is performed; when the send enable is 1 and the send FIFO module is not empty, it enters the start state.

[0131] After entering the start state, the register control module issues a read command to the transmit FIFO module and assigns the read data from the transmit FIFO module to the buffer Dtx. While waiting for the rising edge pulse of the serial port transmit clock (also known as the rising edge pulse) to be valid, the buffer Dtx bit 0, namely D[0], is assigned to the serial port transmit interface (also known as the transmit interface of the serial port transmit processing module), and the current serial port transmit data (also known as the valid data bit currently being transmitted) is XORed with the check register. Then, entering the d0 state, waiting for the rising edge pulse of the serial port transmit clock to be valid, the buffer Dtx bit 1, namely D[1], is assigned to the serial port transmit interface, and the current serial port transmit data is XORed with the check register. Then, entering the d1 state, waiting for the rising edge pulse of the serial port transmit clock to be valid, the buffer Dtx bit 2, namely D[2], is assigned to the serial port transmit interface, and the current serial port transmit data is XORed with the check register. Then, the system enters state d2 and waits for the rising edge pulse of the serial port transmit clock to be valid. The third bit of cached Dtx, i.e., D[3], is assigned to the serial port transmit interface and the current serial port transmit data is XORed with the check register. Then, the system enters state d3 and waits for the rising edge pulse of the serial port transmit clock to be valid. The fourth bit of cached Dtx, i.e., D[4], is assigned to the serial port transmit interface and the current serial port transmit data is XORed with the check register. The register control module then determines the input bit width and check parameters. If the bit width is 5 bits and there is no check, the system enters the 1-bit stop state; if the bit width is 5 bits and there is check, the system enters state d8; if the bit width is not 5 bits, the system enters state d4.

[0132] After entering the D4 state, the rising edge pulse of the serial port transmit clock is valid. The 5th bit of the cached Dtx, i.e., D[5], is assigned to the serial port transmit interface, and the current serial port transmit data is XORed with the check register. The bit width and check parameters of the register control module input are then determined. If the bit width is 6 bits and there is no check, the 1-bit stop state is entered; if the bit width is 6 bits and there is check, the D8 state is entered; if the bit width is not 6 bits, the D5 state is entered.

[0133] After entering the D5 state, when the rising edge pulse of the serial port transmit clock is valid, the 6th bit of the cached Dtx, i.e. D[6], is assigned to the serial port transmit interface, and the current serial port transmit data is XORed with the check register. The bit width and check parameters of the register control module input are then determined. If the bit width is 7 bits and there is no check, the 1-bit stop state is entered; if the bit width is 7 bits and there is check, the D8 state is entered; if the bit width is not 7 bits, the D6 state is entered.

[0134] After entering the D6 state, the rising edge pulse of the serial port transmit clock is valid. The 7th bit of the buffered Dtx, i.e., D[7], is assigned to the serial port transmit interface. The current serial port transmit data is XORed with the check register. The check parameter input by the register control module is then determined. If no check is present, the 1-bit stop state is entered; if a check is present, the d8 state is entered.

[0135] After entering the d8 state, the check bit is assigned to the serial port sending interface according to the check type input by the register control module. When the check type is even, if the check register is 1, the check bit (that is, the check bit signal to be sent) is 1; if the check register is 0, the check bit is 0; when the check type is odd, if the check register is 1, the check bit is 0; if the check register is 0, the check bit is 1; when the check type is mark check, the check bit should be 1; when the check type is space check, the check bit should be 0.

[0136] After entering the 1-bit stop state, the serial port transmit interface is set to 1, indicating that the stop bit is valid. The device waits for the rising edge of the serial port transmit clock pulse to be valid. The device then processes the stop bit type input by the register control module. If the stop bit width is 1 bit, the device enters the wait state. The device then processes the stop bit type input by the register control module. If the stop bit width is 1.5 bits, the device enters the 1.5-bit stop state. The device then processes the stop bit type input by the register control module. If the stop bit width is 2 bits, the device enters the 2-bit stop state. After entering the 1.5-bit stop state, the device waits for the falling edge of the serial port transmit clock pulse to be valid, and then enters the wait state. After entering the 2-bit stop state, the device waits for the rising edge of the serial port transmit clock pulse to be valid, and then enters the wait state.

[0137] Next, we will continue to introduce a method for receiving and sending serial port data provided by an embodiment of the present application. The method is applied to a test system. The test system is connected to a device to be tested. The test system includes a host computer and a field programmable gate array (FPGA). The FPGA includes a clock generation module, a serial port receiving processing module, and a serial port sending processing module. Figure 11 , which is a flow chart of a method for receiving and sending serial data provided by an embodiment of the present application, combined with Figure 11 As shown, the method may specifically include:

[0138] S1101: configuring configuration parameters matching the device to be tested through the host computer, and sending the configuration parameters to the FPGA.

[0139] The configuration parameters include a target data bit width of the serial port data and a target baud rate of the serial port data.

[0140] S1102: Sending a first clock signal to the serial port receiving processing module based on the target baud rate through the clock generating module, and sending a second clock signal to the serial port sending processing module based on the target baud rate.

[0141] S1103: Sampling the first serial port data from the device under test based on the first clock signal by the serial port receiving processing module, and stopping sampling when the data bit width of the sampled first serial port data reaches the target data bit width.

[0142] S1104: Send second serial port data to the device under test based on the second clock signal through the serial port sending processing module, and stop sending when the data bit width of the sent second serial port data reaches the target data bit width.

[0143] It should be noted that the specific implementation of S1101-S1104 can refer to the specific implementation of the test system introduced above, and will not be repeated here.

[0144] An embodiment of the present application also provides a testing device, which includes the testing system described in any embodiment of the present application.

[0145] The embodiments of the present application also provide corresponding serial port data receiving and sending devices and computer-readable storage media for implementing the solutions provided in the embodiments of the present application.

[0146] The serial port data receiving and sending device includes a memory and a processor, the memory is used to store a computer program, and the processor is used to execute the computer program so that the device executes the serial port data receiving and sending method described in any embodiment of the present application.

[0147] The computer-readable storage medium stores a computer program. When the computer program is executed, the device executing the computer program implements the serial port data receiving and sending method described in any embodiment of the present application.

[0148] The "first" and "second" in the names such as "first" and "second" (if any) mentioned in the embodiments of this application are only used as name identifiers and do not represent the first or second in order.

[0149] Through the description of the above embodiments, it can be known that those skilled in the art can clearly understand that all or part of the steps in the above embodiment methods can be implemented by means of software plus a general hardware platform. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a readable storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment or certain parts of the embodiments of the present application.

[0150] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the system embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment. The system embodiment described above is merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components indicated as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without making any creative efforts.

[0151] The above is merely one specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A testing system, characterized in that: The test system is connected to the device to be tested, and the test system includes a host computer and a field programmable gate array (FPGA). The FPGA includes a clock generation module, a serial port receiving processing module, and a serial port sending processing module. The host computer is used to configure configuration parameters that match the device to be tested and send the configuration parameters to the FPGA; the configuration parameters include a target data bit width of the serial port data and a target baud rate of the serial port data; The clock generating module is configured to send a first clock signal to the serial port receiving processing module based on the target baud rate, and send a second clock signal to the serial port sending processing module based on the target baud rate; The serial port receiving processing module is configured to sample the first serial port data from the device under test based on the first clock signal, and stop sampling when the data bit width of the sampled first serial port data reaches the target data bit width; The serial port sending processing module is configured to send second serial port data to the device under test based on the second clock signal, and stop sending when the data bit width of the sent second serial port data reaches the target data bit width.

2. The method according to claim 1, characterized in that The first serial port data includes a plurality of data bits; the serial port receiving processing module includes a first counter; The first counter is configured to count based on the first clock signal, and trigger the serial port receiving processing module to sample the next data bit in the first serial port data from the device under test when the count reaches a first value.

3. The method according to claim 1, characterized in that The second serial port data includes a plurality of data bits; the serial port sending processing module includes a second counter; The second counter is configured to count based on the second clock signal, and trigger the serial port sending processing module to send the next data bit in the second serial port data when the count reaches a second value.

4. The method according to claim 1, wherein The configuration parameters also include target verification type; The serial port receiving processing module is further configured to verify the sampled first serial port data according to the target verification type after stopping sampling and when determining that a verification bit signal of the first serial port data is received; The serial port sending processing module is further configured to generate a check bit signal of the second serial port data according to the target check type after stopping sending, and send the check bit signal of the second serial port data to the device under test.

5. The method according to any one of claims 1 to 4, characterized in that The configuration parameters also include a target stop bit width; The serial port receiving processing module is further configured to continue sampling the stop bit signal of the first serial port data after stopping sampling, and determine whether the stop bit signal of the first serial port data is valid based on the target stop bit width; The serial port sending processing module is further configured to generate a stop bit signal of the second serial port data based on the target stop bit width after stopping sending, and continue to send the stop bit signal of the second serial port data to the device under test.

6. The method according to claims 1-4, characterized in that The system further comprises a processor unit and an Advanced eXtensible Interface (AXI) bus; The host computer is used to send the configuration parameters to the processor unit; The processor unit is configured to receive the configuration parameters sent by the host computer and send the configuration parameters to the AXI bus; The AXI bus is used to send the target baud rate in the configuration parameters to the clock generation module, and to send the target data bit width to both the serial port receiving processing module and the serial port sending processing module.

7. A method for receiving and sending serial port data, characterized in that: The method is applied to a test system connected to a device to be tested, wherein the test system includes a host computer and a field programmable gate array (FPGA), wherein the FPGA includes a clock generation module, a serial port receiving processing module, and a serial port sending processing module; the method includes: The host computer configures configuration parameters that match the device to be tested, and sends the configuration parameters to the FPGA; the configuration parameters include a target data bit width of the serial port data and a target baud rate of the serial port data; Sending a first clock signal to the serial port receiving processing module based on the target baud rate through the clock generating module, and sending a second clock signal to the serial port sending processing module based on the target baud rate; Sampling the first serial port data from the device under test based on the first clock signal by the serial port receiving processing module, and stopping sampling when the data bit width of the sampled first serial port data reaches the target data bit width; The second serial port data is sent to the device under test based on the second clock signal through the serial port sending processing module, and the sending is stopped when the data bit width of the sent second serial port data reaches the target data bit width.

8. A serial port data receiving and sending device, characterized in that: The device includes a memory and a processor: The memory is used to store a computer program and transmit the computer program to the processor; The processor is configured to execute the computer program so as to enable the device to perform the steps of the serial port data receiving and sending method according to claim 7.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program. When the computer program is executed, the device executing the computer program implements the steps of the serial port data receiving and sending method according to claim 7.

10. A testing device, characterized in that: The testing device comprises the testing system according to any one of claims 1 to 6.

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