Solid-state disk performance optimization method, device, equipment, medium and program product

Abstract

The invention provides a solid-state disk performance optimization method which can be applied to the technical field of cloud computing. The solid-state disk performance optimization method comprises the following steps: inputting hardware data of a target solid-state disk into a preset model to obtain a predicted performance index; when it is determined that there is a difference between the predicted performance index and the expected performance index, generating a hardware adjustment scheme for the target solid-state disk, so as to adjust the hardware configuration of the target solid-state disk based on the hardware adjustment scheme; testing the adjusted target solid-state disk in a preset scene to obtain an error injection performance index for the preset scene; and based on the error injection performance index, adjusting a firmware program in the target solid-state disk to optimize the performance of the target solid-state disk in the preset scene. The invention further provides a solid-state disk performance optimization device and equipment, a storage medium and a program product.

Description

Technical Field

[0001] The present invention relates to the field of cloud computing, and in particular to a solid-state disk performance optimization method, device, equipment, medium and program product. Background Art

[0002] Currently, performance testing for SSDs primarily relies on software simulation technology. This involves loading specific test programs to simulate read and write operations in various real-world application scenarios, thereby evaluating the SSD's performance. Based on the test results, developers can optimize the SSD to improve its overall performance.

[0003] During the implementation of the present invention, we discovered at least the following issues with the related art: Due to the inherent characteristics and complex internal workings of solid-state drives, performance can fluctuate significantly under different testing scenarios. This fluctuation makes it difficult to develop optimized solutions for diverse scenarios during performance optimization, resulting in low optimization efficiency. Summary of the Invention

[0004] In view of the above problems, the present invention provides a method, apparatus, device, medium and program product for optimizing solid-state disk performance.

[0005] According to a first aspect of the present invention, a method for optimizing solid-state disk performance is provided, comprising: inputting hardware data of a target solid-state disk into a preset model to obtain a predicted performance indicator; upon determining that there is a difference between the predicted performance indicator and the expected performance indicator, generating a hardware adjustment plan for the target solid-state disk to adjust the hardware configuration of the target solid-state disk based on the hardware adjustment plan; testing the adjusted target solid-state disk in a preset scenario to obtain an injection error performance indicator for the preset scenario; and adjusting the firmware program in the target solid-state disk based on the injection error performance indicator to optimize the performance of the target solid-state disk in the preset scenario.

[0006] The second aspect of the present invention provides a solid-state disk performance optimization device, including: a performance prediction module, used to input the hardware data of the target solid-state disk into a preset model to obtain a predicted performance indicator; a solution generation module, used to generate a hardware adjustment solution for the above-mentioned target solid-state disk when it is determined that there is a difference between the above-mentioned predicted performance indicator and the expected performance indicator, so as to adjust the hardware configuration of the above-mentioned target solid-state disk based on the above-mentioned hardware adjustment solution; a scenario testing module, used to test the preset scenario on the adjusted target solid-state disk to obtain the injection error performance indicator for the above-mentioned preset scenario; a program adjustment module, used to adjust the firmware program in the above-mentioned target solid-state disk based on the above-mentioned injection error performance indicator to optimize the performance of the above-mentioned target solid-state disk in the above-mentioned preset scenario.

[0007] A third aspect of the present invention provides an electronic device, comprising: one or more processors; a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the above method.

[0008] The fourth aspect of the present invention further provides a computer-readable storage medium having a computer program or instructions stored thereon, which implements the steps of the above method when the computer program or instructions are executed by a processor.

[0009] The fifth aspect of the present invention further provides a computer program product, comprising a computer program or instructions, which implement the steps of the above method when executed by a processor.

[0010] According to an embodiment of the present invention, by inputting the hardware data of the target solid-state drive into a preset model, when there is a difference between the predicted performance indicators and the expected performance indicators, a hardware adjustment plan is generated to optimize the hardware configuration, thereby improving the accuracy of the hardware configuration adjustment. At the same time, the optimized solid-state drive is tested in a preset scenario, and the firmware program is adjusted according to the injection error performance indicators in the test to optimize the performance under the preset scenario, thereby improving the stability of the target solid-state drive under different preset scenarios. Through the collaborative mechanism of the preset model and scenario testing, the hardware configuration and firmware program are optimized in a coordinated manner, effectively improving the efficiency and reliability of the target solid-state drive performance optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0012] Figure 1 A diagram illustrating application scenarios of the solid-state disk performance optimization method, apparatus, device, medium, and program product according to an embodiment of the present invention is shown.

[0013] Figure 2 A flow chart of a solid state disk performance optimization method according to an embodiment of the present invention is shown.

[0014] Figure 3 A flowchart of an error injection test of a solid-state disk performance optimization method according to an embodiment of the present invention is shown.

[0015] Figure 4 A schematic diagram of a performance optimization module in a solid-state disk performance optimization method according to an embodiment of the present invention is shown.

[0016] Figure 5 A structural block diagram of a solid-state disk performance optimization device according to an embodiment of the present invention is shown.

[0017] Figure 6A block diagram of an electronic device suitable for implementing a solid-state disk performance optimization method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0019] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0020] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0021] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0022] In the technical solution of the present invention, the data involved (including but not limited to data used for analysis, stored data, displayed data, etc.) are all information and data authorized by the user or fully authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of the relevant data comply with relevant laws, regulations and standards, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0023] An embodiment of the present invention provides a solid-state drive performance optimization method, which inputs hardware data of a target solid-state drive into a preset model to obtain a predicted performance indicator; when it is determined that there is a difference between the predicted performance indicator and the expected performance indicator, generates a hardware adjustment plan for the target solid-state drive to adjust the hardware configuration of the target solid-state drive based on the hardware adjustment plan; tests the adjusted target solid-state drive in a preset scenario to obtain an injection error performance indicator for the preset scenario; and adjusts the firmware program in the target solid-state drive based on the injection error performance indicator to optimize the performance of the target solid-state drive in the preset scenario.

[0024] Figure 1 A diagram illustrating application scenarios of the solid-state disk performance optimization method, apparatus, device, medium, and program product according to an embodiment of the present invention is shown.

[0025] like Figure 1 As shown, the application scenario 100 according to this embodiment may include a first terminal device 101, a second terminal device 102, a third terminal device 103, and a server 105. A network 104 is used as a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links or optical fiber cables.

[0026] A user may use a first terminal device 101, a second terminal device 102, or a third terminal device 103 to interact with a server 105 via a network 104 to receive or send messages, etc. Various communication client applications may be installed on the first terminal device 101, the second terminal device 102, or the third terminal device 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social platform software, etc. (for example only).

[0027] The first terminal device 101 , the second terminal device 102 , and the third terminal device 103 may be various electronic devices having display screens and supporting web browsing, including but not limited to smart phones, tablet computers, laptop computers, desktop computers, and the like.

[0028] The server 105 may be a server that provides various services, such as a background management server (for example only) that supports websites browsed by users using the first terminal device 101, the second terminal device 102, and the third terminal device 103. The background management server may analyze and process received data such as user requests, and feed back processing results (e.g., web pages, information, or data obtained or generated based on user requests) to the terminal devices.

[0029] It should be noted that the solid-state disk performance optimization method provided in the embodiment of the present invention can generally be executed by the server 105. Accordingly, the solid-state disk performance optimization device provided in the embodiment of the present invention can generally be set in the server 105. The solid-state disk performance optimization method provided in the embodiment of the present invention can also be executed by a server or server cluster that is different from the server 105 and can communicate with the first terminal device 101, the second terminal device 102, the third terminal device 103 and / or the server 105. Accordingly, the solid-state disk performance optimization device provided in the embodiment of the present invention can also be set in a server or server cluster that is different from the server 105 and can communicate with the first terminal device 101, the second terminal device 102, the third terminal device 103 and / or the server 105.

[0030] It should be understood that Figure 1 The number of the first terminal device, the second terminal device, the third terminal device, the network and the server is only illustrative. According to implementation requirements, there can be any number of the first terminal device, the second terminal device, the third terminal device, the network and the server.

[0031] The following will be based on Figure 1 The scene described by Figures 2 to 4 A detailed description of the SSD performance optimization method is provided.

[0032] Figure 2 A flow chart of a solid state disk performance optimization method according to an embodiment of the present invention is shown.

[0033] like Figure 2 As shown, the solid state disk performance optimization method includes operations S210 to S240.

[0034] In operation S210 , hardware data of the target solid state disk is input into a preset model to obtain a predicted performance index.

[0035] In operation S220 , when it is determined that there is a difference between the predicted performance indicator and the expected performance indicator, a hardware adjustment plan for the target solid state disk is generated to adjust the hardware configuration of the target solid state disk based on the hardware adjustment plan.

[0036] In operation S230 , a preset scenario test is performed on the adjusted target solid state disk to obtain an injection error performance index for the preset scenario.

[0037] In operation S240 , the firmware program in the target solid-state drive is adjusted based on the injection error performance indicator to optimize the performance of the target solid-state drive in a preset scenario.

[0038] According to an embodiment of the present invention, the hardware data of the target SSD (such as flash memory chip type, main control chip model, cache capacity, interface protocol version, etc.) is input into a pre-trained preset model. The preset model can be constructed based on machine learning algorithms (such as neural networks and random forests). By training with historical hardware data and measured performance indicators, a mapping relationship between hardware data and performance indicators is established, thereby outputting predicted performance indicators such as read and write speed and latency.

[0039] When predicted performance indicators deviate from expected performance indicators (such as standard values defined in the product specification or user-defined performance thresholds), a hardware adjustment plan generation mechanism is activated. This mechanism combines a rule engine with optimization algorithms to analyze the hardware-related factors that cause the discrepancy (such as insufficient flash channel utilization or inappropriate caching strategies) and generate specific hardware adjustment plans. These may include adjusting the operating voltage of flash memory chips, upgrading the main control chip firmware, or replacing higher-performance cache chips. Based on the hardware adjustment plan, targeted adjustments are then made to the target SSD's hardware configuration.

[0040] The adjusted target SSD is tested with fault injection in pre-set scenarios. By injecting simulated errors (such as temperature errors and erase count errors), the SSD's performance data under abnormal conditions is collected. The resulting fault injection performance metrics include error recovery time, data integrity maintenance, and performance degradation under abnormal scenarios.

[0041] Based on the injection error performance indicators, the weak links of the SSD in the preset scenarios are analyzed and the firmware program is adjusted in a targeted manner. For example, if the test finds that the data verification delay increases significantly in a high-temperature environment, the heat dissipation compensation mechanism of the verification algorithm in the firmware can be optimized to dynamically adjust the verification frequency and priority. If the garbage collection efficiency drops sharply due to an incorrect number of erases, the policy parameters in the firmware are reconfigured to start the wear leveling operation in advance and balance the erase and write load of each flash memory block, thereby improving the overall performance of the SSD in complex scenarios such as high temperature and high load. Through iterative optimization of the firmware program, the stability, reliability and performance of the target SSD in the preset scenarios are improved, and the coordinated optimization of hardware and firmware is achieved.

[0042] According to an embodiment of the present invention, by inputting the hardware data of the target solid-state drive into a preset model, when there is a difference between the predicted performance indicators and the expected performance indicators, a hardware adjustment plan is generated to optimize the hardware configuration, thereby improving the accuracy of the hardware configuration adjustment. At the same time, the optimized solid-state drive is tested in a preset scenario, and the firmware program is adjusted according to the injection error performance indicators in the test to optimize the performance under the preset scenario, thereby improving the stability of the target solid-state drive under different preset scenarios. Through the collaborative mechanism of the preset model and scenario testing, the hardware configuration and firmware program are optimized in a coordinated manner, effectively improving the efficiency and reliability of the target solid-state drive performance optimization.

[0043] According to an embodiment of the present invention, the adjusted target solid-state disk is tested in a preset scenario to obtain an error injection performance indicator for the preset scenario, including: generating a test strategy corresponding to the preset scenario based on a preset error injection type, wherein the preset error injection type includes temperature error injection and erase count error injection, and the test strategy is determined by a combination of the temperature value of the temperature error injection and the number of erase counts of the erase count error injection; based on the generated test strategy, the target solid-state disk is tested in the preset scenario to obtain the error injection performance indicator.

[0044] When testing the target SSD in a pre-set scenario, it's necessary to design a combined test strategy for both temperature error injection and erase count error injection. For temperature error injection, select an appropriate temperature as the error injection point based on the target SSD's operating temperature range (e.g., 0°C-70°C). This is accomplished by using a constant temperature chamber or temperature and humidity testing equipment to place the target SSD in a set target temperature environment and ensure that the temperature remains stable at the preset value, thereby simulating abnormal temperature scenarios.

[0045] For erasure error injection, the target SSD's erase / write cycle lifespan needs to be considered (for example, flash memory chips are typically rated for 0-10,000 erase / write cycles). By setting a threshold and using a dedicated firmware testing tool or automated script, the target SSD is subjected to cyclic erase operations until the preset erase cycle limit is reached.

[0046] Combine the temperature value injected for the temperature error with the number of erase cycles injected for the erase count error to form a specific test strategy. For example, perform a 1000-erasure cycle test on the SSD at 20°C to cover different temperature and erase count combinations. During the test, use a performance monitoring tool to collect the target SSD's injection performance indicators in real time, including read and write speeds, data error rates, response delays, and other indicators. Also, record whether the target SSD experiences any faults such as disk drop, data corruption, or abnormal errors.

[0047] The target SSD was tested using this combined testing strategy. The performance data and fault information collected during the test were analyzed to generate error injection performance indicators. These indicators intuitively reflect the reliability and stability of the target SSD under pre-defined scenarios, providing data support for evaluating the target SSD's ability to withstand error injection.

[0048] According to an embodiment of the present invention, the preset scenario includes multiple test strategies; based on the generated test strategy, the preset scenario is tested on the target solid-state disk to obtain the injection error performance index, including: determining the strategy execution order of multiple test strategies according to the number of erasures in each test strategy, wherein the number of erasures in the test strategy corresponds to multiple temperature values; and executing each test strategy according to the strategy execution order.

[0049] When determining the execution order of multiple test strategies, the strategies can be sorted based on the number of erase cycles in the test strategies. First, all test strategies are arranged from low to high according to the number of erase cycles to form a preliminary execution sequence. As shown in Table 1, since each erase cycle in the injection error type corresponds to multiple temperature values, test strategies with the same number of erase cycles are further sorted by temperature value. For example, first perform the test in a low-temperature environment (such as 0°C) and then perform the test in a high-temperature environment (such as 70°C) to determine the final strategy execution order. Here, Y represents the injection error performance indicator at the corresponding erase cycle and temperature.

[0050] Table 1

[0051]

[0052] This sorting method ensures that the test pressure is gradually increased based on a lower number of erase cycles, and at the same time facilitates comparison of the impact of different temperature environments on SSD performance under conditions of similar erase cycles.

[0053] According to an embodiment of the present invention, executing each test strategy includes: while keeping the number of erase times of the current test strategy unchanged, gradually adjusting the operating environment temperature according to a preset temperature gradient to complete the test of the target solid-state disk for multiple temperature values under the current number of erase times; after completing the test of multiple temperature values, performing a grinding process on the target solid-state disk until the current number of erase times of the target solid-state disk reaches the number of erase times required by the next test strategy in the strategy execution order.

[0054] While maintaining the current test strategy's erase count, the target SSD's operating temperature must be gradually adjusted according to a preset temperature gradient (e.g., 10°C intervals) to complete testing at multiple temperatures with the same erase count. To do this, first place the target SSD in a constant temperature chamber, set the initial test temperature (e.g., 0°C), and maintain the temperature until the device temperature stabilizes. Then, initiate the performance test, perform read and write operations on the target SSD at this temperature, and collect error-injection performance metrics until all test metrics for that temperature point are recorded.

[0055] After the current temperature test is completed, gradually increase (or decrease) the constant temperature of the constant temperature chamber according to the preset gradient, for example, adjust it to 0℃, 10℃, 20℃, 30℃, 40℃, etc. After each temperature adjustment, wait until the device and the ambient temperature are fully balanced, and then repeat the above performance test process to ensure that the test scenarios of all temperature values are covered with the same number of erase times.

[0056] After completing all temperature tests corresponding to the current erase count, the target SSD needs to be scrubbed to raise its current erase count to the next test strategy requirement in the policy execution sequence. This scrubbing operation can be performed using a dedicated SSD erase tool or automated script to perform a cyclic erase operation on the entire drive or a specified area (e.g., using random data or all-0 / all-1 data patterns). The accumulated erase count can be monitored in real time through the firmware interface or test tools.

[0057] During the scratching process, the health of the target SSD must be continuously monitored to prevent hardware damage due to excessive erases. When the erase count counter reaches the preset threshold for the next test strategy (e.g., increasing from 1000 to 2000), the scratching operation is immediately stopped to ensure the SSD remains at the target erase count state, preparing for the next set of temperature and erase count combination tests to be executed according to the strategy sequence. This orderly execution method allows for a systematic evaluation of the target SSD's fault injection performance under different temperature and erase count combinations.

[0058] Figure 3 A flowchart of an error injection test of a solid-state disk performance optimization method according to an embodiment of the present invention is shown.

[0059] like Figure 3 As shown, the injection error test process includes operations S310 to S370.

[0060] In operation S310, input the error type. In operation S320, generate a test strategy. In operation S330, grind the disk. In operation S340, determine whether the test point planned by the test strategy has been reached. If so, execute operation S350. If not, return to operation S330. In operation S350, determine whether the maximum number of erasures has been reached. If so, end. If not, execute operation S360. In operation S360, inject other types of errors. In operation S370, perform performance testing. After operation S370 is completed, return to operation S330 until the maximum number of erasures is reached.

[0061] In the test system, first design an input interface or interface for error types (including erase counts and temperature), and generate corresponding preset scenarios based on the input through functions or modules to simulate hardware or firmware errors. Next, call the underlying hardware control and firmware configuration related code to build a test execution environment. Execute the test strategy in the test execution environment to use loops and conditional judgment statements to check whether the test point or maximum threshold has been reached. The test points correspond to the various erase counts in the test strategy. If the test point planned by the test strategy is not reached, the disk is ground to increase the erase count. When the test point is reached but the erase count threshold is not reached, call the error injection module to add a new error type, such as a temperature error, and then trigger the performance test script to collect and analyze the performance indicators of the target SSD after the error injection.

[0062] Through systematic and automated multi-type error injection testing of target SSDs, covering different test points according to preset logic, and using looping and threshold control, we ensure the integrity of the test scenarios while avoiding meaningless repetitive testing. This process provides authentic and reliable test data to support hardware optimization and firmware algorithm improvements, thereby improving product reliability and stability.

[0063] According to an embodiment of the present invention, the hardware data of the target solid-state disk is input into a preset model to obtain a predicted performance indicator, including: inputting the hardware data into multiple decision trees of the preset model respectively to obtain the prediction results output by each decision tree, the hardware data including at least one of the flash memory chip characteristic value, the controller characteristic value, the cache characteristic value and the interface transmission protocol; calculating the average value of multiple prediction results to obtain the predicted performance indicator.

[0064] When inputting hardware data into the multiple decision trees of a pre-set model (using the random forest algorithm), the data must first be preprocessed to ensure that the data format meets the model input requirements. If the hardware data contains heterogeneous features such as flash memory chip features (such as flash memory type, capacity, read / write speed), controller features (such as main controller model, number of cores, and frequency), cache features (such as cache size and type), and interface transmission protocols, these features must be converted into numerical feature vectors. For example, categorical features such as interface transmission protocols can be one-hot encoded, and continuous flash memory read / write speeds can be normalized.

[0065] After preprocessing is completed, the feature vectors are input in parallel into each decision tree of the preset model. Each decision tree recursively divides the input data based on its own node splitting rule (the feature information gain threshold determined in the training phase) and finally outputs the corresponding prediction results.

[0066] After obtaining the prediction results of all decision trees, the final prediction performance index is obtained by calculating the arithmetic mean of these prediction results. In specific implementation, the output values of all decision trees in the random forest can be traversed, the accumulated values are divided by the total number of decision trees N. The specific calculation method is shown in formula (1).

[0067]

[0068] Where fi(x) represents the prediction result of the i-th decision tree, N represents the number of decision trees, and N is an integer greater than 1.

[0069] If the prediction task involves multiple performance metrics (such as read / write latency and throughput), the above average calculation process must be performed separately for each metric. To improve computational efficiency, vectorized operations can be used to process the outputs of all decision trees in parallel, avoiding the use of explicit loops. The resulting predicted performance metrics can be used to evaluate hardware status, predict lifespan, or guide optimization strategies. For example, adjusting cache strategies based on predicted read / write latency or planning data migration plans based on predicted erase / write thresholds. By processing multiple decision trees in parallel and fusing the results, automated prediction of target SSD performance is achieved, improving prediction accuracy and hardware feature utilization.

[0070] According to an embodiment of the present invention, the preset model is trained through the following operations: inputting sample hardware data of multiple sample solid-state disks into multiple decision trees of the initial model to obtain initial performance indicators output by each decision tree; based on the evaluation indicators, evaluating each initial performance indicator to obtain an evaluation result; based on the evaluation results, determining a model optimization strategy for the initial model, wherein the model optimization strategy includes at least one of increasing the number of decision trees and limiting the depth of the decision trees; based on the model optimization strategy, optimizing the initial model to obtain a trained preset model.

[0071] When training a preset model, sample hardware data from multiple SSDs is first preprocessed. This involves using mean filling or interpolation to handle missing values, identifying and correcting outliers, one-hot encoding categorical features (such as interface transmission protocols), and normalizing continuous features (such as flash read / write speeds) to construct a multidimensional feature vector. The processed dataset is then split into a training set and a validation set in an 8:2 ratio, with 80% of the sample data used for model training and 20% used to verify the model's generalization capabilities.

[0072] During model training, the sample hardware data from the training set is fed into multiple decision trees of the initial random forest model in parallel. Each decision tree splits its nodes based on the information gain of the features and outputs the corresponding initial performance metric. The final prediction of the initial model is calculated by averaging the predictions of all decision trees. The accuracy of the predictions is measured using variance or coefficient of determination. A smaller variance indicates a lower deviation between the predicted value and the true value; a coefficient of determination closer to 1 indicates a better fit of the model to the data.

[0073] Develop a model optimization strategy based on the evaluation results. If the variance on the validation set is large, or the coefficient of determination is below the target threshold (for example, less than 0.9), initiate iterative optimization. First, increase the number of decision trees (for example, from 100 to 500) to improve the model's learning ability, and determine the optimal number of trees through cross-validation. If overfitting occurs (i.e., the training set error is much lower than the validation set error), limit the maximum depth of the decision tree (for example, setting the maximum depth to 10) or the minimum number of sample splits (for example, setting the minimum number of sample splits to 5) to reduce model complexity. After each round of optimization, refit the model on the training set and evaluate its performance on the validation set until the model accuracy reaches the preset standard of 90%.

[0074] The feature importance score matrix output by the random forest can quantify the impact of each hardware parameter on the target SSD performance. Ultimately, the optimized initial model is used as the default model for subsequent performance indicator prediction of hardware data.

[0075] According to an embodiment of the present invention, a hardware adjustment plan for a target solid-state disk is generated, including: obtaining a feature importance evaluation of each hardware parameter in the hardware data from a preset model; and generating a hardware adjustment plan for the hardware configuration in the target solid-state disk based on the ranking of multiple feature importance evaluations.

[0076] To obtain feature importance evaluations for hardware data parameters from a pre-set model, you can directly call the properties provided by the random forest model. This property returns an array with the same dimensions as the input features, where each element corresponds to the importance score of a hardware parameter. To facilitate analysis, these scores are associated with hardware parameter names (such as "flash type," "cache size," and "interface protocol") to form a key-value mapping. All hardware parameters are then sorted from high to low by score to generate a ranked importance list. A higher score indicates a greater impact on SSD performance.

[0077] Based on the ranking results of the feature importance evaluation, a hardware adjustment plan for the target SSD is developed. Parameters ranked highly in importance (such as interface protocol and flash memory type) are prioritized for optimization. For example, if the NVMe (NVM Express) protocol has a significantly higher importance score than the Advanced Host Controller Interface (AHCI) protocol, and the current target SSD uses the AHCI interface, the adjustment plan should recommend upgrading to the NVMe interface to improve read and write performance. For less important parameters (such as cache size), if their impact on performance is limited and the adjustment cost is high, the existing configuration can be maintained or optimized in subsequent versions. This data-driven hardware adjustment plan can accurately identify the key parameters that have the greatest impact on SSD performance, achieving efficient resource utilization and targeted performance improvements.

[0078] According to an embodiment of the present invention, a hardware adjustment plan for the hardware configuration in the target solid-state disk is generated based on the ranking of multiple feature importance evaluations, including: when it is determined that the ranking result indicates that the feature importance evaluation of the hardware configuration in the current target solid-state disk is greater than a preset value, a hardware adjustment plan for the hardware configuration in the target solid-state disk is generated based on a preset mapping replacement relationship.

[0079] If the feature importance score of the target SSD hardware configuration in the ranking results exceeds a preset value, a list of replaceable components corresponding to that hardware configuration is first extracted from a preset mapping replacement relationship library. This mapping library pre-stores performance improvement paths for different hardware parameters. If the importance score of a hardware configuration (such as an interface protocol) exceeds a preset threshold (e.g., 0.15), a high-priority replacement option for that module is retrieved from the mapping library, for example, replacing the AHCI interface with an NVMe interface.

[0080] Generate specific adjustment recommendations for each high-importance hardware configuration. For flash memory type parameters, select an appropriate flash memory replacement solution based on the cost-effectiveness ratio. For cache modules, if the importance score is high and the current cache capacity is lower than the recommended value in the mapping library, increase the cache size is recommended. Adjustment plans must comprehensively consider performance improvement potential and cost factors. For example, for components that are extremely important but have high replacement costs (such as main control chips), a phased upgrade strategy can be provided, prioritizing the optimization of the most cost-effective parameters.

[0081] All hardware configuration adjustment suggestions are consolidated into a complete hardware configuration adjustment plan. The plan must clearly define the priority, expected performance improvement, and implementation cost of each adjustment item. This automated plan generation mechanism based on preset mapping relationships can quickly locate performance bottlenecks and provide a precise hardware upgrade path, ensuring that the adjustment plan matches the hardware parameter importance assessment and achieves optimal resource allocation.

[0082] According to an embodiment of the present invention, the method also includes: obtaining updated hardware data of the target solid-state disk after adjustment; inputting the updated hardware data into a preset model for iterative prediction to obtain an updated prediction performance indicator; when it is determined that there is a difference between the updated prediction performance indicator and the expected performance indicator, based on a preset mapping replacement relationship, replacing the hardware configuration whose feature importance evaluation is less than a preset value to generate a hardware adjustment plan; adjusting the target solid-state disk based on the hardware adjustment plan until the adjusted prediction performance indicator is consistent with the expected performance indicator.

[0083] To obtain updated hardware data after the target SSD is adjusted, the system management interface or dedicated detection tools are used to read the real-time parameters of the adjusted hardware configuration, such as interface protocol type, flash memory capacity and type, and cache size. This data is then standardized to ensure that the format is consistent with the input requirements of the preset model, such as using one-hot encoding for categorical variables and normalization for continuous variables. The updated hardware data is then input into the trained preset model, which automatically distributes the data to multiple decision trees for parallel prediction and calculates the average of the outputs of all decision trees to obtain the updated prediction performance metric.

[0084] If there is a discrepancy between the updated predicted performance indicators and the expected performance indicators (e.g., the read and write speeds do not achieve the expected improvement), hardware configurations with feature importance evaluations less than the preset values are screened from the preset mapping replacement relationships. Although these parameters have a small impact on overall performance, there may still be room for optimization. For example, if the cache size has a low importance score but the current capacity is insufficient, the mapping library may recommend increasing the cache capacity; if the interface transmission protocol has been upgraded but the performance does not meet expectations, consider replacing minor components (such as the heat dissipation module) to improve stability. For each screened hardware parameter, a specific replacement plan is generated, including a list of alternative components, expected performance improvement, and cost assessment.

[0085] In addition, to further improve the orderliness and effectiveness of optimization, multiple priorities can be set. The replacement plans are divided into three levels: high, medium, and low. High priority focuses on hardware parameters that are simple to replace, low in cost, and expected to have significant performance improvements. Medium priority targets components that are moderately difficult to replace, have controllable costs, and have a certain effect on performance optimization. Low priority covers hardware that is complex to replace and has a high cost, such as replacing the motherboard chipset and upgrading large-capacity flash memory particles. During the replacement process, the priorities are executed in descending order. After each level of replacement is completed, the performance test is re-performed. If the performance meets the expected indicators, the replacement is stopped. If there is still a difference, the replacement plan of the next priority will be executed, and this cycle will be repeated until the performance meets the standard or the replacement attempts of all priorities are completed.

[0086] The target SSD is iteratively adjusted based on the generated hardware adjustment plan. After each adjustment, the aforementioned data acquisition, model prediction, and variance analysis process is repeated until the difference between the updated predicted performance indicator and the expected performance indicator is within an acceptable range (e.g., the error rate is less than 5%). During this iterative process, the preset threshold is dynamically adjusted to gradually expand or narrow the feature importance screening range, ensuring that potential optimization points are not missed while minor parameters are not over-adjusted. This closed-loop optimization mechanism achieves a precise match between hardware configuration and performance expectations, fully leveraging the data-driven role of the preset model in hardware tuning.

[0087] According to an embodiment of the present invention, the method also includes: determining a target performance indicator from a plurality of injection error performance indicators, wherein the temperature value corresponding to the target performance indicator is a preset temperature, and the number of erasures corresponding to the target performance indicator is a preset number; inputting the target performance indicator into a preset model to perform a deviation analysis on the target performance indicator and the predicted performance indicator to obtain an analysis result; dynamically adjusting the model parameters of the preset model according to the analysis result until the deviation between the predicted performance indicator and the target performance indicator is less than a preset error threshold.

[0088] To determine the target performance metric from multiple injection error performance metrics, we first filter the test dataset to identify all performance metric records where the temperature is equal to a preset temperature (e.g., 25°C) and the number of erases is equal to a preset number (e.g., 0). These records constitute the performance set for a specific injection error scenario. From these records, we select the metric that best reflects the core capabilities of the SSD as the target performance metric.

[0089] When the target performance metric is input into the preset model for deviation analysis, the model predicts performance under the same injection error scenario based on the current hardware parameters and generates a predicted performance metric. The prediction deviation is quantified by calculating the absolute difference or relative error (e.g., |predicted value - target value| / target value) between the two. If the deviation exceeds a preset error threshold (e.g., 10%), the dynamic adjustment mechanism for model parameters is triggered. This adjustment process uses gradient descent or grid search algorithms to iteratively optimize key hyperparameters of the random forest (e.g., the number of decision trees, tree depth, and minimum number of sample splits). After each adjustment, the model's prediction accuracy on the validation set is re-evaluated until the deviation between the predicted performance metric and the target performance metric converges to within the threshold.

[0090] During the dynamic adjustment process, a parameter-bias response surface is established to analyze the sensitivity of each hyperparameter to prediction accuracy. For example, if increasing the number of decision trees significantly reduces bias, then expanding the forest size is prioritized. If limiting the tree depth effectively reduces overfitting, then that parameter is adjusted. Regularization terms are also introduced to prevent model overfitting, ensuring that the optimized model maintains generalization capabilities even in unseen injection error scenarios. Through this closed-loop feedback mechanism, the preset model can automatically calibrate prediction bias, improving the accuracy of target SSD performance predictions under specific temperature and erase count combinations, providing more reliable data analysis support for hardware design optimization.

[0091] Figure 4 A schematic diagram of a performance optimization module in a solid-state disk performance optimization method according to an embodiment of the present invention is shown.

[0092] The SSD performance test optimization process consists of three modules: an indicator prediction module 410 , a performance error testing module 420 , and a performance analysis module 430 .

[0093] After initiating the process, the system first enters the indicator prediction module 410. Based on the target SSD's hardware data, the indicator prediction module 410 uses a preset model to predict performance and obtain predicted performance indicators. Next, the performance error testing module 420 simulates error scenarios such as injection temperature and erase counts to collect error performance indicators. The performance analysis module 430 then compares the predicted data with the actual data to identify deviations and performance bottlenecks. The analysis results are fed back to the indicator prediction module 410 for optimization of the preset model. This cycle continues until the test optimization goal is achieved.

[0094] During implementation, the indicator prediction module 410 can integrate the target SSD's hardware data (interfaces, flash memory, cache, etc.) into a training model based on machine learning algorithms (such as random forests) to output predicted performance indicators. The performance error injection testing module 420 uses hardware control interfaces and firmware simulation tools to inject errors such as temperature fluctuations and abnormal erase counts and collects error-injected performance indicators. The performance analysis module 430 uses statistical analysis and deviation calculation algorithms to compare predicted and measured data, identify sources of errors and performance shortcomings, and generate a feedback report containing optimization directions. This report is then sent back to the indicator prediction module 410 to update model parameters, iteratively improving prediction accuracy and test effectiveness.

[0095] By establishing a closed-loop "prediction-testing-analysis-optimization" process, we leverage pre-set models to predict the performance of target SSDs and plan pre-set scenarios in advance, avoiding blind testing. Testing under pre-set scenarios accurately simulates extreme and abnormal operating conditions, effectively exposing potential performance issues with the target SSDs. This ensures that their performance in real-world scenarios is more in line with expectations, thereby improving their reliability and stability.

[0096] According to an embodiment of the present invention, based on the error injection performance index, the firmware program in the target solid-state disk is adjusted to optimize the performance of the target solid-state disk in a preset scenario, including: forming a first strategy in the firmware program based on the temperature error injection data obtained from multiple error injection performance indicators, the first strategy including at least one of a main frequency adjustment scheme and a cache management scheme; reconstructing the wear leveling algorithm in the firmware program based on the erase error injection data obtained from the multiple error injection performance indicators to form a second strategy, so that during the operation of the target solid-state disk, the first strategy and the second strategy are respectively executed by the policy execution engine in the firmware program.

[0097] Based on the temperature error injection data extracted from multiple error injection performance indicators, the performance degradation pattern and error trigger threshold of the target solid-state drive in different temperature ranges are analyzed, and the first dynamic response strategy is constructed in the firmware program. For example, when the temperature error injection data shows that the read and write delays of the main control chip increase significantly at 70°C, the temperature monitoring threshold is set in the firmware program. When the real-time temperature exceeds the threshold, the processor operating frequency is automatically reduced through the main frequency adjustment scheme, and the cache management scheme is activated synchronously. For example, the write cache strategy is switched from asynchronous mode to synchronous mode to reduce the risk of data loss under high temperature. These cache strategies are associated through the temperature and strategy mapping table in the firmware program to form a configurable parameter group, which is convenient for subsequent iterative optimization based on new error injection data.

[0098] Based on the uneven wear problem of flash memory blocks exposed in the erase misinjection data, the wear leveling algorithm in the firmware program is reconstructed to form a second strategy. Specifically, the block erase count distribution in the erase misinjection scenario is analyzed. If it is found that the number of erases of a specific logical block exceeds the average level (4000 times), a dynamic weight mechanism is introduced into the wear leveling algorithm. The data migration priority is increased for high-frequency erase blocks, and the hot data is dispersed to cold blocks through the scheduling algorithm in the firmware program. At the same time, the garbage collection strategy is adjusted to perform more frequent free block scans for high-wear blocks. The reconstructed scheduling algorithm monitors the number of erases of each physical block in real time (which can be obtained through the firmware register). When the number of erases of a block reaches the preset threshold, a targeted balancing operation is triggered to ensure that the erase pressure is evenly distributed.

[0099] A policy execution engine is integrated into the firmware program. This policy execution engine collects temperature sensor data and erase count counter status in real time through the hardware monitoring module. When the temperature reaches the trigger condition of the first policy, the policy execution engine automatically calls the main frequency adjustment and cache management scheme, and modifies the operating parameters of the main control chip through the register configuration interface. When the erase count meets the activation threshold of the second policy, the engine activates the reconstructed wear leveling algorithm and adjusts the block allocation logic for data writing. During the policy execution process, the policy execution engine will continuously record the performance indicator data after the policy takes effect (such as the temperature drop and the improvement in erase balance), forming a closed-loop optimization mechanism to facilitate the subsequent iteration of the policy parameters based on the new error injection performance indicators.

[0100] According to an embodiment of the present invention, the method also includes: generating a performance change curve of the target solid-state disk under a preset scenario based on temperature error injection data and erase error injection data, and displaying it through a graphical interface, wherein the performance change curve represents the trend of the error injection performance index changing with temperature and number of erase times.

[0101] When generating a performance curve for a target SSD under a preset scenario based on temperature and erase error data, the data must first be structured. The temperature value, erase count, and corresponding error performance metrics (such as read / write speed and latency) are associated into triples. After data cleaning to remove outliers, the data is grouped and aggregated by temperature interval (e.g., every 10°C) and erase count gradient (e.g., every 500 times). The mean and variance of the performance metrics within each group are calculated. For example, on a two-dimensional temperature-erase count plane, with 0°C as the horizontal axis and 0 erase counts as the vertical axis, a grid-like data point matrix is constructed, with each intersection storing the statistical value of the performance metric for the corresponding scenario.

[0102] A data visualization engine is used to draw performance change curves. For two-dimensional trend display, the temperature value can be set on the horizontal axis and the number of erasures can be set on the vertical axis. The depth of the heat map color blocks can be used to indicate the level of performance indicators. At the same time, contour lines are superimposed to mark the temperature-erasure number combinations with the same performance. For dynamic trend display, a three-dimensional surface graph can be generated, with the Z axis representing the performance indicators. The change patterns in different dimensions can be presented through rotation or slicing operations. For example, when the temperature rises from 25°C to 70°C and the number of erasures increases from 1000 to 3000 times, the attenuation trend is marked with a gradient color curve, and data labels are added at the inflection points (such as 50°C / 2000 times).

[0103] The generated visual interface supports curve screenshots, data export, and trend prediction functions, which can help users predict performance in extreme injection error scenarios.

[0104] Based on the above-mentioned solid state disk performance optimization method, the present invention also provides a solid state disk performance optimization device. Figure 5 The device is described in detail.

[0105] Figure 5 A structural block diagram of a solid-state disk performance optimization device according to an embodiment of the present invention is shown.

[0106] like Figure 5 As shown, the solid-state disk performance optimization device 500 of this embodiment includes a performance prediction module 510 , a solution generation module 520 , a scenario testing module 530 and a program adjustment module 540 .

[0107] The performance prediction module 510 is used to input the hardware data of the target solid state disk into a preset model to obtain a predicted performance index. In one embodiment, the performance prediction module 510 can be used to perform the operation S210 described above, which will not be repeated here.

[0108] Solution generation module 520 is configured to, when determining that the predicted performance indicator differs from the expected performance indicator, generate a hardware adjustment solution for the target SSD, thereby adjusting the hardware configuration of the target SSD based on the hardware adjustment solution. In one embodiment, solution generation module 520 may be configured to perform operation S220 described above, which will not be further described herein.

[0109] The scenario testing module 530 is used to test the adjusted target SSD in a preset scenario to obtain an injection error performance index for the preset scenario. In one embodiment, the scenario testing module 530 can be used to perform the operation S230 described above, which will not be repeated here.

[0110] The program adjustment module 540 is used to adjust the firmware program in the target solid-state drive based on the injection error performance index to optimize the performance of the target solid-state drive in a preset scenario. In one embodiment, the program adjustment module 540 can be used to perform the operation S240 described above, which will not be repeated here.

[0111] According to an embodiment of the present invention, any multiple modules among the performance prediction module 510, solution generation module 520, scenario testing module 530, and program adjustment module 540 may be combined into a single module, or any one of these modules may be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of other modules and implemented in a single module. According to an embodiment of the present invention, at least one of the performance prediction module 510, solution generation module 520, scenario testing module 530, and program adjustment module 540 may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or may be implemented in hardware or firmware by any other reasonable means of circuit integration or packaging, or may be implemented in any one of the three implementation methods of software, hardware, and firmware, or in any appropriate combination of any of these. Alternatively, at least one of the performance prediction module 510 , the solution generation module 520 , the scenario testing module 530 and the program adjustment module 540 may be at least partially implemented as a computer program module, which may perform corresponding functions when executed.

[0112] Figure 6 A block diagram of an electronic device suitable for implementing a solid-state disk performance optimization method according to an embodiment of the present invention is shown.

[0113] like Figure 6 As shown, an electronic device 600 according to an embodiment of the present invention includes a processor 601, which can perform various appropriate actions and processes based on programs stored in a read-only memory (ROM) 602 or programs loaded from a storage unit 608 into a random access memory (RAM) 603. The processor 601 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or related chipsets and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 601 may also include onboard memory for caching purposes. The processor 601 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0114] RAM 603 stores various programs and data required for the operation of electronic device 600. Processor 601, ROM 602, and RAM 603 are interconnected via bus 604. Processor 601 executes the programs in ROM 602 and / or RAM 603 to perform various operations according to the method flow of the embodiment of the present invention. It should be noted that the programs may also be stored in one or more memories other than ROM 602 and RAM 603. Processor 601 may also execute the programs stored in one or more memories to perform various operations according to the method flow of the embodiment of the present invention.

[0115] According to an embodiment of the present invention, electronic device 600 may further include an input / output (I / O) interface 605, which is also connected to bus 604. Electronic device 600 may also include one or more of the following components connected to I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including devices such as a cathode ray tube (CRT), liquid crystal display (LCD), and speakers; a storage section 608 including a hard disk; and a communication section 609 including a network interface card such as a LAN card or modem. Communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to I / O interface 605 as needed. Removable media 611, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in drive 610 as needed, so that computer programs read from the removable media can be installed into storage section 608 as needed.

[0116] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments, or may exist independently and not incorporated into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0117] According to an embodiment of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, and may include, for example, but not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present invention, a computer-readable storage medium may include the ROM 602 and / or RAM 603 described above, and / or one or more memories other than ROM 602 and RAM 603.

[0118] Embodiments of the present invention also include a computer program product comprising a computer program containing program code for executing the method shown in the flowchart. When the computer program product is executed in a computer system, the program code is used to cause the computer system to implement the solid-state drive performance optimization method provided in an embodiment of the present invention.

[0119] The computer program executes the above functions defined in the system / device of the embodiment of the present invention when the computer program is executed by the processor 601. According to the embodiment of the present invention, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0120] In one embodiment, the computer program may be stored on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may be transmitted and distributed in the form of a signal on a network medium, downloaded and installed via the communication portion 609, and / or installed from a removable medium 611. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0121] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 609 and / or installed from a removable medium 611. When the computer program is executed by the processor 601, the above-described functions defined in the system of the embodiment of the present invention are performed. According to the embodiment of the present invention, the systems, devices, means, modules, units, etc. described above can be implemented by computer program modules.

[0122] According to an embodiment of the present invention, the program code for executing the computer program provided by the embodiment of the present invention can be written in any combination of one or more programming languages. Specifically, these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages include, but are not limited to, languages such as Java, C++, Python, "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect via the Internet).

[0123] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0124] It will be understood by those skilled in the art that the features described in the various embodiments of the present invention may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention may be combined and / or coupled in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or couplings fall within the scope of the present invention.

[0125] The above describes embodiments of the present invention. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A method for optimizing solid-state disk performance, characterized in that: The method comprises: Input the hardware data of the target SSD into the preset model to obtain the predicted performance index; If it is determined that there is a difference between the predicted performance indicator and the expected performance indicator, generating a hardware adjustment plan for the target solid-state disk, so as to adjust the hardware configuration of the target solid-state disk based on the hardware adjustment plan; Testing the adjusted target solid-state drive in a preset scenario to obtain an injection error performance indicator for the preset scenario; Based on the injection error performance indicator, the firmware program in the target solid-state disk is adjusted to optimize the performance of the target solid-state disk in the preset scenario.

2. The method according to claim 1, characterized in that The adjusted target solid-state drive is tested in a preset scenario to obtain an injection error performance indicator for the preset scenario, including: Generating a test strategy corresponding to the preset scenario according to a preset error injection type, wherein the preset error injection type includes temperature error injection and erase count error injection, and the test strategy is determined by a combination of a temperature value of the temperature error injection and an erase count of the erase count error injection; Based on the generated test strategy, the target solid-state drive is tested in the preset scenario to obtain the injection error performance index.

3. The method according to claim 2, characterized in that The preset scenario includes a plurality of test strategies; the target solid-state drive is tested for the preset scenario based on the generated test strategy to obtain the injection error performance indicator, including: Determining a strategy execution order of the plurality of test strategies according to the number of erasures in each of the test strategies, wherein the number of erasures in the test strategies corresponds to a plurality of temperature values; Execute each of the test strategies in the strategy execution order.

4. The method according to claim 3, characterized in that The executing of each of the test strategies includes: While keeping the number of erasures of the current test strategy unchanged, gradually adjusting the operating environment temperature according to a preset temperature gradient to complete the test of the target solid-state disk at the multiple temperature values under the current number of erasures; When the tests on the plurality of temperature values are completed, the target solid state disk is subjected to a polishing process until the current erasure count of the target solid state disk reaches the erasure count required by the next test strategy in the strategy execution sequence.

5. The method according to claim 1, wherein Inputting the hardware data of the target solid-state drive into a preset model to obtain predicted performance indicators includes: Inputting the hardware data into a plurality of decision trees of the preset model respectively to obtain prediction results output by each decision tree, wherein the hardware data includes at least one of a flash memory chip characteristic value, a controller characteristic value, a cache characteristic value, and an interface transmission protocol; An average value of the plurality of prediction results is calculated to obtain the prediction performance index.

6. The method according to claim 5, characterized in that The preset model is trained by the following operations: Inputting sample hardware data of multiple sample solid-state drives into multiple decision trees of the initial model to obtain initial performance indicators output by each decision tree; Based on the evaluation indicators, each of the initial performance indicators is evaluated to obtain an evaluation result; Determining a model optimization strategy for the initial model based on the evaluation result, wherein the model optimization strategy includes at least one of increasing the number of decision trees and limiting the depth of the decision trees; Based on the model optimization strategy, the initial model is optimized to obtain the trained preset model.

7. The method according to claim 5, characterized in that Generating a hardware adjustment plan for the target solid state disk includes: Obtaining a feature importance evaluation of each hardware parameter in the hardware data from the preset model; A hardware adjustment solution for the hardware configuration of the target solid-state disk is generated according to the ranking of the plurality of feature importance evaluations.

8. The method according to claim 7, characterized in that Generating a hardware adjustment solution for the hardware configuration of the target solid-state drive according to the ranking of the plurality of feature importance evaluations includes: When it is determined that the sorting result indicates that the feature importance evaluation of the hardware configuration in the current target solid-state disk is greater than a preset value, a hardware adjustment solution for the hardware configuration in the target solid-state disk is generated based on a preset mapping replacement relationship.

9. The method according to claim 8, characterized in that The method further comprises: Obtaining updated hardware data of the target solid state drive after adjustment; Inputting the updated hardware data into the preset model for iterative prediction to obtain an updated prediction performance indicator; When it is determined that the updated predicted performance indicator differs from the expected performance indicator, replacing the hardware configuration whose feature importance evaluation is less than the preset value based on the preset mapping replacement relationship to generate the hardware adjustment plan; The target solid-state disk is adjusted based on the hardware adjustment solution until the adjusted predicted performance index is consistent with the expected performance index.

10. The method according to claim 1, characterized in that The method further comprises: Determining a target performance indicator from the plurality of injection error performance indicators, wherein a temperature value corresponding to the target performance indicator is a preset temperature, and a number of erasures corresponding to the target performance indicator is a preset number; Inputting the target performance indicator into the preset model to perform deviation analysis on the target performance indicator and the predicted performance indicator to obtain an analysis result; Dynamically adjust the model parameters of the preset model according to the analysis result until the deviation between the predicted performance indicator and the target performance indicator is less than a preset error threshold.

11. The method according to claim 1, wherein The step of adjusting the firmware program in the target solid-state drive based on the injection error performance indicator to optimize the performance of the target solid-state drive in the preset scenario includes: forming a first strategy in the firmware program based on the temperature error injection data obtained from the plurality of error injection performance indicators, the first strategy including at least one of a main frequency adjustment scheme and a cache management scheme; Based on the erase error data obtained from the multiple error performance indicators, the wear leveling algorithm in the firmware program is reconstructed to form a second strategy, so that during the operation of the target solid-state drive, the first strategy and the second strategy are respectively executed through the policy execution engine in the firmware program.

12. The method according to claim 11, characterized in that The method further comprises: Based on the temperature error injection data and the erase error injection data, a performance change curve of the target solid-state disk under the preset scenario is generated and displayed through a graphical interface, wherein the performance change curve represents the trend of the error injection performance index changing with temperature and number of erase times.

13. An electronic device comprising: one or more processors; a memory for storing one or more computer programs, It is characterized in that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 12.

14. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instructions are executed by a processor, the steps of the method according to any one of claims 1 to 12 are implemented.

15. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 12 when being executed by a processor.

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