Power distribution network inspection method and device, electronic equipment and readable storage medium

Abstract

The invention discloses an inspection method and device of a power distribution network, electronic equipment and a readable storage medium, and relates to the technical field of integrated circuits, in the design stage of the power distribution network, a plurality of first test points are arranged on a first conductive layer of the power distribution network, and a plurality of second test points are arranged on a second conductive layer of the power distribution network, the first test point is used for being electrically connected with a power supply pin of an external power supply, the second test point is used for being electrically connected with a power supply pin of the first logic unit, and the power supply pin of the first logic unit is used for being electrically connected with the power supply pin of the external power supply; and under the condition that the first resistance value is greater than the first threshold value, determining that the connectivity between the first test point and the second test point in the power distribution network is abnormal, so that a worker can timely know and deal with the connectivity, and the connectivity of the power distribution network is checked in the design stage of the power distribution network.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, and specifically relates to a method, device, electronic device and readable storage medium for inspecting a power distribution network. Background Art

[0002] The chip's power distribution network, also known as the chip's power mesh, is used to supply power to the chip's logic units.

[0003] In order to ensure the normal operation of the chip, the connectivity of the power distribution network needs to be guaranteed to be normal. Therefore, during the design phase of the power distribution network, the connectivity of the power distribution network needs to be checked. Summary of the Invention

[0004] The present application aims to provide a method, device, electronic device and readable storage medium for inspecting a power distribution network, at least to solve the problem of needing to inspect the connectivity of a power distribution network during the design phase of the power distribution network.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a method for inspecting a power distribution network, the power distribution network comprising multiple conductive layers, the method comprising:

[0007] During the design phase of the power distribution network, a plurality of first test points are provided on a first conductive layer of the power distribution network, and a plurality of second test points are provided on a second conductive layer of the power distribution network; the first test points are used to be electrically connected to power pins of an external power supply, and the second test points are used to be electrically connected to power pins of a first logic unit; the power pins of the first logic unit are used to be electrically connected to power pins of the external power supply;

[0008] Obtaining a first resistance value between the first test point and the second test point;

[0009] When the first resistance value is greater than a first threshold, it is determined that connectivity between the first test point and the second test point in the power distribution network is abnormal.

[0010] In a second aspect, an embodiment of the present application further provides a device for inspecting a power distribution network, the device comprising:

[0011] a first setting module, configured to set, during a design phase of the power distribution network, a plurality of first test points on a first conductive layer of the power distribution network and a plurality of second test points on a second conductive layer of the power distribution network; the first test points being configured to be electrically connected to power pins of an external power supply, and the second test points being configured to be electrically connected to power pins of a first logic unit; and the power pins of the first logic unit being configured to be electrically connected to power pins of the external power supply;

[0012] A first obtaining module, configured to obtain a first resistance value between the first test point and the second test point;

[0013] The first determining module is configured to determine that connectivity between the first test point and the second test point in the power distribution network is abnormal when the first resistance value is greater than a first threshold.

[0014] In a third aspect, an embodiment of the present application further provides an electronic device comprising a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the method described in the first aspect.

[0015] In a fourth aspect, an embodiment of the present application further provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0016] In an embodiment of the present application, during the design stage of the distribution network, multiple first test points are set on the first conductive layer of the distribution network, and multiple second test points are set on the second conductive layer of the distribution network, wherein the first test point is used to electrically connect to the power pin of the external power supply, the second test point is used to electrically connect to the power pin of the first logic unit, and the power pin of the first logic unit is used to electrically connect to the power pin of the external power supply, and then the first resistance value between the first test point and the second test point is obtained, and then when the first resistance value is greater than the first threshold value, it is determined that the connectivity between the first test point and the second test point in the distribution network is abnormal, so that the staff can be informed and handled in time, thereby realizing the connectivity inspection of the distribution network during the design stage of the distribution network. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a flowchart of a method for inspecting a power distribution network provided in an embodiment of the present application;

[0018] Figure 2 This is a flowchart of the specific steps of a method for inspecting a power distribution network provided in an embodiment of the present application;

[0019] Figure 3is a schematic diagram of a power distribution network provided in an embodiment of the present application;

[0020] Figure 4 is a schematic diagram of another power distribution network provided in an embodiment of the present application;

[0021] Figure 5 is a schematic diagram of a conductive layer provided in an embodiment of the present application;

[0022] Figure 6 is a schematic diagram of another conductive layer provided in an embodiment of the present application;

[0023] Figure 7 This is a schematic diagram of a power distribution network inspection process provided by an embodiment of the present application;

[0024] Figure 8 This is a block diagram of a power distribution network inspection device provided in an embodiment of the present application;

[0025] Figure 9 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application.

[0027] Figure 1 This is a flow chart of the steps of a method for inspecting a power distribution network provided by an embodiment of the present application, such as Figure 1 As shown, the method may include:

[0028] Step 101: During the design phase of the power distribution network, a plurality of first test points are set on a first conductive layer of the power distribution network, and a plurality of second test points are set on a second conductive layer of the power distribution network.

[0029] Among them, the first test point is used to electrically connect to the power pin of the external power supply, and the second test point is used to electrically connect to the power pin of the first logic unit; the power pin of the first logic unit is used to electrically connect to the power pin of the external power supply.

[0030] In some embodiments, the power distribution network is the power distribution network of the chip. The design stage of the power distribution network of the chip is before the manufacturing stage of the chip. In the design stage of the power distribution network, the power distribution network of the chip is designed to form a design file of the power distribution network. For example, the power distribution network of the chip is designed using an automatic placement and routing (APR, AutoPlacement&Route) tool; after the design stage of the power distribution network, the first logic unit of the chip is laid out and placed according to the power distribution network of the chip.

[0031] It should be noted that the first conductive layer is used to electrically connect to the power pin of the external power supply, and the second conductive layer is used to electrically connect to the power pin of the first logic unit; the first test point is a position point of the first conductive layer; the second test point is a position point of the second conductive layer.

[0032] In some embodiments, the power distribution network of the chip is the power distribution network of the entire chip; in other embodiments, the chip includes multiple chip modules, and the power distribution network of the chip is the power distribution network of the chip modules in the chip.

[0033] In some embodiments, the first logic unit is a standard unit of the chip, and the standard unit includes a logic gate unit, a driving unit, a timing unit, an operation unit, a mixed logic unit, etc., wherein the logic gate unit includes an AND gate, an OR gate, a NAND gate, a NOR gate, an AND-NOR gate, an OR-NAND gate, an XOR gate, etc., the driving unit includes a buffer and an inverter, etc., the timing unit includes a trigger, a latch, a shift register, etc., the operation unit includes a half adder, a full adder, a subtractor, a two-bit comparator, etc., and the mixed logic unit includes a multiplexer, a counter, an encoder, a decoder, a parity generator, etc.

[0034] In some embodiments, the types of power pins of the first logic unit include a power supply (POWER) pin and a ground (GND) pin, and the types of power pins of the external power supply include a power supply pin and a ground pin; wherein, the power supply pin is the positive pin, and the ground pin is the negative pin; each power pin of the external power supply has a corresponding first test point, and each power pin of the first logic unit has a corresponding second test point, wherein the first test point corresponding to the power supply pin of the external power supply is used to electrically connect to the power supply pin of the external power supply, the first test point corresponding to the ground pin of the external power supply is used to electrically connect to the ground pin of the external power supply, the second test point corresponding to the power supply pin of the first logic unit is used to electrically connect to the power supply pin of the first logic unit, and the second test point corresponding to the ground pin of the first logic unit is used to electrically connect to the ground pin of the first logic unit.

[0035] In some embodiments, the power distribution network includes multiple conductive layers, and conductive vias are provided between adjacent conductive layers. For example, the conductive vias are in the form of stacked holes, and the conductive vias are solid hole structures. When the connectivity of the power distribution network is normal, adjacent conductive layers are electrically connected through the conductive vias.

[0036] In some embodiments, the power distribution network includes multiple conductive layers, and other layers are provided between adjacent conductive layers. For example, the other layers are insulating layers, and conductive vias are provided in the other layers.

[0037] In an embodiment of the present application, in order to check the connectivity of the distribution network during the design phase of the distribution network, it is necessary to set multiple first test points on the first conductive layer of the distribution network and multiple second test points on the second conductive layer of the distribution network, and then check the connectivity between the first test points and the second test points to achieve the connectivity check of the distribution network.

[0038] Step 102: Obtain a first resistance value between the first test point and the second test point.

[0039] It should be noted that the first resistance value between the first test point and the second test point is the equivalent resistance value of all designed circuits for connecting the first test point and the second test point in the power distribution network.

[0040] In some embodiments, obtaining the first resistance value between the first test point and the second test point includes respectively obtaining the first resistance value between a first test point and each second test point, and respectively obtaining the first resistance value between each first test point and a second test point.

[0041] In an embodiment of the present application, the connectivity of the distribution network is normal, which requires that the equivalent resistance values of all designed lines between the first test point and the second test point in the distribution network are less than or equal to the first threshold value; when the equivalent resistance values of all designed lines between the first test point and the second test point are less than or equal to the first threshold value, it can be determined that the connectivity between the first test point and the second test point is normal, and then it can be determined that the power supply signal is input at the first test point, and the power supply signal passes through the designed line between the first test point and the second test point, so that the second test point can be normally powered. Therefore, by obtaining the first resistance value between the first test point and the second test point, it is possible to determine whether the connectivity between the first test point and the second test point is normal, and then it is determined whether the connectivity of the distribution network is normal.

[0042] Step 103: When the first resistance value is greater than a first threshold, determine that connectivity between the first test point and the second test point in the power distribution network is abnormal.

[0043] It should be noted that the first resistance value is greater than the first threshold value, indicating that there is a weak connection or a break in the design circuit between the first test point and the second test point. When there is a weak connection in the design circuit between the first test point and the second test point, the connectivity between the first test point and the second test point is poor; when there is a break in the design circuit between the first test point and the second test point, the first test point is disconnected from the second test point.

[0044] When the connectivity between the first test point and the second test point in the power distribution network is abnormal, the connectivity of the power distribution network is determined to be abnormal; when the connectivity between any first test point and each second test point corresponding to the power pin of the same external power supply in the power distribution network is normal, or when the connectivity between each first test point and any second test point corresponding to the power pin of the same external power supply in the power distribution network is normal, the connectivity of the power distribution network is determined to be normal.

[0045] In some embodiments, when the first resistance value is less than or equal to a first threshold, it is determined that the connectivity between the first test point and the second test point in the power distribution network is normal.

[0046] In an embodiment of the present application, by determining that the connectivity between the first test point and the second test point in the distribution network is abnormal when the first resistance value is greater than the first threshold, the connectivity abnormality of the distribution network is determined, so that the staff can be informed and handled in time.

[0047] In some embodiments, the first conductive layer is used to electrically connect to multiple external power supplies, each external power supply has a corresponding first test point and a second test point, and each external power supply has a corresponding power pin of a first logic unit; the number of first logic units is multiple; the first test point corresponding to the external power supply is used to electrically connect to the power pin of the external power supply; the second test point corresponding to the external power supply is used to electrically connect to the power pin of the first logic unit corresponding to the external power supply; the first resistance value between the first test point and the second test point is obtained, that is, the first resistance value between the first test point and the second test point corresponding to the external power supply is obtained, and when the first resistance value between the first test point and the second test point corresponding to the external power supply is greater than the first threshold value, it is determined that the connectivity between the first test point and the second test point corresponding to the external power supply in the power distribution network is abnormal.

[0048] Taking steps 101 to 103 as an example, for example, the power distribution network is a power distribution network of a chip module, the first conductive layer is used to be electrically connected to the power pin of the external power supply D1; the second conductive layer is used to be electrically connected to the power pin of the first logic unit E1;

[0049] During the design stage of the power distribution network, four first test points are set on the first conductive layer of the power distribution network, and the four first test points are respectively a first test point A1, a first test point A2, a first test point A3, and a first test point A4, wherein the first test point A1 and the first test point A2 are both used to electrically connect to the power supply pin of the external power supply D1, and the first test point A3 and the first test point A4 are both used to electrically connect to the ground pin of the external power supply D1; four second test points are set on the second conductive layer of the power distribution network, and the four second test points are respectively a second test point B1, a second test point B2, a second test point B3, and a second test point B4, wherein the second test point B1 and the second test point B2 are used to electrically connect to the power supply pin of the first logic unit E1, and the second test point B3 and the second test point B4 are used to electrically connect to the ground pin of the first logic unit E1;

[0050] Obtain a first resistance value C1 between the first test point A1 and the second test point B1, obtain a first resistance value C2 between the first test point A1 and the second test point B2, obtain a first resistance value C3 between the first test point A2 and the second test point B1, obtain a first resistance value C4 between the first test point A2 and the second test point B2; obtain a first resistance value C5 between the first test point A3 and the second test point B3, obtain a first resistance value C6 between the first test point A3 and the second test point B4, obtain a first resistance value C7 between the first test point A4 and the second test point B3, and obtain a first resistance value C8 between the first test point A4 and the second test point B4;

[0051] When the first resistance value is greater than the first threshold value, it is determined that the connectivity between the first test point and the second test point in the distribution network is abnormal, and then the connectivity of the distribution network is determined to be abnormal. For example, when the first resistance value C1 is greater than the first threshold value, it is determined that the connectivity between the first test point A1 and the second test point B1 in the distribution network is abnormal, and then the connectivity of the distribution network is determined to be abnormal; when the first resistance value is less than or equal to the first threshold value, it is determined that the connectivity between the first test point and the second test point in the distribution network is normal. For example, when the first resistance value C1 is less than or equal to the first threshold value, it is determined that the connectivity between the first test point A1 and the second test point B1 in the distribution network is normal; when the first resistance value C1, the first resistance value C2, the first resistance value C3, the first resistance value C4, the first resistance value C5, the first resistance value C6, the first resistance value C7 and the first resistance value C8 are all less than or equal to the first threshold value, it is determined that the connectivity of the distribution network is normal.

[0052] For another example, the power distribution network is a power distribution network of a chip module, and the first conductive layer is used to be electrically connected to the power pin of the external power supply D1 and the power pin of the external power supply D2 respectively; the second conductive layer is used to be electrically connected to the power pin of the first logic unit E1 and the power pin of the first logic unit E2 respectively;

[0053] During the design phase of the power distribution network, eight first test points are set on the first conductive layer of the power distribution network. The eight first test points are respectively the first test point A1, the first test point A2, the first test point A3, the first test point A4, the first test point A5, the first test point A6, the first test point A7, and the first test point A8. Among them, the first test point A1 and the first test point A2 are both used to electrically connect to the power supply pin of the external power supply D1, the first test point A3 and the first test point A4 are both used to electrically connect to the ground pin of the external power supply D1, the first test point A5 and the first test point A6 are both used to electrically connect to the power supply pin of the external power supply D2, and the first test point A7 and the first test point A8 are both used to electrically connect to the ground pin of the external power supply D2. Electrical connection; 8 second test points are set on the second conductive layer of the power distribution network, and the 8 second test points are respectively a second test point B1, a second test point B2, a second test point B3, a second test point B4, a second test point B5, a second test point B6, a second test point B7, and a second test point B8, wherein the second test point B1 and the second test point B2 are used to be electrically connected to the power supply pin of the first logic unit E1, the second test point B3 and the second test point B4 are used to be electrically connected to the ground pin of the first logic unit E1, the second test point B5 and the second test point B6 are used to be electrically connected to the power supply pin of the first logic unit E2, and the second test point B7 and the second test point B8 are used to be electrically connected to the ground pin of the first logic unit E2;

[0054] Obtain a first resistance value C1 between the first test point A1 and the second test point B1, obtain a first resistance value C2 between the first test point A1 and the second test point B2, obtain a first resistance value C3 between the first test point A2 and the second test point B1, obtain a first resistance value C4 between the first test point A2 and the second test point B2; obtain a first resistance value C5 between the first test point A3 and the second test point B3, obtain a first resistance value C6 between the first test point A3 and the second test point B4, obtain a first resistance value C7 between the first test point A4 and the second test point B3, and obtain a first resistance value C8 between the first test point A4 and the second test point B4;

[0055] Obtain a first resistance value C9 between the first test point A5 and the second test point B5, obtain a first resistance value C10 between the first test point A5 and the second test point B6, obtain a first resistance value C11 between the first test point A6 and the second test point B5, obtain a first resistance value C12 between the first test point A6 and the second test point B6; obtain a first resistance value C13 between the first test point A7 and the second test point B7, obtain a first resistance value C14 between the first test point A7 and the second test point B8, obtain a first resistance value C15 between the first test point A8 and the second test point B7, obtain a first resistance value C16 between the first test point A8 and the second test point B8;

[0056] When the first resistance value is greater than the first threshold, it is determined that the connectivity between the first test point and the second test point in the power distribution network is abnormal, and then the connectivity of the power distribution network is abnormal. For example, when the first resistance value C1 is greater than the first threshold, it is determined that the connectivity between the first test point A1 and the second test point B1 in the power distribution network is abnormal, and then the connectivity of the power distribution network is abnormal. When the first resistance value is less than or equal to the first threshold, it is determined that the connectivity between the first test point and the second test point in the power distribution network is normal, such as when the first resistance value C1 is less than or equal to the first threshold. , determine that the connectivity between the first test point A1 and the second test point B1 in the power distribution network is normal; when the first resistance value C1, the first resistance value C2, the first resistance value C3, the first resistance value C4, the first resistance value C5, the first resistance value C6, the first resistance value C7 and the first resistance value C8, the first resistance value C9, the first resistance value C10, the first resistance value C11, the first resistance value C12, the first resistance value C13, the first resistance value C14, the first resistance value C15 and the first resistance value C16 are all less than or equal to the first threshold, determine that the connectivity of the power distribution network is normal.

[0057] To sum up, in an embodiment of the present application, during the design stage of the distribution network, multiple first test points are set on the first conductive layer of the distribution network, and multiple second test points are set on the second conductive layer of the distribution network, wherein the first test point is used to electrically connect to the power pin of the external power supply, the second test point is used to electrically connect to the power pin of the first logic unit, and the power pin of the first logic unit is used to electrically connect to the power pin of the external power supply, and then the first resistance value between the first test point and the second test point is obtained, and then when the first resistance value is greater than the first threshold value, it is determined that the connectivity between the first test point and the second test point in the distribution network is abnormal, so that the staff can be informed and handled in time, thereby realizing the connectivity inspection of the distribution network during the design stage of the distribution network.

[0058] Figure 2 This is a flowchart of the specific steps of a method for inspecting a power distribution network provided by an embodiment of the present application, such as Figure 2 As shown, the method may include:

[0059] Step 201: During the design phase of the power distribution network, a plurality of first test points are set on a first conductive layer of the power distribution network, and a plurality of second test points are set on a second conductive layer of the power distribution network.

[0060] Among them, the first test point is used to electrically connect to the power pin of the external power supply, and the second test point is used to electrically connect to the power pin of the first logic unit; the power pin of the first logic unit is used to electrically connect to the power pin of the external power supply.

[0061] The implementation of this step is similar to the implementation process of the above step 101 and will not be repeated here.

[0062] Optionally, in some embodiments, the first conductive layer is located at the top of the power distribution network; and the second conductive layer is located at the bottom of the power distribution network.

[0063] In an embodiment of the present application, since the first conductive layer is located at the top of the power distribution network, the power pin of the external power supply is electrically connected to the first conductive layer; since the second conductive layer is located at the bottom of the power distribution network, the power pin of each first logic unit is electrically connected to the second conductive layer.

[0064] For example, the power distribution network includes three conductive layers, namely conductive layer F1, conductive layer F2, and conductive layer F3. Conductive layer F1 is located above conductive layer F2, and conductive layer F2 is located above conductive layer F3. Among them, conductive layer F1 is the first conductive layer and conductive layer F3 is the second conductive layer.

[0065] Step 202: Obtain a first resistance value between the first test point and the second test point.

[0066] The implementation of this step is similar to the implementation process of the above step 102 and will not be repeated here.

[0067] Step 203: When the first resistance value is greater than the first threshold and the first resistance value is less than or equal to a second threshold, determine that the connectivity between the first test point and the second test point in the power distribution network is poor.

[0068] The first threshold is smaller than the second threshold.

[0069] In an embodiment of the present application, when the first resistance value is greater than the first threshold value and the first resistance value is less than or equal to the second threshold value, the current input by the external power supply to the second test point through the first test point is too small to meet the power demand of the first logic unit, and the first logic unit operates abnormally. At this time, it is determined that the connectivity between the first test point and the second test point in the power distribution network is poor, so that the staff can discover and handle it in time.

[0070] For example, the first threshold is 1 ohm, the second threshold is 3 ohms, and the first resistance value is 2 ohms. Since the first resistance value is greater than the first threshold and the first resistance value is less than or equal to the second threshold, it is determined that the connectivity between the first test point and the second test point in the power distribution network is poor.

[0071] Step 204: When the first resistance value is greater than the second threshold, determine that the first test point and the second test point in the power distribution network are disconnected.

[0072] For example, the first threshold is 1 ohm, the second threshold is 3 ohms, and the first resistance value is 10 ohms. Since the first resistance value is greater than the second threshold value, it is determined that the first test point and the second test point in the power distribution network are disconnected.

[0073] In an embodiment of the present application, when the first resistance value is greater than the second threshold value, the current input by the external power supply to the second test point through the first test point is 0, and the first logic unit stops working. At this time, it is determined that the first test point and the second test point in the power distribution network are disconnected, so that the staff can discover and handle it in time.

[0074] Optionally, in some embodiments, the conductive layer includes a plurality of conductive lines; and setting a plurality of first test points on the first conductive layer of the power distribution network includes the following sub-steps:

[0075] Sub-step 2011: setting at least one first test point on the conductive line of the first conductive layer for electrically connecting to the power pin of the external power supply.

[0076] In some embodiments, the power distribution network includes multiple conductive layers 10, each of which includes multiple conductive wires 11. Conductive vias 20 are provided between adjacent conductive layers 10, and the conductive vias 20 enable electrical connection between the conductive wires 11 in adjacent conductive layers 10. For example, a first conductive layer 10 is located above a second conductive layer 10, and a first conductive wire 11 of the first conductive layer 10 is electrically connected to a first conductive wire 11 of the second conductive layer 10 through the conductive via 20.

[0077] Reference Figure 3In some embodiments, the conductive lines 11 in the conductive layer 10 are arranged in parallel, and the conductive lines 11 in adjacent conductive layers 10 are perpendicular to each other. For example, the first conductive layer 10 is located above the second conductive layer 10, the conductive lines 11 in the first conductive layer 10 extend in a first direction, and the conductive lines 11 in the second conductive layer 10 extend in a second direction, and the first direction is perpendicular to the second direction; the conductive vias 20 are provided at the intersection of the projections of the conductive lines 11 in adjacent conductive layers 10 on the horizontal plane.

[0078] In some embodiments, the conductive wires of the first conductive layer include conductive wires for electrically connecting to the power supply pins of the external power supply and conductive wires for electrically connecting to the ground pins of the external power supply. The conductive wires for electrically connecting to the power supply pins of the external power supply and the conductive wires for electrically connecting to the ground pins of the external power supply are arranged alternately in the first conductive layer. For example, the first conductive layer includes 4 conductive wires, the first conductive wire is adjacent to the second conductive wire, the second conductive wire is adjacent to the third conductive wire, and the third conductive wire is adjacent to the fourth conductive wire, wherein the first conductive wire and the third conductive wire are both conductive wires for electrically connecting to the power supply pins of the external power supply, and the second conductive wire and the fourth conductive wire are both conductive wires for electrically connecting to the ground pins of the external power supply.

[0079] In some embodiments, a first test point is provided at a midpoint of a conductive line for electrically connecting to a power pin of an external power source.

[0080] In the embodiment of the present application, since at least one first test point is set on the conductive line of the first conductive layer for electrically connecting to the power pin of the external power supply, the first test point is used to electrically connect to the power pin of the external power supply.

[0081] Optionally, in some embodiments, sub-step 2011 includes the following sub-steps:

[0082] In sub-step 2011a, a plurality of the first test points are arranged in an array on the conductive line for electrically connecting to the power pin of the external power source.

[0083] In some embodiments, the array may be a matrix.

[0084] For example, refer to Figure 5 The conductive layer 10 located at the top of the power distribution network is the first conductive layer. The first conductive layer includes a plurality of conductive wires 11. The conductive wires are used to electrically connect to the power pins of the external power supply. Two first test points 40 are set in an array form. The array includes 1 row and 2 columns.

[0085] In the embodiment of the present application, since multiple first test points are arranged in an array on the conductive line for electrically connecting to the power pin of the external power supply, the first test points are regularly distributed, which is conducive to testing within the range of the entire conductive line.

[0086] Optionally, in some embodiments, a plurality of power connection portions are provided on the first conductive layer, and the power connection portions are used to electrically connect to power pins of the external power supply; and providing a plurality of first test points on the first conductive layer of the power distribution network includes the following sub-steps:

[0087] Sub-step 2012: setting at least one of the first test points on the power connection portion.

[0088] In some embodiments, the power connection portion is a pad member disposed on the first conductive layer, such as a ball-shaped pad member.

[0089] In some embodiments, a first test point is set at the geometric center of the power connection portion.

[0090] In the embodiment of the present application, since the power connection portion is used to electrically connect to the power pin of the external power supply, at least one first test point is set on the power connection portion, and the first test point is used to electrically connect to the power pin of the external power supply.

[0091] Optionally, in some embodiments, sub-step 2012 includes the following sub-steps:

[0092] Sub-step 2012a: arranging a plurality of the first test points in an array at the power connection portion.

[0093] For example, at the power connection portion, four first test points are arranged in an array, and the array includes two rows and two columns of first test points.

[0094] In the embodiment of the present application, a plurality of first test points are arranged in an array at the power connection portion, so that the first test points are regularly distributed, which is beneficial for testing within the range of the entire power connection portion.

[0095] Optionally, in some embodiments, the conductive layer includes a plurality of conductive wires; and setting a plurality of second test points on the second conductive layer of the power distribution network includes the following sub-steps:

[0096] Sub-step 2013: setting at least one second test point on the conductive line of the second conductive layer for electrically connecting to the power pin of the first logic unit.

[0097] In some embodiments, a second test point is provided at a midpoint of a conductive line electrically connected to a power pin of the first logic unit.

[0098] In some embodiments, the conductive wires of the second conductive layer include conductive wires for electrically connecting to the power supply pin of the first logic unit and conductive wires for electrically connecting to the ground pin of the first logic unit, and the conductive wires electrically connected to the power supply pin of the first logic unit and the conductive wires for electrically connecting to the ground pin of the first logic unit are alternately arranged in the second conductive layer. For example, the second conductive layer includes 4 conductive wires, the first conductive wire is adjacent to the second conductive wire, the second conductive wire is adjacent to the third conductive wire, and the third conductive wire is adjacent to the fourth conductive wire, wherein the first conductive wire and the third conductive wire are both conductive wires for electrically connecting to the power supply pin of the first logic unit, and the second conductive wire and the fourth conductive wire are both conductive wires for electrically connecting to the ground pin of the first logic unit.

[0099] In the embodiment of the present application, since at least one second test point is provided on the conductive line of the second conductive layer for electrically connecting to the power pin of the first logic unit, the second test point is used to electrically connect to the power pin of the first logic unit.

[0100] Optionally, in some embodiments, sub-step 2013 includes the following sub-steps:

[0101] Sub-step 2013a: arranging a plurality of second test points in an array on the conductive line electrically connected to the power pin of the first logic unit.

[0102] For example, refer to Figure 6 The conductive layer 10 located at the bottom of the power distribution network is the second conductive layer. The second conductive layer includes a plurality of conductive wires 11. The conductive wires 11 used to be electrically connected to the power pins of the first logic unit are provided with a plurality of second test points 50 in an array form. The array includes one row of second test points 50.

[0103] In the embodiment of the present application, since multiple second test points are arranged in an array on the conductive line electrically connected to the power pin of the first logic unit, the second test points are regularly distributed, which is conducive to testing within the range of the entire conductive line.

[0104] Optionally, in some embodiments, before step 202, the method further includes the following steps:

[0105] Step 205: electrically connect each of the first test points for electrically connecting to the power pin of the same external power source to each other.

[0106] In some embodiments, each of the first test points for electrically connecting to power pins of the same external power source is electrically connected to each other using a resistance-free wire.

[0107] For example, the first conductive line and the second conductive line are both used to electrically connect to the power pin of the same external power supply, and each first test point of the first conductive line and each first test point of the second conductive line are electrically connected to each other.

[0108] In an embodiment of the present application, by electrically connecting each first test point for electrically connecting to the power pin of the same external power supply to each other, the first resistance value between each first test point for electrically connecting to the power pin of the same external power supply and the second test point is equal, so that each first test point is treated as a first node, the third resistance value between the first node and the second node is calculated once, and the third resistance value is determined as the first resistance value between each first test point for electrically connecting to the power pin of the same external power supply and the second test point, without the need for multiple calculations, that is, there is no need to calculate the first resistance value between each first test point for electrically connecting to the power pin of the same external power supply and the second test point.

[0109] Optionally, in some embodiments, step 202 includes the following sub-steps:

[0110] Sub-step 2021: Obtain resistance information of the power distribution network, and generate a resistance network based on the resistance information; the resistance network includes multiple first nodes and multiple second nodes; the first test point has a corresponding first node, and the second test point has a corresponding second node.

[0111] It should be noted that each conductive line, each conductive via, power connection part, hard macro unit and other components in the distribution network are equivalent to multiple resistor devices, and information such as the multiple resistor devices equivalent to the distribution network and the connection relationship between the multiple resistor devices is determined as the resistance information of the distribution network; the resistor network is a circuit network composed of multiple resistor devices equivalent to the distribution network connected according to the connection relationship between the multiple resistor devices.

[0112] In some embodiments, each first test point electrically connected to a power pin of the same external power source corresponds to a first node.

[0113] In an embodiment of the present application, by obtaining the resistance information of the distribution network, and generating a resistance network based on the resistance information, and then listing a resistance equation based on the resistance network, since the first test point has a corresponding first node and the second test point has a corresponding second node, the third resistance value can be calculated by solving the resistance equation.

[0114] Sub-step 2022: Obtain a resistance equation of the resistor network according to Kirchhoff's law and Ohm's law.

[0115] In some embodiments, the resistance equation of the resistor network is:

[0116]

[0117] The resistor network consists of N nodes. The resistance value to be calculated is the resistance value between the first node X and the second node Y. A unit current is set to flow into the first node X and outflow from the second node Y. The direction of current inflow is positive and the direction of current outflow is negative. M is the set of nodes j adjacent to node i. ΔV(j,i) is the voltage drop between nodes j and i, and:

[0118] ΔV(j,i)=V j -V i

[0119] V j is the level of node j, V i is the level of node i;

[0120] ΔR(j,i) is the resistance between node j and node i, and:

[0121] ΔR(j,i)=k(j,i)×R0

[0122] k(j,i) is the resistance coefficient, R0 is the unit resistance value;

[0123] I(i) is the current value of node i. When i=X, I(X)=I0; when i=Y, I(Y)=-I0, where I0 is the unit current value; when i is equal to other node numbers, I(i)=0.

[0124] The resistance equation of the resistor network can be organized as:

[0125] K×v=l

[0126] Where K is an N×N matrix containing node and resistor coefficient information, v and l are N×1 matrices, v represents the level of each node, l represents the relative current value of each node, and the relative current value is the product of the node current value and the unit resistance value.

[0127] After solving the resistance equation of the resistor network, the resistance value between the first node X and the second node Y can be obtained. The expression for the resistance value between the first node X and the second node Y is:

[0128] Reff XY =ΔV(X,Y) / I0

[0129] Among them, Reff XY is the resistance value between the first node X and the second node Y, and ΔV(X, Y) is the voltage drop between the first node X and the second node Y.

[0130] In an embodiment of the present application, a resistance equation of the resistance network is obtained according to Kirchhoff's law and Ohm's law, and then the third resistance value between the first node and the second node can be obtained by solving the resistance equation.

[0131] Sub-step 2023: Solve the resistance equation to obtain a third resistance value between the first node and the second node.

[0132] In an embodiment of the present application, the third resistance value between the first node and the second node is obtained by solving the resistance equation. Since the first test point has a corresponding first node and the second test point has a corresponding second node, the third resistance value between the first node corresponding to the first test point and the second node corresponding to the second test point can be determined as the first resistance value.

[0133] Sub-step 2024: determine a third resistance value between a first node corresponding to the first test point and a second node corresponding to the second test point as the first resistance value.

[0134] In some embodiments, each first test point electrically connected to the power pin of the same external power supply corresponds to a first node, and the third resistance value between the first node corresponding to the first test point and the second node corresponding to the second test point is determined as the first resistance value between each first test point electrically connected to the power pin of the same external power supply and the second test point.

[0135] In an embodiment of the present application, by determining the third resistance value between the first node corresponding to the first test point and the second node corresponding to the second test point as the first resistance value, and then determining that the connectivity between the first test point and the second test point in the power distribution network is abnormal when the first resistance value is greater than the first threshold.

[0136] In some embodiments, an electronic design automation (EDA) tool is used to obtain a first resistance value between the first test point and the second test point.

[0137] By executing sub-steps 2021 to 2024 , it is possible to obtain the first resistance value between the first test point and the second test point.

[0138] Optionally, in some embodiments, a second logic unit is provided in the power distribution network, and a power pin of the second logic unit is used to be electrically connected to a power pin of the external power supply; the method further comprises the following steps:

[0139] Step 206: Set at least one third test point on the power pin of the second logic unit.

[0140] In some embodiments, a third test point is set at the geometric center of the power pin of the second logic unit.

[0141] In an embodiment of the present application, in order to check the connectivity between the power pin of an external power supply and the power pin of a second logic unit in a power distribution network, at least one third test point is set at the power pin of the second logic unit, and then a second resistance value between the first test point and the third test point is obtained. Then, when the second resistance value is greater than a first threshold, it is determined that the connectivity between the first test point and the third test point in the power distribution network is abnormal, that is, the connectivity between the power pin of the external power supply and the power pin of the second logic unit is abnormal.

[0142] Optionally, in some embodiments, the second logic unit is a hard macro unit (Hard Macro).

[0143] It should be noted that hard macro cells are usually larger than standard cells. Figure 4 , the hard macro cells penetrate multiple conductive layers.

[0144] A hard macrocell is a pre-designed functional module in chip design. Its internal layout and routing are fixed and cannot be modified. Hard macrocells are typically used to implement complex functions such as memory, phase-locked loops, and analog-to-digital / digital-to-analog converters.

[0145] In some embodiments, the conductive layer of the power distribution network further includes a connection portion of the hard macro unit, and the power pins of the hard macro unit are connected to the connection portion of the hard macro unit through structures such as adapter wires and metal rings.

[0146] In some embodiments, the power pins of the hard macro cells are solid hole structures.

[0147] In the embodiment of the present application, since the second logic unit is a hard macro unit, it is necessary to set the second logic unit in the power distribution network during the design phase of the power distribution network to facilitate the power distribution network to adapt to the position of the hard macro unit.

[0148] Optionally, in some embodiments, step 206 includes the following sub-steps:

[0149] Sub-step 2061 : setting at least one third test point in an array on the power pin of the second logic unit.

[0150] For example, at the power pin of the second logic unit, four third test points are set in an array form, and the array includes two rows and two columns of third test points.

[0151] In the embodiment of the present application, at least one third test point is arranged in an array at the power pins of the second logic unit, so that the third test points are regularly distributed, which is conducive to testing within the range of the power pins of the entire second logic unit.

[0152] Step 207: Obtain a second resistance value between the first test point and the third test point.

[0153] In some embodiments, the resistance network includes multiple first nodes and multiple second nodes, and the third test point has a corresponding second node. By solving the resistance equation, the third resistance value between the first node and the second node is obtained, and then the third resistance value between the first node corresponding to the first test point and the second node corresponding to the third test point is determined as the second resistance value.

[0154] In an embodiment of the present application, in order to check the connectivity between the power pin of the external power supply and the power pin of the second logic unit in the power distribution network, the second resistance value between the first test point and the third test point is obtained, and then when the second resistance value is greater than the first threshold, it is determined that the connectivity between the first test point and the third test point in the power distribution network is abnormal, that is, the connectivity between the power pin of the external power supply and the power pin of the second logic unit is abnormal.

[0155] Step 208: When the second resistance value is greater than the first threshold, determine that the connectivity between the first test point and the third test point in the power distribution network is abnormal.

[0156] In some embodiments, when the second resistance value is greater than the first threshold and the second resistance value is less than or equal to the second threshold, it is determined that the connectivity between the first test point and the third test point in the power distribution network is poor; when the second resistance value is greater than the second threshold, it is determined that the first test point and the second test point in the power distribution network are disconnected.

[0157] For example, the first threshold is 1 ohm, the second threshold is 3 ohms, and the second resistance value is 2 ohms. Since the second resistance value is greater than the first threshold and the second resistance value is less than or equal to the second threshold, it is determined that the connectivity between the first test point and the third test point in the power distribution network is poor.

[0158] For another example, the first threshold is 1 ohm, the second threshold is 3 ohms, and the second resistance value is 9 ohms. Since the second resistance value is greater than the second threshold, it is determined that the first test point and the third test point in the power distribution network are disconnected.

[0159] In an embodiment of the present application, when the second resistance value is greater than the first threshold value and the second resistance value is less than or equal to the second threshold value, the current input by the external power supply to the third test point through the first test point is too small to meet the power demand of the second logic unit, and the second logic unit operates abnormally. At this time, it is determined that the connectivity between the first test point and the third test point in the distribution network is poor, so that the staff can discover and handle it in time; when the second resistance value is greater than the second threshold value, the current input by the external power supply to the third test point through the first test point is 0, and the second logic unit stops working. At this time, it is determined that the first test point and the third test point in the distribution network are disconnected, so that the staff can discover and handle it in time.

[0160] In some embodiments, when the second resistance value is less than or equal to the first threshold, it is determined that the connectivity between the first test point and the third test point in the power distribution network is normal.

[0161] By executing steps 206 to 208 , it is possible to check the connectivity between the external power supply and the second logic unit in the power distribution network.

[0162] Optionally, in some embodiments, before step 207, the method further includes the following steps:

[0163] Step 209: electrically connect the plurality of third test points provided on the power pins of the same second logic unit to each other.

[0164] In some embodiments, each third test point of the power supply pin of the same second logic unit is electrically connected to each other using a resistance-free wire.

[0165] In an embodiment of the present application, by electrically connecting each third test point of the power pin of the same second logic unit to each other, so that the first resistance value between each third test point set at the power pin of the same second logic unit and the first test point is equal, each third test point of the power pin of the same second logic unit corresponds to a second node, so that each third test point is treated as a second node, the third resistance value between the second node and the first node is calculated once, and the third resistance value is determined as the second resistance value between each third test point of the power pin of the same second logic unit and the first test point, without the need for multiple calculations, that is, there is no need to calculate the second resistance value between each third test point of the power pin of the same second logic unit and the first test point.

[0166] In some embodiments, a result list and a visual distribution map are generated, i.e., a correspondence list of the first resistance value, the conductive layer information, the conductive line information, the coordinate information of the first test point, and the coordinate information of the second test point between the first test point and the second test point is generated, wherein the first resistance values in the correspondence list are sorted in a preset order, for example, the first resistance values are sorted in descending order. For the case where each third test point of the power pin of the same second logic unit is electrically connected to each other, a correspondence list of the first resistance values between the power pin of the second logic unit, the first test point, and the third test point is generated, wherein the second resistance values in the correspondence list are sorted in a preset order, for example, the second resistance values are sorted in descending order. In addition, based on the correspondence list, a schematic diagram of the power distribution network including the first test point, the second test point, and the third test point is generated, i.e., a visual distribution map, wherein the first resistance value is identified by color at the second test point, and the second resistance value is identified by color at the third test point, wherein the color has a different brightness than the first resistance value, and the color has a different brightness than the second resistance value, for example, red is used for a larger resistance value and blue is used for a smaller resistance value.

[0167] Reference Figure 7 In some embodiments, the inspection process of the power distribution network includes: X1. During the design phase of the power distribution network, a plurality of first test points are set on the first conductive layer of the power distribution network; X2. A plurality of second test points are set on the second conductive layer of the power distribution network; X3. A first resistance value between the first test point and the second test point is obtained; X4. A result list and a visual distribution diagram are generated. The specific process is similar to the above and will not be repeated here.

[0168] In the related art, an automatic layout and routing tool is used to perform a structural check on the power distribution network to see if there are any missing conductive vias, that is, a graphical calculation check is performed on whether there are any conductive vias at the intersections of the conductive lines of adjacent conductive layers. However, it is impossible to check for missing conductive lines or other conductive via structures, such as missing conductive lines and conductive vias in the gaps between hard macro units or between hard macro units and voltage domain boundaries. Therefore, the automatic layout and routing tool cannot check: abnormal connectivity of the power distribution network caused by missing conductive lines or other conductive via structures; and after the design stage of the power distribution network, after the chip design is completed, the connectivity of the power distribution network is checked through voltage drop analysis and other methods. However, at this time, the chip is close to tape-out, and adjusting the power distribution network requires readjusting the logic units of the chip, that is, redesigning the chip, resulting in reduced chip design efficiency.

[0169] In an embodiment of the present application, during the design stage of the power distribution network, a plurality of first test points are set on the first conductive layer of the power distribution network, and a plurality of second test points are set on the second conductive layer of the power distribution network, wherein the first test point is used to be electrically connected to the power pin of the external power supply, the second test point is used to be electrically connected to the power pin of the first logic unit, and the power pin of the first logic unit is used to be electrically connected to the power pin of the external power supply, and then a first resistance value between the first test point and the second test point is obtained, and then when the first resistance value is greater than a first threshold value, it is determined that the connectivity between the first test point and the second test point in the power distribution network is abnormal, so as to provide information for staff and The problem is known and processed in time, thereby realizing that the connectivity of the power distribution network can be checked in the design phase of the power distribution network, and abnormal connectivity of the power distribution network caused by the lack of conductive wires or conductive via structures can be discovered in time, and connectivity problems missed by graphic calculation checks can be discovered. Moreover, since the inspection is carried out in the design phase of the power distribution network, after the abnormal connectivity of the power distribution network is detected, there is no need to readjust the logic unit of the chip, that is, there is no need to redesign the chip, and the power distribution network can be flexibly adjusted to restore the connectivity of the power distribution network to normal, thereby improving the design efficiency of the chip. In addition, the embodiment of the present application can detect the problem that there is no problem with the voltage drop but the connectivity of the power distribution network is poor.

[0170] To sum up, in an embodiment of the present application, during the design stage of the distribution network, multiple first test points are set on the first conductive layer of the distribution network, and multiple second test points are set on the second conductive layer of the distribution network, wherein the first test point is used to electrically connect to the power pin of the external power supply, the second test point is used to electrically connect to the power pin of the first logic unit, and the power pin of the first logic unit is used to electrically connect to the power pin of the external power supply, and then the first resistance value between the first test point and the second test point is obtained, and then when the first resistance value is greater than the first threshold value, it is determined that the connectivity between the first test point and the second test point in the distribution network is abnormal, so that the staff can be informed and handled in time, thereby realizing the connectivity inspection of the distribution network during the design stage of the distribution network.

[0171] Figure 8 This is a block diagram of a power distribution network inspection device provided by an embodiment of the present application, such as Figure 8 As shown, the device 300 includes:

[0172] A first setting module 301 is configured to, during a design phase of the power distribution network, set a plurality of first test points on a first conductive layer of the power distribution network and a plurality of second test points on a second conductive layer of the power distribution network; the first test points are configured to be electrically connected to power pins of an external power supply, and the second test points are configured to be electrically connected to power pins of a first logic unit; the power pins of the first logic unit are configured to be electrically connected to power pins of the external power supply;

[0173] A first obtaining module 302 is configured to obtain a first resistance value between the first test point and the second test point;

[0174] The first determining module 303 is configured to determine that the connectivity between the first test point and the second test point in the power distribution network is abnormal when the first resistance value is greater than a first threshold.

[0175] Optionally, the conductive layer includes a plurality of conductive lines; and the first setting module 301 includes:

[0176] The first setting submodule is configured to set at least one first test point on a conductive line of the first conductive layer that is electrically connected to a power pin of the external power supply.

[0177] Optionally, the first setting submodule includes:

[0178] The first setting unit is configured to set a plurality of the first test points in an array on the conductive line electrically connected to the power pin of the external power supply.

[0179] Optionally, a plurality of power connection parts are provided on the first conductive layer, and the power connection parts are used to be electrically connected to the power pins of the external power supply; the first setting module 301 includes:

[0180] The second setting submodule is configured to set at least one of the first test points on the power connection portion.

[0181] Optionally, the second setting submodule includes:

[0182] The second setting unit is configured to set a plurality of the first test points in an array on the power connection portion.

[0183] Optionally, the first setting module 301 includes:

[0184] The third setting submodule is configured to set at least one second test point on a conductive line of the second conductive layer that is electrically connected to a power pin of the first logic unit.

[0185] Optionally, the third setting submodule includes:

[0186] The third setting unit is configured to set a plurality of the second test points in an array on the conductive line electrically connected to the power pin of the first logic unit.

[0187] Optionally, the apparatus 300 further includes:

[0188] The first processing module is configured to electrically connect each of the first test points electrically connected to a power pin of the same external power supply before obtaining the first resistance value between the first test point and the second test point.

[0189] Optionally, the first obtaining module 302 includes:

[0190] a first acquisition submodule, configured to acquire resistance information of the power distribution network and generate a resistance network based on the resistance information; the resistance network includes a plurality of first nodes and a plurality of second nodes; the first test point has a corresponding first node, and the second test point has a corresponding second node;

[0191] A second acquisition submodule is configured to obtain a resistance equation of the resistor network according to Kirchhoff's law and Ohm's law;

[0192] a third obtaining submodule, configured to solve the resistance equation to obtain a third resistance value between the first node and the second node;

[0193] The determining submodule is configured to determine a third resistance value between a first node corresponding to the first test point and a second node corresponding to the second test point as the first resistance value.

[0194] Optionally, the first determining module 303 includes:

[0195] a first determining submodule, configured to determine that connectivity between the first test point and the second test point in the power distribution network is poor when the first resistance value is greater than the first threshold and the first resistance value is less than or equal to a second threshold; and the first threshold is less than the second threshold;

[0196] The second determining submodule is configured to determine that the first test point and the second test point in the power distribution network are disconnected when the first resistance value is greater than the second threshold value.

[0197] Optionally, a second logic unit is provided in the power distribution network, and a power pin of the second logic unit is used to be electrically connected to a power pin of the external power supply; the device 300 further includes:

[0198] A second setting module is configured to set at least one third test point on a power pin of the second logic unit;

[0199] A second obtaining module, configured to obtain a second resistance value between the first test point and the third test point;

[0200] The second determining module is configured to determine that the connectivity between the first test point and the third test point in the power distribution network is abnormal when the second resistance value is greater than the first threshold.

[0201] Optionally, the second setting module includes:

[0202] The fourth setting submodule is configured to set at least one third test point in an array on the power pin of the second logic unit.

[0203] Optionally, the apparatus 300 further includes:

[0204] The second processing module is configured to electrically connect a plurality of the third test points provided on the power pins of the same second logic unit to each other before obtaining the second resistance value between the first test point and the third test point.

[0205] Optionally, the second logic unit is a hard macro unit.

[0206] Optionally, the first conductive layer is located at the top of the power distribution network; and the second conductive layer is located at the bottom of the power distribution network.

[0207] The inspection device for the power distribution network in the embodiment of the present application can be a device, or a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. For example, the mobile electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc. The non-mobile electronic device can be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), an ATM, or an kiosks, etc., which are not specifically limited in the embodiment of the present application.

[0208] The inspection device for the power distribution network in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0209] The inspection device for the power distribution network provided in the embodiment of the present application can achieve Figure 1 In order to avoid repetition, the various processes implemented by the inspection device for the power distribution network in the method embodiment will not be described here.

[0210] In an embodiment of the present application, during the design stage of the distribution network, multiple first test points are set on the first conductive layer of the distribution network, and multiple second test points are set on the second conductive layer of the distribution network, wherein the first test point is used to electrically connect to the power pin of the external power supply, the second test point is used to electrically connect to the power pin of the first logic unit, and the power pin of the first logic unit is used to electrically connect to the power pin of the external power supply, and then the first resistance value between the first test point and the second test point is obtained, and then when the first resistance value is greater than the first threshold value, it is determined that the connectivity between the first test point and the second test point in the distribution network is abnormal, so that the staff can be informed and handled in time, thereby realizing the connectivity inspection of the distribution network during the design stage of the distribution network.

[0211] Optionally, an embodiment of the present application also provides an electronic device, including a processor, a memory, and a program or instruction stored in the memory and executable on the processor. When the program or instruction is executed by the processor, the various processes of the above-mentioned distribution network inspection method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, they will not be described here.

[0212] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0213] Figure 9 A schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.

[0214] The electronic device 400 includes but is not limited to components such as a radio frequency unit 401 , a network module 402 , an audio output unit 403 , an input unit 404 , a sensor 405 , a display unit 406 , a user input unit 407 , an interface unit 408 , a memory 409 , and a processor 410 .

[0215] Those skilled in the art will understand that the electronic device 400 may also include a power source (such as a battery) to power each component, and the power source may be logically connected to the processor 410 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system. Figure 9 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be repeated here.

[0216] The processor 410 is configured to, during a design phase of the power distribution network, set a plurality of first test points on a first conductive layer of the power distribution network and a plurality of second test points on a second conductive layer of the power distribution network; the first test points are configured to be electrically connected to power pins of an external power supply, and the second test points are configured to be electrically connected to power pins of a first logic unit; the power pins of the first logic unit are configured to be electrically connected to power pins of the external power supply; and the power distribution network includes a plurality of conductive layers.

[0217] Obtaining a first resistance value between the first test point and the second test point;

[0218] When the first resistance value is greater than a first threshold, it is determined that connectivity between the first test point and the second test point in the power distribution network is abnormal.

[0219] In an embodiment of the present application, during the design stage of the distribution network, multiple first test points are set on the first conductive layer of the distribution network, and multiple second test points are set on the second conductive layer of the distribution network, wherein the first test point is used to electrically connect to the power pin of the external power supply, the second test point is used to electrically connect to the power pin of the first logic unit, and the power pin of the first logic unit is used to electrically connect to the power pin of the external power supply, and then the first resistance value between the first test point and the second test point is obtained, and then when the first resistance value is greater than the first threshold value, it is determined that the connectivity between the first test point and the second test point in the distribution network is abnormal, so that the staff can be informed and handled in time, thereby realizing the connectivity inspection of the distribution network during the design stage of the distribution network.

[0220] Optionally, the conductive layer includes a plurality of conductive lines; the processor 410 is further configured to set at least one of the first test points on the conductive lines of the first conductive layer that are electrically connected to the power pins of the external power supply.

[0221] Optionally, the processor 410 is further configured to set a plurality of the first test points in an array on the conductive line electrically connected to the power pin of the external power supply.

[0222] Optionally, a plurality of power connection parts are provided on the first conductive layer, and the power connection parts are used to be electrically connected to the power pins of the external power supply; the processor 410 is further used to set at least one of the first test points on the power connection parts.

[0223] Optionally, the processor 410 is further configured to set a plurality of the first test points in an array at the power connection portion.

[0224] Optionally, the conductive layer includes a plurality of conductive lines; the processor 410 is further configured to set at least one second test point on a conductive line of the second conductive layer that is electrically connected to a power pin of the first logic unit.

[0225] Optionally, the processor 410 is further configured to set a plurality of second test points in an array on the conductive line electrically connected to the power pin of the first logic unit.

[0226] Optionally, the processor 410 is further configured to electrically connect each of the first test points that are electrically connected to the power pins of the same external power supply to each other.

[0227] Optionally, the processor 410 is further used to obtain resistance information of the power distribution network and generate a resistance network based on the resistance information; the resistance network includes multiple first nodes and multiple second nodes; the first test point has a corresponding first node, and the second test point has a corresponding second node; according to Kirchhoff's law and Ohm's law, a resistance equation of the resistance network is obtained; the resistance equation is solved to obtain a third resistance value between the first node and the second node; and the third resistance value between the first node corresponding to the first test point and the second node corresponding to the second test point is determined as the first resistance value.

[0228] Optionally, the processor 410 is further used to determine that the connectivity between the first test point and the second test point in the power distribution network is poor when the first resistance value is greater than the first threshold and the first resistance value is less than or equal to a second threshold; the first threshold is less than the second threshold; and when the first resistance value is greater than the second threshold, determine that the first test point and the second test point in the power distribution network are disconnected.

[0229] Optionally, a second logic unit is provided in the power distribution network, and a power pin of the second logic unit is used to be electrically connected to a power pin of the external power supply; the processor 410 is also used to set at least one third test point at the power pin of the second logic unit; obtain a second resistance value between the first test point and the third test point; and when the second resistance value is greater than the first threshold, determine that the connectivity between the first test point and the third test point in the power distribution network is abnormal.

[0230] Optionally, the processor 410 is further configured to set at least one third test point in an array form on the power pin of the second logic unit.

[0231] Optionally, the processor 410 is further configured to electrically connect a plurality of the third test points provided on the power pins of the same second logic unit to each other.

[0232] Optionally, the second logic unit is a hard macro unit.

[0233] Optionally, the first conductive layer is located at the top of the power distribution network; and the second conductive layer is located at the bottom of the power distribution network.

[0234] In an embodiment of the present application, during the design stage of the distribution network, multiple first test points are set on the first conductive layer of the distribution network, and multiple second test points are set on the second conductive layer of the distribution network, wherein the first test point is used to electrically connect to the power pin of the external power supply, the second test point is used to electrically connect to the power pin of the first logic unit, and the power pin of the first logic unit is used to electrically connect to the power pin of the external power supply, and then the first resistance value between the first test point and the second test point is obtained, and then when the first resistance value is greater than the first threshold value, it is determined that the connectivity between the first test point and the second test point in the distribution network is abnormal, so that the staff can be informed and handled in time, thereby realizing the connectivity inspection of the distribution network during the design stage of the distribution network.

[0235] It should be understood that in an embodiment of the present application, the input unit 404 may include a graphics processing unit (GPU) 4041 and a microphone 4042, and the graphics processor 4041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 406 may include a display panel 4061, and the display panel 4061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 407 includes a touch panel 4071 and at least one of other input devices 4072. The touch panel 4071 is also called a touch screen. The touch panel 4071 may include two parts: a touch detection device and a touch controller. Other input devices 4072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and an operating stick, which will not be repeated here.

[0236] The memory 409 can be used to store software programs and various data. The memory 409 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, applications or instructions required for at least one function (such as a sound playback function, an image playback function, etc.). In addition, the memory 409 may include a volatile memory or a non-volatile memory, or the memory 409 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAM bus random access memory (DRRAM). The memory 409 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0237] Processor 410 may include one or more processing units. Optionally, processor 410 integrates an application processor and a modem processor. The application processor primarily handles operations related to the operating system, user interface, and application programs, while the modem processor primarily processes wireless communication signals, such as a baseband processor. It is understood that the modem processor may not be integrated into processor 410.

[0238] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned distribution network inspection method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0239] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0240] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned distribution network inspection method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0241] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0242] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0243] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A method for inspecting a power distribution network, characterized in that: The power distribution network includes a plurality of conductive layers, and the method includes: During the design phase of the power distribution network, a plurality of first test points are provided on a first conductive layer of the power distribution network, and a plurality of second test points are provided on a second conductive layer of the power distribution network; the first test points are used to be electrically connected to power pins of an external power supply, and the second test points are used to be electrically connected to power pins of a first logic unit; the power pins of the first logic unit are used to be electrically connected to power pins of the external power supply; Obtaining a first resistance value between the first test point and the second test point; When the first resistance value is greater than a first threshold, it is determined that connectivity between the first test point and the second test point in the power distribution network is abnormal.

2. The method according to claim 1, characterized in that The conductive layer includes a plurality of conductive lines; and a plurality of first test points are set on the first conductive layer of the power distribution network, including: At least one first test point is provided on a conductive line of the first conductive layer for electrically connecting to a power pin of the external power supply.

3. The method according to claim 2, characterized in that The conductive line on the first conductive layer for electrically connecting to the power pin of the external power supply is provided with at least one first test point, including: A plurality of first test points are arranged in an array on the conductive line for electrically connecting to the power pin of the external power source.

4. The method according to claim 1, wherein A plurality of power connection parts are provided on the first conductive layer, and the power connection parts are used to be electrically connected to the power pins of the external power supply; The setting of a plurality of first test points on the first conductive layer of the power distribution network comprises: At least one first test point is provided on the power connection portion.

5. The method according to claim 4, characterized in that The providing at least one first test point on the power connection portion includes: A plurality of first test points are arranged in an array on the power connection portion.

6. The method according to claim 1, characterized in that The conductive layer includes a plurality of conductive lines; and the second conductive layer of the power distribution network is provided with a plurality of second test points, including: At least one second test point is provided on a conductive line of the second conductive layer for electrically connecting to a power pin of the first logic unit.

7. The method according to claim 6, characterized in that The conductive line on the second conductive layer for electrically connecting to the power pin of the first logic unit is provided with at least one second test point, including: A plurality of second test points are arranged in an array on the conductive line electrically connected to the power pin of the first logic unit.

8. The method according to claim 1, characterized in that Before obtaining the first resistance value between the first test point and the second test point, the method further includes: Each of the first test points for electrically connecting to the power pin of the same external power source is electrically connected to each other.

9. The method according to claim 1, characterized in that The obtaining of a first resistance value between the first test point and the second test point includes: Obtaining resistance information of the power distribution network and generating a resistance network based on the resistance information; the resistance network includes a plurality of first nodes and a plurality of second nodes; the first test point has a corresponding first node, and the second test point has a corresponding second node; Obtaining a resistance equation of the resistor network according to Kirchhoff's law and Ohm's law; Solving the resistance equation to obtain a third resistance value between the first node and the second node; A third resistance value between a first node corresponding to the first test point and a second node corresponding to the second test point is determined as the first resistance value.

10. The method according to claim 1, characterized in that The determining, when the first resistance value is greater than a first threshold, that connectivity between the first test point and the second test point in the power distribution network is abnormal includes: determining that connectivity between the first test point and the second test point in the power distribution network is poor when the first resistance value is greater than the first threshold and the first resistance value is less than or equal to a second threshold; and the first threshold is less than the second threshold; When the first resistance value is greater than the second threshold, it is determined that the first test point and the second test point in the power distribution network are disconnected.

11. The method according to claim 1, characterized in that A second logic unit is provided in the power distribution network, and a power pin of the second logic unit is used to be electrically connected to a power pin of the external power supply; the method further includes: Setting at least one third test point on the power pin of the second logic unit; Obtaining a second resistance value between the first test point and the third test point; When the second resistance value is greater than the first threshold, it is determined that connectivity between the first test point and the third test point in the power distribution network is abnormal.

12. The method according to claim 11, characterized in that The step of setting at least one third test point on the power pin of the second logic unit includes: At least one third test point is arranged in an array at the power pin of the second logic unit.

13. The method according to claim 11, characterized in that Before obtaining the second resistance value between the first test point and the third test point, the method further includes: The plurality of third test points provided at the power supply pins of the same second logic unit are electrically connected to each other.

14. The method according to claim 11, characterized in that The second logic unit is a hard macro unit.

15. The method according to any one of claims 1 to 14, characterized in that The first conductive layer is located at the top of the power distribution network; the second conductive layer is located at the bottom of the power distribution network.

16. An inspection device for a power distribution network, characterized in that: The device comprises: a first setting module, configured to set, during a design phase of the power distribution network, a plurality of first test points on a first conductive layer of the power distribution network and a plurality of second test points on a second conductive layer of the power distribution network; the first test points being configured to be electrically connected to power pins of an external power supply, and the second test points being configured to be electrically connected to power pins of a first logic unit; and the power pins of the first logic unit being configured to be electrically connected to power pins of the external power supply; A first obtaining module, configured to obtain a first resistance value between the first test point and the second test point; The first determining module is configured to determine that connectivity between the first test point and the second test point in the power distribution network is abnormal when the first resistance value is greater than a first threshold.

17. An electronic device, characterized in that: The method comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the method for inspecting a power distribution network as claimed in any one of claims 1 to 15.

18. A readable storage medium, characterized in that The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the method for inspecting a power distribution network according to any one of claims 1 to 15 are implemented.

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