Memory device and operating method of memory device

Abstract

A memory device and an operating method of the memory device are disclosed. The memory device includes a memory cell array, a voltage generator, and control logic. The memory cell array has a plurality of active blocks, each including a plurality of memory cells operating at the same clock frequency. The voltage generator supplies an operating voltage to the plurality of memory cells. The control logic controls independent memory operations for each active block. The voltage generator includes a pump circuit that varies a clock frequency for generating the operating voltage in accordance with a number of active blocks that are activated during the independent memory operation.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2024-0022309 filed on February 16, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a memory device and a method for operating the memory device. Background Art

[0003] For example, semiconductor memory can be categorized as either volatile memory or nonvolatile memory. Generally, volatile memory (e.g., dynamic random access memory (DRAM) or static random access memory (SRAM)) can exhibit faster read and / or write speeds compared to nonvolatile memory. However, when the power applied to the volatile memory is turned off, the data stored in the volatile memory may disappear. In contrast, nonvolatile memory can retain data even when the power is turned off. Summary of the Invention

[0004] Example embodiments of the present disclosure provide a memory device that can reduce current consumption in a peripheral circuit by changing a clock frequency according to the number of active blocks to be activated, and a memory device including the memory device.

[0005] Example embodiments of the present disclosure described herein relate to a semiconductor memory device, and more particularly, to a memory device whose clock frequency varies according to the number of active blocks to be activated and a memory device including the same.

[0006] A representative example of nonvolatile memory is flash memory. Flash memory can store two or more bits of multi-bit data in a single memory cell. Depending on the threshold voltage distribution, flash memory can have at least one erased state and multiple programmed (e.g., written) states.

[0007] A flash memory's memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. The flash memory may provide an operating voltage to a word line during operations such as programming, reading, and erasing. The flash memory may generate the operating voltage using a clock signal from a pump circuit.

[0008] Flash memory uses a clock signal with a single clock frequency to generate operating voltage. Flash memory can consume significant current in peripheral circuits. For example, the clock frequency is set based on the maximum number of memory blocks that can be activated simultaneously. However, if only a portion of the memory blocks are activated, excessive current may be consumed unnecessarily.

[0009] According to an embodiment, a memory device includes: a memory cell array having a plurality of active blocks, each active block including a plurality of memory cells operating at the same clock frequency; a voltage generator configured to provide an operating voltage to the plurality of memory cells; and control logic configured to control independent memory operations for each active block. The voltage generator includes a pump circuit configured to vary the clock frequency used to generate the operating voltage depending on the number of active blocks activated during the independent memory operations.

[0010] According to an embodiment, a memory device includes: a first stack in which first memory cells are stacked in a direction perpendicular to a substrate; and a second stack in which second memory cells are stacked on the first stack in a direction perpendicular to the substrate. The first memory cells and the second memory cells are divided into a plurality of active blocks that operate at the same clock frequency. The memory device performs an independent memory operation for each active block, and changes the clock frequency used to perform the independent memory operation depending on the number of active blocks activated during the independent memory operation.

[0011] According to an embodiment, a method for operating a memory device includes: a memory cell array having a plurality of active blocks, each active block including a plurality of memory cells; a voltage generator configured to provide an operating voltage to the plurality of memory cells; and control logic configured to control an independent memory operation for each active block. The method includes: counting the number of active blocks activated during the independent memory operation; changing the frequency of a clock signal used to generate the operating voltage according to the counted number of active blocks; and providing the clock signal having the changed frequency to the voltage generator. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0013] Figure 1 is a block diagram illustrating an example embodiment of a storage device according to the present disclosure.

[0014] Figure 2 It shows Figure 1 A block diagram of an example implementation of a memory device is shown in FIG.

[0015] Figure 3 It shows Figure 2 1 is a circuit diagram of an example embodiment of a memory block BLK1 of a memory cell array shown in FIG.

[0016] Figure 4is shown by the first string selection line SSL1 from Figure 3 FIG. 4 is a circuit diagram of a cell string selected from among the cell strings of the memory block BLK1 shown in FIG.

[0017] Figure 5 It shows Figure 2 The block diagram of the pump circuit is shown in .

[0018] Figure 6 It shows Figure 5 The circuit diagram of the first stage pump is shown in FIG.

[0019] Figure 7 It shows Figure 5 A block diagram of an example implementation of a mode selector is shown in FIG.

[0020] Figure 8 It shows Figure 7 0004 is a timing diagram of an example implementation of the clock frequency of the clock generator shown in FIG.

[0021] Figure 9 is a graph illustrating an example embodiment showing a clock frequency that varies according to the number of activated active blocks.

[0022] Figure 10 and Figure 11 is a graph showing an average amount of operating current in a peripheral circuit according to a mode change.

[0023] Figure 12 is a block diagram illustrating an example embodiment of a storage device according to the present disclosure.

[0024] Figure 13 It shows Figure 12 A flow chart of an example implementation of a method of operating a pump scheduler is shown in FIG.

[0025] Figure 14 is a diagram illustrating an example embodiment of a flash memory having a multi-stack structure.

[0026] Figure 15 and Figure 16 It is shown in Figure 14 A conceptual diagram of an example embodiment of operation in a third mode in a second stack of a flash memory having a multi-stack structure is shown in FIG.

[0027] Figure 17 is a block diagram illustrating an example in which a storage device according to an example embodiment of the present disclosure is implemented using a solid state drive (SSD). DETAILED DESCRIPTION

[0028] Hereinafter, example embodiments of the present disclosure will be described in detail and clearly to the extent that a person having ordinary skill in the art can easily implement the example embodiments of the present disclosure.

[0029] Figure 1 1 is a block diagram illustrating an example embodiment of a storage device according to the present disclosure. Storage device 1000 may be a flash memory storage device based on flash memory. For example, storage device 1000 may be implemented as a solid state drive (SSD), universal flash storage (UFS), a memory card, etc.

[0030] Reference Figure 1 , the memory device 1000 may include a memory device 1100 and a memory controller 1200. The memory device 1100 may receive an input / output signal IO from the memory controller 1200 via an input / output line, a control signal CTRL via a control line, and external power PWR via a power line. The memory device 1000 may store data in the memory device 1100 under the control of the memory controller 1200.

[0031] The memory device 1100 may include a memory cell array 1110 and a peripheral circuit 1115. The memory cell array 1110 may have a vertical 3D structure. The memory cell array 1110 may include a plurality of memory cells. Multi-bit data may be stored in each memory cell.

[0032] In terms of design layout structure, the memory cell array 1110 may be located (eg, disposed) next to or above the peripheral circuit 1115. A structure in which the memory cell array 1110 is located above the peripheral circuit 1115 may be referred to as a cell-on-periphery (COP) structure.

[0033] The memory cell array 1110 may be manufactured as a separate chip from the peripheral circuit 1115. The upper chip including the memory cell array 1110 and the lower chip including the peripheral circuit 1115 may be connected to each other by a bonding method. Such a structure may be referred to as a chip-to-chip (C2C) structure.

[0034] The peripheral circuit 1115 may include analog circuits and / or digital circuits required to store or read data in the memory cell array 1110. The peripheral circuit 1115 may receive external power PWR through a power line and generate various levels of internal power.

[0035] The peripheral circuit 1115 may receive commands, addresses, and / or data from the memory controller 1200 through input / output lines. The peripheral circuit 1115 may store data in the memory cell array 1110 according to the control signal CTRL. Alternatively or additionally, the peripheral circuit 1115 may read data stored in the memory cell array 1110 and provide the read data to the memory controller 1200.

[0036] The peripheral circuit 1115 may include a pump circuit 2000. The pump circuit 2000 may include a plurality of stages of pumps. The pump circuit 2000 may generate a desired operating voltage by sequentially operating the plurality of stages of pumps from an output terminal according to a clock signal.

[0037] The memory controller 1200 may include a pump scheduler 2001. The pump scheduler 2001 may include a command queue and may calculate the amount of operating current required to drive the memory device 1100 (e.g., peripheral circuits of the memory device 1100) based on commands stored in the command queue. The pump scheduler 2001 may compare the amount of operating current with a threshold current and change the clock frequency of a clock signal generated in the pump circuit 2000 based on the comparison result.

[0038] Figure 2 It shows Figure 1 A block diagram of an example embodiment of a memory device is shown in FIG. Figure 2 , the memory device 1100 may include a memory cell array 1110 and a peripheral circuit 1115 (see Figure 1 The peripheral circuit 1115 may include an address (ADDR) decoder 1120 , a page buffer circuit 1130 , an input / output (I / O) circuit 1140 , a voltage generator 1150 , and control logic 1160 .

[0039] Memory cell array 1110 may include a plurality of active blocks (Active BLK1 to Active BLKn). Here, an active block refers to a group of memory cells operating at the same clock frequency. For example, an active block may be a mat or plane separated in the layout structure of memory cell array 1110.

[0040] Each active block may include multiple memory blocks. For example, the first active block (Active BLK1) may include the first to p-th memory blocks (BLK1 to BLKp). Each memory block may include multiple pages. Each page may include multiple memory cells. Each memory cell may store multi-bit data (e.g., two or more bits). Each memory block may correspond to an erase unit, and each page may correspond to a read unit and / or a write unit.

[0041] Memory cell array 1110 may be formed perpendicular to the substrate. Gate electrode layers and insulating layers may be alternately deposited on the substrate. Each memory block (e.g., BLK1) may be connected to one or more string select lines SSL, multiple word lines WL1 to WLm, and one or more ground select lines GSL. WLk is the selected word line sWL, and the remaining word lines (WL1 to WLk-1, WLk+1 to WLm) are unselected word lines uWL.

[0042] The address decoder 1120 can be connected to the memory cell array 1110 through the string selection line SSL and the ground selection line GSL and the word lines WL1 to WLm. The address decoder 1120 can select a word line during a program operation or a read operation. The address decoder 1120 can receive a word line voltage VWL from the voltage generator 1150 and provide a program voltage or a read voltage to the selected word line.

[0043] The page buffer circuit 1130 may be connected to the memory cell array 1110 via bit lines BL1 to BLz. The page buffer circuit 1130 may temporarily store data to be stored in the memory cell array 1110 or data read from the memory cell array 1110. The page buffer circuit 1130 may include page buffers PB1 to PBz connected to corresponding bit lines. Each page buffer may include a plurality of latches for storing or reading multi-bit data.

[0044] The input / output circuit 1140 may be internally connected to the page buffer circuit 1130 through a data line, and externally connected to the memory controller 1200 through input / output lines IO1 to IOn (refer to FIG. Figure 1 ). The input / output circuit 1140 may receive program data from the memory controller 1200 during a program operation. In addition, the input / output circuit 1140 may provide data read from the memory cell array 1110 to the memory controller 1200 during a read operation.

[0045] The voltage generator 1150 may receive internal power from the control logic 1160 and generate a word line voltage VWL required for reading or writing data. The word line voltage VWL may be provided to a selected word line (sWL) or an unselected word line (uWL) through the address decoder 1120 .

[0046] Voltage generator 1150 may include a word line voltage generator 1155. Word line voltage generator 1155 may include a program voltage generator and a pass voltage generator. The program voltage generator may generate a program voltage Vpgm provided to a selected word line during a program operation. The pass voltage generator may generate a pass voltage Vpass provided to the selected word line and unselected word lines.

[0047] The word line voltage generator 1155 may include a read voltage generator and a read pass voltage generator. The read voltage generator may generate a selected read voltage provided to a selected word line during a read operation. The read pass voltage generator may generate a read pass voltage provided to unselected word lines. The read pass voltage may be a voltage sufficient to turn on memory cells connected to unselected word lines during a read operation.

[0048] The voltage generator 1150 may further include a pump circuit 2000. The pump circuit 2000 may be operated by receiving a pump enable signal (EN_PUMP) from the control logic 1160. The pump circuit 2000 may receive a power supply voltage and provide an output voltage (Vout) to the word line voltage generator 1155. The pump circuit 2000 may change the clock frequency of a clock signal used to generate the output voltage Vout according to the number of active blocks activated during operation of the memory device 1100.

[0049] The control logic 1160 may control operations (such as reading, writing, and erasing) of the memory device 1100 using a command CMD, an address ADDR, external power PWR, and a control signal CTRL provided from the memory controller 1200. The control logic 1160 may provide an active block use signal (ACT) and a pump enable signal (EN_PUMP) to the pump circuit 2000. The control logic 1160 may generate operating voltages required for read operations, write operations, and erase operations.

[0050] The control logic 1160 can be configured to control an independent memory operation for each active block. Here, an independent memory operation can be an independent read operation, an independent program operation, or an independent erase operation performed for each active block (e.g., between activated active blocks). An independent read operation can be an operation that supports an independent read operation for each active block to provide high read performance. The pump circuit 2000 can change the clock frequency of the clock signal used to generate the operating voltage according to the number of active blocks activated during the independent read operation.

[0051] Figure 3 It shows Figure 2 1 is a circuit diagram of an example embodiment of a memory block BLK1 of a memory cell array shown in FIG. Figure 3 In the memory block BLK1, a plurality of cell strings STR11 to STR8z may be formed between bit lines BL1 to BLz and a common source line CSL. Each cell string includes a string selection transistor SST, a plurality of memory cells MC1 to MCm, and a ground selection transistor GST.

[0052] String selection transistors SST may be connected to string selection lines SSL1 to SSL8. Ground selection transistors GST may be connected to ground selection lines GSL1 to GSL8. String selection transistors SST may be connected to bit lines BL1 to BLz, and ground selection transistors GST may be connected to a common source line CSL.

[0053] The first to m-th word lines WL1 to WLm may be connected to the plurality of memory cells MC1 to MCm in a row direction. The first to z-th bit lines BL1 to BLz may be connected to the plurality of memory cells MC1 to MCm in a column direction. The first to z-th page buffers PB1 to PBz may be connected to the first to z-th bit lines BL1 to BLz.

[0054] The first word line WL1 may be positioned above the first to eighth ground selection lines GSL1 to GSL8. First memory cells MC1 positioned at the same height from the substrate may be connected to the first word line WL1. The mth word line WLm may be positioned below the first to eighth string selection lines SSL1 to SSL8. The mth memory cell MCm positioned at the same height from the substrate may be connected to the mth word line WLm. Similarly, the second to (m-1)th memory cells MC2 to MCm-1, positioned at the same height from the substrate, may be connected to the second to (m-1)th word lines WL2 to WLm-1, respectively.

[0055] Figure 4 is shown by the first string selection line SSL1 from Figure 3 FIG1 is a circuit diagram of a selected cell string among the cell strings of the memory block BLK1 shown in FIG1. The 11th to 1zth cell strings STR11 to STR1z may be selected via a first string selection line SSL1. The 11th to 1zth cell strings STR11 to STR1z may be connected to the first to zth bit lines BL1 to BLz, respectively. The first to zth page buffers PB1 to PBz may be connected to the first to zth bit lines BL1 to BLz, respectively.

[0056] The eleventh cell string STR11 may be connected to a first bit line BL1 and a common source line CSL. The eleventh cell string STR11 may include a string selection transistor SST selected by a first string selection line SSL1, first to mth memory cells MC1 to MCm connected to first to mth word lines WL1 to WLm, and a ground selection transistor GST selected by a first ground selection line GSL1. The twelfth cell string STR12 may be connected to a second bit line BL2 and a common source line CSL. The 1zth cell string STR1z may be connected to a zth bit line BLz and a common source line CSL.

[0057] The first word line WL1 and the mth word line WLm may be edge word lines (edge WL). The second word line WL2 and the (m-1)th word line WLm-1 may be edge adjacent word lines. The kth word line WLk may be the selected word line sWL. The (k-1)th word line WLk-1 and the (k+1)th word line WLk+1 may be adjacent word lines adjacent to the selected word line. If the kth word line WLk is the selected word line sWL, the remaining word lines WL1 to WLk-1 and WLk+1 to WLm may be unselected word lines uWL.

[0058] The first memory cell MC1 and the mth memory cell MCm may be edge memory cells. The second memory cell MC2 and the (m-1)th memory cell MCm-1 may be edge-adjacent memory cells. The kth memory cell MCk may be the selected memory cell sMC. The (k-1)th memory cell MCk-1 and the (k+1)th memory cell MCk+1 may be memory cells adjacent to the selected memory cell (neighboring MCs). If the kth memory cell MCk is the selected memory cell sMC, the remaining memory cells MC1 to MCk-1 and MCk+1 to MCm may be unselected memory cells uMC.

[0059] A group of memory cells selected by one string selection line and connected to one word line can be a page. For example, memory cells selected by the first string selection line SSL1 and connected to the k-th word line WLk can be a page. For example, eight pages can be configured on the k-th word line WLk. Among the eight pages, the page connected to the first string selection line SSL1 is a selected page, and the pages connected to the second to eighth string selection lines SSL2 to SSL8 are unselected pages.

[0060] Figure 5 It shows Figure 2 The block diagram of the pump circuit is shown in FIG. Figure 5 The pump circuit 2000 may include first to eighth stage pumps 2100 to 2800 and a stage controller 2900 . The stage controller 2900 may include a mode selector 2910 and a clock (CLK) generator 2920 .

[0061] The clock generator 2920 may receive the mode signal (MOD) from the mode selector 2910 and the pump enable signal (EN_PUMP) from the control logic 1160. The clock generator 2920 may receive the mode signal (MOD) and the pump enable signal (EN_PUMP) and generate the first to eighth stage signals (STG <1> To STG <8> ) and / or the first to eighth clock signals (CLK1 to CLK8). The first to eighth stage pumps 2100 to 2800 may generate an output voltage Vout in response to the stage signal and / or the clock signal from the stage controller 2900.

[0062] The pump circuit 2000 can sequentially drive multiple stages of pumps, starting with the first-stage pump 2100 and continuing through the eighth-stage pump 2800. That is, first, the first-stage pump 2100 can operate in response to the first clock signal CLK1. Next, the second-stage pump 2200 can operate in response to the second clock signal CLK2. As described above, the seventh-stage pump 2700 can operate in response to the seventh clock signal CLK7. And finally, the eighth-stage pump 2800 can operate in response to the eighth clock signal CLK8. Here, the first through eighth clock signals CLK1 through CLK8 can be a single clock signal having the same frequency. That is, a single clock signal can be simultaneously provided to the first through eighth pump circuits (PUMP1 through PUMP8).

[0063] The pump circuit 2000 may generate a first level output voltage Vout by using a first stage pump 2100. The first stage pump 2100 may include a first switch circuit SW1 and a first pump circuit PUMP1. The first switch circuit SW1 may respond to a first stage signal STG <1> The power supply voltage VCC is provided to the first pump node PN1. The first pump circuit PUMP1 may receive the first clock signal CLK1 and may generate an output voltage Vout by using the first pump node power.

[0064] The pump circuit 2000 may generate a second level output voltage Vout by using the first stage pump 2100 and the second stage pump 2200. The second switch circuit SW2 of the second stage pump 2200 may respond to the second stage signal STG <2> The power supply voltage VCC is provided to the second pump node PN2. The second pump circuit PUMP2 can receive the second clock signal CLK2 and can generate the first pump node power by using the second pump node power. The first stage pump 2100 can generate the second level output voltage Vout by using the first pump node power.

[0065] As described above, the pump circuit 2000 can generate the eighth level output voltage Vout by using the first to eighth stage pumps 2100 to 2800. The eighth switch circuit SW8 of the eighth stage pump 2800 can respond to the eighth stage signal STG <8> The power supply voltage VCC is provided to the eighth pump node PN8. The eighth pump circuit PUMP8 may receive the eighth clock signal CLK8 and may generate the seventh pump node power by using the eighth pump node power.

[0066] The seventh-stage pump 2700 may receive the seventh clock signal CLK7 and may generate the sixth pump node power by using the seventh pump node power. As described above, the second-stage pump 2200 may generate the first pump node power by using the second pump node power. The first-stage pump 2100 may generate the output voltage Vout of the eighth level by using the first pump node power.

[0067] The pump circuit 2000 may not necessarily start driving the operation from the first stage pump 2100. In some cases, the pump circuit 2000 may start driving the operation from the second stage pump to the eighth stage pump. For example, the pump circuit 2000 may start driving the operation from the fourth stage pump.

[0068] Figure 6 It shows Figure 5 The circuit diagram of the first stage pump is shown in FIG. Figure 6 , the first-stage pump 2100 may include a first switching circuit SW1 and a first pump circuit PUMP1.

[0069] The first switch circuit SW1 may include a p-type metal oxide semiconductor (PMOS) transistor PM and a depletion type n-type metal oxide semiconductor (NMOS) transistor DN connected between the power supply terminal and the first pump node PN1. An inverter INV may be connected to the gate of the depletion type NMOS transistor DN. The first stage signal STG may be <1> Input to the gate of the PMOS transistor PM and the input terminal of the inverter INV. When the first stage signal STG <1> When at a low level, the power supply voltage VCC may be provided to the first pump circuit PUMP1 through the first switch circuit SW1 .

[0070] The first pump circuit PUMP1 may include a plurality of transistors and a plurality of capacitors. The first NMOS transistor NM1 may be connected between the first pump node PN1 of the first pump circuit PUMP1 and the first node N1. The second NMOS transistor NM2 may be connected between the first pump node PN1 and the second node N2. The first capacitor C1 may be connected to the first node N1, and the first complementary clock signal / CLK1 may be input to the first capacitor C1. The second capacitor C2 may be connected to the second node N2, and the first clock signal CLK1 may be input to the second capacitor C2. The gate of the first NMOS transistor NM1 may be connected to the second node N2, and the gate of the second NMOS transistor NM2 may be connected to the first node N1.

[0071] The first PMOS transistor PM1 may be connected between the output terminal Nout of the first pump circuit PUMP1 and the third node N3. The second PMOS transistor PM2 may be connected between the output terminal Nout and the fourth node N4. The third capacitor C3 may be connected to the third node N3, and the first complementary clock signal / CLK1 may be input to the third capacitor C3. The fourth capacitor C4 may be connected to the fourth node N4, and the first clock signal CLK1 may be input to the fourth capacitor C4. The gate of the first PMOS transistor PM1 may be connected to the fourth node N4, and the gate of the second PMOS transistor PM2 may be connected to the third node N3.

[0072] The third NMOS transistor NM3 may be connected between the first pump node PN1 of the first pump circuit PUMP1 and the fifth node N5. The fourth NMOS transistor NM4 may be connected between the first pump node PN1 and the sixth node N6. The fifth capacitor C5 may be connected to the fifth node N5, and the first clock signal CLK1 may be input to the fifth capacitor C5. The sixth capacitor C6 may be connected to the sixth node N6, and the first complementary clock signal / CLK1 may be input to the sixth capacitor C6. The gate of the third NMOS transistor NM3 may be connected to the first node N1, and the gate of the fourth NMOS transistor NM4 may be connected to the second node N2.

[0073] The third PMOS transistor PM3 may be connected between the output terminal Nout of the first pump circuit PUMP1 and the fifth node N5. The fourth PMOS transistor PM4 may be connected between the output terminal Nout and the sixth node N6. The gate of the third PMOS transistor PM3 may be connected to the third node N3, and the gate of the fourth PMOS transistor PM4 may be connected to the fourth node N4.

[0074] When receiving the high-level first clock signal CLK1 and the low-level first complementary clock signal / CLK1, the first NMOS transistor NM1 and the fourth NMOS transistor NM4 are turned on, and the second NMOS transistor NM2 and the third NMOS transistor NM3 are turned off. In addition, the first PMOS transistor PM1 and the fourth PMOS transistor PM4 are turned off, and the second PMOS transistor PM2 and the third PMOS transistor PM3 are turned on.

[0075] A charge path of the first pump circuit PUMP1 can be formed by the fourth NMOS transistor NM4 and the third PMOS transistor PM3. The charge of the first pump node PN1 can be transferred to the sixth node N6 through the fourth NMOS transistor NM4. In this case, the voltage level of the sixth node N6 can be "L" (Vin1). The charge of the fifth node N5 can be transferred to the output terminal Nout through the third PMOS transistor PM3, and the voltage at the output terminal Nout can be increased. In addition, charge sharing can occur between the fourth capacitor C4, the fifth capacitor C5 and the output capacitor Co. In this case, the voltage levels of the fourth node N4 and the fifth node N5 can be "H" (Vout).

[0076] When receiving the low-level first clock signal CLK1 and the high-level first complementary clock signal / CLK1, the first NMOS transistor NM1 and the fourth NMOS transistor NM4 are turned off, and the second NMOS transistor NM2 and the third NMOS transistor NM3 are turned on. In addition, the first PMOS transistor PM1 and the fourth PMOS transistor PM4 are turned on, and the second PMOS transistor PM2 and the third PMOS transistor PM3 are turned off.

[0077] A charge path of the first pump circuit PUMP1 can be formed by a third NMOS transistor NM3 and a fourth PMOS transistor PM4. The charge of the first pump node PN1 can be transferred to the fifth node N5 through the third NMOS transistor NM3. In this case, the voltage level of the fifth node N5 can be "L" (Vin1). The charge of the sixth node N6 can be transferred to the output terminal Nout through the fourth PMOS transistor PM4, and the voltage at the output terminal Nout can be increased. In addition, charge sharing can occur between the third capacitor C3, the sixth capacitor C6 and the output capacitor Co. In this case, the voltage levels of the third node N3 and the sixth node N6 can be "H" (Vout).

[0078] The first stage pump 2100 may generate an output voltage Vout in this manner. The output voltage Vout may correspond to "Vin1+Vclk." Here, Vin1 may be the first pump node voltage, and Vclk may be the voltage increased by the first pump circuit PUMP1.

[0079] Figure 7 It shows Figure 5 A block diagram of an example embodiment of a mode selector is shown in FIG. Figure 7 , the mode selector 2910 may include an active block counter 2911 and a mode register 2912 .

[0080] The active block counter 2911 may receive the first active block use signal to the nth active block use signal (ACT_USEi, i=1 to n) and count the number of active blocks in use (activated). The active block counter 2911 may count the number of active blocks in use and provide a count signal CNT to the mode register 2912.

[0081] Mode register 2912 may include multiple modes. For example, mode register 2912 may include first to third modes (MOD1 to MOD3). Mode register 2912 may select any one of the first to third modes (MOD1 to MOD3) in response to a mode selection signal SEL_MOD and provide the selected mode signal MOD to clock generator 2920.

[0082] The control logic 1160 of the memory device 1100 (see Figure 2 ) provides a mode selection signal SEL_MOD. When booting up the memory device 1100, a boot code for the mode selection signal stored in the memory cell array 1110 may be uploaded to the control logic 1160. The mode selector 2910 may receive the mode selection signal SEL_MOD provided from the control logic 1160 and select one of the first to third modes (MOD1 to MOD3).

[0083] The clock generator 2920 may receive the mode signal MOD and change the clock frequencies of the first to eighth clock signals (CLK1 to CLK8 ) and provide the changed clock signals (CLK1 to CLK8 ) to the first to eighth pump circuits (PUMP1 to PUMP8 ).

[0084] Figure 8 It shows Figure 7 A timing diagram of an example embodiment of the clock frequency of the clock generator is shown in FIG. Figure 8, the first to eighth clock signals (CLK1 to CLK8) may have first to fourth clock frequencies (F1 to F4), respectively.

[0085] The clock signal may have a first clock frequency F1, which has four cycles in a time interval (T0 to T4). A second clock frequency F2 may have eight cycles. A third clock frequency F3 may have 16 cycles. And a fourth clock frequency F4 may have 32 cycles. That is, the second clock frequency F2 may be twice the first clock frequency F1. The third clock frequency F3 may be twice the second clock frequency F2. And the fourth clock frequency F4 may be twice the third clock frequency F3. Clock generator 2920 may change the clock frequency according to the number of activated active blocks.

[0086] Figure 9 is a graph illustrating an example embodiment showing a clock frequency that varies according to the number of activated active blocks. Figure 9 , one or more of the first to fourth active blocks may be activated.

[0087] In a first time interval (T0 to T1), the first active block may be activated (e.g., the signal Active BLK1 may be low). In a second time interval (T1 to T2), the first and second active blocks may be activated (e.g., the signals Active BLK1 and Active BLK2 may be low). In a third time interval (T2 to T3), the first to third active blocks may be activated (e.g., the signals Active BLK1, Active BLK2, and Active BLK3 may be low). And in a fourth time interval (T3 to T4), the first to fourth active blocks may be activated (e.g., all four signals Active BLK1, Active BLK2, Active BLK3, and Active BLK4 may be low). The active block usage rate may be 25% in the first time interval (T0 to T1), 50% in the second time interval (T1 to T2), 75% in the third time interval (T2 to T3), and 100% in the fourth time interval.

[0088] In the fifth time interval (T4 to T5), the second to fourth active blocks may be activated (for example, the signals ActiveBLK2, ActiveBLK3, and ActiveBLK4 may be low). In the sixth time interval (T5 to T6), the third and fourth active blocks may be activated (for example, the signals ActiveBLK3 and ActiveBLK4 may be low). In the seventh time interval (T6 to T7), the fourth active block may be activated (for example, the signal ActiveBLK4 may be low). The active block usage rate may be 75% in the fifth time interval (T4 to T5), 50% in the sixth time interval (T5 to T6), and 25% in the seventh time interval (T6 to T7).

[0089] The pump circuit 2000 may select one of a plurality of modes and change the clock frequency of the clock signal in response to the selected mode signal.

[0090] In the first mode MOD1, the clock generator 2920 may generate a clock signal having the same clock frequency in all time intervals, regardless of the count signal CNT. For example, the clock generator 2920 may generate a clock signal having the fourth clock frequency F4 in all of the first through seventh time intervals. In the first mode MOD1, a clock signal having a different clock frequency (e.g., F3) may be generated instead of the clock signal having the fourth clock frequency F4.

[0091] In the second mode MOD2, the clock generator 2920 may generate clock signals having one clock frequency and another clock frequency in response to the count signal CNT and the mode selection signal SEL_MOD. For example, the one clock frequency may be the fourth clock frequency F4, and the other clock frequency may be a clock frequency other than the fourth clock frequency F4 ("non-F4").

[0092] Clock generator 2920 may generate a clock signal having a fourth clock frequency F4 in a fourth time interval (T3 to T4), and may generate a clock signal having a second clock frequency F2 in other time intervals. Here, "non-F4" may also refer to the first clock frequency F1 or the third clock frequency F3 instead of the second clock frequency F2.

[0093] In the third mode MOD3, the clock generator 2920 may generate a clock signal having a clock frequency that varies according to the number of activated active blocks in response to the count signal CNT and the mode selection signal SEL_MOD. The clock generator 2920 may generate a clock signal having a first clock frequency F1 when one active block is activated, and a clock signal having a second clock frequency F2 when two active blocks are activated. The clock generator 2920 may also generate a clock signal having a third clock frequency F3 when three active blocks are activated, and a clock signal having a fourth clock frequency F4 when four active blocks are activated.

[0094] For example, the clock generator 2920 may generate a clock signal having a first clock frequency F1 in a first time interval (T0 to T1), and a clock signal having a second clock frequency F2 in a second time interval (T1 to T2). The clock generator 2920 may generate a clock signal having a third clock frequency F3 in a third time interval (T2 to T3), and a clock signal having a fourth clock frequency F4 in a fourth time interval (T3 to T4).

[0095] Figure 10 and Figure 11 is a graph showing an average amount of operating current in a peripheral circuit according to a mode change. Figure 10 A change in the average amount ICCavg of the operating current when changing from the first mode MOD1 to the second mode MOD2 is shown. Figure 11 A change in the average amount ICCavg of the operating current when changing from the first mode MOD1 to the third mode MOD3 is shown.

[0096] Reference Figure 10 , the first active block may be activated in a first time interval (T0 to T1). Clock generator 2920 may generate a clock signal having a fourth clock frequency F4 in the first mode MOD1, and a clock signal having a second clock frequency F2 in the second mode MOD2. During the first time interval (T0 to T1), the first mode MOD1 may consume an average amount of operating current A1 in the peripheral circuit, and the second mode MOD2 may consume an average amount of operating current B1. The difference between the average amount of operating current in the peripheral circuit in the first mode MOD1 and the second mode MOD2 may be A1-B1.

[0097] During the second time interval (T1 to T2), the first active block and the second active block may be activated. Clock generator 2920 may generate a clock signal having a fourth clock frequency F4 in the first mode MOD1 and a clock signal having a second clock frequency F2 in the second mode MOD2. During the second time interval (T1 to T2), the first mode MOD1 may consume an average operating current of A2 in the peripheral circuit, while the second mode MOD2 may consume an average operating current of B2. The difference between the average current of the peripheral circuit in the first mode MOD1 and the second mode MOD2 may be A2-B2. A2-B2 may be the same as A1-B1.

[0098] During a third time interval (T2 to T3), the first through third active blocks may be activated. During the third time interval (T2 to T3), the first mode MOD1 may consume an average amount of operating current A3 in the peripheral circuits, and the second mode MOD2 may consume an average amount of operating current B3. The difference in the average amount of operating current in the peripheral circuits between the first mode MOD1 and the second mode MOD2 may be A3-B3. A3-B3 may be the same as A1-B1 and / or A2-B2.

[0099] During the fourth time interval (T3 to T4), the first to fourth active blocks may be activated. Clock generator 2920 may generate a clock signal having a fourth clock frequency F4 in the first mode MOD1 and the second mode MOD2. The first mode MOD1 may consume an average operating current of A4 in the peripheral circuit, and the second mode MOD2 may consume an average operating current of B4. Here, A4 may be equal to B4.

[0100] Reference Figure 11 In the first time interval (T0 to T1), the first mode MOD1 may consume an average amount of operating current A1 in the peripheral circuit, and the third mode MOD3 may consume an average amount of operating current C1. The difference between the average current consumption of the peripheral circuits in the first mode MOD1 and the third mode MOD3 may be A1-C1. Here, A1-C1 may be greater than A1-B1. That is, when the memory device 1100 changes from the first mode MOD1 to the third mode MOD3, the average current consumption of the peripheral circuits can be further reduced.

[0101] During the second time interval (T1 to T2), the first mode MOD1 may consume an average operating current of A2 in the peripheral circuit, and the third mode MOD3 may consume an average operating current of C2. The difference in the average current of the peripheral circuit in the first mode MOD1 and the third mode MOD3 may be A2-C2. Here, A2-C2 may be equal to A2-B2.

[0102] In the third time interval (T2 to T3), the first mode MOD1 may consume an average amount of operating current A3 in the peripheral circuit, and the third mode MOD3 may consume an average amount of current C3. The average current difference between the peripheral circuits in the first mode MOD1 and the third mode MOD3 may be A3-C3.

[0103] In the fourth time interval (T3 to T4), the first mode MOD1 may consume an average amount of operating current A4 in the peripheral circuit, and the third mode MOD3 may consume an average amount of operating current C4. Here, A4 may be equal to C4.

[0104] Figure 12 is a block diagram illustrating an example embodiment of a memory device according to the present disclosure. Figure 7 The mode selection signal is shown in FIG. Figure 12 , the memory controller 1200 may include a pump scheduler 2001. The pump scheduler 2001 may include a command queue (CMD queue).

[0105] The command queue may receive command requests (such as program, read, erase, etc.) provided from the host, and may perform queue scheduling according to the amount of available power by considering the power state of the memory device 1100. The pump scheduler 2001 may effectively manage the power of the memory device 1100 by managing the command queue and the clock frequency mode.

[0106] The mode selector 2910 may receive a mode selection signal SEL_MOD from the pump scheduler 2001. The pump scheduler 2001 may calculate average current consumption in the peripheral circuit by considering commands (such as program, read, erase, etc.) stored in the command queue and provide the mode selection signal SEL_MOD according to the calculation result.

[0107] Figure 13 It shows Figure 12 A flow chart of an example embodiment of a method of operating a pump scheduler is shown in FIG. Figure 13 , the pump scheduler 2001 may receive commands such as program (PGM), read (READ), and erase (ERASE) ( S110 ).

[0108] The pump scheduler 2001 may store the input command in the command queue (S120). The pump scheduler 2001 may determine whether at least one command is stored in the command queue. The pump scheduler 2001 may check the depth of the command queue. If the queue depth is greater than a reference depth, the pump scheduler 2001 may store the command. If the queue depth is not greater than the reference depth, the pump scheduler 2001 may not store the command.

[0109] The pump scheduler 2001 may calculate the average operating current ICCavg of the memory device 1100 based on the commands stored in the command queue and determine whether the average operating current ICCavg is greater than the threshold current Ith (S130). Here, the average operating current ICCavg may be the total average operating current consumed in the peripheral circuit 1115 of the memory device 1100.

[0110] If the average operating current ICCavg is greater than the threshold current Ith, the pump scheduler 2001 may provide a mode selection signal SEL_MOD for selecting the third mode MOD3 ( S140 ). If the average operating current ICCavg is less than or equal to the threshold current Ith, the pump scheduler 2001 may provide a mode selection signal SEL_MOD for selecting the second mode MOD2 ( S145 ).

[0111] If the second mode MOD2 is selected, the clock generator 2920 may generate a clock signal having a fourth clock frequency F4 or a clock frequency "non-F4" which is not the fourth clock frequency (S155). If the third mode MOD3 is selected, the clock generator 2920 may generate clock signals having first to fourth clock frequencies (F1 to F4) according to the number of active blocks to be activated. (S150) The memory device 1100 according to an embodiment of the present disclosure can change the operating mode of the clock frequency according to the number of active blocks to be activated. The memory device 1100 can reduce the average current consumption of the peripheral circuit 1115. The memory device 1100 according to an embodiment of the present disclosure can also be applied to active blocks having a vertical structure. For example, active blocks having a vertical structure can also be applied when the memory device 1100 has a multi-stack structure, a COP structure, or a C2C structure.

[0112] Figure 14 is a diagram illustrating an example embodiment of a flash memory having a multi-stack structure. Figure 14 , the flash memory 3000 may have a first stack ST1 and a second stack ST2. The first stack ST1 may be located at the bottom, and the second stack ST2 may be located at the top.

[0113] The pillars of flash memory 3000 can be formed by joining a first stack ST1 and a second stack ST2. A plurality of dummy word lines (e.g., Dummy1 WL and Dummy2 WL) can be included at the junction of the first stack ST1 and the second stack ST2. The first stack ST1 can be positioned between the common source line CSL and the first dummy word line Dummy1 WL. The second stack ST2 can be positioned between the second dummy word line Dummy2 WL and the bit line BL.

[0114] The first stack ST1 may include a ground select line GSL, a first edge word line Edge1 WL, and a first stack word line Stack1 WL. The second stack ST2 may include a string select line SSL, a second stack word line Stack2 WL, and a second edge word line Edge2 WL. Memory cells connected to the first and second edge word lines Edge1 WL and Edge2 WL may store bit data differently from other memory cells. For example, the memory cells connected to the first and second edge word lines Edge1 WL and Edge2 WL may be single-level cells (SLCs) or multi-level cells (MLCs), while the memory cells connected to the other word lines may be triple-level cells (TLCs) or quad-level cells (QLCs).

[0115] The flash memory 3000 can perform independent memory operations for each active block. During independent memory operations, the flash memory 3000 can control the clock frequency operation mode differently depending on the height of the word line. For example, the flash memory 3000 can be controlled to operate in the second mode MOD2 in the first stack ST1 and in the third mode MOD3 in the second stack ST2.

[0116] Figure 15 and Figure 16 It is shown in Figure 14 A conceptual diagram of an example embodiment of operation in a third mode in a second stack of a flash memory having a multi-stack structure is shown in FIG.

[0117] Reference Figure 15 , the flash memory 3000 can divide the second stack ST2 into four active blocks that operate at the same clock frequency. For example, the first active block Active BLK1 is a group of memory cells between WLa and WLb, and can operate at the same clock frequency. The second active block Active BLK2 is a group of memory cells between WLb and WLc, and can operate at the same clock frequency. The third active block Active BLK3 is a group of memory cells between WLc and WLd, and can operate at the same clock frequency. The fourth active block Active BLK4 is a group of memory cells between WLd and WLe, and can operate at the same clock frequency.

[0118] Reference Figure 16 In the first time interval (T0 to T1), one active block is activated in the second stack ST2. Since the second stack ST2 operates in the third mode MOD3, the second stack ST2 may consume an average operating current of C1. The difference in average current consumption of the peripheral circuits in the first mode MOD1 and the third mode MOD3 may be A1-C1.

[0119] During the second time interval (T1 to T2), two active blocks in the second stack ST2 are activated. The second stack ST2 may consume an average operating current of C2. The difference in average current of the peripheral circuits in the first mode MOD1 and the third mode MOD3 may be A2-C2.

[0120] In the third time interval (T2 to T3), the three active blocks of the second stack ST2 are activated. The second stack ST2 may consume an average operating current of C3. The difference in average current of the peripheral circuits in the first mode MOD1 and the third mode MOD3 may be A3-C3.

[0121] During the fourth time interval (T3 to T4), the four active blocks of the second stack ST2 are activated. The second stack ST2 may consume an average operating current of C4 in the third mode MOD3. The first mode MOD1 may consume an average operating current of A4 in the peripheral circuit. Here, A4 may be equal to C4.

[0122] Figure 17 is a block diagram illustrating an example in which a storage device according to an embodiment of the present disclosure is implemented using a solid state drive (SSD). Figure 17 , the SSD 4000 may include a plurality of flash memories 4101 to 4104 and an SSD controller 4200 .

[0123] The first flash memory 4101 and the second flash memory 4102 can be connected to the SSD controller 4200 via a first channel CH1. The third flash memory 4103 and the fourth flash memory 4104 can be connected to the SSD controller 4200 via a second channel CH2. The number of channels connected to the SSD controller 4200 can be two or more. The number of flash memories connected to one channel can be two or more.

[0124] The SSD controller 4200 may include a host interface 4201, a flash memory interface 4202, a buffer interface 4203, a control unit 4210, and a working memory 4220. The SSD controller 4200 may be connected to the host 1500 through the host interface 4201. Based on a request from the host 1500, the SSD controller 4200 may write data to or read data from a corresponding flash memory.

[0125] The SSD controller 4200 can be connected to the plurality of flash memories 4101 to 4104 via a flash memory interface 4202, and can be connected to the buffer memory 1300 via a buffer interface 4203. The flash memory interface 4202 can provide data temporarily stored in the buffer memory 1300 to the flash memory via channels CH1 and CH2. The flash memory interface 4202 can transfer data read from the flash memories 4101 to 4104 to the buffer memory 1300.

[0126] The control unit 4210 may analyze and process a signal received from the host 1500. The control unit 4210 may control the host 1500 or the flash memories 4101 to 4104 through the host interface 4201 or the flash memory interface 4202. The control unit 4210 may control operations of the flash memories 4101 to 4104 by using firmware for driving the SSD 4000.

[0127] The SSD controller 4200 may manage data to be stored in the flash memories 4101 to 4104. In the event of a sudden power outage, the SSD controller 4200 may back up data stored in the working memory 4220 or the buffer memory 1300 to the flash memories 4101 to 4104.

[0128] According to the present disclosure, it is possible to effectively use the operating current of a memory device and reduce current consumption by changing the clock frequency according to the number of active blocks to be activated.

[0129] Although this disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the claims. Specific features described in this disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable subcombination. Furthermore, although features may be described above as functioning in a particular combination, in some cases one or more features from a combination may be excluded from the combination, and the combination may involve subcombinations or variations of subcombinations.

[0130] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A memory device comprising: a memory cell array having a plurality of active blocks, each of the plurality of active blocks including a plurality of memory cells configured to operate at a clock frequency; a voltage generator configured to provide an operating voltage to the plurality of memory cells; as well as control logic configured to control independent memory operations for each of the plurality of active blocks, The voltage generator includes a pump circuit configured to change the clock frequency for generating the operating voltage according to the number of active blocks activated during the independent memory operation.

2. The memory device according to claim 1, in, The independent memory operation is a read operation or a program operation independently performed between activated active blocks.

3. The memory device according to claim 1, in, The independent memory operation is an erase operation independently performed between activated active blocks.

4. The memory device according to claim 1, in, The plurality of active blocks are a plurality of pads, and each of the plurality of pads includes a plurality of memory cells configured to operate at the clock frequency.

5. The memory device according to claim 1, in, The pump circuit includes: a mode selector configured to receive an active block usage signal and a mode selection signal from the control logic and select one of a plurality of modes; and The clock generator is configured to change the clock frequency in response to a mode signal selected by the mode selector.

6. The memory device according to claim 5, in, The mode selector includes: an active block counter configured to receive the active block usage signal and count the number of activated active blocks; and a mode register configured to store the plurality of modes, The mode register is configured to receive a mode selection signal and a signal indicating the number of activated active blocks from an active block counter, and provide one of the plurality of modes to the clock generator.

7. The memory device according to claim 6, in, The mode register is configured to store: A first mode for generating a clock signal having the clock frequency; a second mode for generating a clock signal having a first clock frequency and a second clock frequency different from the first clock frequency; as well as The third mode is for generating a clock signal having a clock frequency that varies according to the number of activated active blocks.

8. The memory device according to claim 5, in, The mode select signal is provided from the pump scheduler of the memory controller.

9. The memory device according to claim 8, in, The pump scheduler is configured to store incoming commands in a command queue, and The pump scheduler is configured to calculate an amount of operating current required by a peripheral circuit of the memory device based on commands stored in the command queue.

10. The memory device according to claim 8, in, The pump scheduler is configured to compare the operating current amount with a threshold current amount and provide a mode selection signal for selecting one of the plurality of modes to the mode selector according to a result of the comparison.

11. A memory device comprising: a first stack in which first memory cells are stacked in a direction perpendicular to the substrate; as well as a second stack in which the second memory cell is stacked on the first stack in a direction perpendicular to the substrate, wherein the first memory unit and the second memory unit are divided into a plurality of active blocks, each active block being configured to operate at a selected clock frequency among a plurality of clock frequencies, The memory controller is configured to perform an independent memory operation for each active block and to change a selected clock frequency for performing the independent memory operation according to the number of active blocks activated during the independent memory operation.

12. The memory device according to claim 11, in, Independent memory operations include a read operation or a program operation independently performed between activated active blocks.

13. The memory device according to claim 11, in, Independent memory operations include erase operations that are performed independently between activated active blocks.

14. The memory device of claim 11, further comprising: The pump circuit is configured to receive a mode selection signal for selecting one of a plurality of modes and change a selected clock frequency in response to the selected mode signal.

15. The memory device of claim 14, in, The mode selection signal is provided from the memory controller.

16. A method for operating a memory device, the memory device comprising: a memory cell array having a plurality of active blocks, each active block including a plurality of memory cells; a voltage generator configured to provide an operating voltage to the plurality of memory cells; and control logic configured to control independent memory operations for each active block, the operating method comprising: counting a number of active blocks activated during a selected one of the independent memory operations; changing a frequency of a clock signal for generating an operating voltage according to the number of counted active blocks; and The clock signal having the changed frequency is supplied to the voltage generator.

17. The operating method according to claim 16, further comprising: receiving an active block use signal and a mode selection signal for selecting one of a plurality of modes, Wherein, in the step of changing the frequency of the clock signal, the frequency of the clock signal is changed in response to the mode selection signal.

18. The operating method according to claim 17, in, The multiple modes include: a first mode for generating a clock signal having a selected clock frequency; a second mode for generating a clock signal having a first clock frequency and a second clock frequency different from the first clock frequency; and The third mode is for generating a clock signal having a clock frequency that varies according to the number of activated active blocks.

19. The operating method according to claim 16, in, The selected independent memory operation is a read operation or a program operation independently performed between activated active blocks.

20. The operating method according to claim 17, in, The mode select signal is generated within the memory device or provided from a memory controller.

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