Trench gate MOSFET and manufacturing method, unit cell structure manufacturing method

Abstract

The present invention relates to a trench gate MOSFET and a manufacturing method, as well as a unit cell structure manufacturing method in the field of semiconductor technology. The trench gate MOSFET comprises a channel layer, two or more groups of trenches formed in the channel layer, a first current circulation layer, a second current circulation layer, a gate dielectric layer and a gate electrode; the first current circulation layer is located at the bottom of the trench, and the first current circulation layer also extends along the non-channel side of the trench to the upper surface of the trench; the second current circulation layer is arranged close to the channel side of the trench, and the second current circulation layer is located on the upper surface of the channel layer; the gate dielectric layer covers the first current circulation layer and the second current circulation layer, and is arranged in contact with part of the sidewall of the trench; the gate electrode covers the gate dielectric layer and fills the trench, thereby solving the problem that the trench gate cannot avoid the influence of parasitic resistance by replicating the long channel of the planar gate structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a trench gate MOSFET and its manufacturing method, and a method for manufacturing a unit cell structure. Background Technology

[0002] The core component of a metal-oxide-semiconductor field-effect transistor (MOSFET) is the oxide-semiconductor interface. The characteristics of the oxide-semiconductor interface located at the channel directly affect the channel mobility of the device, which in turn affects the channel on-state characteristic resistance of the MOSFET device. Therefore, it is desirable to be able to accurately evaluate the channel mobility of the device.

[0003] Currently, MOSFET devices are mainly divided into two types: planar gate MOSFETs and trench gate MOSFETs. As a core parameter of power devices, channel mobility is generally achieved by increasing the channel length to increase the channel resistance, thus avoiding the influence of parasitic resistance on mobility. To increase the channel length, it is only necessary to modify the layout to increase the distance between the source electrode and the drain electrode, which is a simple and easy method to implement.

[0004] However, for trench gate MOSFETs, since the channel and semiconductor are located inside the semiconductor, the trench depth is generally less than 2µm, and the channel length is usually less than the trench depth. To achieve a longer channel, it is necessary to etch to form a deep trench. Therefore, for trench devices, it is not possible to avoid the influence of parasitic resistance by replicating the planar gate to construct a long channel. In other words, it is not possible to directly increase the channel length through layout, and it is not possible to effectively increase the channel length. Summary of the Invention

[0005] This invention addresses the shortcomings of existing technologies by providing a trench gate MOSFET and its manufacturing method, as well as a cell structure manufacturing method, which solves the problem that trench gates cannot avoid the influence of parasitic resistance by replicating planar gates to construct long channels.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] A trench field-effect transistor includes a channel layer, two or more sets of trenches formed in the channel layer, a first current flow layer, a second current flow layer, a gate dielectric layer, and a gate electrode, wherein the depth of the two or more sets of trenches is less than the depth of the channel layer.

[0008] The first current flow layer is located at the bottom of the trench, and the first current flow layer also extends along the non-channel side of the trench to the upper surface of the trench.

[0009] The second current flow layer is disposed on the channel side of the trench, and the second current flow layer is located on the upper surface of the channel layer, and the depth of the second current flow layer is less than the depth of the trench.

[0010] The gate dielectric layer covers the first current flow layer and the second current flow layer, and is in contact with a portion of the sidewall of the trench.

[0011] The gate electrode covers the gate dielectric layer and fills the trench;

[0012] In two adjacent sets of trenches, the first current flow layer in one set of trenches is in contact with the second current flow layer in the other set of trenches.

[0013] Optionally, the thickness of the gate dielectric layer on the non-channel sidewall is equal to the thickness of the gate dielectric layer on the channel sidewall.

[0014] Optionally, the thickness of the gate dielectric layer on the non-channel sidewall is set to be greater than the thickness of the gate dielectric layer on the channel sidewall.

[0015] Optionally, a current shielding layer is also included, which is embedded in the first current flow layer and is in contact with the sidewall of the non-channel side of the trench, and is also in contact with the gate dielectric layer.

[0016] Optionally, the doping concentration of the current shielding layer is greater than 1×10⁻⁶. 19 cm -3 Furthermore, the current shielding layer is doped with a first conductivity type.

[0017] Optionally, the effective conductive channel length formed in each group of trenches is 0.3μm to 2.0μm.

[0018] Optionally, the depth of the first current-flow layer at the bottom of the trench is greater than 0.1 μm; and the width of the first current-flow layer at the non-channel side near the trench sidewall is greater than 0.2 μm.

[0019] Optionally, the depth of the second current-conducting layer is 0.1~0.2μm.

[0020] Optionally, it further includes a source electrode, a drain electrode, a first contact region, and a second contact region, wherein the source electrode, drain electrode, first contact region, and second contact region are all located on the upper surface of the channel layer, the second contact region is in contact with the sidewall of the first contact region, the source electrode is in contact with the second contact region and a portion of the first contact region to form an ohmic contact, the drain electrode is in contact with a portion of the first contact region to form an ohmic contact, the first contact region is in contact with the first current flow layer, and the first contact region is also in contact with the second current flow layer, and the first contact region, the first current flow layer, and the second current flow layer form a current flow path.

[0021] Optionally, it may also include an epitaxial layer, a substrate layer, and a substrate electrode, wherein the epitaxial layer is located on the lower surface of the channel layer, the substrate layer is located on the lower surface of the epitaxial layer, the substrate electrode is located on the lower surface of the substrate layer, and the second current-passing layer is disposed in a manner that does not contact the substrate layer.

[0022] Optionally, the channel layer and the second contact region are both doped with a first conductivity type, and the first current flow layer, the second current flow layer, the first contact region, the epitaxial layer, and the substrate layer are all doped with a second conductivity type opposite to the first conductivity type doping.

[0023] A method for testing the channel mobility of a trench field-effect transistor, the method being used to test the trench field-effect transistor as described in any one of the above claims, comprising the following steps:

[0024] A constant drain-source voltage is applied between the drain electrode and the source electrode of the trench field-effect transistor, and a gate-source voltage is applied at the gate electrode.

[0025] Measure the drain current and generate a drain current-gate-source voltage variation curve based on the drain current and the gate-source voltage;

[0026] The transconductance is calculated based on the drain current-gate-source voltage variation curve, and the total effective conductive channel length, the unit area capacitance of the gate dielectric layer, and the dimension length along the channel width direction of the trench field-effect transistor are obtained.

[0027] The field-effect mobility of channel carriers is calculated based on the transconductance, total effective channel length, capacitance per unit area, and dimension length.

[0028] A method for testing the channel mobility of a trench field-effect transistor, the method being used to test the trench field-effect transistor as described in any one of the above claims, comprising the following steps:

[0029] A constant gate-source voltage is applied to the gate electrode of the trench field-effect transistor, and a drain-source voltage is applied between the drain electrode and the source electrode.

[0030] Measure the drain current and generate a drain current-drain voltage variation curve based on the drain-source voltage and the drain current;

[0031] The on-resistance is calculated based on the slope of the drain current-drain voltage variation curve in the drain-source low voltage region, and the total effective conductive channel length, the unit area capacitance of the gate dielectric layer, the dimension length along the channel width direction, and the threshold voltage of the trench field-effect transistor are obtained.

[0032] The effective mobility of channel carriers is calculated based on the gate-source voltage, total effective conductive channel length, volume per unit area, dimension length, threshold voltage, and on-resistance.

[0033] A method for manufacturing a unit cell structure of a trench field-effect transistor, the method being used to prepare a unit cell structure as described above, comprising a channel layer, a first current-current-current layer, a second current-current-current-current layer, a gate dielectric layer, a gate electrode, an epitaxial layer, a substrate layer, and a substrate electrode, comprising the following steps:

[0034] Obtain a substrate layer, and form an epitaxial layer on the substrate layer by epitaxial growth;

[0035] A trench layer is formed on the epitaxial layer by epitaxial growth or ion implantation, and after transferring the trench pattern in the trench layer by photolithography, the trench is formed by etching.

[0036] A first current-flowing layer is formed by ion implantation at the bottom of the trench and on the trench sidewall region on the non-channel side, and a second current-flowing layer is formed by ion implantation on the trench sidewall region on the channel side of the trench.

[0037] A grid dielectric layer is formed on the sidewalls and bottom of the trench by thermal oxidation or deposition.

[0038] A gate electrode is formed in the trench by low-pressure chemical vapor deposition or atomic layer deposition, and the gate electrode covers the gate dielectric layer.

[0039] Optionally, after forming a first current-passing layer by ion implantation at the bottom of the trench and on the trench sidewall region on the non-channel side, the method further includes the following step:

[0040] A current shielding layer is formed in the sidewall region of the first current flow layer near the trench on the non-channel side by ion sidewall implantation.

[0041] A method for manufacturing a trench field-effect transistor, the method comprising the steps described above, for fabricating a trench field-effect transistor as described in any one of the preceding claims:

[0042] An epitaxial layer is grown on the substrate layer, and a channel layer is formed by in-situ doping or ion implantation.

[0043] Trenches are formed in the channel layer by photolithography and etching processes, and a first current flow layer and a second current flow layer are formed sequentially in the trenches by selective ion implantation.

[0044] A gate dielectric layer is formed in the trench by thermal oxidation or deposition, and a gate electrode is formed by depositing conductive material and photolithography etching.

[0045] An insulating dielectric layer is formed on the gate electrode, and a first contact region and a second contact layer are formed through the insulating dielectric layer, wherein the first contact region is electrically connected to the first current flow layer and the second current flow layer, and the second contact region is electrically connected to the source side region.

[0046] A drain electrode is formed on the first contact region, and a source electrode is formed on the second contact region;

[0047] The drain electrode and source electrode are annealed to form an ohmic contact, and a substrate electrode is formed on the back side of the substrate layer.

[0048] Optionally, it also includes forming a current shielding layer in the trench using a selective ion implantation process, wherein the second contact area is electrically connected to the current shielding layer or the source-side region.

[0049] Compared with the prior art, the technical solution provided by this invention has the following advantages:

[0050] By forming two or more sets of trenches within the channel layer, and providing a first current-passing layer and a second current-passing layer, the first current-passing layer is located at the bottom of the trench and extends along the non-channel side of the trench to the upper surface of the trench. The second current-passing layer is located near the channel side of the trench and is situated on the upper surface of the channel layer. The depth of the second current-passing layer is less than the depth of the trench. This creates an effective conductive channel length on one side of the channel of each set of trenches. Since the total effective conductive channel length of the device is equal to the sum of the effective conductive channel lengths of multiple sets of trenches, and since the total effective conductive channel length is proportional to the channel resistance, as the total effective conductive channel length increases, the total channel resistance of the device increases, thereby increasing the proportion of channel resistance in the total resistance of the device. Consequently, the proportion of parasitic resistance in the total resistance of the device decreases, thus reducing the impact of parasitic resistance on the device. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of a trench field-effect transistor structure proposed in Embodiment 1;

[0053] Figure 2 This is a schematic diagram of the unit cell structure in a trench field-effect transistor proposed in this embodiment 1;

[0054] Figure 3 The two sets proposed in this embodiment one Figure 2 The diagram shows a series connection of unit cell structures.

[0055] Figure 4 This is a schematic diagram of the unit cell structure in a trench field-effect transistor proposed in Embodiment 2.

[0056] Figure 5 This is a schematic diagram of the unit cell structure in a trench field-effect transistor proposed in Embodiment 3;

[0057] Figure 6 This is a current path diagram of a trench field-effect transistor proposed in Embodiment 3 when it is turned on;

[0058] Figure 7 This is a test structure layout of a trench field-effect transistor proposed in Embodiment 4;

[0059] Figure 8 This is a test structure layout of a trench field-effect transistor in different crystal orientations as proposed in Embodiment 4;

[0060] Figure 9 This is a comparison chart of the test method for the channel mobility of a trench field-effect transistor proposed in Embodiment 5 and the simulated mobility.

[0061] Figure 10 This is a sensitivity diagram of parasitic resistance for unit cell structures with different numbers of series connections proposed in Example 5.

[0062] Reference numerals: 1. Channel layer; 2. First current flow layer; 3. Second current flow layer; 4. Gate dielectric layer; 5. Gate electrode; 6. Current shielding layer; 7. Epitaxial layer; 8. Substrate layer; 9. Substrate electrode; 10. First contact region; 11. Second contact region; 12. Source electrode; 13. Drain electrode. Detailed Implementation

[0063] The present invention will be further described in detail below with reference to the embodiments. The following embodiments are explanations of the present invention, but the present invention is not limited to the following embodiments. Example

[0064] like Figure 1 As shown, a trench field-effect transistor includes two or more sets of unit cell structures connected in series along the current flow direction. Each set of unit cell structures includes a channel layer 1, a trench formed within the channel layer 1, a first current flow layer 2, a second current flow layer 3, a gate dielectric layer 4, and a gate electrode 5. Figure 1 In this context, n is an integer greater than or equal to 2, and the depth d of the trench is less than the depth of trench layer 1.

[0065] Specifically, this embodiment provides a structural configuration for one type of unit cell structure, such as... Figure 2 As shown, the first current-current-current layer 2 in the unit cell structure is located at the bottom of the trench, and the first current-current-current layer 2 also extends along the non-channel side of the trench to the upper surface of the trench; the second current-current-current layer 3 is disposed near the channel side of the trench, and the second current-current-current layer 3 is located on the upper surface of the channel layer 1, and the depth of the second current-current-current layer 3 is less than the depth of the trench; the gate dielectric layer 4 covers the first current-current-current layer 2 and the second current-current-current layer 3, and is disposed in contact with part of the sidewall of the trench, and the thickness of the gate dielectric layer 4 on the non-channel sidewall is equal to the thickness of the gate dielectric layer 4 on the channel sidewall; the gate electrode 5 covers the gate dielectric layer 4 and fills the trench; in two adjacent sets of trenches, the first current-current-current layer 2 in one set of trenches is disposed in contact with the second current-current-current layer 3 in the other set of trenches.

[0066] It should be noted that, as Figure 2 As shown, in this embodiment, the depth (Deep1) of the first current flow layer 2 at the bottom of the trench is greater than 0.1 μm; and the width (Width) of the first current flow layer 2 near the trench sidewall on the non-channel side is greater than 0.2 μm. This depth setting of the first current flow layer 2 at the bottom of the trench ensures that when current is conducted, the current flowing through the first current flow layer 2 avoids the interface position of the gate dielectric layer 4 at the bottom of the trench. Furthermore, the width setting of the first current flow layer 2 near the trench sidewall on the non-channel side prevents the current flow path from being forced close to the trench sidewall due to excessive narrowness, thus preventing channels like those in this location from participating in current conduction and preventing current from the non-channel side from being added to the total current.

[0067] like Figure 2As shown, the depth of the second current flow layer 3 in this embodiment is 0.1μm ~ 0.2μm, thereby preventing the current flowing through the second current flow layer 3 from avoiding the interface position of the gate dielectric layer 4 when the current is turned on. The depth of the second current flow layer 3, Deep2, is set to less than 0.2μm to avoid affecting the channel length due to excessive depth.

[0068] On the other hand, since the cell structure of this application is applied to trench gate MOSFET devices, the effective conductive channel length formed in the trenches within each group of cell structures is... l Set to 0.3μm~2.0μm.

[0069] In addition to two or more sets of series-connected unit cell structures, the trench field-effect transistor of this embodiment also includes a source electrode 12, a drain electrode 13, a first contact region 10, and a second contact region 11. The source electrode 12, drain electrode 13, first contact region 10, and second contact region 11 are all located on the upper surface of the channel layer 1. The second contact region 11 is in contact with the sidewall of the first contact region 10. The source electrode 12 is in contact with the second contact region 11 and a portion of the first contact region 10, forming an ohmic contact. The drain electrode 13 is in contact with a portion of the first contact region 10, forming an ohmic contact. The first contact region 10 is in contact with the first current flow layer 2 and also with the second current flow layer 3. The first contact region 10, the first current flow layer 2, and the second current flow layer 3 form a current flow path. The source electrode 12 and the drain electrode 13 can be made of metals such as nickel, aluminum, and titanium, and the ohmic contact is formed by laser annealing or rapid thermal annealing.

[0070] The trench field-effect transistor also includes an epitaxial layer 7, a substrate layer 8, and a substrate electrode 9. The epitaxial layer 7 is located on the lower surface of the channel layer 1, the substrate layer 8 is located on the lower surface of the epitaxial layer 7, the substrate electrode 9 is located on the lower surface of the substrate layer 8, and the second current flow layer 3 is disposed in non-contact with the substrate layer 8.

[0071] It should be noted that both the channel layer 1 and the second contact region 11 are doped with the first conductivity type, while the first current flow layer 2, the second current flow layer 3, the first contact region 10, the epitaxial layer 7, and the substrate layer 8 are doped with the second conductivity type, which is opposite to the first conductivity type. The doping concentration of the first current flow layer 2, the second current flow layer 3, the first contact region 10, and the second contact region 11 is set to 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 The doping concentration settings of the first contact region 10 and the second contact region 11 can improve the performance of the ohmic contact and reduce the resistivity of the ohmic contact.

[0072] like Figure 3 As shown, this embodiment takes two sets of unit cell structures connected in series as an example. At this time, a gate voltage is applied to the gate to open the channel, and a voltage is applied to the drain. During this process, the source potential remains at 0V. At this time, a current will be formed from the drain to the source in the constructed trench field-effect transistor. The current flow path of the unit cell structure is as follows: first, it flows through the first current flow layer 2, then through the channel layer 1 of the trench sidewall, and then through the second current flow layer 3. Since in the series structure, the second current flow layer 3 of one set of unit cell structures in the adjacent unit cell structure is in contact with the first current flow layer 2 of the other set of unit cell structures, the current flowing through the second current flow layer 3 will continue to flow through the first current flow layer 2 of the adjacent unit cell structure, thus forming a current flow path when the unit cell structures are connected in series.

[0073] This application, by setting two or more unit cell structures in series as described above, avoids the effects of parasitic resistance in trench field-effect transistors without constructing long channels by replicating planar gates. Specifically, this application does not use the method of constructing long channels to avoid the effects of parasitic resistance, but instead sets two or more unit cell structures so that the total effective conductive channel length L of the device is equal to the effective conductive channel length of n unit cell structures. l The sum, that is: L=n l Since the total effective conductive channel length is directly proportional to the channel resistance, as the total effective conductive channel length increases, the total channel resistance of the device increases, thereby increasing the proportion of channel resistance in the total resistance of the device. Consequently, the proportion of parasitic resistance in the total resistance of the device decreases, thus reducing the impact of parasitic resistance on the device. Example

[0074] like Figure 4 As shown, the difference between this embodiment and Embodiment 1 is that the thickness T of the gate dielectric layer 4 on the non-channel sidewall in this embodiment is... ox The thickness t of the gate dielectric layer 4 on one side wall of the channel is greater than the thickness t ox This configuration ensures sufficient isolation between the gate electrode 5 and the non-channel sidewall, preventing the formation of a current path in the channel at this location when a voltage is applied to the gate, which would affect the device's ability to extract channel parameters.

[0075] Specifically, according to the threshold voltage formula: NA and tox are the doping concentration of the channel layer 1 and the thickness of the oxide layer (gate dielectric layer 4) at the channel, respectively. Therefore, when the thickness of the gate dielectric layer 4 increases, the threshold voltage will increase. This will prevent the formation of a current path on the non-channel sidewall when the gate voltage is applied by increasing the thickness. Example

[0076] like Figure 5 As shown, the difference between this embodiment and Embodiment 1 is that the trench field-effect transistor in this embodiment further includes a current shielding layer 6. The current shielding layer 6 is embedded in the first current flow layer 2, and the current shielding layer 6 is in contact with the sidewall of the non-channel side of the trench. The current shielding layer 6 is also in contact with the gate dielectric layer 4, and the doping concentration of the current shielding layer 6 is greater than 1×10⁻⁶. 19 cm -3 Furthermore, the current shielding layer 6 is doped with the first conductivity type.

[0077] In this embodiment, by setting a high concentration of current shielding layer 6, the threshold voltage of the sidewall on the non-channel side is increased, so that when a current path is formed at that location, the channel located at the current shielding layer 6 remains completely turned off, thus forming a non-channel.

[0078] Furthermore, such as Figure 6 As shown, this embodiment takes a trench field-effect transistor formed by two sets of unit cell structures connected in series as an example to provide a current flow path when the current is turned on. When a current shielding layer 6 is provided in the first current flow layer 2, since the doping concentration of the current shielding layer 6 is greater than 1×10⁻⁶, 19 cm -3 To form a conductive path at this location, a sufficiently large gate voltage, exceeding the threshold voltage at that position, is required. However, according to the threshold voltage formula, when the doping concentration is set to 1×10⁻⁶, the threshold voltage is significantly higher. 19 cm -3 When the threshold voltage Vth is large, it will not be turned on within the test voltage range, such as within 25V. However, during the test, when the thickness of the gate dielectric layer 4 is 50nm, the channel at the target channel has already been turned on, and no larger gate voltage will be applied, thus avoiding damage to the gate dielectric layer 4 at this time; at the same time, it avoids the channel at this time from participating in conduction, thus achieving effective separation of the channel on both sides of the trench.

[0079] It should be noted that, in this embodiment, when the device is turned on, such as Figure 6 As shown, the current flows through the drain electrode 13, then sequentially through the first contact region 10, the first current flow layer 2, the channel layer 1 and the second current flow layer 3, and then through the first current flow layer 2, the channel layer 1 and the second current flow layer 3 in the adjacent unit cell structure, and finally enters the source electrode to realize the device turn-on. Example

[0080] A method for testing the channel mobility of a trench field-effect transistor, the method being used to test trench field-effect transistors as described in any one of Examples 1 to 3.

[0081] like Figure 7The diagram shows a top view of a trench field-effect transistor with n unit cell structures connected in series. Each unit cell structure has a single-sided channel providing a current flow path. The trench field-effect transistor has a source electrode 12 and a gate electrode 5 on both sides. Figure 7 The trench structure referred to herein refers to the sum of all structures formed within the trench. Therefore, the testing process includes the following steps:

[0082] S1. A constant drain-source voltage is applied between the drain electrode 13 and the source electrode 12 of the trench field-effect transistor, and a gate-source voltage is applied to the gate electrode 5.

[0083] S2. Measure the drain current and generate a drain current-gate-source voltage variation curve based on the drain current and gate-source voltage;

[0084] S3. Calculate the transconductance based on the drain current-gate-source voltage variation curve, and obtain the total effective conductive channel length, the unit area capacitance of the gate dielectric layer 4, and the length along the channel width direction of the trench field-effect transistor. The length of the device along the channel width direction is the length of the device in the projection direction. The formula for calculating the transconductance is: ;

[0085] S4, based on transconductance Total effective channel length L, capacitance per unit area Size and length The field-effect mobility of channel carriers is calculated using the following formula: .

[0086] In step S1, the drain-source voltage Vds remains constant between 0.02V and 0.1V. When the gate dielectric layer 4 has a thickness of 50nm, the gate-source voltage Vg is applied, and the range is set from 0V to 25V. In step S2, a step size of 0.1V or 0.5V can be set to obtain the drain current-gate-source voltage change curve (also referred to as the Id-Vg curve in this embodiment). It should be noted that the test process at this time is only an exemplary process. The specific test needs to follow the test specifications of the MOSFET gate characteristic curve and be adjusted according to device characteristics such as oxide layer thickness and doping concentration of channel layer 1.

[0087] On the other hand, the above method is for testing the channel mobility of a trench field-effect transistor with one crystal orientation. Since trench field-effect transistors have multiple crystal orientations, in actual operation, to improve the testing accuracy, other methods can be used as follows: Figure 8As shown, each independent trench field-effect transistor is rotated at a certain angle, so that the mobility of the channel in different crystal orientations of the semiconductor can be tested in the same layout. For example, taking silicon carbide as an example, with its flat edge as 0°, when the trench field-effect transistor is rotated 90°, the mobility in the two crystal orientations (11-20) and (-1-120) can be tested. Example

[0088] A method for testing the channel mobility of a trench field-effect transistor, the method being used to test a trench field-effect transistor as described in any one of Examples 1 to 3, comprising the following steps:

[0089] S1. A constant gate-source voltage is applied to the gate electrode 5 of the trench field-effect transistor, and a drain-source voltage is applied between the drain electrode 13 and the source electrode 12.

[0090] S2. Measure the drain current and generate a drain current-drain voltage variation curve based on the drain-source voltage and the drain current;

[0091] S3. Calculate the on-resistance based on the slope of the drain current-drain voltage variation curve in the drain-source low-voltage region, and obtain the total effective conductive channel length of the trench field-effect transistor, the capacitance per unit area of ​​the gate dielectric layer 4, the dimension length along the channel width direction, and the threshold voltage. The formula for calculating the on-resistance is: Rt ;

[0092] S4, Based on gate-source voltage Total effective conductive channel length L, volume per unit area Size length W, threshold voltage The effective mobility of channel carriers is calculated using the on-resistance Rt. The formula for calculating the effective mobility is as follows:

[0093] .

[0094] In step S1, the drain-source voltage Vds is applied and varies from 0V to 0.1V to measure the drain voltage and obtain the drain current-drain voltage variation curve in step S2 (also referred to as the Id-Vds curve in this embodiment).

[0095] like Figure 9 As shown, this embodiment uses five unit cells connected in series, with an ohmic contact resistivity of 1×10⁻⁶. -4 mΩcm 2 For example, at this time, a comparison chart of the effective mobility of channel carriers and the effective mobility of channel carriers obtained by simulation is generated according to the test method of this embodiment. Figure 9It can be seen that the migration rate calculated by the test at this time is more consistent with the migration rate of the simulation, and the deviation of the data is small.

[0096] like Figure 10 As shown, this embodiment also presents current change rate graphs under different ohmic contact resistivities and different numbers of unit cell structures connected in series, ideally without the influence of parasitic resistance, to demonstrate the sensitivity of different numbers of unit cell structures connected in series to parasitic resistance. Figure 10 It is known that as the number of unit cell structures in series increases, its sensitivity to parasitic resistance decreases. That is, increasing the number of unit cells in series can effectively avoid the influence of parasitic resistance on the extracted channel resistance, thus improving the accuracy of the test. When one hundred unit cell structures of this application are connected in series, and the ohmic contact resistivity is 1×10⁻⁶... -2 mΩcm 2 When the current change rate drops below 40%, compared to the structure of two unit cells in series, the current change rate is greatly improved when it approaches 100%. It is foreseeable that the accuracy of the test will further increase when the number of unit cells in series continues to increase. Example

[0097] A method for manufacturing a unit cell structure of a trench field-effect transistor, the method being used to prepare a unit cell structure as described in any one of Examples 1 to 3, consisting of a channel layer 1, a first current-flow layer 2, a second current-flow layer 3, a gate dielectric layer 4, a gate electrode 5, an epitaxial layer 7, a substrate layer 8, and a substrate electrode 9, comprising the following steps:

[0098] S1. Obtain the substrate layer 8 and form the epitaxial layer 7 on the substrate layer 8 by epitaxial growth;

[0099] S2. A trench layer 1 is formed on the epitaxial layer 7 by epitaxial growth or ion implantation, and a trench pattern is transferred in the trench layer 1 by photolithography and then formed by etching.

[0100] S3. A first current flow layer 2 is formed by ion implantation at the bottom of the trench and on the trench sidewall region on the non-channel side, and a second current flow layer 3 is formed by ion implantation on the trench sidewall region on the channel side of the trench.

[0101] S4. A grid dielectric layer 4 is formed on the sidewalls and bottom of the trench by thermal oxidation or deposition.

[0102] S5 forms a gate electrode 5 in the trench by means of low-pressure chemical vapor deposition or atomic layer deposition, and the gate electrode 5 is covered by the gate dielectric layer 4.

[0103] According to the above preparation steps, the following can be formed: Figure 2 or Figure 4The unit cell structure shown. Example

[0104] The difference between this embodiment and Embodiment Six is ​​that, after forming the first current-passing layer 2 by ion implantation in the bottom of the trench and the trench sidewall region on the non-channel side, this embodiment further includes the following step: forming a current-shielding layer 6 in the sidewall region of the first current-passing layer 2 near the non-channel side of the trench by ion sidewall implantation, thereby forming a current shielding layer 6. Figure 5 The unit cell structure shown includes a current shielding layer 6, which can increase the threshold voltage of the sidewall on the non-channel side, so that when a current path is formed there, the channel located at the current shielding layer 6 remains completely off, thus forming a non-channel. Example

[0105] A method for manufacturing a trench field-effect transistor, the method being used to prepare a trench field-effect transistor as described in any one of Examples 1 to 3, includes the following steps:

[0106] An epitaxial layer 7 is grown on the substrate layer 8, and a channel layer 1 is formed by in-situ doping or ion implantation.

[0107] Trenches are formed in the channel layer 1 by photolithography and etching processes, and a first current flow layer 2 and a second current flow layer 3 are formed sequentially in the trenches by selective ion implantation.

[0108] A gate dielectric layer 4 is formed in the trench by thermal oxidation or deposition process, and a gate electrode 5 is formed by depositing conductive material and photolithography etching.

[0109] An insulating dielectric layer is formed on the gate electrode 5, and a first contact region 10 and a second contact layer are formed through the insulating dielectric layer. The first contact region 10 is electrically connected to the first current flow layer 2 and the second current flow layer 3, and the second contact region 11 is electrically connected to the source side region.

[0110] A drain electrode 13 is formed on the first contact region 10, and a source electrode 12 is formed on the second contact region 11;

[0111] The drain electrode 13 and the source electrode 12 are annealed to form an ohmic contact, and a substrate electrode 9 is formed on the back side of the substrate layer 8. Example

[0112] The difference between this embodiment and embodiment eight is that this embodiment further includes forming a current shielding layer 6 in the trench through a selective ion implantation process. At this time, the second contact region 11 is electrically connected to the current shielding layer 6 or the source side region, thereby forming a trench field-effect transistor with the current shielding layer 6. The trench field-effect transistor containing the current shielding layer 6 can increase the threshold voltage of the sidewall on the non-channel side, so that when a current path is formed at that location, the channel located at the current shielding layer 6 remains completely off, forming a non-channel.

[0113] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any form or substance. It should be noted that those skilled in the art can make various improvements and additions without departing from the method of the present invention, and these improvements and additions should also be considered within the scope of protection of the present invention. Any modifications, alterations, and equivalent changes made by those skilled in the art based on the above-disclosed technical content without departing from the spirit and scope of the present invention are equivalent embodiments of the present invention. Furthermore, any modifications, alterations, and evolutions made to the above embodiments based on the essential technology of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A trench field-effect transistor, characterized in that, It includes a channel layer, two or more sets of trenches formed in the channel layer, a first current flow layer, a second current flow layer, a gate dielectric layer, and a gate electrode, wherein the depth of the two or more sets of trenches is less than the depth of the channel layer. The first current flow layer is located at the bottom of the trench, and the first current flow layer also extends along the non-channel side of the trench to the upper surface of the trench. The second current flow layer is disposed on the channel side of the trench, and the second current flow layer is located on the upper surface of the channel layer, and the depth of the second current flow layer is less than the depth of the trench. The gate dielectric layer covers the first current flow layer and the second current flow layer, and is in contact with a portion of the sidewall of the trench. The gate electrode covers the gate dielectric layer and fills the trench; In two adjacent sets of trenches, the first current flow layer in one set of trenches is in contact with the second current flow layer in the other set of trenches; It also includes a source electrode, a drain electrode, a first contact region, and a second contact region, wherein the source electrode, the drain electrode, the first contact region, and the second contact region are all located on the upper surface of the channel layer, the second contact region is in contact with the sidewall of the first contact region, and the source electrode is in contact with the second contact region and part of the first contact region to form an ohmic contact. The drain electrode is disposed in contact with a portion of the first contact area, forming an ohmic contact; The first contact area is in contact with the first current flow layer, and the first contact area is also in contact with the second current flow layer. The first contact area, the first current flow layer, and the second current flow layer form a current flow path. The channel layer and the second contact area are both doped with a first conductivity type. The first current flow layer, the second current flow layer, and the first contact area are all doped with a second conductivity type opposite to the first conductivity type doping.

2. The trench field-effect transistor according to claim 1, characterized in that, The thickness of the gate dielectric layer on the non-channel sidewall is equal to the thickness of the gate dielectric layer on the channel sidewall.

3. A trench field-effect transistor according to claim 1, characterized in that, The thickness of the gate dielectric layer on the non-channel sidewall is set to be greater than the thickness of the gate dielectric layer on the channel sidewall.

4. A trench field-effect transistor according to any one of claims 1-3, characterized in that, It also includes a current shielding layer, which is embedded in the first current flow layer and is in contact with the sidewall of the non-channel side of the trench, and is also in contact with the gate dielectric layer.

5. A trench field-effect transistor according to claim 4, characterized in that, The doping concentration of the current shielding layer is greater than 1×10⁻⁶. 19 cm -3 Furthermore, the current shielding layer is doped with a first conductivity type.

6. A trench field-effect transistor according to claim 5, characterized in that, The effective conductive channel length formed in each group of trenches is 0.3μm~2.0μm.

7. A trench field-effect transistor according to claim 5, characterized in that, The depth of the first current-conducting layer at the bottom of the trench is greater than 0.1 μm; and the width of the first current-conducting layer at the non-channel side near the trench sidewall is greater than 0.2 μm.

8. A trench field-effect transistor according to claim 5, characterized in that, The depth of the second current-conducting layer is 0.1~0.2μm.

9. A trench field-effect transistor according to claim 1, characterized in that, It also includes an epitaxial layer, a substrate layer, and a substrate electrode. The epitaxial layer is located on the lower surface of the channel layer, the substrate layer is located on the lower surface of the epitaxial layer, and the substrate electrode is located on the lower surface of the substrate layer. The second current-passing layer is disposed in a manner that does not contact the substrate layer.

10. A trench field-effect transistor according to claim 9, characterized in that, Both the epitaxial layer and the substrate layer are doped with a second conductivity type, which is opposite to the first conductivity type doping.

11. A method for manufacturing a unit cell structure of a trench field-effect transistor, characterized in that, The method for manufacturing a unit cell structure is used to prepare a unit cell structure as described in any one of claims 1-10, consisting of a channel layer, a first current-flow layer, a second current-flow layer, a gate dielectric layer, a gate electrode, an epitaxial layer, a substrate layer, and a substrate electrode, comprising the following steps: Obtain a substrate layer, and form an epitaxial layer on the substrate layer by epitaxial growth; A trench layer is formed on the epitaxial layer by epitaxial growth or ion implantation, and after transferring the trench pattern in the trench layer by photolithography, the trench is formed by etching. A first current-flowing layer is formed by ion implantation at the bottom of the trench and on the trench sidewall region on the non-channel side, and a second current-flowing layer is formed by ion implantation on the trench sidewall region on the channel side of the trench. A grid dielectric layer is formed on the sidewalls and bottom of the trench by thermal oxidation or deposition. A gate electrode is formed in the trench by low-pressure chemical vapor deposition or atomic layer deposition, and the gate electrode covers the gate dielectric layer; The channel layer is doped with a first conductivity type, and both the first current flow layer and the second current flow layer are doped with a second conductivity type opposite to the first conductivity type doping.

12. The method for manufacturing a unit cell structure of a trench field-effect transistor according to claim 11, characterized in that, After forming a first current-passing layer by ion implantation at the bottom of the trench and on the trench sidewall region on the non-channel side, the following steps are also included: A current shielding layer is formed in the sidewall region of the first current flow layer near the trench on the non-channel side by ion sidewall implantation.

13. A method for manufacturing a trench field-effect transistor, characterized in that, The manufacturing method is used to prepare a trench field-effect transistor as described in any one of claims 1-10, and includes the following steps: An epitaxial layer is grown on the substrate layer, and a channel layer is formed by in-situ doping or ion implantation. Trenches are formed in the channel layer by photolithography and etching processes, and a first current flow layer and a second current flow layer are formed sequentially in the trenches by selective ion implantation. A gate dielectric layer is formed in the trench by thermal oxidation or deposition, and a gate electrode is formed by depositing conductive material and photolithography etching. An insulating dielectric layer is formed on the gate electrode, and a first contact region and a second contact layer are formed through the insulating dielectric layer, wherein the first contact region is electrically connected to the first current flow layer and the second current flow layer, and the second contact region is electrically connected to the source side region. A drain electrode is formed on the first contact region, and a source electrode is formed on the second contact region; The drain electrode and source electrode are annealed to form an ohmic contact, and a substrate electrode is formed on the back side of the substrate layer. In this configuration, the source electrode, drain electrode, first contact region, and second contact region are all located on the upper surface of the channel layer. The second contact region is in contact with the sidewall of the first contact region. The source electrode is in contact with the second contact region and a portion of the first contact region, forming an ohmic contact. The drain electrode is in contact with a portion of the first contact region, forming an ohmic contact. The first contact region is in contact with the first current flow layer and also with the second current flow layer. The first contact region, the first current flow layer, and the second current flow layer form a current flow path. The channel layer and the second contact region are both doped with a first conductivity type. The first current flow layer, the second current flow layer, and the first contact region are all doped with a second conductivity type, which is opposite to the first conductivity type doping.

14. The method for manufacturing a trench field-effect transistor according to claim 13, characterized in that, It also includes forming a current shielding layer in the trench through a selective ion implantation process, wherein the second contact area is electrically connected to the current shielding layer or the source-side region.

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