MOSFET device

Abstract

The invention provides an MOSFET device which comprises a first part, a second part and a third part, the first part and the third part are adjacently connected in the first direction, and the second part is located on the third part. The first well region is located in the first part, and the second well region is located in the second part; a first source region, a second source region, a first channel region and a second channel region, the first source region and the first channel region are located in the first well region, the second source region and the second channel region are located in the second well region, and a partial region located on the side, away from the first source region, of the first channel region is arranged in the first part in the first direction; the second part in the second direction is provided with a partial region which is positioned on one side, far away from the second source region, of the second channel region and is in contact with the third part; and the gate structure is located on the first part, the gate structure covers the second source region and the second channel region in the first direction, and the gate structure covers the first source region and the first channel region in the second direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a MOSFET device. Background Art

[0002] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a voltage-controlled device whose core structure consists of a source, gate, drain, and substrate. The gate is isolated from the semiconductor material by an oxide layer, forming a capacitor. When a voltage is applied to the gate, an electric field is generated in the semiconductor material, controlling the current from the source to the drain. This contactless control gives MOSFETs very low on-resistance and high switching speeds.

[0003] MOSFETs mainly include planar gate MOSFETs and trench gate MOSFETs. Currently, planar gate MOSFETs have a higher breakdown voltage than trench gate MOSFETs, ensuring stability and reliability in high-voltage environments. However, their higher specific on-resistance limits their efficiency and current carrying capacity in high-power density applications. On the other hand, trench gate MOSFETs have a lower specific on-resistance than planar gate MOSFETs, and can support higher current densities and lower conduction losses. However, at the edges and bottom of the trenches, due to the uneven distribution of the electric field, local areas may be subjected to excessively high electric field strengths, making premature breakdown more likely to occur.

[0004] Therefore, the MOSFET in the prior art still has the problem of low device performance. Summary of the Invention

[0005] The main purpose of the present application is to provide a MOSFET device to solve the problem in the prior art that the specific on-resistance of the planar gate MOSFET tends to be a bottleneck and is difficult to reduce.

[0006] To achieve the above-mentioned purpose, according to one aspect of the present application, a MOSFET device is provided, comprising: a semiconductor substrate, comprising a first portion, a second portion, and a third portion, the first portion and the third portion being adjacent to each other along a first direction, and the second portion being located on the third portion; a well region, comprising a first well region and a second well region, the first well region being located in the first portion, the second well region being located in the second portion, and the conductivity types of the well region and the semiconductor substrate being opposite; an active region, comprising a first source region, a second source region, a first channel region, and a second channel region, the first source region and the first channel region being located in the first well region, the second source region and the second channel region being located in the second well region, the first portion in the first direction having a partial region located on a side of the first channel region away from the first source region, and the second portion in the second direction having a partial region located on a side of the second channel region away from the second source region and in contact with the third portion, the first direction being perpendicular to the second direction; and a gate structure located on the first portion, the gate structure covering the second source region and the second channel region in the first direction, and covering the first source region and the first channel region in the second direction.

[0007] Optionally, the first well region has a partial region in the first direction that is located on a side of the first source region away from the first channel region.

[0008] Optionally, the MOSFET device also includes: a first electric field shielding region, located in the second part, and in a third direction, the first electric field shielding region is adjacent to the second source region, the second channel region and a partial area in the second part, respectively, the third direction is perpendicular to the first direction and the second direction, respectively, and the first electric field shielding region has an opposite conductivity type to the semiconductor substrate.

[0009] Optionally, the MOSFET device also includes: a second electric field shielding region, located in the second part, and in the third direction, the second electric field shielding region is located on a side away from the first electric field shielding region in a partial area of the second source region, the second channel region and the second part; the first electric field shielding region and the second electric field shielding region have the same conductivity type.

[0010] Optionally, the MOSFET device further includes: a third electric field shielding region located in the third portion, and the third electric field shielding region is connected to the first well region in the first direction and is connected to the first electric field shielding region in the second direction.

[0011] Optionally, the MOSFET device also includes: a third source region located in the first well region, the third source region being connected to the first source region in the first direction; a fourth source region located in the third electric field shielding region, the fourth source region being connected to the third source region in the first direction, and having a partial region in the third part in the third direction being located on the side of the third electric field shielding region away from the fourth source region; a fifth source region located in the second electric field shielding region, the fifth source region being connected to the fourth source region in the second direction, and having a partial region in the second part in the third direction being located on the side of the second electric field shielding region away from the fifth source region.

[0012] Optionally, the MOSFET device further includes: a source metal located on a surface of the second portion away from the third portion, and the source metal covers a portion of the surface where the second source region and the fifth source region are located.

[0013] Optionally, the doping concentration of the first channel region is less than the doping concentration of the first well region; and / or the doping concentration of the second channel region is less than the doping concentration of the second well region.

[0014] Optionally, the doping concentration of the first well region is less than the doping concentration of the second well region.

[0015] Optionally, the doping concentration of the second well region is the same as the doping concentration of a partial region of the first portion in the first direction located on a side of the first channel region away from the first source region.

[0016] Applying the technical solution of the present application, a MOSFET device includes a semiconductor substrate, a well region, an active region, and a gate structure. The well region and the semiconductor substrate have opposite conductivity types. The semiconductor substrate includes a first portion, a second portion, and a third portion. The first and third portions are adjacent along a first direction, and the second portion is located on the third portion. The well region includes a first well region and a second well region. The first well region is located in the first portion, and the second well region is located in the second portion. The active region includes a first source region, a second source region, a first channel region, and a second channel region. The first source region and the first channel region are located in the first well region, and the second source region and the second channel region are located in the second well region. In the first direction, the first portion includes a portion located on the side of the first channel region away from the first source region; in the second direction, the second portion includes a portion located on the side of the second channel region away from the second source region and in contact with the third portion. The first direction is perpendicular to the second direction. The gate structure is located on the first portion. Furthermore, in the first direction, the gate structure covers the second source region and the second channel region; in the second direction, the gate structure covers the first source region and the first channel region. It can be understood that the gate structure is shared by both source regions (the first source region and the second source region) and the channel region (the first channel region and the second channel region) to simultaneously control the first channel region and the second channel region. On this basis, when a forward voltage is applied to the gate structure, the forward voltage between the gate structure and the first source region can cause the majority carriers in the first well region to be depleted, and the minority carriers are attracted to the first channel region by the electric field. Consequently, a first conductive channel is formed in the first channel region when inversion carriers are formed in the first channel region. The forward voltage between the gate structure and the second source region can cause the minority carriers in the second well region to be attracted to the second channel region by the electric field. Consequently, a second conductive channel is formed in the second channel region when inversion carriers are formed in the second channel region. Therefore, compared to traditional planar gate MOSFETs, this application forms a second conductive channel on the sidewall of the gate structure without reducing the cell size, significantly improving the channel density and increasing the effective conductive area of the channel. This allows for more independent channels to conduct current within the same active area, thereby increasing the current path per unit area, reducing the device's specific on-resistance, and improving device performance. In summary, this application solves the bottleneck of further reducing the specific on-resistance of planar gate MOSFETs in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0018] Figure 1 A schematic diagram of a three-dimensional structure of a MOSFET device according to an embodiment of the present application is shown;

[0019] Figure 2 Shown Figure 1 The three-dimensional structure diagram of the MOSFET device after removing the gate structure is shown;

[0020] Figure 3 Shown Figure 2 A top view of the MOSFET device shown;

[0021] Figure 4 Shown Figure 1 The MOSFET device shown along Figure 3 A schematic cross-sectional view of the A1-A2 plane shown;

[0022] Figure 5 Shown Figure 1 The MOSFET devices shown are along Figure 3 A schematic cross-sectional view of the B1-B2 plane shown;

[0023] Figure 6 Shown Figure 1 The MOSFET devices shown are along Figure 3 A schematic cross-sectional view of the C1-C2 plane is shown;

[0024] Figure 7 Shown Figure 1 The MOSFET devices shown are along Figure 3 Schematic cross-sectional view of the D1-D2 plane shown.

[0025] The above drawings include the following reference numerals:

[0026] 10. Substrate; 20. Epitaxial layer; 301. First well region; 302. Second well region; 401. First source region; 402. Second source region; 501. First channel region; 502. Second channel region; 60. Gate structure; 601. Gate oxide layer; 602. Gate; 701. First electric field shield region; 702. Second electric field shield region; 703. Third electric field shield region; 801. Third source region; 802. Fourth source region; 803. Fifth source region; 901. Source metal; 902. Drain metal. DETAILED DESCRIPTION

[0027] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0028] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0029] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0030] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being “on” another element, the element may be directly on the other element or intervening elements may be present. Furthermore, in the specification and claims, when it is described that an element is “connected to” another element, the element may be “directly connected to” the other element or “connected to” the other element through a third element.

[0031] As introduced in the background technology, the planar gate MOSFET in the prior art has a higher breakdown voltage than the trench gate MOSFET, which ensures stability and reliability in high-voltage environments, but its specific on-resistance is higher, which limits the efficiency and current carrying capacity in high-power density applications. On the other hand, the trench gate MOSFET has a lower specific on-resistance than the planar gate MOSFET, which can support higher current density and lower conduction loss. However, at the edge and bottom of the trench, due to the uneven distribution of the electric field, local areas may be subjected to excessively high electric field strength, which makes premature breakdown prone. Therefore, MOSFET still has the problem of low device performance. In order to solve the problem of high specific on-resistance of the planar gate MOSFET in the prior art, the embodiments of the present application provide a MOSFET.

[0032] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0033] like Figure 1 and Figure 2As shown, the present application provides a MOSFET device, comprising: a semiconductor substrate, comprising a first portion, a second portion, and a third portion, wherein the first portion and the third portion are adjacent to each other along a first direction A, and the second portion is located on the third portion; a well region, comprising a first well region 301 and a second well region 302, wherein the first well region 301 is located in the first portion, and the second well region 302 is located in the second portion, and the conductivity types of the well region and the semiconductor substrate are opposite; an active region, comprising a first source region 401, a second source region 402, a first channel region 501, and a second channel region 502, wherein the first source region 401 and the first channel region 501 are located in the first well region 301, The second source region 402 and the second channel region 502 are located in the second well region 302, and in the first direction A, the first part includes a partial area located on the side of the first channel region 501 away from the first source region 401, and in the second direction B, the second part includes a partial area located on the side of the second channel region 502 away from the second source region 402 and in contact with the third part, and the first direction A is perpendicular to the second direction B; the gate structure 60 is located on the first part, and in the first direction A, the gate structure 60 covers the second source region 402 and the second channel region 502, and in the second direction B, the gate structure 60 covers the first source region 401 and the first channel region 501.

[0034] It can be understood that when the above-mentioned first part, second part and third part are corresponded in the three-dimensional coordinate system (XYZ), the first part can be located in the fifth quadrant of the three-dimensional coordinate system (XYZ), the third part can be located in the eighth quadrant of the three-dimensional coordinate system (XYZ), and the second part can be located in the fourth quadrant of the three-dimensional coordinate system (XYZ).

[0035] In some optional embodiments, such as Figure 1 As shown, the semiconductor substrate includes a stacked substrate 10 and an epitaxial layer 20. The substrate 10 includes a portion located in the first portion of the semiconductor substrate and a portion located in the third portion of the semiconductor substrate. The epitaxial layer 20 includes a portion located in the first portion of the semiconductor substrate, a portion located in the second portion of the semiconductor substrate, and a portion located in the third portion of the semiconductor substrate. The substrate 10 has a supporting function, and its material may include, but is not limited to, silicon carbide and diamond. Furthermore, in order to enable the MOSFET device to have low on-resistance and low contact resistance, the doping concentration of the substrate 10 may be heavily doped. In addition, the thickness and doping concentration of the epitaxial layer 20 may be determined according to the device design requirements and are not specifically limited in this application.

[0036] Optionally, the doping ions in the first well region 301 , the second well region 302 , the first channel region 501 and the second channel region 502 independently include but are not limited to aluminum (Al) and boron (B).

[0037] Alternatively, as Figure 1 、 Figure 2 and Figure 3 As shown, the doping ions in the first source region 401 and the second source region 402 independently include but are not limited to nitrogen (N) and phosphorus (P).

[0038] Alternatively, as Figure 1 and Figure 4 、 Figure 5 、 Figure 6 and Figure 7 As shown, the gate structure 60 may include a gate oxide layer 601 and a gate 602, wherein the gate oxide layer 601 is located between the gate 602 and the semiconductor substrate. Furthermore, the material of the gate oxide layer 601 may include, but is not limited to, silicon oxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), and aluminum nitride (AlN), and the thickness of the gate oxide layer 601 may include, but is not limited to, 10 to 1000 nm; the material of the gate 602 may include, but is not limited to, doped polysilicon and silicon carbide, and the dopants therein may include, but are not limited to, phosphorus (P), nitrogen (N), and boron (B). Furthermore, the doping concentration of the dopant in the gate 602 may be 1E18-1E20 cm -3 .

[0039] Alternatively, as Figure 2 As shown, the first portion of the semiconductor substrate has a first surface, a first direction A is parallel to the first surface, and a second direction B is perpendicular to the first surface; the second portion of the semiconductor substrate has a second surface and a third surface opposite to each other, the first direction A is perpendicular to the second surface and the third surface, the second direction B is parallel to the second surface and the third surface, and the first surface and the second surface are adjacent to each other. When the first well region 301 is located in the first portion of the semiconductor substrate and the second well region 302 is located in the second portion of the semiconductor substrate, the first well region 301 extends from the first surface into the first portion of the semiconductor substrate, and the first source region 401 and the first channel region 501 extend from different surface areas of the first surface into the first well region 301; furthermore, the second well region 302 extends from the second surface into the second portion of the semiconductor substrate, and the second source region 402 and the second channel region 502 extend from different surface areas of the second surface into the second well region 302.

[0040] Specifically, combined Figure 2 and Figure 3 As shown, the first source region 401 and the first channel region 501 are adjacently arranged in the first direction A, and the second source region 402 and the second channel region 502 are adjacently arranged in the second direction B.

[0041] Alternatively, as Figure 1 、 Figure 2 and Figure 5As shown, in the first direction A, the first channel region 501 is arranged adjacent to a partial area in the first part of the semiconductor substrate, and in the second direction B, the second channel region 502 is arranged adjacent to a partial area in the second part of the semiconductor substrate that is in contact with the third part, so that when a conductive channel is formed in the first channel region and the second channel region, carriers can enter the partial area in the first part of the semiconductor substrate from the first source region 401 through the first channel region 501 and can enter the partial area in the second part of the semiconductor substrate that is in contact with the third part from the second source region 402 through the second channel region 502, so that the MOSFET is in the on state.

[0042] Optionally, the second portion of the semiconductor substrate includes two adjacent first sub-portions and a second sub-portion, and the first sub-portion is located between the second sub-portion and the third portion of the semiconductor substrate in the second direction B. On this basis, as Figure 1 、 Figure 2 and Figure 5 As shown, in the case where the second well region 302 is located in the second part of the semiconductor body, the second well region 302 can extend from the surface of the second sub-part located in the second surface to the surface of the second sub-part located in the third surface; the second sub-part located in the second surface may include adjacent first and second sub-regions, and in the second direction B, the second sub-region is located between the first sub-region and the surface of the first sub-part located in the second surface. In the case where the second source region 402 and the second channel region 502 are located in the second well region 302, the second source region 402 can extend from the first sub-region to the second sub-part, and the second channel region 502 can extend from the second sub-region to the second sub-part.

[0043] Specifically, the conductivity types of the first part of the semiconductor substrate, the second part of the semiconductor substrate and the third part of the semiconductor substrate can be the same; the conductivity types of the first well region 301 and the second well region 302 can be the same; the conductivity types of the first source region 401 and the second source region 402 can be the same; and the conductivity types of the first channel region 501 and the second channel region 502 can be the same.

[0044] Specifically, the first part of the semiconductor substrate can have a different conductivity type from the first well region 301 and the second well region 302, respectively; the second part of the semiconductor substrate can have a different conductivity type from the first well region 301 and the second well region 302, respectively; and the third part of the semiconductor substrate can have a different conductivity type from the first well region 301 and the second well region 302, respectively.

[0045] Specifically, the first source region 401 may have the same conductivity type as the first portion of the semiconductor body, the second portion of the semiconductor body, and the third portion of the semiconductor body, respectively.

[0046] Specifically, the first channel region 501 may have the same conductivity type as the first well region 301 and the second well region 302 .

[0047] In summary, it can be understood that the gate structure 60 in the above embodiment is shared by both source regions (the first source region 401 and the second source region 402) and the channel region (the first channel region 501 and the second channel region 502), thereby simultaneously controlling the first channel region 501 and the second channel region 502. Based on this, when a forward voltage is applied to the gate structure 60, the forward voltage between the gate structure 60 and the first source region 401 can cause the majority carriers in the first well region 301 to be depleted, and the minority carriers are attracted to the first channel region 501 by the electric field. Consequently, when inversion carriers are formed in the first channel region 501, a first conductive channel is formed in the first channel region 501. Furthermore, the forward voltage between the gate structure 60 and the second source region 402 can cause the minority carriers in the second well region 302 to be attracted to the second channel region 502 by the electric field. Consequently, when inversion carriers are formed in the second channel region 502, a second conductive channel is formed in the second channel region 502. Therefore, compared to traditional planar gate MOSFETs, the present application forms a second conductive channel on the sidewall of the gate structure 60 without reducing the cell size, significantly improving the channel density and increasing the effective conductive area of the channel. This allows for more independent channels to conduct current within the same active area, thereby increasing the current path per unit area, reducing the device's specific on-resistance, and improving device performance. In summary, the present application solves the bottleneck of the prior art planar gate MOSFET's difficulty in further reducing its specific on-resistance.

[0048] In some optional embodiments, such as Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 and Figure 6 As shown, the first well region 301 includes a partial region located on the side of the first source region 401 away from the first channel region 501 in the first direction A. Furthermore, ion implantation can be performed in the partial region of the first well region 301 located on the side of the first source region 401 away from the first channel region 501 in the first direction A, so that the doping concentration of the partial region is consistent with the doping concentration of the second well region 302 and is connected to the second well region 302. It can be understood that the partial region of the first well region 301 located on the side of the first source region 401 away from the first channel region 501 in the first direction A can serve as an electric field shielding region to prevent electric field concentration at the gate corner.

[0049] In the above embodiment, the third part of the semiconductor substrate in the first direction A may include a partial area located on the side of the first source region 401 away from the first channel region 501. By retaining a partial area of the first well region 301 in the first direction A on the side of the first source region 401 away from the first channel region 501, the partial area in the first well region 301 can be used to isolate the first source region 401 and the third part of the semiconductor substrate, thereby effectively preventing the first source region 401 and the third part of the semiconductor substrate from forming a conductive path. Further, when the MOSFET device is turned off, the problem of high leakage current affecting the blocking capability and overall performance of the device due to direct contact between the first source region 401 and the third part of the semiconductor substrate can be improved.

[0050] It should be noted that if Figure 5 As shown, a partial area of the first well region 301 located on the side of the first source region 401 away from the first channel region 501 in the first direction A is also adjacent to a partial area in the second part of the semiconductor substrate in the second direction B that is in contact with the third part of the semiconductor substrate, so that the partial area of the first well region 301 located on the side of the first source region 401 away from the first channel region 501 in the first direction A can isolate the partial area in the second part of the semiconductor substrate in the second direction B that is in contact with the third part of the semiconductor substrate from the first source region 401, thereby effectively preventing the first source region 401 and the second part of the semiconductor substrate from forming a conductive path, and further, when the MOSFET device is turned off, the problem of high leakage current caused by direct contact between the first source region 401 and the second part of the semiconductor substrate affecting the blocking capability and overall performance of the device can be improved.

[0051] In some optional embodiments, such as Figure 1 、 Figure 2 、 Figure 3 and Figure 4 As shown, the MOSFET device also includes: a first electric field shielding region 701, which is located in the second part of the semiconductor substrate, and in the third direction C, the first electric field shielding region 701 is adjacent to the second source region 402, the second channel region 502 and a partial area in the second part of the semiconductor substrate, respectively. The third direction C is perpendicular to the first direction A and the second direction B, respectively. The conductivity type of the first electric field shielding region 701 is opposite to that of the semiconductor substrate.

[0052] Specifically, the conductivity type of the first electric field shielding region 701 is opposite to the conductivity types of the first portion of the semiconductor body, the second portion of the semiconductor body, and the third portion of the semiconductor body.

[0053] Optionally, the third direction C is also parallel to the first surface, the second surface and the third surface respectively.

[0054] In the above embodiment, the adjacent first electric field shielding region 701 and a partial area in the second part can form a PN junction, so that when the MOSFET device is turned off, a depletion region will be formed between the first electric field shielding region 701 and a partial area in the second part. The depletion region will force the electric field lines to bypass the depletion region, thereby transferring the gate corner electric field to the edge of the depletion region, effectively preventing the gate corner electric field from concentrating, thereby making the device have a higher breakdown voltage and improving the stability and reliability of the device in a high-voltage environment.

[0055] Alternatively, as Figure 2 and Figure 3 As shown, the first electric field shielding region 701 is connected to the second well region 302 in the first direction A, and the conductivity type of the first electric field shielding region 701 is the same as the conductivity type of the second well region 302. Furthermore, the doping concentration of the first electric field shielding region 701 can be the same as the doping concentration of the second well region 302. In this embodiment, the side surface of the second well region 302 away from the first electric field shielding region 701 in the second portion of the semiconductor substrate and the side surface of the first electric field shielding region 701 away from the second channel region 502 can both be device surfaces. Therefore, it can be understood that after the first electric field shielding region 701 and the second well region 302 are connected, the first electric field shielding region 701 and the second well region 302 can absorb and redistribute the electric field, reducing the surface electric field strength of the device and guiding the surface electric field strength to the middle portion of the device (the portion of the second portion of the semiconductor substrate located on the side of the second channel region 502 away from the second source region 402 and in contact with the third portion of the semiconductor substrate), thereby further improving the breakdown voltage of the device and enhancing the withstand voltage capability of the device.

[0056] Alternatively, as Figure 1 、 Figure 2 and Figure 3 As shown, the first electric field shielding region 701 is also connected to a portion of the first well region 301 located on the side of the first source region 401 away from the first channel region 501. In this embodiment, a portion of the first well region 301 located on the side of the first source region 401 away from the first channel region 501 can also serve as an electric field shielding region. Therefore, after the first electric field shielding region 701 is connected to the portion of the first well region 301 located on the side of the first source region 401 away from the first channel region 501, the surface electric field of the device can be guided to a deeper portion of the device, further improving the concentration of the surface electric field, further increasing the breakdown voltage of the device, and enhancing the withstand voltage capability of the device.

[0057] In some optional embodiments, such as Figure 1 、 Figure 2 、 Figure 3 and Figure 6As shown, the MOSFET device further includes: a second electric field shielding region 702, which is located in the second part, and in the third direction C, the second electric field shielding region 702 is located on a side of the second source region 402 away from the first electric field shielding region 701, a side of the second channel region 502 away from the first electric field shielding region 701, and a side of a portion of the second part of the semiconductor body away from the first electric field shielding region 701; the first electric field shielding region 701 and the second electric field shielding region 702 have the same conductivity type.

[0058] Specifically, in the third direction C, the second electric field shielding region 702 is adjacent to the second source region 402 , the second channel region 502 , and a portion of the second portion.

[0059] In the above embodiment, the adjacent second electric field shielding region 702 and a partial area in the second part can form a PN junction, so that when the MOSFET device is turned off, a depletion region will be formed between the second electric field shielding region 702 and a partial area in the second part. The depletion region will force the electric field lines to bypass the depletion region, thereby transferring the gate corner electric field to the edge of the depletion region, effectively preventing the gate corner electric field from concentrating, thereby making the device have a higher breakdown voltage and improving the stability and reliability of the device in a high-voltage environment.

[0060] Optionally, the second electric field shielding region 702 is connected to the second well region 302 in the first direction A, and the conductivity type of the second electric field shielding region 702 is the same as that of the second well region 302. Furthermore, the doping concentration of the second electric field shielding region 702 may be the same as that of the second well region 302. In this embodiment, the side surface of the second well region 302 away from the second electric field shielding region 702 in the second part of the semiconductor substrate and the side surface of the second electric field shielding region 702 away from the second channel region 502 can both be device surfaces. Therefore, it can be understood that after the second electric field shielding region 702 and the second well region 302 are connected, the second electric field shielding region 702 and the second well region 302 can both absorb and redistribute the electric field, reduce the surface electric field strength of the device, and thus guide the surface electric field strength to the middle part of the device (the partial area in the second part of the semiconductor substrate located on the side of the second channel region 502 away from the second source region 402 and in contact with the third part of the semiconductor substrate), thereby further improving the breakdown voltage of the device and enhancing the voltage resistance of the device.

[0061] Alternatively, as Figure 2 and Figure 3As shown, a portion of the first well region 301 located on the side of the first source region 401 away from the first channel region 501 is further connected to the first electric field shielding region 701 and the second electric field shielding region 702. In this embodiment, a portion of the first well region 301 located on the side of the first source region 401 away from the first channel region 501 can also serve as an electric field shielding region. Thus, after the first electric field shielding region 701 is connected to a portion of the first well region 301 located on the side of the first source region 401 away from the first channel region 501, and the second electric field shielding region 702 is connected to a portion of the first well region 301 located on the side of the first source region 401 away from the first channel region 501, the surface electric field of the device can be guided to a deeper portion of the device, thereby further improving the concentration of the surface electric field, further increasing the breakdown voltage of the device, and enhancing the withstand voltage capability of the device.

[0062] In some optional embodiments, combined with Figure 1 、 Figure 2 、 Figure 4 、 Figure 6 and Figure 7 As shown, the MOSFET device further includes: a third electric field shielding region 703 located in the third portion of the semiconductor body, and the third electric field shielding region 703 is connected to the first well region 301 in the first direction A, and is connected to the first electric field shielding region 701 in the second direction B.

[0063] Specifically, the third electric field shielding region 703 and the first electric field shielding region 701 may have the same conductivity type.

[0064] In the above embodiment, the adjacent third electric field shielding region 703 and a partial area in the third part of the semiconductor substrate can form a PN junction, so that when the MOSFET device is turned off, a depletion region will be formed between the third electric field shielding region 703 and a partial area in the third part of the semiconductor substrate. The depletion region will force the electric field lines to bypass the depletion region, thereby transferring the gate corner electric field to the edge of the depletion region, effectively preventing the gate corner electric field from concentrating, thereby making the device have a higher breakdown voltage and improving the stability and reliability of the device in a high-voltage environment.

[0065] Optionally, in order to form a conductive channel in the second channel region 502 and enable the MOSFET device to be in a conductive state after carriers pass through the second channel region 502 and enter a partial region of the second portion of the semiconductor substrate, the third electric field shielding region 703 includes a first sub-electric field shielding region and a second sub-electric field shielding region spaced apart in the third direction C. A partial region of the third portion in the third direction C is located between the first sub-electric field shielding region and the second sub-electric field shielding region, and a partial region of the third portion located between the first sub-electric field shielding region and the second sub-electric field shielding region in the third direction C is connected to a partial region of the second portion in the second direction B. Furthermore, in the first direction A, a partial region of the first well region 301 located on a side of the first source region 401 away from the first channel region 501 can be connected to the first sub-electric field shielding region and the second sub-electric field shielding region, respectively. In the second direction B, the third electric field shielding region 703 can also be connected to the second electric field shielding region 702. Further, in the second direction B, the first sub-electric field shielding region may be connected to the first electric field shielding region 701 , and the second sub-electric field shielding region may be connected to the second electric field shielding region 702 .

[0066] Optionally, in order to form a stable charge distribution when the third electric field shielding region 703 is connected to the first electric field shielding region 701 and the second electric field shielding region 702, respectively, the third electric field shielding region 703 includes a third sub-electric field shielding region and a fourth sub-electric field shielding region in the second direction B, and the second electric field shielding region 702 is connected to the fourth sub-electric field shielding region through the third sub-electric field shielding region, and the first electric field shielding region 701 is connected to the fourth sub-electric field shielding region through the third sub-electric field shielding region. Furthermore, the conductivity type of the third sub-electric field shielding region and the conductivity type of the fourth sub-electric field shielding region can be the same. Furthermore, the doping concentration of the third sub-electric field shielding region can be greater than the doping concentration of the fourth sub-electric field shielding region. Furthermore, the doping concentration of the third sub-electric field shielding region is the same as the doping concentration of the second well region 302, and the doping concentration of the fourth sub-electric field shielding region is the same as the doping concentration of the first well region 301. This helps maintain a uniform electric field around the second channel region 502, further improving the breakdown voltage of the device.

[0067] Combine Figures 1 to 7As shown, when the MOSFET device includes the above-mentioned first electric field shielding region 701, second electric field shielding region 702 and third electric field shielding region 703 at the same time, the first well region 301, the second well region 302, the first electric field shielding region 701, the second electric field shielding region 702 and the third electric field shielding region 703 can be connected. Among them, since the second source region 402, the second channel region 502 and the partial area of the second part of the semiconductor substrate are adjacent to the first electric field shielding region 701 and the second electric field shielding region 702 on opposite sides in the third direction C, and the third electric field shielding region 703 is adjacent to the partial area of the third part of the semiconductor substrate, when the MOSFET device is turned off, the depletion region between the first electric field shielding region 701 and the partial area of the second part of the semiconductor substrate, the depletion region between the second electric field shielding region 702 and the partial area of the second part of the semiconductor substrate, and the depletion region between the third electric field shielding region 703 and the third part of the semiconductor substrate can disperse the electric fields at different gate angles, that is, the MOSFET device in this embodiment can have multi-dimensional electric field shielding regions, and the multi-dimensional electric field shielding regions can more effectively prevent the electric field concentration at the gate angle, thereby further improving the breakdown voltage of the device, so as to further improve the stability and reliability of the device in a high-voltage environment.

[0068] Further, combined with Figures 1 to 7As shown, a longer channel length helps to disperse the current, reduce local heat and voltage drop, and thus support a higher current density under certain conditions, and a shorter channel length helps to reduce the on-resistance of the device. Therefore, in order to maintain a higher current density while reducing the on-resistance of the device, the channel lengths of the first channel region 501 and the second channel region 502 can be 0.3~0.8μm; the channel width of the first channel region 501 can be the same as the length of the MOSFET cell in the third direction C, and the third direction C is perpendicular to the first direction A and the second direction B respectively. The channel width of the second channel region 502 can be 1~5μm. By setting the channel width of the second channel region 502 to be greater than or equal to 1, the current density of the device can be improved. By Setting the width to less than 5 can increase the area of the first electric field shielding region 701 and the second electric field shielding region 702 in the second portion, thereby helping to prevent electric field concentration at the gate. Since the smaller the distance between the channel region and the electric field shielding region, the better the protection of the gate corner by the electric field shielding region, and the larger the size of the portion of the second portion located on the side of the second source region 402 away from the second channel region 502 in a direction perpendicular to the first surface, the lower the resistance of the device. Therefore, to strike a balance between the on-resistance of the device and the protection of the gate corner by the electric field shielding region, the length of the portion of the second portion of the semiconductor body located on the side of the second channel region 502 away from the second source region 402 and in contact with the third portion of the semiconductor body in the second direction B can be 0.2 to 1 μm in the second direction B. It will be understood that the channel length direction of the first channel region 501 is parallel to the first direction A, and the channel length direction of the second channel region 502 is parallel to the second direction B.

[0069] In some optional embodiments, combined with Figure 2 、 Figure 3 and Figure 7 As shown, the MOSFET device also includes: a third source region 801, located in the first well region 301, and connected to the first source region 401 in the first direction A; a fourth source region 802, located in the third electric field shielding region 703, and connected to the third source region 801 in the first direction A, and having a partial area on the side of the third electric field shielding region 703 away from the fourth source region 802 in the third part of the semiconductor substrate in the third direction C; a fifth source region 803, located in the second electric field shielding region 702, and connected to the fourth source region 802 in the second direction B, and having a partial area on the side of the second electric field shielding region 702 away from the fifth source region 803 in the second part of the semiconductor substrate in the third direction C.

[0070] Specifically, the second portion of the semiconductor substrate may have a fourth surface, which is the surface of the second portion of the semiconductor substrate on a side away from the third portion of the semiconductor substrate. The second electric field shielding region 702 is located in the second portion of the semiconductor substrate, and the fifth source region 803 is located in the second electric field shielding region 702, so that the fifth source region 803 is located in the second portion of the semiconductor substrate. The second well region 302 is located in the second portion of the semiconductor substrate, and the second source region 402 is located in the second well region 302, so that the second source region 402 is located in the second portion of the semiconductor substrate. Based on this, the second source region 402 can have a first preset area in the fourth surface, and the fifth source region 803 can have a second preset area in the fourth surface, where the first preset area and the second preset area are different.

[0071] Optionally, the third source region 801 and the second portion of the semiconductor substrate, as well as the third source region 801 and the third portion of the semiconductor substrate, are isolated by a partial region of the first well region 301 located on a side of the first source region 401 away from the first channel region 501. In this embodiment, this partial region of the first well region 301 can effectively prevent the third source region 801 from forming a conductive path with the second portion of the semiconductor substrate, and can effectively prevent the third source region 801 from forming a conductive path with the third portion of the semiconductor substrate. This can alleviate the problem of high leakage current affecting the blocking capability and overall performance of the device due to direct contact between the third source region 801 and the second portion of the semiconductor substrate and the third portion of the semiconductor substrate, respectively, when the MOSFET is turned off.

[0072] In some optional embodiments, combined with Figure 2 、 Figure 3 and Figure 7 As shown, since the fifth source region 803 is located in the second electric field shielding region 702, the second sub-electric field shielding region is connected to the second electric field shielding region 702. When the third electric field shielding region 703 includes the first sub-electric field shielding region and the second sub-electric field shielding region, the fourth source region 802 can be located in the second sub-electric field shielding region. Thus, in this embodiment, the first source region 401, the third source region 801, the fourth source region 802, and the fifth source region 803 can be connected in sequence. Furthermore, when the fifth source region 803 has the second predetermined area on the fourth surface, the source connection portion of the first source region 401 can be drawn out.

[0073] Optionally, combined Figures 1 to 7As shown, in the third direction C, a portion of the third electric field shielding region 703 is located between the fourth source region 802 and a portion of the third portion of the semiconductor body that contacts the second portion of the semiconductor body in the second direction B, and this portion of the third electric field shielding region 703 is adjacent to a portion of the second portion in the third direction C. Therefore, in this embodiment, this portion of the third electric field shielding region 703 can effectively prevent the fourth source region 802 from forming a conductive path with a portion of the second portion of the semiconductor body that contacts the third portion, and can achieve isolation between the portion of the third portion and the fourth source region 802, effectively preventing the fourth source region 802 from forming a conductive path with the third portion of the semiconductor body. This can improve the problem of high leakage current affecting the device's blocking capability and overall performance due to direct contact between the fourth source region 802 and the second portion of the semiconductor body, and the problem of high leakage current affecting the device's blocking capability and overall performance due to direct contact between the fourth source region 802 and the third portion of the semiconductor body when the MOSFET device is turned off.

[0074] Similarly, combined Figures 1 to 7 As shown, since the second electric field shielding region 702 in the third direction C has a partial area between the fifth source region 803 and the partial area in the second part of the semiconductor substrate in the second direction B on the side of the second channel region 502 away from the second source region 402, isolation between the partial area in the second part of the semiconductor substrate in the second direction B on the side of the second channel region 502 away from the second source region 402 and the fifth source region 803 can be achieved, effectively preventing the fifth source region 803 and the second part from forming a conductive path, and thus when the MOSFET device is turned off, the problem of high leakage current affecting the blocking capability and overall performance of the device due to direct contact between the fifth source region 803 and the second part of the semiconductor substrate can be improved.

[0075] Similarly, the doping ions in the third source region 801, the fourth source region 802, and the fifth source region 803 may independently include, but are not limited to, nitrogen (N) and phosphorus (P). Optionally, the doping concentration of the doping ions in the first source region 401, the second source region 402, the third source region 801, the fourth source region 802, and the fifth source region 803 may be, but are not limited to, 1E18-1E21 cm -3 .

[0076] In the above embodiment, combined Figure 1 、 Figure 2 、 Figure 3 and Figure 7As shown, since the third source region 801 is connected to the first source region 401, the fourth source region 802 is connected to the third source region 801, and the fifth source region 803 is connected to the fourth source region 802, and the fifth source region 803 and the second source region 402 can have independent preset areas in the fourth surface of the second part of the semiconductor substrate, the first source region 401 and the second source region 402 in this embodiment can both realize source connection on the fourth surface, which facilitates the formation of the source metal 901 of the MOSFET device.

[0077] In some optional embodiments, such as Figure 1 As shown, the MOSFET device further includes: a source metal 901 located on the surface of the second portion away from the third portion, and the source metal 901 covers a portion of the surface where the second source region 402 and the fifth source region 803 are located.

[0078] Alternatively, as Figure 1 As shown, the above-mentioned source metal 901 also covers a portion of the surface of the second well region 302 located on the side of the second part of the semiconductor substrate away from the third part of the semiconductor substrate. It can be understood that the source metal 901 covering the second well region 302 increases the contact area between the metal and the semiconductor, thereby reducing the contact resistance per unit area.

[0079] Optionally, the material of the source metal 901 includes but is not limited to titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), etc.

[0080] In the above embodiment, since the source metal 901 respectively covers part of the surface of the second source region 402 and the fifth source region 803 located on the side of the third part of the second part away from the semiconductor substrate, the current can be more evenly distributed between the first channel region 501 and the second channel region 502, thereby improving the overall current carrying capacity.

[0081] In some optional embodiments, the doping concentration of the first channel region 501 is less than the doping concentration of the first well region 301; and / or the doping concentration of the second channel region 502 is less than the doping concentration of the second well region 302. Optionally, the doping concentration of the doping ions in the first well region 301 is selected from 1E18-1E20 cm -3 The doping concentration of the doping ions in the second well region 302 is selected from 1E19-1E21 cm -3 The doping concentration of the doping ions in the first channel region 501 and the second channel region 502 is selected to be 1E17-1E21cm -3 .

[0082] In the above embodiment, because the doping concentrations of the first and second channel regions 501 and 502 are lower than those of the first and second well regions 301 and 302, the initial concentration of free charge carriers (electrons for the N-channel) in the semiconductor region below the gate structure 60 is lower. A lower initial electron concentration results in a larger potential barrier (i.e., a higher gate voltage) that must be overcome before the gate voltage generates a sufficiently strong electric field to form an effective conductive channel. Therefore, the threshold voltage of the device is increased through the above embodiment.

[0083] In some optional embodiments, the doping concentration of the first well region 301 is less than the doping concentration of the second well region 302 .

[0084] In the above embodiment, the first well region 301 with a relatively low doping concentration can reduce the storage effect of carriers during the switching process of the MOSFET device, thereby accelerating the switching time and improving the frequency response of the device. The second well region 302 with a relatively high doping concentration can ensure that a stable current path is formed in the second channel region 502 when the MOSFET device is in the on state, reducing the impact of gate voltage fluctuations on the MOSFET current output.

[0085] It should be noted that the high doping concentration of the second well region 302 means that the semiconductor material in this region has a high conductivity. Furthermore, when the source metal 901 directly contacts the second well region 302, the ohmic resistance from the source to the second channel region 502 can be significantly reduced, which further means that the voltage drop during current conduction is reduced, and the efficiency of the device in the on state is higher.

[0086] In order to ensure the consistency of the electrical performance of the device in different directions and improve the overall performance of the device, in some optional embodiments, the doping concentration of the second well region 302 is the same as the doping concentration of a partial area in the first part of the semiconductor substrate in the first direction A located on the side of the first channel region 501 away from the first source region 401.

[0087] In addition, if Figure 1 、 Figure 2 as well as Figures 4 to 7 As shown, the MOSFET device further includes a drain metal 902, which is located on a side of the semiconductor substrate away from the gate structure 60. Furthermore, the material of the drain metal 902 may include, but is not limited to, titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au).

[0088] According to one embodiment of the present application, a specific method for forming a MOSFET device is provided, comprising the following steps:

[0089] First, a stacked substrate and an epitaxial layer are provided, and then multiple ion implantations are performed on the side of the epitaxial layer facing away from the substrate to form a second well region, a first electric field shielding region, a second electric field shielding region, a third electric field shielding region, a second source region, a second channel region, a fourth source region and a fifth source region.

[0090] Secondly, the epitaxial layer is etched to form a groove in the surface of the epitaxial layer facing away from the substrate, and the remaining substrate and epitaxial layer form a semiconductor base, which includes a first part, a second part and a third part, and the first part and the third part are adjacent along a first direction, and the second part is located on the third part. Among them, the second well region is located in the second part, the second source region and the second channel region are located in the second well region, and in the second direction, the second part has a partial area located on the side of the second channel region away from the second source region and in contact with the third part; the first electric field shielding region is located in the second part, and in the third direction, the first electric field shielding region is adjacent to the second source region, the second channel region, and the partial area in the second part respectively; the second electric field shielding region is located in the second part, and in the third direction, the second electric field shielding region is located on the side of the second source region, the second channel region, and the partial area in the second part away from the first electric field shielding region; the third electric field shielding region is located in the third part, and in the second direction, the third electric field shielding region is connected with the first electric field shielding region; the fourth source region is located in the third electric field shielding region; the fifth source region is located in the second electric field shielding region, and in the second direction, the fifth source region is connected with the fourth source region, and in the third direction, the second part has a partial area located on the side of the second electric field shielding region away from the fifth source region.

[0091] Next, multiple ion implantations are performed in the first portion to form a first well region, a first source region, a first channel region, and a third source region. The first well region is located in the first portion; the first source region and the first channel region are located in the first well region, with a portion of the first portion located on a side of the first channel region away from the first source region in the first direction, and a portion of the first well region located on a side of the first source region away from the first channel region in the first direction; the third electric field shield region is connected to the first well region in the first direction; the third source region is located in the first well region, with the third source region connected to the first source region in the first direction, and the fourth source region is connected to the third source region in the first direction.

[0092] Then, a gate structure is formed in the groove so that the gate structure is located on the first part, and the gate structure covers the second source region and the second channel region in the first direction, and covers the first source region and the first channel region in the second direction; a source metal is formed on the surface of the second part away from the third part, and the source metal covers the part of the surface where the second source region and the fifth source region are located; a drain metal is formed on the side of the semiconductor substrate away from the gate structure.

[0093] According to another embodiment of the present application, a specific method for forming a MOSFET device is provided, comprising the following steps:

[0094] On the basis of the planar gate MOSFET, a secondary epitaxial growth is performed on the non-gate structure area, and then multiple ion implantations are performed on the secondary epitaxial part to form the above-mentioned MOSFET device.

[0095] It can be understood that the planar gate MOSFET may include a first portion, a third portion, a first well region, a first source region, a first channel region, a third source region, and a gate structure in a semiconductor substrate. The first portion and the third portion are adjacent to each other along a first direction, the first well region is located in the first portion, the first source region and the first channel region are located in the first well region, the first portion has a partial region located on a side of the first channel region away from the first source region in the first direction, the first well region has a partial region located on a side of the first source region away from the first channel region in the first direction, the third source region is located in the first well region, the third source region is connected to the first source region in the first direction, the gate structure is located on the first portion, and the gate structure covers the first source region and the first channel region in the second direction.

[0096] The non-gate structure region is the third portion of the MOSFET device. A second epitaxial growth is performed on the non-gate structure region to obtain the second portion of the MOSFET device. Multiple ion implantation of the second epitaxial portion is equivalent to multiple ion implantation of the second portion to form the MOSFET device. It is understood that after multiple ion implantation of the second portion, the MOSFET device further includes a second well region, a second source region, a second channel region, a first electric field shield region, a second electric field shield region, a third electric field shield region, a fourth source region, and a fifth source region. The second well region is located in the second part, the second source region and the second channel region are located in the second well region, and in the second direction, the second part has a partial region located on a side of the second channel region away from the second source region and in contact with the third part. The first electric field shielding region is located in the second part, and in the third direction, the first electric field shielding region is adjacent to the second source region, the second channel region, and a partial region in the second part, respectively. The second electric field shielding region is located in the second part, and in the third direction, the second electric field shielding region is located on a side of a partial region in the second source region, the second channel region, and the second part away from the first electric field shielding region. The third electric field shielding region is located in the third part. The third electric field shielding region is connected to the first well region in the first direction, and is connected to the first electric field shielding region in the second direction. The fourth source region is located in the third electric field shielding region, and is connected to the third source region in the first direction. In the third part in the third direction, there is a partial area located on the side of the third electric field shielding region away from the fourth source region. The fifth source region is located in the second electric field shielding region, and is connected to the fourth source region in the second direction. In the second part in the third direction, there is a partial area located on the side of the second electric field shielding region away from the fifth source region. The gate structure covers the second source region and the second channel region in the first direction.

[0097] In addition, the above-mentioned MOSFET device also includes source metal and drain metal. The source metal can be formed on the surface of the second part away from the third part, and the source metal covers the portion of the surface where the second source region and the fifth source region are located; the drain metal is formed on the side of the semiconductor substrate away from the gate structure.

[0098] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0099] Applying the technical solution of the present application, a MOSFET device includes a semiconductor substrate, a well region, an active region, and a gate structure. The well region and the semiconductor substrate have opposite conductivity types. The semiconductor substrate includes a first portion, a second portion, and a third portion. The first and third portions are adjacent along a first direction, and the second portion is located on the third portion. The well region includes a first well region and a second well region. The first well region is located in the first portion, and the second well region is located in the second portion. The active region includes a first source region, a second source region, a first channel region, and a second channel region. The first source region and the first channel region are located in the first well region, and the second source region and the second channel region are located in the second well region. In the first direction, the first portion includes a portion located on the side of the first channel region away from the first source region; in the second direction, the second portion includes a portion located on the side of the second channel region away from the second source region and in contact with the third portion. The first direction is perpendicular to the second direction. The gate structure is located on the first portion. Furthermore, in the first direction, the gate structure covers the second source region and the second channel region; in the second direction, the gate structure covers the first source region and the first channel region. It can be understood that the gate structure is shared by the two source regions (the first source region and the second source region) and the channel regions (the first channel region and the second channel region) in both the first and second directions, thereby simultaneously controlling the first and second channel regions. On this basis, when a forward voltage is applied to the gate structure, the forward voltage between the gate structure and the first source region can cause the majority carriers in the first well region to be depleted, and the minority carriers are attracted to the first channel region by the electric field. Consequently, a first conductive channel is formed in the first channel region when inversion carriers are formed in the first channel region. The forward voltage between the gate structure and the second source region can cause the minority carriers in the second well region to be attracted to the second channel region by the electric field. Consequently, a second conductive channel is formed in the second channel region when inversion carriers are formed in the second channel region. Therefore, compared to traditional planar gate MOSFETs, this application forms a second conductive channel on the sidewall of the gate structure without reducing the cell size, significantly improving the channel density and increasing the effective conductive area of the channel. This allows for more independent channels to conduct current within the same active area, thereby increasing the current path per unit area, reducing the device's specific on-resistance, and improving device performance. In summary, this application solves the bottleneck of the prior art planar gate MOSFET's difficulty in further reducing its specific on-resistance.

[0100] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A MOSFET device, characterized in that: include: A semiconductor body comprising a first portion, a second portion and a third portion, wherein the first portion and the third portion are adjacent to each other along a first direction, and the second portion is located on the third portion; a well region, comprising a first well region and a second well region, wherein the first well region is located in the first portion, the second well region is located in the second portion, and the conductivity types of the well region and the semiconductor substrate are opposite; an active region, comprising a first source region, a second source region, a first channel region, and a second channel region, wherein the first source region and the first channel region are located in the first well region, and the second source region and the second channel region are located in the second well region; in the first direction, the first portion includes a partial region located on a side of the first channel region away from the first source region, and in the second direction, the second portion includes a partial region located on a side of the second channel region away from the second source region and in contact with the third portion; and the first direction is perpendicular to the second direction; A gate structure is located on the first portion, and covers the second source region and the second channel region in the first direction, and covers the first source region and the first channel region in the second direction.

2. The MOSFET device according to claim 1, wherein The first well region includes a partial area located on a side of the first source region away from the first channel region in the first direction.

3. The MOSFET device according to claim 1, wherein The MOSFET device further comprises: A first electric field shielding region is located in the second part, and in a third direction, the first electric field shielding region is adjacent to the second source region, the second channel region and a partial area in the second part, respectively. The third direction is perpendicular to the first direction and the second direction, respectively. The first electric field shielding region has a conductivity type opposite to that of the semiconductor base.

4. The MOSFET device according to claim 3, wherein: The MOSFET device further comprises: a second electric field shielding region, located in the second portion, and in the third direction, located on a side of the second source region, the second channel region, and a portion of the second portion away from the first electric field shielding region; The first electric field shielding region and the second electric field shielding region have the same conductivity type.

5. The MOSFET device according to claim 3, wherein: The MOSFET device further comprises: The third electric field shielding region is located in the third portion and is connected to the first well region in the first direction and is connected to the first electric field shielding region in the second direction.

6. The MOSFET device according to claim 5, characterized in that The MOSFET device further comprises: a third source region, located in the first well region, and connected to the first source region in the first direction; a fourth source region located in the third electric field shielding region, the fourth source region being connected to the third source region in the first direction, and the third portion having a partial region located on a side of the third electric field shielding region away from the fourth source region in the third direction; The fifth source region is located in the second electric field shielding region. The fifth source region is connected to the fourth source region in the second direction. In the second part in the third direction, there is a partial area located on the side of the second electric field shielding region away from the fifth source region.

7. The MOSFET device according to claim 6, wherein: The MOSFET device further comprises: A source metal is located on a surface of the second portion away from the third portion, and the source metal covers a portion of the surface of the second source region and the fifth source region located on the surface.

8. The MOSFET device according to any one of claims 1 to 7, characterized in that The doping concentration of the first channel region is lower than the doping concentration of the first well region; and / or, The doping concentration of the second channel region is lower than the doping concentration of the second well region.

9. The MOSFET device according to any one of claims 1 to 7, wherein: The doping concentration of the first well region is lower than the doping concentration of the second well region.

10. The MOSFET device according to any one of claims 1 to 7, characterized in that The doping concentration of the second well region is the same as the doping concentration of a portion of the first portion in the first direction located on a side of the first channel region away from the first source region.

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