I2C interface circuit and chip

Abstract

The invention provides an I2C interface circuit and a chip. The I2C interface circuit is characterized in that a first end of a first switch module is connected to a grounding voltage; one end of the second switch module is connected with the control end of the first switch module, and the second switch module is switched off under the condition that the first switch module is switched on and switched on under the condition that the first switch module is switched off; one end of the third switch module is connected with the power supply voltage, the other end is connected with the other end of the second switch module, and the third switch module is conducted along with the conduction of the first switch module; one end of the fourth switch module is connected with the power supply voltage, and the fourth switch module is used for being switched on along with the conduction of the second switch module and switched off along with the conduction of the third switch module, and the third switch module is switched off under the conduction condition; and the output interface is connected between the other end of the fourth switch module and the second end of the first switch module and is used for taking the grounding voltage to the power supply voltage as an output voltage domain of the I2C signal. Therefore, the electric leakage risk can be reduced, and the circuit stability is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an I2C interface circuit and chip. Background Art

[0002] The Inter-Integrated Circuit (I2C) interface circuit is a simple, bidirectional, two-wire synchronous serial bus that uses serial data lines and serial clock lines to achieve short-distance communication between integrated circuits. It has low hardware complexity and communication overhead and is widely used in communication connections between microcontrollers and devices such as sensors and memories.

[0003] However, in actual applications, when the power supply voltage of the I2C interface circuit is high, there is usually at least one path from the power supply terminal to the ground, which causes leakage problems. Summary of the Invention

[0004] In view of this, the present application provides an I2C interface circuit and chip, which can reduce the risk of leakage and improve the stability of the circuit.

[0005] In a first aspect, the present application provides an I2C interface circuit, comprising: a first switch module, wherein a first end of the first switch module is connected to a ground voltage; a second switch module, wherein one end of the second switch module is connected to a control end of the first switch module, and is configured to be turned off when the first switch module is turned on, and to be turned on when the first switch module is turned off; a third switch module, wherein one end of the third switch module is connected to a power supply voltage, and the other end of the third switch module is connected to the other end of the second switch module, and is configured to be turned on when the first switch module is turned on; one end of the fourth switch module is connected to the power supply voltage, and is configured to be turned on when the second switch module is turned on, and to be turned off when the third switch module is turned on, and to turn off the third switch module when turned on; and an output interface, connected between the other end of the fourth switch module and the second end of the first switch module, and configured to use the ground voltage to the power supply voltage as the output voltage domain of the I2C signal.

[0006] In a second aspect, the present application provides a chip, which includes the I2C interface circuit described in the first aspect.

[0007] The present application provides an I2C interface circuit and chip. In the I2C interface circuit, on the one hand, by designing the conduction logic of the second switch module and the third switch module to be opposite, and the conduction logic of the fourth switch module to be opposite to that of the first switch module, there is no path from the power supply voltage to the ground under different power supply voltages, thereby reducing the risk of leakage and improving the stability of the circuit; on the other hand, the circuit structure of the I2C interface circuit is simple and the circuit area is small, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0009] Figure 1 It is a structural diagram of an I2C interface circuit;

[0010] Figure 2 This is a schematic diagram of the structure of an I2C interface circuit provided in an embodiment of the present application. Figure 1 ;

[0011] Figure 3 This is a schematic diagram of the structure of an I2C interface circuit provided in an embodiment of the present application. Figure 2 ;

[0012] Figure 4 This is a schematic diagram of the structure of an I2C interface circuit provided in an embodiment of the present application. Figure 3 ;

[0013] Figure 5 This is a schematic diagram of the structure of an I2C interface circuit provided in an embodiment of the present application. Figure 4 ;

[0014] Figure 6 This is a schematic diagram of the structure of an I2C interface circuit provided in an embodiment of the present application. Figure 5 ;

[0015] Figure 7 This is a schematic diagram of the structure of an I2C interface circuit provided in an embodiment of the present application. Figure 6 ;

[0016] Figure 8 This is a schematic diagram of the structure of an I2C interface circuit provided in an embodiment of the present application. Figure 7 ;

[0017] Figure 9 This is a schematic diagram of the structure of an I2C interface circuit provided in an embodiment of the present application. Figure 8;

[0018] Figure 10 This is a schematic diagram of the structure of an I2C interface circuit provided in an embodiment of the present application. Figure 9 ;

[0019] Figure 11 This is a schematic diagram of the structure of an I2C interface circuit provided in an embodiment of the present application. Figure 10 ;

[0020] Figure 12 This is a schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and in detail described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present application.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0023] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0024] It should also be pointed out that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0025] To facilitate understanding of the technical solutions of the embodiments of the present application, the relevant technologies of the embodiments of the present application are described below. The following relevant technologies can be arbitrarily combined with the technical solutions of the embodiments of the present application as optional solutions, and they all fall within the protection scope of the embodiments of the present application.

[0026] The I2C interface circuit is a simple, bidirectional, two-wire synchronous serial bus that uses serial data lines and serial clock lines to achieve short-distance communication between integrated circuits. It has low hardware complexity and communication overhead and is widely used in communication connections between microcontrollers and devices such as sensors and memories.

[0027] However, in actual applications, when the power supply voltage of the I2C interface circuit is high, there is usually at least one path from the power supply terminal to the ground, which causes leakage problems.

[0028] For example, Figure 1 This is a schematic diagram of the structure of an I2C interface circuit. Figure 1 As shown, one end of the pull-up resistors R1 and R2 is connected to the voltage VIO (voltage VIO can be set to 1.2V or 1.8V). The I2C master device can input the serial data signal PAD_SDA and the serial clock signal PAD_SCL through the pull-up resistors R1 and R2 and the two I2C interface circuits, and then input the obtained serial data signal SDA_IN and serial clock signal SCL_IN to the I2C slave device. The connection relationship of the I2C interface circuit may include:

[0029] The sources of the PMOS transistors M1 and M4 are both connected to the voltage VDD, the gate of the PMOS transistor M1 is grounded, and the drain of the PMOS transistor M1 is connected between the source of the PMOS transistor M2 and the drain of the PMOS transistor M4. The drain of the PMOS transistor M4 is also connected to one end of the capacitor C, the other end of which is grounded. The gate of the PMOS transistor M4 is connected between inverters INV1 and INV2. The other end of the inverter INV1 is connected between the drain of the PMOS transistor M2 and the drain of the NMOS transistor M3. The other end of the inverter INV2 outputs the voltage domain OUT of the I2C signal (i.e., the serial data signal SDA_IN and the serial clock signal SCL_IN). After the serial data signal PAD_SDA and the serial clock signal PAD_SCL pass through pull-up resistors R1 and R2, the resulting input voltage IN is connected between the gate of the PMOS transistor M2 and the gate of the NMOS transistor M3.

[0030] I understand. Figure 1The I2C interface circuit in the figure can be considered a Schmitt trigger. When the voltage VDD is high, the Schmitt trigger often enters an intermediate state. At this time, the PMOS transistors M1, M2, and M3 are all turned on, creating a path from the voltage VDD to ground, causing leakage. Furthermore, this leakage can be considered as leakage in the off state. The shutdown current (ISD) will still be relatively large, and this leakage will also affect the quiescent current (IQ) during operation.

[0031] Based on this, an embodiment of the present application provides an I2C interface circuit, comprising: a first switch module, a first end of the first switch module being connected to a ground voltage; a second switch module, one end of the second switch module being connected to a control end of the first switch module, configured to be turned off when the first switch module is turned on, and turned on when the first switch module is turned off; a third switch module, one end of the third switch module being connected to a power supply voltage, and the other end of the third switch module being connected to the other end of the second switch module, configured to be turned on when the first switch module is turned on; a fourth switch module, one end of the third switch module being connected to a power supply voltage, configured to be turned on when the second switch module is turned on, and turned off when the third switch module is turned on, and to turn off the third switch module when it is turned on; and an output interface, connected between the other end of the fourth switch module and the second end of the first switch module, configured to use the ground voltage to the power supply voltage as the output voltage domain of the I2C signal. Thus, by designing the conduction logic of the second switch module to be opposite to that of the third switch module, and the conduction logic of the fourth switch module to be opposite to that of the first switch module, a path from the power supply voltage to ground will not exist under different power supply voltages, thereby reducing the risk of leakage and improving the stability of the circuit.

[0032] To facilitate understanding of the technical solutions of the embodiments of the present application, the technical solutions of the present application are described in detail below through specific embodiments. The above related technologies can be combined with the technical solutions of the embodiments of the present application as optional solutions, and they all fall within the scope of protection of the embodiments of the present application. The embodiments of the present application include at least part of the following contents.

[0033] Figure 2 This is a schematic diagram of the structure of an I2C interface circuit provided in an embodiment of the present application. Figure 1 ,like Figure 2 As shown, the I2C interface circuit 200 may include:

[0034] A first switch module 201, wherein a first end of the first switch module 201 is connected to a ground voltage; a second switch module 202, wherein one end of the second switch module 202 is connected to a control end of the first switch module 201, and is configured to be turned off when the first switch module 201 is turned on, and to be turned on when the first switch module 201 is turned off; a third switch module 203, wherein one end of the third switch module 203 is connected to a power supply voltage VDD, and the other end of the third switch module 203 is connected to the other end of the second switch module 202, and is configured to be turned on when the first switch module 201 is turned on; a fourth switch module 204, wherein one end of the fourth switch module 204 is connected to the power supply voltage VDD, and is configured to be turned on when the second switch module 202 is turned on, and to be turned off when the third switch module 203 is turned on, and to turn off the third switch module 203 when it is turned on; an output interface 205, connected between the other end of the fourth switch module 204 and the second end of the first switch module 201, and configured to use a voltage range from ground voltage to power supply voltage VDD as an output voltage domain of the I2C signal.

[0035] It should be noted that when the first switch module 201 is turned on, the second switch module 202 is turned off, the third switch module 203 can be turned on as the first switch module 201 is turned on, and the fourth switch module 204 can be turned off as the third switch module 203 is turned on, so that the conduction logic of the second switch module 202 is opposite to that of the third switch module 203, and the conduction logic of the fourth switch module 204 is opposite to that of the first switch module 201.

[0036] It should also be noted that when the first switch module 201 is turned off, the second switch module 202 is turned on, the fourth switch module 204 can be turned on as the second switch module 202 is turned on, and the third switch module 203 can be turned off as the fourth switch module 204 is turned on, so that the conduction logic of the second switch module 202 and the third switch module 203 are opposite, and the conduction logic of the fourth switch module 204 and the first switch module 201 are opposite.

[0037] It should be understood that when the first switch module 201 is on and the fourth switch module 204 is off, the voltage at the node between the first switch module 201 and the fourth switch module 204 is the ground voltage. However, when the first switch module 201 is off and the fourth switch module 204 is on, the voltage at the node between the first switch module 201 and the fourth switch module 204 is the power supply voltage VDD. Based on this, the output interface 205 can use the ground voltage to the power supply voltage VDD as the output voltage range of the I2C signal.

[0038] Based on the above technical solution, on the one hand, by designing the conduction logic of the second switch module and the third switch module to be opposite, and the conduction logic of the fourth switch module to be opposite to that of the first switch module, there will be no path from the power supply voltage to the ground under different power supply voltages, thereby reducing the risk of leakage and improving the stability of the circuit; on the other hand, the circuit structure of the I2C interface circuit is simple and the circuit area is small, thereby reducing power consumption.

[0039] In some embodiments, Figure 2 The I2C interface circuit 200 shown is based on Figure 3 As shown, the first switch module 201 may include a first NMOS transistor M1, the source of the first NMOS transistor M1 is connected to the ground voltage, the gate of the first NMOS transistor M1 and one end of the second switch module 202 are connected to the input voltage IN, and the drain of the first NMOS transistor M1 is respectively connected to the output port and the other end of the fourth switch module 204.

[0040] It should be noted that the first switch module 201 may include one NMOS transistor (such as the first NMOS transistor M1 ), or may include multiple NMOS transistors, which is not limited in the embodiment of the present application.

[0041] It should also be noted that, in addition to being an NMOS tube, the first switch module 201 may also be a thyristor, a transistor, an insulated-gate bipolar transistor (IGBT), etc., which is not limited in the embodiment of the present application.

[0042] It should be understood that the input voltage IN and the ground voltage can control the conduction or shutdown of the first NMOS transistor M1. Furthermore, when the input voltage IN is at a high level, the difference between the input voltage IN and the ground voltage is greater than or equal to the threshold voltage of the first NMOS transistor M1, thereby controlling the first NMOS transistor M1 to be turned on; when the input voltage IN is at a low level, the difference between the input voltage IN and the ground voltage is less than the threshold voltage of the first NMOS transistor M1, thereby controlling the first NMOS transistor M1 to be turned off.

[0043] Based on the above technical solution, the conduction or shutdown of the first NMOS tube is controlled by the input voltage and the ground voltage, so that there is no path from the power supply voltage to the ground under different power supply voltages, thereby reducing the risk of leakage and improving the stability of the circuit.

[0044] In some embodiments, Figure 2 The I2C interface circuit 200 shown is based on Figure 4As shown, the second switch module 202 may include a second NMOS transistor M2, the source of the second NMOS transistor M2 and the gate of the first NMOS transistor M1 are connected to the input voltage IN, the gate of the second NMOS transistor M2 is connected to the bias voltage VGS, and the drain of the second NMOS transistor M2 is connected to the other end of the third switch module 203.

[0045] It should be noted that the second switch module 202 may include one NMOS transistor (such as the second NMOS transistor M2 ), or may include multiple NMOS transistors, which is not limited in the embodiment of the present application.

[0046] It should also be noted that, in addition to being an NMOS tube, the second switch module 202 may also be a thyristor, a transistor, an IGBT, etc., which is not limited in the embodiment of the present application.

[0047] It should be understood that the input voltage IN and the bias voltage VGS can control the conduction or shutdown of the second NMOS transistor M2. Furthermore, when the input voltage IN is at a high level, by setting the bias voltage VGS so that the difference between the bias voltage VGS and the input voltage IN is less than the threshold voltage of the second NMOS transistor M2, the second NMOS transistor M2 can be controlled to be turned off when the first NMOS transistor M1 is turned on. When the input voltage IN is at a low level, by setting the bias voltage VGS so that the difference between the bias voltage VGS and the input voltage IN is greater than or equal to the threshold voltage of the second NMOS transistor M2, the second NMOS transistor M2 can be controlled to be turned on when the first NMOS transistor M1 is turned off.

[0048] That is, the bias voltage VGS needs to be set within a certain range so that when the second NMOS transistor M2 is turned on or off based on the input voltage IN and the bias voltage VGS, the conduction logic of the first NMOS transistor M1 and the second NMOS transistor M2 can be opposite.

[0049] Based on the above technical solution, the conduction or shutdown of the second NMOS tube is controlled by the input voltage and the bias voltage, so that there is no path from the power supply voltage to the ground under different power supply voltages, thereby reducing the risk of leakage and improving the stability of the circuit.

[0050] In some embodiments, Figure 2 The I2C interface circuit 200 shown is based on Figure 5 As shown, the third switch module 203 may include a first PMOS transistor M3, the source of the first PMOS transistor M3 is connected to the power supply voltage VDD, the gate of the first PMOS transistor M3 is connected between the drain of the first NMOS transistor M1 and the other end of the fourth switch module 204, and the drain of the first PMOS transistor M3 is connected to the drain of the second NMOS transistor M2.

[0051] It should be noted that the third switch module 203 may include one PMOS transistor (such as the first PMOS transistor M3 ), or may include multiple PMOS transistors, which is not limited in the embodiment of the present application.

[0052] It should also be noted that, in addition to being a PMOS tube, the third switch module 203 may also be a thyristor, a transistor, an IGBT, etc., which is not limited in the embodiment of the present application.

[0053] It should be understood that the power supply voltage VDD and the gate voltage of the first PMOS transistor M3 can control the on / off state of the first PMOS transistor M3. Furthermore, when the first NMOS transistor M1 is on (corresponding to the second NMOS transistor M2 being off and the fourth switch module 204 being off), the gate voltage of the first PMOS transistor M3 is at a low level, and the difference between the power supply voltage VDD and the gate voltage of the first PMOS transistor M3 is greater than or equal to the threshold voltage of the first PMOS transistor M3, thereby controlling the first PMOS transistor M3 to be on. When the fourth switch module 204 is on (corresponding to the first NMOS transistor M1 being off and the second NMOS transistor M2 being on), the gate voltage of the first PMOS transistor M3 is at a high level, and the difference between the power supply voltage VDD and the gate voltage of the first PMOS transistor M3 is less than the threshold voltage of the first PMOS transistor M3, thereby controlling the first PMOS transistor M3 to be off.

[0054] Based on the above technical solution, the first PMOS tube is controlled to be turned on or off by the power supply voltage and the gate voltage of the first PMOS tube, so that the conduction logic of the first PMOS tube and the second NMOS tube are opposite. Under different power supply voltages, there is no path from the power supply voltage to the ground, thereby reducing the risk of leakage and improving the stability of the circuit.

[0055] In some embodiments, Figure 2 The I2C interface circuit 200 shown is based on Figure 6 As shown, the fourth switch module 204 may include a second PMOS transistor M4, a source of the second PMOS transistor M4 is connected to the power supply voltage VDD, a gate of the second PMOS transistor M4 is connected between the drain of the first PMOS transistor M3 and the drain of the second NMOS transistor M2, and a drain of the second PMOS transistor M4 is respectively connected to the output port, the drain of the first NMOS transistor M1, and the gate of the first PMOS transistor M3.

[0056] It should be noted that the fourth switch module 204 may include one PMOS transistor (such as the second PMOS transistor M4 ), or may include multiple PMOS transistors, which is not limited in the embodiment of the present application.

[0057] It should also be noted that, in addition to being a PMOS tube, the fourth switch module 204 may also be a thyristor, a transistor, an IGBT, etc., which is not limited in the embodiment of the present application.

[0058] It should be understood that the power supply voltage VDD and the gate voltage of the second PMOS transistor M4 can control the conduction or shutdown of the second PMOS transistor M4. Furthermore, when the second NMOS transistor M2 is turned on (corresponding to the first NMOS transistor M1 being turned off and the first PMOS transistor M3 being turned off), the gate voltage of the second PMOS transistor M4 is at a low level, and the difference between the power supply voltage VDD and the gate voltage of the second PMOS transistor M4 is greater than or equal to the threshold voltage of the second PMOS transistor M4, thereby controlling the conduction of the second PMOS transistor M4. When the first PMOS transistor M3 is turned on (corresponding to the first NMOS transistor M1 being turned on and the second NMOS transistor M2 being turned off), the gate voltage of the second PMOS transistor M4 is at a high level, and the difference between the power supply voltage VDD and the gate voltage of the second PMOS transistor M4 is less than the threshold voltage of the second PMOS transistor M4, thereby controlling the shutdown of the second PMOS transistor M4.

[0059] It should also be understood that the input voltage IN can be used to control the gate of the first NMOS transistor M1 and the source of the second NMOS transistor M2 respectively, thereby controlling the two different NMOS transistors to pull up or down the drain voltage to achieve the voltage domain shift of the I2C signal, thereby reducing the leakage risk of the I2C interface circuit 200.

[0060] Based on the above technical solution, the second PMOS tube is controlled to be turned on or off by the power supply voltage and the gate voltage of the second PMOS tube, so that the conduction logic of the second PMOS tube is opposite to that of the first NMOS tube. Under different power supply voltages, there is no path from the power supply voltage to the ground, thereby reducing the risk of leakage and improving the stability of the circuit.

[0061] In related art, when the input voltage is high, the I2C interface circuit will have a certain amount of quiescent current, thereby increasing the circuit power consumption. Based on this, the embodiment of the present application introduces a regulation module into the I2C interface circuit 200. On the one hand, it can provide a bias voltage, and on the other hand, it can regulate the quiescent current of the I2C interface circuit 200, thereby reducing the circuit power consumption.

[0062] In some embodiments, Figure 2 The I2C interface circuit 200 shown is based on Figure 7 As shown, the I2C interface circuit 200 may further include a regulating module 206 , wherein: one end of the regulating module 206 is connected to the power supply voltage VDD, and the other end is connected to the gate of the second NMOS transistor M2 , for providing a bias voltage VGS and regulating the static current of the I2C interface circuit 200 .

[0063] Based on the above technical solution, by introducing a regulation module into the I2C interface circuit to regulate the quiescent current of the I2C interface circuit, the I2C interface circuit has a lower quiescent current under different input voltages, thereby further reducing circuit power consumption.

[0064] In some embodiments, Figure 2 The I2C interface circuit 200 shown is based on Figure 8 As shown, the regulating module 206 may include a first resistor R1 , one end of the first resistor R1 is connected to the power supply voltage VDD, and the other end is connected to the gate of the second NMOS transistor M2 .

[0065] It should be noted that the adjustment module 206 may use one resistor (such as the first resistor R1 ) or multiple resistors, which is not limited in the embodiment of the present application.

[0066] It should also be noted that, in addition to using resistors, the adjustment module 206 may also use diodes, adjustable resistors, operational amplifiers, etc., which is not limited in the embodiment of the present application.

[0067] Based on the above technical solution, by selecting first resistors with different resistance values, it is possible to provide a bias voltage and adjust the quiescent current of the I2C interface circuit, so that the I2C interface circuit has a lower quiescent current under different input voltages, thereby further reducing circuit power consumption.

[0068] In some embodiments, Figure 2 The I2C interface circuit 200 shown is based on Figure 9 As shown, the regulating module 206 may further include a third NMOS transistor M5 and a bias module 207. The source of the third NMOS transistor M5 is connected in series with the bias module 207 and then grounded. The gate of the third NMOS transistor M5 is respectively connected to the other end of the first resistor R1 and the gate of the second NMOS transistor M2. The drain of the third NMOS transistor M5 is connected to the other end of the first resistor R1. The bias module 207 is used to regulate the voltage between the source and the gate of the third NMOS transistor M5.

[0069] It should be noted that the bias module 207 can be a series diode, an operational amplifier, a voltage-stabilized power supply, etc., and the embodiment of the present application does not limit this.

[0070] It should also be noted that in Figure 8 In the process, since the resistance value of a single resistor varies under different processes, the adjustment of the static current of the I2C interface circuit 200 will also vary. Based on this, it can be Figure 8 On the basis of Figure 9The third NMOS transistor M5 and the bias module 207 in the circuit 200 form a current mirror structure with the second NMOS transistor M2. The bias module 207 is used to adjust the voltage between the source and the gate of the third NMOS transistor M5, so that the I2C interface circuit 200 can have a stable low quiescent current under different input voltages IN.

[0071] Based on the above technical solution, by designing a regulation module including a first resistor, a third NMOS transistor and a bias module, it is possible to provide a bias voltage and regulate the quiescent current of the I2C interface circuit, so that the I2C interface circuit has a lower quiescent current under different input voltages, thereby further reducing circuit power consumption.

[0072] In some embodiments, Figure 2 The I2C interface circuit 200 shown is based on Figure 10 As shown, the I2C interface circuit 200 may further include a waveform adjustment module 208, wherein: one end of the waveform adjustment module 208 is connected between the other end of the fourth switch module 204 and the second end of the first switch module 201, and the other end is connected to the output interface 205, and is configured to adjust the waveform of the ground voltage or the power supply voltage VDD so that the output interface 205 uses the adjusted ground voltage to the adjusted power supply voltage VDD as the output voltage domain of the I2C signal.

[0073] It should be noted that the waveform adjustment module 208 can be an even number of inverters, buffers, level converters, Schmitt triggers, etc. connected in series, which is not limited in this embodiment of the present application.

[0074] Based on the above technical solution, by designing a waveform adjustment module in the I2C interface circuit, the ground voltage or power supply voltage can be stabilized, the jitter and noise in the ground voltage or power supply voltage can be reduced, and the voltage provided by the output interface meets the voltage domain requirements of the I2C signal, thereby ensuring the stability and reliability of I2C communication.

[0075] The I2C interface circuit provided by the above embodiment is described in detail below in conjunction with specific application scenarios.

[0076] exist Figure 2 The I2C interface circuit 200 shown is based on Figure 11 As shown, the bias current IBIAS provided by the current source is equivalent to the bias module 207 in the aforementioned embodiment, the first inverter INV1 and the second inverter INV2 are equivalent to the waveform adjustment module 208 in the aforementioned embodiment, and the connection relationship between the various components is as follows:

[0077] One end of the first resistor R1, the source of the first PMOS transistor M3, and the source of the second PMOS transistor M4 are all connected to the power supply voltage VDD; the other end of the first resistor R1 is connected to the drain of the third NMOS transistor M5, and between the gate of the third NMOS transistor M5 and the gate of the second NMOS transistor M2. The source of the third NMOS transistor M5 is connected in series with the bias current IBIAS provided by the current source and then grounded. The current source is used to adjust the voltage between the source and gate of the third NMOS transistor M5; the gate of the second PMOS transistor M4 is connected to the drain of the first PMOS transistor M3 and the gate of the second NMOS transistor M2. The first and second NMOS transistors M2 and M3 are connected in series, and the other end of the second inverter INV1 is connected between the drain of the second PMOS transistor M4 and the drain of the first NMOS transistor M1. The other end of the second inverter INV2 is connected to the output interface 205.

[0078] When the input voltage IN is at a high level, the difference between the input voltage IN and the ground voltage is greater than or equal to the threshold voltage of the first NMOS transistor M1, thereby controlling the first NMOS transistor M1 to be turned on; by setting the bias voltage VGS so that the difference between the bias voltage VGS and the input voltage IN is less than the threshold voltage of the second NMOS transistor M2, thereby controlling the second NMOS transistor M2 to be turned off; the gate voltage of the first PMOS transistor M3 is at a low level, and the difference between the power supply voltage VDD and the gate voltage of the first PMOS transistor M3 is greater than or equal to the threshold voltage of the first PMOS transistor M3, thereby controlling the first PMOS transistor M3 to be turned on; the gate voltage of the second PMOS transistor M4 is at a high level, and the difference between the power supply voltage VDD and the gate voltage of the second PMOS transistor M4 is less than the threshold voltage of the second PMOS transistor M4, thereby controlling the second PMOS transistor M4 to be turned off.

[0079] When the input voltage IN is at a low level, the difference between the input voltage IN and the ground voltage is less than the threshold voltage of the first NMOS transistor M1, thereby controlling the first NMOS transistor M1 to be turned off. By setting the bias voltage VGS, the difference between the bias voltage VGS and the input voltage IN is greater than or equal to the threshold voltage of the second NMOS transistor M2, thereby controlling the second NMOS transistor M2 to be turned on. The gate voltage of the second PMOS transistor M4 is at a low level, and the difference between the power supply voltage VDD and the gate voltage of the second PMOS transistor M4 is greater than or equal to the threshold voltage of the second PMOS transistor M4, thereby controlling the second PMOS transistor M4 to be turned on. The gate voltage of the first PMOS transistor M3 is at a high level, and the difference between the power supply voltage VDD and the gate voltage of the first PMOS transistor M3 is less than the threshold voltage of the first PMOS transistor M3, thereby controlling the first PMOS transistor M3 to be turned off.

[0080] The adjustment module 208 may include a first resistor R1, a third NMOS transistor M5 and IBIAS, which can not only provide a bias voltage VGS, but also adjust the quiescent current of the I2C interface circuit 200, so that the I2C interface circuit 200 has a lower quiescent current under different input voltages IN, thereby further reducing circuit power consumption.

[0081] It should be understood that when the first NMOS transistor M1 is turned on and the second PMOS transistor M4 is turned off, the node voltage between the first NMOS transistor M1 and the second PMOS transistor M4 (corresponding to the drain voltage of the first NMOS transistor M1 or the drain voltage of the second PMOS transistor M4) is the ground voltage, while when the first NMOS transistor M1 is turned off and the second PMOS transistor M4 is turned on, the node voltage between the first NMOS transistor M1 and the second PMOS transistor M4 is the power supply voltage VDD. Based on this, after the first inverter INV1 and the second inverter INV2 adjust the waveform of the ground voltage or the power supply voltage VDD, the output interface 205 can use the adjusted ground voltage to the power supply voltage VDD as the output voltage domain of the I2C signal.

[0082] It should also be understood that the first inverter INV1 and the second inverter INV2 adjust the waveform of the ground voltage or the power supply voltage VDD. It can be understood that the first inverter INV1 and the second inverter INV2 can stabilize the ground voltage or the power supply voltage VDD, reduce jitter and noise in the ground voltage or the power supply voltage VDD, and thus ensure the stability and reliability of I2C communication.

[0083] Based on the above technical solution, by designing the conduction logic of the first NMOS tube and the second PMOS tube to be opposite, and the conduction logic of the second NMOS tube to be opposite to that of the first PMOS tube, there will be no path from the power supply voltage to the ground under different power supply voltages, thereby preventing leakage.

[0084] The preferred embodiments of the present application are described in detail above in conjunction with the accompanying drawings. However, the present application is not limited to the specific details in the above embodiments. Within the technical concept of the present application, the technical solution of the present application can be subjected to a variety of simple modifications, and these simple modifications all fall within the scope of protection of the present application. For example, the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present application will not further describe the various possible combinations. For another example, the various different embodiments of the present application can also be arbitrarily combined, as long as they do not violate the ideas of the present application, they should also be regarded as the contents disclosed in the present application. For another example, under the premise of no conflict, the various embodiments and / or the technical features in each embodiment described in the present application can be arbitrarily combined with the relevant technologies, and the technical solution obtained after the combination should also fall within the scope of protection of the present application.

[0085] Figure 12 This is a schematic diagram of the structure of a chip provided in an embodiment of the present application. Figure 12 As shown, the chip 1200 may include the I2C interface circuit 200 in the above embodiment, and has the beneficial effects of the I2C interface circuit in the above embodiment, which will not be described in detail here.

[0086] It should be noted that, in this application, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, article, or device comprising the element.

[0087] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0088] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0089] The above implementation methods are only used to illustrate the embodiments of the present application, and are not intended to limit the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.

Claims

1. An I2C interface circuit, characterized in that: include: a first switch module, wherein a first terminal of the first switch module is connected to a ground voltage; a second switch module, one end of which is connected to the control end of the first switch module, and configured to be turned off when the first switch module is turned on, and turned on when the first switch module is turned off; a third switch module, one end of which is connected to the power supply voltage, and the other end of which is connected to the other end of the second switch module, and is configured to be turned on when the first switch module is turned on, and turned off when the fourth switch module is turned on; a fourth switch module, one end of which is connected to the power supply voltage, and configured to be turned on when the second switch module is turned on, and turned off when the third switch module is turned on, and to turn off the third switch module when turned on; An output interface is connected between the other end of the fourth switch module and the second end of the first switch module, and is used to use the ground voltage to the power supply voltage as the output voltage domain of the I2C signal.

2. The I2C interface circuit according to claim 1, wherein: The first switch module includes a first NMOS transistor, the source of the first NMOS transistor is connected to the ground voltage, the gate of the first NMOS transistor and one end of the second switch module are connected to the input voltage, and the drain of the first NMOS transistor is respectively connected to the output port and the other end of the fourth switch module.

3. The I2C interface circuit according to claim 2, wherein: The second switch module includes a second NMOS transistor, the source of the second NMOS transistor and the gate of the first NMOS transistor are connected to the input voltage, the gate of the second NMOS transistor is connected to the bias voltage, and the drain of the second NMOS transistor is connected to the other end of the third switch module.

4. The I2C interface circuit according to claim 3, wherein: The third switch module includes a first PMOS transistor, the source of the first PMOS transistor is connected to the power supply voltage, the gate of the first PMOS transistor is connected between the drain of the first NMOS transistor and the other end of the fourth switch module, and the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor.

5. The I2C interface circuit according to claim 4, wherein: The fourth switch module includes a second PMOS transistor, the source of the second PMOS transistor is connected to the power supply voltage, the gate of the second PMOS transistor is connected between the drain of the first PMOS transistor and the drain of the second NMOS transistor, and the drain of the second PMOS transistor is respectively connected to the output port, the drain of the first NMOS transistor, and the gate of the first PMOS transistor.

6. The I2C interface circuit according to any one of claims 3 to 5, characterized in that: The I2C interface circuit further includes a regulating module, wherein: One end of the regulating module is connected to the power supply voltage, and the other end is connected to the gate of the second NMOS transistor, and is used to provide the bias voltage and regulate the static current of the I2C interface circuit.

7. The I2C interface circuit according to claim 6, wherein: The regulating module includes a first resistor, one end of which is connected to the power supply voltage, and the other end of which is connected to the gate of the second NMOS transistor.

8. The I2C interface circuit according to claim 7, wherein: The regulation module also includes a third NMOS transistor and a bias module. The source of the third NMOS transistor is connected in series with the bias module and then grounded. The gate of the third NMOS transistor is respectively connected to the other end of the first resistor and the gate of the second NMOS transistor. The drain of the third NMOS transistor is connected to the other end of the first resistor. The bias module is used to adjust the voltage between the source and gate of the third NMOS transistor.

9. The I2C interface circuit according to claim 1, wherein: The I2C interface circuit further includes a waveform adjustment module, wherein: One end of the waveform adjustment module is connected between the other end of the fourth switch module and the second end of the first switch module, and the other end is connected to the output interface, and is used to adjust the waveform of the ground voltage or the power supply voltage so that the output interface uses the adjusted ground voltage to the adjusted power supply voltage as the output voltage domain of the I2C signal.

10. An I2C interface circuit, characterized in that: include: A first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, and an output interface; The source of the first NMOS transistor is connected to the ground voltage, and the gate of the first NMOS transistor is connected to the input voltage; The source of the second NMOS transistor is connected to the input voltage; the gate of the second NMOS transistor is connected to the bias voltage; The source of the first PMOS transistor is connected to the power supply voltage; the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor; and the gate of the first PMOS transistor is connected to the drain of the first NMOS transistor; The source of the second PMOS transistor is connected to the power supply voltage; the gate of the second PMOS transistor is connected between the drain of the first PMOS transistor and the drain of the second NMOS transistor; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor; The output interface is connected between the drain of the first NMOS transistor and the drain of the second PMOS transistor.

11. The I2C interface circuit according to claim 10, wherein: The I2C interface circuit further includes: a first resistor; One end of the first resistor is connected to the power supply voltage, and the other end is connected to the gate of the second NMOS transistor, so as to provide the bias voltage to the gate of the second NMOS transistor.

12. The I2C interface circuit according to claim 11, wherein: The I2C interface circuit further includes: a third NMOS transistor and a current source; The source of the third NMOS transistor is connected in series with the current source and then grounded, the gate of the third NMOS transistor is connected to the other end of the first resistor and the gate of the second NMOS transistor respectively, and the drain of the third NMOS transistor is connected to the other end of the first resistor.

13. The I2C interface circuit according to any one of claims 10 to 12, characterized in that: The I2C interface circuit further includes: a first inverter and a second inverter; The first inverter and the second inverter are connected in series, and the other end of the first inverter is connected between the drain of the second PMOS transistor and the drain of the first NMOS transistor, and the other end of the second inverter is connected to the output interface.

14. A chip, characterized in that: The I2C interface circuit comprises the I2C interface circuit according to any one of claims 1 to 13.

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