Absolute pressure sensor of silicon-silicon bonding structure and preparation process
By setting channels and partition channels in the absolute pressure pressure sensor of silicon-silicon bonding structure, the problems of insufficient vacuum degree and parasitic capacitance during bonding are solved, and the test accuracy and sensitivity of the sensor are improved.
Patent Information
- Application Number
- CN202510707673.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-08-26
AI Technical Summary
During the bonding process of existing silicon and silicon, oxidation diffusion heating is carried out under air pressure, which cannot guarantee the vacuum in the absolute pressure chamber, resulting in low sensor sensitivity and temperature noise affecting the test accuracy.
The absolute pressure pressure sensor preparation process using silicon-silicon bonding structure is used. By bonding between the double-spray silicon wafer and the SOI silicon wafer, and setting a channel to extract air in the pressure-sensitive cavity, setting a partition channel to reduce parasitic capacitance, and improving the sensor testing accuracy.
A high vacuum pressure-sensitive cavity structure is realized, reducing the influence of parasitic capacitance and improving the test accuracy and sensitivity of the sensor.
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Figure CN120538733A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of pressure sensors, and in particular to an absolute pressure sensor with a silicon-silicon bonding structure and a preparation process thereof. Background Art
[0002] Silicon material has excellent mechanical properties. With the maturity of semiconductor technology, there is a means to make sensors using silicon material, and bonding technology is one of the important means to make sensors.
[0003] The bonding between silicon and silicon is a crystalline bond. In the current silicon-to-silicon bonding process, since the bonding process is carried out in an oxidation diffusion furnace and the oxidation diffusion heating process is carried out under air pressure conditions, the vacuum of the absolute pressure cavity cannot be guaranteed. In other words, it is difficult to completely empty the air in the absolute pressure cavity. The sensitivity of the sensor after bonding is not high, and the temperature noise has a great impact on the test accuracy (temperature will affect the accuracy of the sensor).
[0004] In view of this, the inventors specially designed an absolute pressure sensor with a silicon-silicon bonding structure and a preparation process, which resulted in this case. Summary of the Invention
[0005] The present invention aims to address at least one of the technical problems existing in the prior art. To this end, the present invention proposes a process for fabricating an absolute pressure sensor with a silicon-on-silicon bonded structure. By first bonding a double-polished silicon wafer to a thin silicon layer of an SOI silicon wafer, a channel is then created to evacuate air from the pressure-sensing chamber. This results in a vacuum pressure sensor structure with a high vacuum within the pressure-sensing chamber, overcoming the shortcomings of existing direct silicon-on-silicon bonding. Furthermore, a barrier channel is provided to isolate thin films other than the pressure-sensing membrane, reducing parasitic capacitance and improving sensor testing accuracy.
[0006] The invention also proposes an absolute pressure sensor with a silicon-silicon bonding structure.
[0007] According to the present invention, a preparation process for an absolute pressure sensor with a silicon-silicon bonding structure is provided, and the preparation process comprises the following steps: Step 1: Setting a pressure-sensing cavity, a flow channel, a channel, and a lower electrode on a double-polished silicon wafer: a pressure-sensing cavity and a flow channel are connected on the upper surface of the double-polished silicon wafer, a channel is set through the double-polished silicon wafer corresponding to the flow channel, and a lower electrode is set on the lower surface of the double-polished silicon wafer; Step 2: Providing an isolation channel, a top electrode position photolithography pattern, and a deep cavity photolithography pattern on the SOI silicon wafer: the SOI silicon wafer comprises a thick silicon layer, a silicon oxide layer, and a thin silicon layer, wherein the isolation channel is etched on the thin silicon layer, and the isolation channel is etched to the surface of the silicon oxide layer, and the top electrode position photolithography pattern and the deep cavity photolithography pattern are provided on the surface of the thick silicon layer; Step 3, performing anodically bonding the double-polished silicon wafer in step 1 to the SOI silicon wafer in step 2: performing anodically bonding on the surface of the double-polished silicon wafer having the pressure-sensing cavity and the surface of the SOI silicon wafer having the isolation channel; Step 4: Anodically bond the double-polished silicon wafer from step 3 to the glass surface. The surface of the double-polished silicon wafer with the lower electrode position is anodically bonded to the glass surface. The air in the pressure-sensing cavity can be evacuated through the channel before bonding. Step 5, setting a deep cavity and an upper electrode position on the SOI silicon wafer: etching a deep cavity and an upper electrode position on the thick silicon layer and within the deep cavity lithography pattern and the upper electrode position lithography pattern respectively; Step 6, cutting the glass: Cut the glass to expose the lower electrode position.
[0008] The flow channel connects the through hole and the pressure-sensing cavity, and its purpose is to avoid the loss of pressure-sensing measurement area caused by drilling in the pressure-sensing cavity, thereby improving the accuracy of vacuum pressure testing. Isolation channel: This isolates the thin film outside the pressure-sensing membrane to reduce parasitic capacitance and improve sensor testing accuracy. The isolation channel is fabricated on the pressure-sensing membrane, and the pressure-sensing cavity is fabricated on a double-polished silicon wafer. The pressure-sensing membrane is bonded to the cavity via silicon-silicon bonding. The silicon, silicon dioxide, and silicon structure in the bonding area can generate significant parasitic capacitance, affecting measurement. By creating a barrier around the periphery of the pressure-sensing cavity, the bonding area outside the pressure-sensing membrane is minimized while ensuring the pressure-sensing membrane can adequately support the operating pressure. Specifically, after the double-polished silicon wafer is bonded to the thin silicon layer of the SOI silicon wafer, upper and lower electrodes are formed between the double-polished silicon wafer and the thin silicon layer. In addition to the capacitance of the sensing cavity, parasitic capacitance also forms at the bonding surface. The bonding surface is insulated by an oxide layer, and because the dielectric constant of the oxide layer is greater than that of the cavity, significant parasitic capacitance forms at the silicon-silicon bonding surface, affecting measurement accuracy. To reduce the parasitic capacitance generated at the bonding surface, an isolation channel is required around the sensing cavity to improve measurement accuracy.
[0009] In some embodiments of the present invention, the preparation process further comprises: Step 7, disposing a first electrode at the upper electrode position: sputtering the first electrode at the upper electrode position using a magnetron sputtering process; Step 8: Disposing a second electrode at the lower electrode position: forming a second electrode at the lower electrode position and on the glass surface by using a magnetron sputtering or evaporation process.
[0010] In some embodiments of the present invention, the second electrode formed as the lower electrode is a silicon electrode.
[0011] In some embodiments of the present invention, in step 7, before setting the first electrode, a template or high-temperature resistant tape is used to protect the deep cavity area, exposing only the upper electrode portion. After sputtering the first electrode, the template or high-temperature resistant tape is removed.
[0012] In some embodiments of the present invention, after the template or the high-temperature resistant tape is protected, only the non-sputtering area is exposed.
[0013] In some embodiments of the present invention, step 1 includes the following steps: Step 11: Place the double-polished silicon wafer in an oxidation furnace at 1000° C. or higher for oxidation, so that a first oxide layer and a second oxide layer are formed on the upper and lower surfaces of the double-polished silicon wafer, wherein the thickness of the first oxide layer and the second oxide layer are 500-1000 nm. After oxidation, the double-polished silicon wafer is double-polished silicon oxide. Step 12, after coating the surface of the second oxide layer with photoresist, performing smearing and pre-baking, then performing photolithography exposure and developing to obtain a lower electrode bit photolithography pattern in the shape of the lower electrode bit and a channel photolithography pattern in the shape of the channel; then coating the surface of the first oxide layer with photoresist, performing smearing and pre-baking; Step 13, using BOE solution to remove the second oxide layer in the lower electrode photolithography pattern and the channel photolithography pattern; Step 14, removing the remaining photoresist on the surface of the second oxide layer and the photoresist on the surface of the first oxide layer; Step 15, forming a channel by penetrating double-polished silicon oxide into the corresponding channel photolithography pattern; Step 16, after coating the surface of the first oxide layer with photoresist, performing smearing and pre-baking, then performing photolithography exposure and developing to obtain a pressure-sensing cavity photolithography pattern in the shape of the pressure-sensing cavity and a flow channel photolithography pattern in the shape of the flow channel; then coating the surface of the second oxide layer with photoresist, performing smearing and pre-baking; Step 17, using BOE solution to remove the first oxide layer in the pressure-sensing cavity photolithography pattern and the flow channel photolithography pattern; Step 18, removing the remaining photoresist on the surface of the first oxide layer and the photoresist on the surface of the second oxide layer; Step 19: Use a mixture of TMAH solution and ammonium persulfate to etch the pressure-sensing cavity, the flow channel, and the lower electrode on the double-polished silicon oxide, respectively, in the pressure-sensing cavity photolithography pattern, the flow channel photolithography pattern, and the lower electrode photolithography pattern. Finally, use BOE solution to remove the remaining first oxide layer and second oxide layer on the surface.
[0014] In some embodiments of the present invention, in step 11, cleaning is performed before oxidation, and the mixture is sequentially placed in liquid No. 3, liquid No. 1, and liquid No. 2 for cleaning. Specifically: Place the double-polished silicon wafer in solution 3, boil for 15-20 minutes, and then rinse with deionized water; Place the double-polished silicon wafer in solution 1, boil for 15 minutes, and then rinse with deionized water; Place the double-polished silicon wafer in solution 2, boil for 15 minutes, rinse with deionized water, and blow dry with nitrogen; Among them, the No. 3 liquid is a mixture of hydrogen peroxide and sulfuric acid, and the mixing ratio is: 1:3 or 1:4; the No. 2 liquid is a mixture of ammonia water, hydrogen peroxide, and deionized water, and the mixing ratio is: 1:1:5; the No. 1 liquid is a mixture of hydrochloric acid, hydrogen peroxide, and deionized water, and the mixing ratio is 1:1:5.
[0015] In some embodiments of the present invention, in step 12 and step 16, the photoresist is coated respectively with a tackifier and 5214-E. When leveling the photoresist, the speed is first 500 rpm for 3-5 seconds, and then 1500-3000 rpm for 60-90 seconds. The temperature of the heating plate for pre-baking is 85-96°C, and the baking is carried out for 4-5 minutes. The post-baking is carried out in an oven at 120-130°C for 15 minutes.
[0016] In some embodiments of the present invention, in step 14 and step 18, the remaining photoresist is removed by the following method: Acetone ultrasound for 3 min; Alcohol ultrasound for 3 minutes; Put double-polished silica into liquid No. 3, boil for 15-20 minutes, and rinse with deionized water.
[0017] In some embodiments of the present invention, in step 15, the double-polished silicon oxide is penetrated by using any one of laser, ultrasonic or wet etching processes.
[0018] In some embodiments of the present invention, in step 19, shallow etching is used, and the surface after etching is smooth and mirror-like. Specifically, a mixture of TMAH solution and ammonium persulfate is prepared and heated to 60° C.; double-polished silicon oxide is placed in the mixture for 20-30 minutes, and the pressure-sensing cavity, the flow channel position, and the lower electrode position are etched on the double-polished silicon oxide in the pressure-sensing cavity photolithography pattern, the flow channel position photolithography pattern, and the lower electrode position photolithography pattern, respectively; the ratio of the TMAH solution to ammonium persulfate is 100:2.5.
[0019] In some embodiments of the present invention, in step 19, cleaning is performed after etching is completed, and the cleaning steps are as follows: Soak in acetone for 3 minutes, soak in alcohol for 3 minutes, then rinse with deionized water; Put double-polished silica into liquid No. 3, boil for 15-20 minutes, and then rinse with deionized water; Place double-polished silica in solution No. 2, boil for 15 minutes, and then rinse with deionized water; Put double-polished silica into liquid No. 1, boil for 15 minutes, rinse with deionized water and blow dry with nitrogen.
[0020] In some embodiments of the present invention, step 2 includes the following steps: Step 21, placing the SOI silicon wafer in an oxidation furnace at 1000° C. or higher for oxidation, so that a third oxide layer is formed on the surface of the thick silicon layer and a fourth oxide layer is formed on the surface of the thin silicon layer, wherein the thickness of the third oxide layer and the fourth oxide layer is 500-1000 nm; Step 22, coating the surface of the fourth oxide layer with photoresist, then performing smearing and pre-baking, then performing photolithography exposure and developing a partition channel photolithography pattern in the shape of the partition channel; then coating the surface of the third oxide layer with photoresist, then performing smearing and pre-baking; Step 23, using a BOE solution to remove the fourth oxide layer in the partition channel lithography pattern; Step 24, removing the remaining photoresist on the surface of the fourth oxide layer and the photoresist on the surface of the third oxide layer; Step 25, using a mixture of TMAH solution and ammonium persulfate to etch a partition channel on the thin silicon layer and within the partition channel photolithography pattern; Step 26, coating the surface of the third oxide layer with photoresist, performing spread coating and pre-baking, and then performing photolithography exposure and developing to obtain a deep cavity photolithography pattern in the shape of a deep cavity and an upper electrode bit photolithography pattern in the shape of an upper electrode bit; Step 27, using BOE solution to remove the third oxide layer in the deep cavity photolithography pattern and the upper electrode photolithography pattern; Step 28: removing the remaining photoresist on the surface of the third oxide layer.
[0021] In some embodiments of the present invention, in step 21 , cleaning is performed before oxidation, and the cleaning step is the same as step 11 .
[0022] In some embodiments of the present invention, in step 22 and step 26, the photoresist is coated respectively with a tackifier and 5214-E. When uniformly distributing the photoresist, the speed is first 500 rpm for 3-5 seconds, and then 1500-3000 rpm for 60-90 seconds. The temperature of the heating plate for pre-baking is 85-96°C, and the baking is carried out for 4-5 minutes. The post-baking is carried out in an oven at 120-130°C for 15 minutes.
[0023] In some embodiments of the present invention, the method of removing the photoresist in step 24 and step 28 is the same as that in step 14.
[0024] In some embodiments of the present invention, in step 25, a mixture of TMAH solution and ammonium persulfate is prepared and heated to 60° C.; an SOI silicon wafer is placed in the mixture for 20-30 minutes, and a partition channel is etched on the SOI silicon wafer within the partition channel photolithography pattern; the ratio of the TMAH solution to ammonium persulfate is 100:2.5.
[0025] In some embodiments of the present invention, a cleaning process is performed before applying the photoresist, and the cleaning steps are as follows: Soak and clean in acetone for 5 minutes; Soak in alcohol and clean for 30 seconds; After boiling in liquid No. 3 for 15-20 minutes, rinse with deionized water; Put it in the oven and bake at 135℃ for 15-30 minutes.
[0026] In some embodiments of the present invention, in step 1, the number of flow channel positions is consistent with the number of channels, and both are greater than or equal to 1.
[0027] In some embodiments of the present invention, three flow channel positions and channels are provided.
[0028] In some embodiments of the present invention, the partition channel is in a ring shape. In some embodiments of the present invention, in step 3, in an ultra-quiet environment, the surface of a double-polished silicon wafer having a pressure-sensing cavity is aligned with the surface of an SOI silicon wafer having a blocking channel, and the double-polished silicon wafer surface and the SOI silicon wafer surface are brought into contact with each other. The SOI silicon wafer surface and the encapsulation glass surface are then bonded together using a heating and electrostatic bonding process, wherein the heating temperature is 350° C. to 600° C. and the electrostatic voltage is 600 to 1200 volts. In step 4, the upper surface of the glass is aligned with the surface of the double-polished silicon wafer with the lower electrode position in an ultra-quiet environment, and the glass surface is brought into contact with the surface of the double-polished silicon wafer. Then, a heating and electrostatic bonding process is used to bond the SOI silicon wafer surface to the packaging glass surface. The heating temperature is 350°C to 600°C, and the electrostatic voltage is 600 to 1200 volts.
[0029] In some embodiments of the present invention, in step 5, a mixture of TMAH solution and ammonium persulfate is used to etch the upper electrode position and the deep cavity on the SOI silicon wafer and in the upper electrode position photolithography pattern and the deep cavity photolithography pattern, respectively; specifically, a mixture of TMAH solution and ammonium persulfate is prepared, and the mixture is heated to 60° C.; the SOI silicon wafer is placed in the mixture for 20-30 minutes, and the upper electrode position and the deep cavity are etched on the SOI silicon wafer and in the upper electrode position photolithography pattern and the deep cavity photolithography pattern, respectively; the ratio of the TMAH solution to ammonium persulfate is 100:2.5, and then the silicon wafer oxide layer in the upper electrode position and the deep cavity is washed away, specifically, BOE is used to wash away the silicon wafer oxide layer.
[0030] In some embodiments of the present invention, the preparation process uses a whole wafer to process several sensors. In step 6, a dicing machine is used to cut the glass with a shallow knife so that the glass at the lower electrode position falls off, exposing the lower electrode position. At the same time, a protective template is used to protect the deep cavity, leaving only the upper electrode position exposed. Metal is sputtered at the upper electrode position to form a first electrode. Then, the protective template is removed, and metal is sputtered at the lower electrode position to form a second electrode. Finally, cutting is performed in both the horizontal and vertical directions to form several sensors. Specifically, to avoid the dicing machine tool directly cutting the metal film and causing the blade to curl, a shallow knife cut is first performed at the device dividing scribe line position to reduce metal sputtering.
[0031] According to the present invention, an absolute pressure sensor with a silicon-silicon bonding structure is prepared using a preparation process. The structure of the pressure sensor includes: A double-polished silicon wafer, wherein one surface of the double-polished silicon wafer is provided with a pressure-sensing cavity and a flow channel that are interconnected, and a channel is provided through the corresponding flow channel, and the other surface of the double-polished silicon wafer is provided with a lower electrode position; An SOI silicon wafer is disposed on a double-polished silicon wafer and is located on one side of the pressure-sensing cavity. The SOI silicon wafer comprises a thick silicon layer, a silicon oxide layer, and a thin silicon layer. A deep cavity and an upper electrode are disposed on the surface of the thick silicon layer, and an isolation channel is disposed on the thin silicon layer. Glass, the glass is disposed on a double-polished silicon wafer and is located on a side away from the SOI silicon wafer, and the glass does not cover the lower electrode position; A third oxide layer is provided on the surface of the thick silicon layer of the SOI silicon wafer, and a fourth oxide layer is provided on the surface of the thin silicon layer.
[0032] In some embodiments of the present invention, the lower electrode is located at an edge of the double-polished silicon wafer, and the upper electrode is located at an edge of a thick silicon layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The drawings described herein are used to provide further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.
[0034] in: Figure 1 1 is a schematic structural diagram of the pressure sensor of the present invention; Figure 2 This is a schematic diagram of the explosion of the pressure sensor of the present invention Figure 1 ; Figure 3 This is a schematic diagram of the explosion of the pressure sensor of the present invention Figure 2 ; Figure 4 This is a schematic structural diagram of a double-polished silicon wafer according to the present invention; Figure 5is a flow chart of step 1 in the preparation method of the present invention; Figure 6 is a flow chart of step 2 in the preparation method of the present invention; Figure 7 is a flow chart of the remaining steps in the preparation method of the present invention; Figure 8 Schematic diagram of cutting in step 6 of the present invention; Figure 9 1 is a schematic diagram of a cut of the pressure sensor of the present invention; Figure 10 This invention Figure 9 A partial cross-sectional view of .
[0035] Description of labels: 10. Double-polished silicon wafer; 101. First oxide layer; 102. Second oxide layer; 11. Pressure-sensing cavity; 12. Flow channel; 13. Channel; 14. Lower electrode; 20. SOI silicon wafer; 201. Thick silicon layer; 202. Silicon wafer oxide layer; 203. Thin silicon layer; 204. Third oxide layer; 205. Fourth oxide layer; 21. Deep cavity; 22. Upper electrode; 23. Partition channel; 30. Glass; 40. First electrode; 50. Second electrode; 60. Baffle. DETAILED DESCRIPTION
[0036] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and more understandable, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Example 1
[0037] See also Figures 1 to 10 , is a preparation process of an absolute pressure sensor with a silicon-silicon bonding structure as embodiment 1 of the present invention, the preparation process comprises the following steps: Step 1: Setting a pressure-sensing cavity, a flow channel, a channel, and a lower electrode on a double-polished silicon wafer: a pressure-sensing cavity and a flow channel are connected on the upper surface of the double-polished silicon wafer, a channel is set through the double-polished silicon wafer corresponding to the flow channel, and a lower electrode is set on the lower surface of the double-polished silicon wafer; Step 2: Providing an isolation channel, a top electrode position photolithography pattern, and a deep cavity photolithography pattern on the SOI silicon wafer: the SOI silicon wafer comprises a thick silicon layer, a silicon oxide layer, and a thin silicon layer, wherein the isolation channel is etched on the thin silicon layer, and the isolation channel is etched to the surface of the silicon oxide layer, and the top electrode position photolithography pattern and the deep cavity photolithography pattern are provided on the surface of the thick silicon layer; Step 3, performing anodically bonding the double-polished silicon wafer in step 1 to the SOI silicon wafer in step 2: performing anodically bonding on the side of the double-polished silicon wafer having the pressure-sensing cavity and the side of the SOI silicon wafer having the isolation channel; Step 4, anodically bonding the double-polished silicon wafer in step 3 to the glass: anodically bonding the surface of the double-polished silicon wafer with the lower electrode position to the glass surface; Step 5, setting a deep cavity and a top electrode position on the SOI silicon wafer: etching a deep cavity and a top electrode position on the thick silicon layer and within the deep cavity lithography pattern and the top electrode position lithography pattern, respectively. Specifically, the deep cavity opening is rectangular or square, and the size gradually decreases from the opening inward; Step 6, cutting the glass: cutting the glass to expose the lower electrode position; Step 7, disposing a first electrode at the upper electrode position: sputtering the first electrode at the upper electrode position using a magnetron sputtering process; Step 8: Disposing a second electrode at the lower electrode position: forming a second electrode at the lower electrode position and on the glass surface by using a magnetron sputtering or evaporation process.
[0038] It should be pointed out that the above steps do not have to be performed in sequence. For example, step 1 and step 2 can be swapped according to actual conditions without affecting the entire preparation process.
[0039] The second electrode formed by the lower electrode position is a silicon electrode; in the step 7, before setting the first electrode, a template or a high-temperature resistant tape is used to protect the deep cavity area, exposing only the upper electrode position part, and after sputtering the first electrode, the template or the high-temperature resistant tape is removed to protect the deep cavity and the remaining third oxide layer surface to prevent the first electrode from being sputtered and affecting the deep cavity interior and the third oxide layer surface. Therefore, after protection by the template or the high-temperature resistant tape, only the non-sputtered area is exposed.
[0040] Please refer to the following for details: Figure 5 , the step 1 comprises the following steps: Step 11: Place the double-polished silicon wafer in an oxidation furnace at 1000°C or above for oxidation, so that a first oxide layer and a second oxide layer are formed on the upper and lower surfaces of the double-polished silicon wafer, wherein the thickness of the first oxide layer and the second oxide layer is 500-1000nm. The double-polished silicon wafer after oxidation is double-polished silicon oxide; and before oxidation, it is first cleaned and placed in liquid No. 3, liquid No. 1, and liquid No. 2 for cleaning in sequence. Specifically: Place the double-polished silicon wafer in liquid No. 3, boil for 15-20 minutes, and then rinse with deionized water; Place the double-polished silicon wafer in liquid No. 1, boil for 15 minutes, and then rinse with deionized water; place the double-polished silicon wafer in liquid No. 2, boil for 15 minutes, rinse with deionized water, and then blow dry with nitrogen; Liquid No. 3 is a mixture of hydrogen peroxide and sulfuric acid in a ratio of 1:3 or 1:4; Liquid No. 2 is a mixture of ammonia, hydrogen peroxide, and deionized water in a ratio of 1:1:5; Liquid No. 1 is a mixture of hydrochloric acid, hydrogen peroxide, and deionized water in a ratio of 1:1:5; Step 12, after applying photoresist on the surface of the second oxide layer, performing smearing and pre-baking, and then performing photolithography exposure and developing to obtain a lower electrode bit photolithography pattern in the shape of the lower electrode bit and a channel photolithography pattern in the shape of the channel (in the present invention, the lower electrode bit shape refers to the shape of the horizontal cross-section of the lower electrode bit, and the channel shape refers to the shape of the horizontal cross-section of the channel. For example, when the channel is cylindrical, the channel shape is circular); then, after applying photoresist on the surface of the first oxide layer, performing smearing and pre-baking, specifically, the photoresist is applied using a tackifier and 5214-E respectively. When smearing, the rotation speed is first 500 rpm for 3-5 seconds, and then the rotation speed is 1500-3000 rpm for 60-90s. The temperature of the heating plate for pre-baking is 85-96°C, and the baking is carried out for 4-5 minutes. The post-baking is carried out in an oven at 120-130°C for 15 minutes. Step 13, using BOE solution to remove the second oxide layer in the lower electrode photolithography pattern and the channel photolithography pattern; Step 14: remove the remaining photoresist on the surface of the second oxide layer and the photoresist on the surface of the first oxide layer. Specifically, the remaining photoresist is removed by the following methods: ultrasonic treatment with acetone for 3 minutes; ultrasonic treatment with alcohol for 3 minutes; placing double-polished silicon oxide in liquid No. 3, boiling for 15-20 minutes, and rinsing with deionized water; Step 15: penetrate the double-polished silicon oxide in the corresponding channel lithography pattern to form a channel; specifically, penetrate the double-polished silicon oxide by any one of laser, ultrasonic or wet etching processes; Step 16: After applying photoresist on the surface of the first oxide layer, the coating is performed and pre-baking is performed, and then photolithography exposure is performed and a pressure-sensing cavity photolithography pattern in the shape of the pressure-sensing cavity and a flow channel photolithography pattern in the shape of the flow channel are developed. For details, please refer to step 12; then, after applying photoresist on the surface of the second oxide layer, the coating is performed and pre-baking is performed; Step 17, using BOE solution to remove the first oxide layer in the pressure-sensing cavity photolithography pattern and the flow channel photolithography pattern; Step 18, removing the remaining photoresist on the surface of the first oxide layer and the photoresist on the surface of the second oxide layer. For details, please refer to step 14; Step 19: Use a mixture of TMAH solution and ammonium persulfate to etch the pressure-sensing cavity, the flow channel, and the lower electrode on the double-polished silicon oxide, respectively, in the pressure-sensing cavity photolithography pattern, the flow channel photolithography pattern, and the lower electrode photolithography pattern. Finally, use BOE solution to remove the remaining first oxide layer and second oxide layer on the surface.
[0041] In step 19, shallow etching is used to produce a smooth, mirror-like surface after etching. Specifically, a mixture of TMAH solution and ammonium persulfate is prepared and heated to 60°C. Double-polished silicon oxide is placed in the mixture for 20-30 minutes, thereby etching the pressure-sensing cavity, the flow channel, and the bottom electrode on the double-polished silicon oxide, respectively, within the pressure-sensing cavity photolithography pattern, the flow channel photolithography pattern, and the bottom electrode photolithography pattern. The ratio of the TMAH solution to ammonium persulfate is 100:2.5. In step 19, cleaning is performed after etching, and the cleaning steps are as follows: soaking in acetone for 3 minutes, soaking in alcohol for 3 minutes, and then rinsing with deionized water; placing the double-polished silicon oxide in liquid No. 3, boiling for 15-20 minutes, and then rinsing with deionized water; placing the double-polished silicon oxide in liquid No. 2, boiling for 15 minutes, and then rinsing with deionized water; placing the double-polished silicon oxide in liquid No. 1, boiling for 15 minutes, and then rinsing with deionized water, and then drying with nitrogen.
[0042] Please refer to the following for details: Figure 6 , the step 2 comprises the following steps: Step 21, placing the SOI silicon wafer in an oxidation furnace at 1000° C. or higher for oxidation, so that a third oxide layer is formed on the surface of the thick silicon layer and a fourth oxide layer is formed on the surface of the thin silicon layer, wherein the thickness of the third oxide layer and the fourth oxide layer is 500-1000 nm; Step 22, coating the surface of the fourth oxide layer with photoresist, then performing smearing and pre-baking, then performing photolithography exposure and developing a partition channel photolithography pattern in the shape of the partition channel; then coating the surface of the third oxide layer with photoresist, then performing smearing and pre-baking; Step 23, using a BOE solution to remove the fourth oxide layer in the partition channel lithography pattern; Step 24, removing the remaining photoresist on the surface of the fourth oxide layer and the photoresist on the surface of the third oxide layer; Step 25, using a mixture of TMAH solution and ammonium persulfate to etch a partition channel on the thin silicon layer and within the partition channel photolithography pattern; specifically, preparing a mixture of TMAH solution and ammonium persulfate and heating the mixture to 60° C.; placing the SOI silicon wafer in the mixture for 20-30 minutes, thereby etching the partition channel on the SOI silicon wafer and within the partition channel photolithography pattern; the ratio of the TMAH solution to ammonium persulfate is 100:2.5; Step 26, coating the surface of the third oxide layer with photoresist, performing spread coating and pre-baking, and then performing photolithography exposure and developing to obtain a deep cavity photolithography pattern in the shape of a deep cavity and an upper electrode bit photolithography pattern in the shape of an upper electrode bit; Step 27, using BOE solution to remove the third oxide layer in the deep cavity photolithography pattern and the upper electrode photolithography pattern; Step 28: removing the remaining photoresist on the surface of the third oxide layer.
[0043] In step 21, cleaning is performed before oxidation, and the cleaning step is the same as step 11. In steps 22 and 26, photoresist is applied using a tackifier and 5214-E, respectively. When spreading the photoresist, the rotation speed is first 500 rpm for 3-5 seconds, then 1500-3000 rpm for 60-90 seconds. The heating plate temperature for pre-baking is 85-96°C and the baking time is 4-5 minutes. The post-baking is carried out in an oven at 120-130°C for 15 minutes. In steps 24 and 28, the method used to remove the photoresist is the same as that in step 14.
[0044] In the specific steps of step 1 and step 2 of this embodiment, a cleaning treatment is performed before coating the photoresist. The cleaning steps are as follows: immersion in acetone for 5 minutes; immersion in alcohol for 30 seconds; boiling in liquid No. 3 for 15-20 minutes, and then rinsing with deionized water; placing in an oven and baking at a high temperature of 135°C for 15-30 minutes.
[0045] In step 1, the number of flow channel positions and channels is the same and both are greater than or equal to 1; in this embodiment, there are three flow channel positions and channels. The partition channel is in a ring shape. Please refer to the following for details: Figure 7 In step 3, in an ultra-quiet environment, the surface of the double-polished silicon wafer with the pressure-sensing cavity is aligned with the surface of the SOI silicon wafer with the isolation channel, and the double-polished silicon wafer surface and the SOI silicon wafer surface are brought into contact with each other. Then, a heating and electrostatic bonding process is used to bond the SOI silicon wafer surface to the packaging glass surface, wherein the heating temperature is 350° C. to 600° C. and the electrostatic voltage is 600 to 1200 volts. Please refer to the following for details: Figure 7 In step 4, the upper surface of the glass is aligned with the surface of the double-polished silicon wafer with the lower electrode position in an ultra-quiet environment, and the glass surface is brought into contact with the surface of the double-polished silicon wafer. Then, a heating and electrostatic bonding process is used to bond the SOI silicon wafer surface to the packaging glass surface. The heating temperature is 350°C to 600°C, and the electrostatic voltage is 600 to 1200 volts.
[0046] Please refer to the following for details: Figure 7In step 5, a mixture of TMAH solution and ammonium persulfate is used to etch the upper electrode position and the deep cavity on the SOI silicon wafer and in the upper electrode position photolithography pattern and the deep cavity photolithography pattern, respectively. The depth of the deep cavity is not limited and is only used to support the pressure-sensitive film. The depth depends on the thickness of all silicon wafers. Specifically, a mixture of TMAH solution and ammonium persulfate is prepared and heated to 60° C. The SOI silicon wafer is placed in the mixture for 20-30 minutes, and the upper electrode position and the deep cavity can be etched on the SOI silicon wafer and in the upper electrode position photolithography pattern and the deep cavity photolithography pattern, respectively. The ratio of the TMAH solution to ammonium persulfate is 100:2.5, and then the silicon wafer oxide layer in the upper electrode position and the deep cavity is washed away. Specifically, BOE is used to wash away the silicon wafer oxide layer.
[0047] Please refer to the following for details: Figure 7 The manufacturing process uses a whole wafer to process several sensors. In step 6, a dicing machine is used to cut the glass shallowly so that the glass at the lower electrode position falls off and the lower electrode position is exposed. The cutting line refers to Figure 7 A1 and A2 in the figure are protected by a protective template at the same time, and only the upper electrode position is exposed. Metal is sputtered at the upper electrode position to form the first electrode. Then the protective template is removed and metal is sputtered at the lower electrode position to form the second electrode. Finally, the electrodes are formed from both the horizontal and vertical directions (refer to Figure 8 Specifically, to prevent the dicing tool from directly cutting the metal film and causing edge curling, shallow cutting is first performed at the device separation scribe line to reduce metal sputtering. Example 2
[0048] See also Figures 1 to 4 , is an absolute pressure sensor with a silicon-silicon bonded structure as embodiment 2 of the present invention, comprising: a double-polished silicon wafer, an SOI silicon wafer, and glass. A pressure-sensing cavity and a flow channel are interconnected on one surface of the double-polished silicon wafer, and a channel is provided through the corresponding flow channel. A lower electrode is provided on another surface of the double-polished silicon wafer. The SOI silicon wafer is disposed on the double-polished silicon wafer and located on one side of the pressure-sensing cavity. The SOI silicon wafer comprises a thick silicon layer, a silicon oxide layer, and a thin silicon layer. A deep cavity and an upper electrode are provided on the surface of the thick silicon layer, and a partition channel is provided on the thin silicon layer. The glass is disposed on the double-polished silicon wafer and located away from the SOI silicon wafer, and does not cover the lower electrode. A third oxide layer is provided on the thick silicon layer of the SOI silicon wafer, and a fourth oxide layer is provided on the thin silicon layer. The lower electrode is located at the edge of the double-polished silicon wafer, and the upper electrode is located at the edge of the thick silicon layer.
[0049] In summary, the preparation process of the present invention first bonds a double-polished silicon wafer to a thin silicon layer of an SOI silicon wafer, and then opens a channel to extract the air in the pressure-sensing cavity. The pressure-sensing cavity has a high vacuum degree vacuum pressure sensor structure. During measurement, the pressure-sensing film is deformed by the external pressure, and the pressure is judged by the capacitance display method; in addition, an isolation channel is set to isolate the thin film outside the pressure-sensing film, reduce parasitic capacitance, and thus improve the sensor test accuracy.
[0050] The present invention is described above by way of example in conjunction with the accompanying drawings. It is obvious that the specific implementation of the present invention is not limited to the above-mentioned method. As long as various non-substantial improvements are made using the method concept and technical solution of the present invention, or the concept and technical solution of the present invention are directly applied to other occasions without improvement, they are all within the scope of protection of the present invention.
Claims
1. A process for preparing an absolute pressure sensor with a silicon-silicon bonding structure, characterized in that: The preparation process includes the following steps: Step 1: Setting a pressure-sensing cavity, a flow channel, a channel, and a lower electrode on a double-polished silicon wafer: a pressure-sensing cavity and a flow channel are connected on the upper surface of the double-polished silicon wafer, a channel is set through the double-polished silicon wafer corresponding to the flow channel, and a lower electrode is set on the lower surface of the double-polished silicon wafer; Step 2: Providing an isolation channel, a top electrode position photolithography pattern, and a deep cavity photolithography pattern on the SOI silicon wafer: the SOI silicon wafer comprises a thick silicon layer, a silicon oxide layer, and a thin silicon layer, wherein the isolation channel is etched on the thin silicon layer, and the isolation channel is etched to the surface of the silicon oxide layer, and the top electrode position photolithography pattern and the deep cavity photolithography pattern are provided on the surface of the thick silicon layer; Step 3, performing anodically bonding the double-polished silicon wafer in step 1 to the SOI silicon wafer in step 2: performing anodically bonding on the side of the double-polished silicon wafer having the pressure-sensing cavity and the side of the SOI silicon wafer having the isolation channel; Step 4, anodically bonding the double-polished silicon wafer in step 3 to the glass: anodically bonding the surface of the double-polished silicon wafer with the lower electrode position to the glass surface; Step 5, setting a deep cavity and an upper electrode position on the SOI silicon wafer: etching a deep cavity and an upper electrode position on the thick silicon layer and within the deep cavity lithography pattern and the upper electrode position lithography pattern respectively; Step 6, cutting the glass: Cut the glass to expose the lower electrode position.
2. The process for preparing an absolute pressure sensor with a silicon-silicon bonding structure according to claim 1, characterized in that: The preparation process also includes: Step 7, disposing a first electrode at the upper electrode position: sputtering the first electrode at the upper electrode position using a magnetron sputtering process; Step 8: Disposing a second electrode at the lower electrode position: forming a second electrode at the lower electrode position and on the glass surface by using a magnetron sputtering or evaporation process.
3. The process for preparing an absolute pressure sensor with a silicon-silicon bonding structure according to claim 2, characterized in that: In step 7, before setting the first electrode, a template or a high-temperature resistant tape is used to protect the deep cavity area, leaving only the upper electrode portion exposed. After sputtering the first electrode, the template or the high-temperature resistant tape is removed.
4. The process for preparing an absolute pressure sensor with a silicon-silicon bonding structure according to claim 1, characterized in that: The step 1 comprises the following steps: Step 11: Place the double-polished silicon wafer in an oxidation furnace at 1000° C. or higher for oxidation, so that a first oxide layer and a second oxide layer are formed on the upper and lower surfaces of the double-polished silicon wafer, wherein the thickness of the first oxide layer and the second oxide layer are 500-1000 nm. After oxidation, the double-polished silicon wafer is double-polished silicon oxide. Step 12, after coating the surface of the second oxide layer with photoresist, performing smearing and pre-baking, then performing photolithography exposure and developing to obtain a lower electrode bit photolithography pattern in the shape of the lower electrode bit and a channel photolithography pattern in the shape of the channel; then coating the surface of the first oxide layer with photoresist, performing smearing and pre-baking; Step 13, using BOE solution to remove the second oxide layer in the lower electrode photolithography pattern and the channel photolithography pattern; Step 14, removing the remaining photoresist on the surface of the second oxide layer and the photoresist on the surface of the first oxide layer; Step 15, forming a channel by penetrating double-polished silicon oxide into the corresponding channel photolithography pattern; Step 16, after coating the surface of the first oxide layer with photoresist, performing smearing and pre-baking, then performing photolithography exposure and developing to obtain a pressure-sensing cavity photolithography pattern in the shape of the pressure-sensing cavity and a flow channel photolithography pattern in the shape of the flow channel; then coating the surface of the second oxide layer with photoresist, performing smearing and pre-baking; Step 17, using BOE solution to remove the first oxide layer in the pressure-sensing cavity photolithography pattern and the flow channel photolithography pattern; Step 18, removing the remaining photoresist on the surface of the first oxide layer and the photoresist on the surface of the second oxide layer; Step 19: Use a mixture of TMAH solution and ammonium persulfate to etch the pressure-sensing cavity, the flow channel, and the lower electrode on the double-polished silicon oxide, respectively, in the pressure-sensing cavity photolithography pattern, the flow channel photolithography pattern, and the lower electrode photolithography pattern. Finally, use BOE solution to remove the remaining first oxide layer and second oxide layer on the surface.
5. The process for preparing an absolute pressure sensor with a silicon-silicon bonding structure according to claim 1, characterized in that: The step 2 comprises the following steps: Step 21, placing the SOI silicon wafer in an oxidation furnace at 1000° C. or higher for oxidation, so that a third oxide layer is formed on the surface of the thick silicon layer and a fourth oxide layer is formed on the surface of the thin silicon layer, wherein the thickness of the third oxide layer and the fourth oxide layer is 500-1000 nm; Step 22, coating the surface of the fourth oxide layer with photoresist, then performing smearing and pre-baking, then performing photolithography exposure and developing a partition channel photolithography pattern in the shape of the partition channel; then coating the surface of the third oxide layer with photoresist, then performing smearing and pre-baking; Step 23, using a BOE solution to remove the fourth oxide layer in the partition channel lithography pattern; Step 24, removing the remaining photoresist on the surface of the fourth oxide layer and the photoresist on the surface of the third oxide layer; Step 25, using a mixture of TMAH solution and ammonium persulfate to etch a partition channel on the thin silicon layer and within the partition channel photolithography pattern; Step 26, coating the surface of the third oxide layer with photoresist, performing spread coating and pre-baking, and then performing photolithography exposure and developing to obtain a deep cavity photolithography pattern in the shape of a deep cavity and an upper electrode bit photolithography pattern in the shape of an upper electrode bit; Step 27, using BOE solution to remove the third oxide layer in the deep cavity photolithography pattern and the upper electrode photolithography pattern; Step 28: removing the remaining photoresist on the surface of the third oxide layer.
6. The process for preparing an absolute pressure sensor with a silicon-silicon bonding structure according to claim 1, characterized in that: In step 1, the number of flow channel positions is consistent with the number of channels, and both are greater than or equal to 1.
7. The process for preparing an absolute pressure sensor with a silicon-silicon bonding structure according to claim 1, characterized in that: In step 3, in an ultra-quiet environment, the surface of the double-polished silicon wafer with the pressure-sensing cavity is aligned with the surface of the SOI silicon wafer with the isolation channel, and the double-polished silicon wafer surface and the SOI silicon wafer surface are brought into contact. Then, a heating and electrostatic bonding process is used to bond the SOI silicon wafer surface to the encapsulation glass surface. The heating temperature is 350° C. to 600° C., and the electrostatic voltage is 600 to 1200 volts. In step 4, the upper surface of the glass is aligned with the surface of the double-polished silicon wafer with the lower electrode position in an ultra-quiet environment, and the glass surface is brought into contact with the surface of the double-polished silicon wafer. Then, a heating and electrostatic bonding process is used to bond the SOI silicon wafer surface to the packaging glass surface. The heating temperature is 350°C to 600°C, and the electrostatic voltage is 600 to 1200 volts.
8. The process for preparing an absolute pressure sensor with a silicon-silicon bonding structure according to claim 1, characterized in that: In step 5, a mixture of TMAH solution and ammonium persulfate is used to etch the upper electrode site and the deep cavity on the SOI silicon wafer, respectively, within the upper electrode site photolithography pattern and the deep cavity photolithography pattern, and then the silicon wafer oxide layer in the upper electrode site and the deep cavity is washed away (specifically, BOE is used to wash away the silicon wafer oxide layer).
9. The process for preparing an absolute pressure sensor with a silicon-silicon bonding structure according to claim 1, characterized in that: This preparation process uses a whole wafer to process several sensors. In step 6, a dicing machine is used to cut the glass shallowly so that the glass at the lower electrode position falls off, exposing the lower electrode position. At the same time, a protective template is used to protect the deep cavity, leaving only the upper electrode position exposed. Metal is sputtered at the upper electrode position to form a first electrode. Then, the protective template is removed, and metal is sputtered at the lower electrode position to form a second electrode. Finally, cutting is performed in both the horizontal and vertical directions to form several sensors.
10. An absolute pressure sensor with a silicon-silicon bonding structure, characterized in that: include: A double-polished silicon wafer, wherein one surface of the double-polished silicon wafer is provided with a pressure-sensing cavity and a flow channel that are interconnected, and a channel is provided through the corresponding flow channel, and the other surface of the double-polished silicon wafer is provided with a lower electrode position; An SOI silicon wafer is disposed on a double-polished silicon wafer and is located on one side of the pressure-sensing cavity. The SOI silicon wafer comprises a thick silicon layer, a silicon oxide layer, and a thin silicon layer. A deep cavity and an upper electrode are disposed on the surface of the thick silicon layer, and an isolation channel is disposed on the thin silicon layer. Glass, the glass is disposed on a double-polished silicon wafer and is located on a side away from the SOI silicon wafer, and the glass does not cover the lower electrode position; A third oxide layer is provided on the surface of the thick silicon layer of the SOI silicon wafer, and a fourth oxide layer is provided on the surface of the thin silicon layer.