Method for controlling critical dimensions of a multilayer mask

Abstract

This invention provides a method for controlling the critical dimensions of a multilayer photomask, comprising: dividing the layout of the multilayer photomask into multiple chip layers, each chip layer having a dicing area around its perimeter; for each chip layer, placing at least one set of critical dimension measurement pattern groups in the dicing area around its perimeter, each set of critical dimension measurement pattern groups including at least one dense pattern whose size matches the critical dimension specifications of the chip layer and at least one isolated pattern whose size matches the critical dimension specifications of the chip layer; fabricating the multilayer photomask; measuring the dimensions of each dense pattern and each isolated pattern in each set of critical dimension measurement pattern groups in the multilayer photomask; and controlling the fabrication process of the multilayer photomask based on the measurement results of the dimensions of each dense pattern and each isolated pattern. This invention can solve the problem of decreased critical dimension uniformity of different chip layers caused by manufacturing multilayer chips integrated on a single photomask.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing and manufacturing technology, and in particular to a method for controlling the critical dimensions of multilayer photomasks. Background Technology

[0002] In the chip manufacturing industry, the number of photomasks required for chip manufacturing varies depending on the node, ranging from approximately 40 to 80. This results in high economic costs for semiconductor companies, especially for more advanced nodes. As a result, the industry has developed a technology called hybrid multi-layer masks. The manufacturing of these masks can save chip companies costs during the R&D and production phases, and can combine the manufacturing of multiple layers of chips with different designs. This further reduces the waiting time for production orders, which is beneficial for chip R&D and manufacturing.

[0003] Using multi-layer photomasks can reduce the amount of substrates, photoresist, and consumables, thereby effectively reducing costs. Furthermore, multi-layer photomasks allow for parallel processing of multiple chip layers, avoiding the production time caused by frequent production runs, thus effectively shortening the chip production cycle. This is suitable for early-stage process setup and small-batch verification in wafer fabs.

[0004] As Moore's Law advances, chip nodes are constantly approaching the limits of lithography machines. In particular, the number of revisions required for advanced nodes is twice that of mature nodes. Without the use of hybrid multilayer mask technology, the progress and cost of chip development would increase dramatically.

[0005] A complete mask set typically contains two types of masks manufactured using two different processes: BIM (Binary Mask) and PSM (Phase-Shift Mask). In a mask set, BIM accounts for approximately 60%, and PSM accounts for approximately 40%.

[0006] Within the same type of photomask, they are further classified into grades, with different grades representing differences in photomask materials, manufacturing processes, and manufacturing prices. Among them, photomask substrates can be divided into positive photoresist substrates and negative photoresist substrates based on their materials.

[0007] Building upon multi-mask technology, the problems arising from multi-mask systems can be solved by considering the mask type, grade, and material. However, since multi-mask systems contain at least two mask patterns, and these two patterns... Figure 1 Generally, different technologies control the critical dimensions and overlay precision, which leads to a decrease in the uniformity of the CD (critical dimension) of chips in different layers, making it impossible to meet the process specifications of advanced process nodes.

[0008] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0009] The purpose of this invention is to provide a method for controlling the critical dimensions of multilayer photomasks, which can solve the problem of reduced uniformity of critical dimensions of different layers of chips caused by manufacturing multilayer chips integrated on a single photomask, thereby affecting chip yield and failing to meet the process specifications requirements of advanced nodes.

[0010] To achieve the above objectives, the present invention provides a method for controlling the key dimensions of a multilayer photomask, the method comprising:

[0011] The layout of the multilayer photomask is divided into multiple chip layers, and each chip layer has a dicing area around its perimeter.

[0012] For each chip layer, at least one set of critical dimension measurement patterns is placed in each of the dicing regions located around the chip layer. Each set of critical dimension measurement patterns includes at least one dense pattern whose size matches the critical dimension specification requirements of the chip layer and at least one isolated pattern whose size matches the critical dimension specification requirements of the chip layer.

[0013] A multi-layer photomask is fabricated based on the layout of the multi-layer photomask in which the key dimension measurement pattern group is arranged in the cutting area.

[0014] Measure the dimensions of each dense pattern and each isolated pattern in each group of key dimension measurement pattern groups in the multilayer photomask;

[0015] The fabrication process of the multilayer photomask is controlled based on the measurement results of the dimensions of each of the dense patterns and each of the isolated patterns.

[0016] Optionally, each set of the critical dimension measurement graphics includes dense lines, dense squares, and dense through holes.

[0017] Optionally, the dense lines include multiple parallel lines arranged at equal intervals.

[0018] Optionally, the dense blocks include multiple blocks that are equally spaced and arranged in a square array.

[0019] Optionally, the dense vias include a plurality of vias that are equally spaced and arranged in a square array.

[0020] Optionally, each set of the critical dimension measurement graphics includes isolated lines, isolated squares, and isolated through holes.

[0021] Optionally, the size of each dense pattern and each isolated pattern in the critical dimension measurement pattern group ranges from 80nm to 1500nm.

[0022] Optionally, for each of the chip layers, at least one set of critical dimension measurement patterns is placed in each of the dicing regions located around the chip layer, including:

[0023] For each chip layer, multiple sets of key dimension measurement patterns are evenly placed in each of the cut-out areas around the chip layer.

[0024] Optionally, measuring the dimensions of each dense pattern and each isolated pattern in each group of key dimension measurement patterns in the multilayer photomask includes:

[0025] The dimensions of each dense pattern and each isolated pattern in each group of key dimension measurement patterns in the multilayer photomask were measured using a scanning electron microscope.

[0026] Optionally, controlling the fabrication process of the multilayer photomask based on the measurement results of the dimensions of each of the dense patterns and each of the isolated patterns includes:

[0027] For each chip layer, based on the measurement results of the dimensions of each dense pattern and each isolated pattern in all the key dimension measurement pattern groups located around the chip layer, the dimensional uniformity of each dense pattern and each isolated pattern located around the chip layer is calculated respectively.

[0028] The fabrication process of the multilayer photomask is controlled based on the dimensional uniformity of each dense pattern and each isolated pattern in the dicing area surrounding each chip layer.

[0029] Compared with the prior art, the key dimension control method for multilayer photomasks provided by the present invention has the following beneficial effects:

[0030] The critical dimension control method for multilayer photomasks provided by this invention first divides the layout of the multilayer photomask into multiple chip layers, each chip layer having a dicing area around its perimeter. Then, for each chip layer, at least one set of critical dimension measurement pattern groups is placed in each dicing area around that chip layer. Each set of critical dimension measurement pattern groups includes at least one dense pattern with dimensions matching the critical dimension specifications of that chip layer, and at least one isolated pattern with dimensions matching the critical dimension specifications of that chip layer. The multilayer photomask is then fabricated based on the layout of the multilayer photomask with the critical dimension measurement pattern groups arranged in the dicing areas. Next, the dimensions of each dense pattern and each isolated pattern in each set of critical dimension measurement pattern groups in the multilayer photomask are measured. Finally, the fabrication process of the multilayer photomask is controlled based on the measurement results of the dimensions of each dense pattern and each isolated pattern. This solves the problem of decreased critical dimension uniformity between different chip layers caused by integrating multiple chips onto a single photomask, thus affecting chip yield and failing to meet the process specifications requirements of advanced nodes. Furthermore, this invention, through the targeted design of a critical dimension measurement pattern set, addresses the issue of critical dimension uniformity caused by the integration of different chip layers in multilayer photomasks. Measurement control is performed in the dicing area, allowing for the detection of poor critical dimension uniformity during the measurement steps of the multilayer photomask manufacturing stage. This enables the analysis of problems arising from the manufacturing process, thereby promoting the mass production and standard manufacturing process specification control of multilayer photomasks at advanced nodes. Simultaneously, since dense patterns are susceptible to proximity effects, and isolated patterns are more sensitive to exposure dose, setting up a critical dimension measurement pattern set consisting of at least one dense pattern and at least one isolated pattern ensures fine-grained control of different patterns during the photomask manufacturing stage, further contributing to solving problems caused by multilayer masks. Moreover, since the dicing area is a blank area used for physically dividing the chip and does not contain actual circuitry, it is removed and discarded after chip manufacturing. Therefore, placing the critical dimension measurement pattern set in the dicing area avoids occupying effective chip area, further saving costs. Attached Figure Description

[0031] Figure 1 A flowchart of a method for controlling the key dimensions of a multilayer photomask according to an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the layout of a multilayer photomask provided according to an embodiment of the present invention;

[0033] Figure 3 A schematic diagram showing the placement of a key dimension measurement graphic set in the cutting channel area according to an embodiment of the present invention;

[0034] Figure 4aA schematic diagram of dense lines of 80nm provided for one embodiment of the present invention;

[0035] Figure 4b A schematic diagram of dense lines of 1500nm provided for one embodiment of the present invention;

[0036] Figure 5a A schematic diagram of an 80nm dense square provided in one embodiment of the present invention;

[0037] Figure 5b A schematic diagram of a 1500nm dense square provided in one embodiment of the present invention;

[0038] Figure 6a A schematic diagram of dense vias of 80nm provided in one embodiment of the present invention;

[0039] Figure 6b A schematic diagram of dense vias of 1500nm provided in one embodiment of the present invention;

[0040] Figure 7a A schematic diagram of an isolated line of 80nm provided according to an embodiment of the present invention;

[0041] Figure 7b A schematic diagram of an isolated line of 1500nm provided according to an embodiment of the present invention;

[0042] Figure 8a A schematic diagram of an 80nm isolated cube provided in one embodiment of the present invention;

[0043] Figure 8b A schematic diagram of an isolated cube of 1500 nm provided in one embodiment of the present invention;

[0044] Figure 9a A schematic diagram of an 80nm isolated via provided in one embodiment of the present invention;

[0045] Figure 9b A schematic diagram of a 1500nm isolated via provided in one embodiment of the present invention;

[0046] Figure 10 A flowchart for the photomask design phase;

[0047] Figure 11 This is a flowchart of the photomask manufacturing process.

[0048] The reference numerals in the attached figures are explained as follows:

[0049] Chip layer - 110, 110A, 110B, 110C, 110D; Cutting area - 120; Critical dimension measurement pattern group - 130; Dense lines - 131; Dense squares - 132; Dense vias - 133; Isolated lines - 134; Opaque lines - 134A; Transparent lines - 134B; Isolated squares - 135; Isolated vias - 136. Detailed Implementation

[0050] The key dimension control method for multilayer photomasks proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. Please refer to the accompanying drawings for a clearer understanding of the objectives, features, and advantages of this invention. It should be noted that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are only for illustrative purposes and to enable those skilled in the art to understand and read the invention, and are not intended to limit the implementation conditions of the invention. Any modifications to the structure, changes in proportions, or adjustments to the size, provided they produce the same or similar effects and achieve the same objectives as this invention, should still fall within the scope of the technical content disclosed in this invention. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts with the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings. Additionally, if the methods described herein include a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be performed, some of the steps may be omitted and / or some other steps not described herein may be added to the method.

[0051] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations, nor should they be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms “a,” “one,” and “the” include plural objects. The term “or” is generally used to mean “and / or.” The term “several” is generally used to mean “at least one.” The term “at least two” is generally used to mean “two or more.” The term “multiple” is generally used to mean “at least two.”

[0052] The core idea of ​​this invention is to provide a method for controlling the critical dimensions of multilayer photomasks. This method can solve the problem of decreased uniformity of critical dimensions of different layers of chips caused by integrating multiple chips onto a single photomask, thereby affecting chip yield and failing to meet the process specifications requirements of advanced nodes. It should be noted that, as those skilled in the art will understand, the critical dimension control method for multilayer photomasks provided by this invention is applicable not only to the control of critical dimensions of BIM multilayer photomasks but also to the control of critical dimensions of PSM multilayer photomasks.

[0053] To achieve the above-mentioned goals, this invention provides a method for controlling the key dimensions of multilayer photomasks. Please refer to [the relevant documentation]. Figure 1 This is a flowchart of a key dimension control method for a multilayer photomask provided in one embodiment of the present invention. Figure 1 As shown, the key dimension control method for multilayer photomasks provided by the present invention includes the following steps:

[0054] Step S100: Divide the layout of the multilayer photomask into multiple chip layers, and each chip layer has a dicing area around its perimeter;

[0055] Step S200: For each chip layer, at least one set of critical dimension measurement pattern groups are placed in each of the dicing areas around the chip layer. Each set of critical dimension measurement pattern groups includes at least one dense pattern whose size matches the critical dimension specification requirements of the chip layer and at least one isolated pattern whose size matches the critical dimension specification requirements of the chip layer.

[0056] Step S300: Fabricate a multilayer photomask based on the layout of the multilayer photomask with the key dimension measurement pattern group arranged in the cutting area.

[0057] Step S400: Measure the dimensions of each dense pattern and each isolated pattern in each group of key dimension measurement pattern groups in the multilayer photomask.

[0058] Step S500: Control the fabrication process of the multilayer photomask based on the measurement results of the dimensions of each of the dense patterns and each of the isolated patterns.

[0059] Therefore, the critical dimension control method for multilayer photomasks provided by this invention can solve the problem of decreased critical dimension uniformity of different chip layers caused by integrating multiple chips onto a single photomask, thus affecting chip yield and failing to meet the process specifications requirements of advanced nodes. Furthermore, by specifically designing critical dimension measurement pattern sets, this invention can address the critical dimension uniformity problem caused by integrating different chip layers in multilayer photomasks. Measurement control can be performed in the dicing area, allowing for the detection of poor critical dimension uniformity during the measurement steps of multilayer photomask manufacturing. This enables analysis of problems arising from the manufacturing process, thereby promoting the mass production and standard manufacturing process specification control of multilayer photomasks at advanced nodes. Additionally, since exposure, etching, and other processes vary at different locations on the substrate during photomask fabrication, this invention, by placing at least one set of critical dimension measurement pattern sets in each dicing area around each chip layer, can help capture process fluctuations across the entire photomask area. Meanwhile, since dense patterns are susceptible to the proximity effect, while isolated patterns are more sensitive to exposure dose, setting up a critical dimension measurement pattern group consisting of at least one dense pattern and at least one isolated pattern can ensure fine-grained control over different patterns during the photomask manufacturing stage, thus helping to solve the problems caused by multi-layer masks. Furthermore, since the dicing area is a blank area used for physically dividing the chip and does not contain actual circuitry, it is removed and discarded after chip manufacturing. Therefore, setting the critical dimension measurement pattern group in the dicing area can avoid occupying effective chip area, thereby further saving costs.

[0060] It should be noted that, as those skilled in the art will understand, the critical dimension (CD) of a photomask refers to the smallest structural dimension that is most critical in the photomask pattern, typically involving line width, spacing, or contact hole diameter. The accuracy of the critical dimension directly affects the accuracy of pattern transfer during photolithography. Poor control of the critical dimension may lead to short circuits, open circuits, or unstable performance. Different process nodes (such as 7nm and 5nm) have different requirements for the critical dimension; more advanced processes require smaller critical dimensions and higher precision. Critical dimension deviations significantly reduce chip yield and increase manufacturing costs. Therefore, high-precision equipment (such as electron beam lithography and extreme ultraviolet lithography) and stringent inspection methods (such as scanning electron microscopy) are required during manufacturing to ensure that the critical dimension meets the standards. It should also be noted that, as those skilled in the art will understand, this invention does not limit the size of the area occupied by each group of critical dimension measurement patterns in the dicing area. For example, the size of the area occupied by each group of critical dimension measurement patterns in the dicing area can be 120μm × 75μm.

[0061] Please continue to refer to this. Figure 2 This is a schematic diagram of the layout of a multilayer photomask provided in one embodiment of the present invention. For example... Figure 2 As shown in the figure, the layout of the multi-layer photomask is divided into four chip layers 110: chip layer 110A, chip layer 110B, chip layer 110C, and chip layer 110D. These four chip layers 110 have different critical dimension specifications. The gray area surrounding chip layers 110A, 110B, 110C, and 110D is the dicing area 120. It should be noted that although... Figure 2 The illustration is based on the example of dividing the layout of the multilayer photomask into four chip layers 110. However, as those skilled in the art will understand, this does not constitute a limitation of the present invention. In other embodiments, the layout of the multilayer photomask may also be divided into two chip layers 110, three chip layers 110, five chip layers 110, or more chip layers 110. The specific configuration can be set according to actual needs.

[0062] In some exemplary embodiments, for each of the chip layers 110, at least one set of critical dimension measurement patterns 130 is placed in each of the dicing regions 120 located around the chip layer 110, including:

[0063] For each chip layer 110, multiple sets of key dimension measurement pattern groups 130 are evenly placed in each of the cut-out areas 120 around the chip layer 110.

[0064] Therefore, for each chip layer 110, multiple sets of key dimension measurement pattern groups 130 are evenly placed in each of the dicing regions 120 around the chip layer 110. This ensures that both dense and isolated patterns of each chip layer 110 can obtain sufficient sampling points. Thus, for each chip layer 110, the key dimension performance of the chip layer 110 can be monitored by measuring the dimensions of various dense and isolated patterns in these key dimension measurement pattern groups 130 in the dicing regions 120 around the chip layer 110. This ensures fine control of different chip layers 110 during the photomask manufacturing stage.

[0065] Please continue to refer to this. Figure 3 This is a schematic diagram showing the placement of the key dimension measurement graphic group 130 in the cutting channel area 120 according to an embodiment of the present invention. Figure 3 As shown, for each chip layer 110, 14 sets of key dimension measurement patterns 130 are evenly arranged in each dicing region 120 around the chip layer 110. It should be noted that, although... Figure 3 The example given is that 14 sets of key dimension measurement pattern groups 130 are evenly arranged in each dicing area 120 around each chip layer 110. However, as those skilled in the art will understand, this does not constitute a limitation of the present invention. In other embodiments, fewer or more than 14 sets of key dimension measurement pattern groups 130 may be evenly arranged in each dicing area 120 around each chip layer 110. The specific number of sets of key dimension measurement pattern groups 130 can be set according to the actual situation.

[0066] In some exemplary embodiments, the dimensions of each dense pattern and each isolated pattern in the critical dimension measurement pattern group 130 range from 80 nm to 1500 nm. Therefore, by setting the dimension range of each dense pattern and each isolated pattern in the critical dimension measurement pattern group 130 to 80 nm to 1500 nm, critical dimensions requiring control under different photomask specifications can be covered.

[0067] In some exemplary embodiments, each group of critical dimension measurement patterns 130 includes dense lines 131, dense contacts 132, and dense holes 133. Since the dense lines 131 are greatly affected by the proximity effect, monitoring their dimensions can reflect the lithographic resolution limit. Similarly, since the dense contacts 132 and dense holes 133 exhibit significant etching load effects, monitoring their dimensions can detect etching uniformity.

[0068] Please continue to refer to this. Figure 4a and Figure 4b ,in, Figure 4a A schematic diagram of dense lines 131 at 80 nm provided in one embodiment of the present invention; Figure 4b This is a schematic diagram of a dense line 131 of 1500nm provided according to an embodiment of the present invention. Figure 4a and Figure 4b As shown, in some exemplary embodiments, the dense lines 131 comprise a plurality of parallel and equally spaced lines. Thus, by configuring the dense lines 131 to comprise a plurality of parallel and equally spaced lines, it is not only ensured that line size changes respond only to exposure / etching parameters, eliminating layout interference and helping to shorten the process debugging cycle, but also that the dimensions of the dense lines 131 are more easily measured.

[0069] It should be noted that, as those skilled in the art will understand, the dimensions of the dense lines 131 include linewidth (dense linewidth) and spacing (dense spacing). It should also be noted that, as those skilled in the art will understand, during the layout design phase, for each chip layer 110, the target value for the width (dense linewidth) of the dense lines 131 in the dicing area 120 surrounding the chip layer 110 can be determined based on the dense linewidth specification requirements of the chip layer 110 (i.e., the linewidth of the dense lines 131 in the dicing area 120 surrounding the chip layer 110 matches the dense linewidth specification requirements of the chip layer 110); and the target value for the spacing (dense spacing) of the dense lines 131 in the dicing area 120 surrounding the chip layer 110 can be determined based on the dense spacing specification requirements of the chip layer 110 (i.e., the spacing of the dense lines 131 in the dicing area 120 surrounding the chip layer 110 matches the dense spacing specification requirements of the chip layer 110).

[0070] Please continue to refer to this. Figure 5a and Figure 5b ,in, Figure 5a A schematic diagram of an 80nm dense block 132 provided in one embodiment of the present invention; Figure 5b This is a schematic diagram of a 1500nm dense square 132 provided according to an embodiment of the present invention. Figure 5a and Figure 5b As shown, in some exemplary embodiments, the dense block 132 comprises a plurality of equally spaced blocks arranged in a square array. Therefore, by setting the dense block 132 to include a plurality of equally spaced blocks arranged in a square array, it is not only easier to accurately capture the etching load effect, but also to enhance the statistical significance of the process window, effectively ensuring the accuracy of monitoring the size (dense side length) of the dense block 132.

[0071] It should be noted that, as those skilled in the art will understand, during the layout design phase, for each chip layer 110, the target value of the side length (dense side length) of the dense squares 132 in the cutaway regions 120 surrounding the chip layer 110 can be determined according to the dense side length specification requirements of the chip layer 110 (i.e., the side length of the dense squares 132 surrounding the chip layer 110 matches the dense side length specification requirements of the chip layer 110). It should also be noted that, although... Figure 5a and Figure 5b The example given is that the dense block 132 includes 7×7 equally spaced blocks arranged in a square array. However, as those skilled in the art will understand, this does not constitute a limitation of the present invention. In other embodiments, the dense block 132 may also include fewer than 7×7 equally spaced blocks arranged in a square array or more than 7×7 equally spaced blocks arranged in a square array, which can be configured according to actual needs.

[0072] Please continue to refer to this. Figure 6a and Figure 6b ,in, Figure 6a A schematic diagram of a dense via 133 with a diameter of 80 nm provided in one embodiment of the present invention; Figure 6b This is a schematic diagram of a densely packed via 133 at 1500 nm provided according to an embodiment of the present invention. (See diagram below.) Figure 6a and Figure 6b As shown, in some exemplary embodiments, the dense vias 133 include a plurality of vias that are equally spaced and arranged in a square array. Therefore, by configuring the dense vias 133 to include a plurality of vias that are equally spaced and arranged in a square array, it is not only easier to accurately capture the etching load effect, but also to enhance the statistical significance of the process window, effectively ensuring the accuracy of monitoring the size (dense via diameter) of the dense vias 133.

[0073] It should be noted that, as those skilled in the art will understand, during the layout design phase, for each chip layer 110, the target value of the aperture (dense aperture) of the dense vias 133 located around the chip layer 110 can be determined according to the dense aperture specification requirements of the chip layer 110 (i.e., the aperture of the dense vias 133 located around the chip layer 110 matches the dense aperture specification requirements of the chip layer 110). It should also be noted that, although... Figure 6a and Figure 6bThe example given is that the dense through-hole 133 includes 7×7 through-holes that are equally spaced and arranged in a square array. However, as those skilled in the art will understand, this does not constitute a limitation of the present invention. In other embodiments, the dense through-hole 133 may also include fewer than 7×7 through-holes that are equally spaced and arranged in a square array or more than 7×7 through-holes that are equally spaced and arranged in a square array, which can be configured according to actual needs.

[0074] In some exemplary embodiments, each set of critical dimension measurement patterns 130 includes isolated lines 134 (iso line / space), isolated squares 135 (iso contact), and isolated holes 136 (iso hole). Since isolated lines 134 are highly sensitive to exposure dose, precise control of the exposure dose can be achieved by monitoring the size of isolated lines 134; since developer diffusion causes morphological distortion of isolated squares 135, precise control of the consistency of developer diffusion can be achieved by monitoring the size (isolated side length) of isolated squares 135; since etching residue can cause isolated holes 136 to remain unopened, precise control of etching residue can be achieved by monitoring the size (isolated aperture) of isolated holes 136.

[0075] Please continue to refer to this. Figure 7a and Figure 7b ,in, Figure 7a A schematic diagram of an 80nm isolated line 134 provided for one embodiment of the present invention; Figure 7b This is a schematic diagram of an isolated line 134 at 1500 nm provided according to an embodiment of the present invention. Figure 7a and Figure 7b As shown, the isolated line 134 includes an opaque line 134A and a translucent line 134B, wherein the width of the opaque line 134A represents the width of the isolated line, and the width of the translucent line 134B represents the isolated gap. It should be noted that, as those skilled in the art will understand, during the layout design phase, for each chip layer 110, the target value of the linewidth (isolated linewidth) of the isolated lines 134 in the dicing area 120 surrounding the chip layer 110 can be determined according to the isolated linewidth specification requirements of the chip layer 110 (i.e., the linewidth of the isolated lines 134 in the dicing area 120 surrounding the chip layer 110 matches the isolated linewidth specification requirements of the chip layer 110); and the target value of the gap (isolated gap) of the isolated lines 134 in the dicing area 120 surrounding the chip layer 110 can be determined according to the isolated gap specification requirements of the chip layer 110 (i.e., the gap of the isolated lines 134 in the dicing area 120 surrounding the chip layer 110 matches the isolated gap specification requirements of the chip layer 110).

[0076] Please continue to refer to this. Figure 8a and Figure 8b ,in, Figure 8a A schematic diagram of an 80nm isolated cube 135 provided for one embodiment of the present invention; Figure 8b This is a schematic diagram of an isolated cube 135 of 1500nm provided according to an embodiment of the present invention. It should be noted that, as those skilled in the art will understand, during the layout design stage, for each chip layer 110, the target value of the side length (isolated side length) of the isolated cube 135 located in the dicing area 120 around the chip layer 110 can be determined according to the isolated side length specification requirements of the chip layer 110. (That is, the side length of the isolated cube 135 located in the dicing area 120 around the chip layer 110 matches the isolated side length specification requirements of the chip layer 110.)

[0077] Please continue to refer to this. Figure 9a and Figure 9b ,in, Figure 9a A schematic diagram of an 80nm isolated via 136 provided in one embodiment of the present invention; Figure 9b This is a schematic diagram of a 1500nm isolated via 136 provided according to an embodiment of the present invention. It should be noted that, as those skilled in the art will understand, during the layout design stage, for each chip layer 110, the target value of the aperture (isolated aperture) of the isolated via 136 located in the dicing region 120 surrounding the chip layer 110 can be determined according to the isolated aperture specification requirements of the chip layer 110 (i.e., the aperture of the isolated via 136 located in the dicing region 120 surrounding the chip layer 110 matches the isolated aperture specification requirements of the chip layer 110).

[0078] In some exemplary embodiments, measuring the dimensions of each dense pattern and each isolated pattern in each group of critical dimension measurement pattern sets 130 in the multilayer photomask includes:

[0079] The dimensions of each dense pattern and each isolated pattern in each group of key dimension measurement pattern 130 in the multilayer photomask are measured using a scanning electron microscope.

[0080] Since the electron beam wavelength of a scanning electron microscope is much smaller than that of visible light (400nm~700nm), it breaks through the optical diffraction limit and has high resolution. Therefore, by using a scanning electron microscope to measure the size of each dense pattern and each isolated pattern of the critical dimension measurement pattern group 130 in the multilayer photomask, the accuracy of the measurement results can be effectively guaranteed. This can help to discover the problem of poor uniformity of critical dimensions in the measurement step during the photomask manufacturing stage.

[0081] Specifically, the details of how to use a scanning electron microscope to measure the line width and gap of dense lines 131 and isolated lines 134, the side length of dense blocks 132 and isolated blocks 135, and the aperture of dense through holes 133 and isolated through holes 136 can be adapted to the relevant content known to those skilled in the art, and will not be elaborated here.

[0082] In some exemplary embodiments, controlling the fabrication process of the multilayer photomask based on measurements of the dimensions of each of the dense patterns and each of the isolated patterns includes:

[0083] For each chip layer 110, based on the measurement results of the dimensions of each dense pattern and each isolated pattern in all the key dimension measurement pattern groups of the cut-out region 120 around the chip layer 110, the dimensional uniformity of each dense pattern and each isolated pattern in the cut-out region 120 around the chip layer 110 is calculated respectively.

[0084] The fabrication process of the multilayer photomask is controlled based on the dimensional uniformity of each dense pattern and each isolated pattern in the dicing region 120 surrounding each chip layer 110.

[0085] Therefore, by calculating the dimensional uniformity of each dense pattern and each isolated pattern in the critical dimension measurement pattern group of the dicing region 120 surrounding the chip layer 110 for each chip layer 110, based on the measurement results of the dimensions of each dense pattern and each isolated pattern in the critical dimension measurement pattern group surrounding the chip layer 110, multi-layer monitoring can be completed in a single photomask manufacturing process, effectively avoiding the repeated measurement costs of traditional single-layer photomasks. Moreover, by combining layered and classified data analysis, the source of fluctuation can be accurately located. By controlling the manufacturing process of the multi-layer photomask based on the dimensional uniformity of each dense pattern or isolated pattern in the dicing region 120 surrounding each chip layer 110, the critical dimension consistency of the multi-layer photomask can be effectively controlled, which can help promote the mass production and standard production process specification control of multi-layer photomask development at advanced nodes.

[0086] Specifically, for each chip layer 110, the mean value of the dense line width can be calculated based on the measurement results of the line width of all dense lines 131 around the chip layer 110. Then, the standard deviation of the dense line width can be calculated based on the measurement results of the line width of all dense lines 131 around the chip layer 110 and the calculated mean value of the dense line width. Finally, the uniformity of the dense line width corresponding to the chip can be calculated based on the calculated standard deviation of the dense line width and the target value of the dense line width.

[0087] Similarly, the uniformity of dense gaps, dense side lengths, dense apertures, isolated linewidths, isolated gaps, isolated side lengths, and isolated apertures corresponding to each chip layer 110 can be calculated.

[0088] It should be noted that for each chip layer 110, if the dimensional uniformity of any type of dense pattern or isolated pattern around the chip layer 110 exceeds the standard, the cause needs to be analyzed and the process adjusted to ensure the critical dimensional uniformity of the chip layer 110.

[0089] Please continue to refer to this. Figure 10 This is a flowchart of the photomask design phase. For example... Figure 10 As shown, during the photomask design stage, a dedicated software tool called MDP (Mask Data Preparation) can be used to process and generate multiple chip layers 110 integrated on a single photomask layout, which are then fabricated and sent to the photomask factory.

[0090] Please continue to refer to this. Figure 11 This is a flowchart of the photomask manufacturing process. For example... Figure 11 As shown, in the photomask manufacturing stage, a production process for multi-chip photomasks (multi-layer photomasks) is established. For different chip layers 110, after the photomask has undergone exposure, development, etching, and resist removal processes to expose the dense and isolated patterns in the critical dimension measurement pattern group 130 located in the dicing area 120, the dimensions of these dense and isolated patterns can be measured. Based on the measurement results of these dense and isolated patterns, the preceding production process (such as exposure parameters, etching time, etc.) can be checked and optimized. This can solve the problems in the production of multi-layer photomasks and achieve the purpose of mass production and specification control of multi-layer photomasks.

[0091] In summary, compared with the prior art, the key dimension control method for multilayer photomasks provided by the present invention has the following beneficial effects:

[0092] (1) The critical dimension control method for multilayer photomasks provided by the present invention first divides the layout of the multilayer photomask into multiple chip layers 110, and each chip layer 110 is provided with a dicing area 120 around its perimeter; then, for each chip layer 110, at least one set of critical dimension measurement pattern groups 130 are placed in each dicing area 120 around the chip layer 110, and each set of critical dimension measurement pattern groups 130 includes at least one dense pattern whose size matches the critical dimension specification requirements of the chip layer 110 and at least one isolated pattern whose size matches the critical dimension specification requirements of the chip layer 110. The process involves creating a pattern, then fabricating a multilayer photomask based on the layout of the critical dimension measurement pattern group 130 arranged in the dicing area 120. Next, the dimensions of each dense pattern and each isolated pattern in each critical dimension measurement pattern group 130 of the multilayer photomask are measured. Finally, based on the measurement results of each dense pattern and each isolated pattern, the fabrication process of the multilayer photomask is controlled. This addresses the problem of decreased critical dimension uniformity between different chip layers caused by integrating multiple chips onto a single photomask, which affects chip yield and fails to meet the process specifications of advanced nodes. Furthermore, by specifically designing the critical dimension measurement pattern group 130, this invention addresses the critical dimension uniformity problem caused by integrating different chip layers 110 into the multilayer photomask. Measurement control is performed in the dicing area 120, allowing for the detection of poor critical dimension uniformity during the measurement steps of the multilayer photomask manufacturing stage. This enables analysis of problems arising from the production process, thereby promoting mass production and standard production process specification control for multilayer photomask development at advanced nodes. Meanwhile, since dense patterns are susceptible to the proximity effect, while isolated patterns are more sensitive to exposure dose, setting at least one dense pattern and at least one isolated pattern together to form a critical dimension measurement pattern group 130 ensures fine-grained control over different patterns during the photomask manufacturing stage, thus helping to solve the problems caused by multi-layer masks. Furthermore, since the dicing area 120 is a blank area used for physically dividing the chip and does not contain actual circuitry, it is cut off and discarded after chip manufacturing. Therefore, by setting the critical dimension measurement pattern group 130 in the dicing area 120, it avoids occupying effective chip area, thereby further saving costs.

[0093] (2) Since different patterns correspond to different physical structures and process sensitivities, the present invention sets up a key dimension measurement pattern group 130 by setting up dense lines 131, dense blocks 132, dense through holes 133, isolated lines 134, isolated blocks 135 and isolated through holes 136 together. This can ensure that the different patterns can be finely controlled in the photomask manufacturing stage, thereby promoting the mass production and standard production process specification control of multilayer photomask development at advanced nodes, and making it easier to realize the mass production of multilayer photomasks.

[0094] (3) By uniformly placing multiple sets of key dimension measurement pattern groups 130 in each of the dicing regions 120 around each chip layer 110, the present invention can ensure that both dense and isolated patterns of each chip layer 110 can obtain sufficient sampling points. Thus, for each chip layer 110, the key dimension performance of the chip layer 110 can be monitored by measuring the dimensions of various dense and isolated patterns in these key dimension measurement pattern groups 130 in the dicing regions 120 around the chip layer 110. This ensures fine control of different chip layers 110 during the photomask manufacturing stage.

[0095] (4) By setting the size range of each dense pattern and each isolated pattern in the critical dimension measurement pattern group 130 to 80nm to 1500nm, the present invention can cover the critical dimensions controlled by different photomask specifications.

[0096] It should be noted that in the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0097] It should also be noted that the above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A method for controlling the key dimensions of a multilayer photomask, characterized in that, The control method includes: The layout of the multilayer photomask is divided into multiple chip layers, and each chip layer has a dicing area around its perimeter. For each chip layer, at least one set of critical dimension measurement patterns is placed in each of the dicing regions located around the chip layer. Each set of critical dimension measurement patterns includes at least one dense pattern whose size matches the critical dimension specification requirements of the chip layer and at least one isolated pattern whose size matches the critical dimension specification requirements of the chip layer. A multi-layer photomask is fabricated based on the layout of the multi-layer photomask in which the key dimension measurement pattern group is arranged in the cutting area. Measure the dimensions of each dense pattern and each isolated pattern in each group of key dimension measurement pattern groups in the multilayer photomask; The fabrication process of the multilayer photomask is controlled based on the measurement results of the dimensions of each of the dense patterns and each of the isolated patterns. The step of controlling the fabrication process of the multilayer photomask based on the measurement results of the dimensions of each of the dense patterns and each of the isolated patterns includes: For each chip layer, based on the measurement results of the dimensions of each dense pattern and each isolated pattern in all the key dimension measurement pattern groups located around the chip layer, the dimensional uniformity of each dense pattern and each isolated pattern located around the chip layer is calculated respectively. The fabrication process of the multilayer photomask is controlled based on the dimensional uniformity of each dense pattern and each isolated pattern in the dicing area surrounding each chip layer.

2. The method for controlling the key dimensions of a multilayer photomask according to claim 1, characterized in that, Each set of the critical dimension measurement graphics includes dense lines, dense squares, and dense through holes.

3. The method for controlling the key dimensions of a multilayer photomask according to claim 2, characterized in that, The dense lines consist of multiple parallel lines arranged at equal intervals.

4. The method for controlling the key dimensions of a multilayer photomask according to claim 2, characterized in that, The dense blocks include multiple blocks that are equally spaced and arranged in a square array.

5. The method for controlling the key dimensions of a multilayer photomask according to claim 2, characterized in that, The dense through-holes include multiple through-holes that are equally spaced and arranged in a square array.

6. The method for controlling the key dimensions of a multilayer photomask according to claim 1, characterized in that, Each set of critical dimension measurement graphics includes isolated lines, isolated squares, and isolated through holes.

7. The method for controlling the key dimensions of a multilayer photomask according to claim 1, characterized in that, The dimensions of each dense pattern and each isolated pattern in the critical dimension measurement pattern set range from 80nm to 1500nm.

8. The method for controlling the key dimensions of a multilayer photomask according to claim 1, characterized in that, For each of the chip layers, at least one set of key dimension measurement patterns is placed in each of the dicing regions located around the chip layer, including: For each chip layer, multiple sets of key dimension measurement patterns are evenly placed in each of the cut-out areas around the chip layer.

9. The method for controlling the key dimensions of a multilayer photomask according to claim 1, characterized in that, The measurement of the dimensions of each dense pattern and each isolated pattern in each group of key dimension measurement patterns in the multilayer photomask includes: The dimensions of each dense pattern and each isolated pattern in each group of key dimension measurement patterns in the multilayer photomask were measured using a scanning electron microscope.

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