Instruction execution method and apparatus, electronic device, and storage medium

Abstract

The present disclosure provides an instruction execution method and device, electronic equipment and storage medium, and relates to the technical field of computer processors. The method comprises: after the register renaming pipeline stage, identifying the instruction type of the to-be-executed instruction; and performing instruction operation on the to-be-executed instruction based on the instruction type. Thus, compared with the current technology in which all types of instructions need to be sent to the dispatch queue to implement subsequent instruction operation, the present scheme can improve the instruction execution efficiency, reduce resource consumption, and enhance the flexibility and adaptability of the processor by setting different instruction types corresponding to different instruction operations.

Description

Technical Field

[0001] This disclosure relates to the field of computer processor technology, and in particular to an instruction execution method, apparatus, electronic device, and storage medium. Background Technology

[0002] Processor operations on the Control and Status Register (CSR) must ensure atomicity and state consistency. Because CSR operations may trigger exceptions (such as unauthorized access or interrupts), it is necessary to ensure that when an exception occurs, the preceding instructions have completed the CSR state update (e.g., modifying the mstatus register responsible for global interrupt management, privilege mode switching, and processor state monitoring), and the subsequent instructions have not performed state-dependent operations (e.g., the return address stored in the context save register mepc). In this case, the pipeline must be blocked until the CSR operation is committed; otherwise, the accurate state cannot be reconstructed during exception recovery. Summary of the Invention

[0003] This disclosure aims to at least partially address one of the technical problems in the related art.

[0004] Therefore, one objective of this disclosure is to propose an instruction execution method.

[0005] The second objective of this disclosure is to provide an instruction execution device.

[0006] The third objective of this disclosure is to propose an electronic device.

[0007] The fourth objective of this disclosure is to provide a non-transitory computer-readable storage medium.

[0008] The fifth objective of this disclosure is to provide a computer program product.

[0009] To achieve the above objectives, the first aspect of this disclosure provides an instruction execution method, comprising: identifying the instruction type of the instruction to be executed after a register renaming pipeline stage; and performing instruction operations on the instruction to be executed based on the instruction type.

[0010] According to one embodiment of this disclosure, the instruction operation on the instruction to be executed based on the instruction type includes: in response to the instruction type of the instruction to be executed being a Control and Status Register (CSR) instruction, executing the instruction to be executed and stopping the execution of other instruction operations besides the instruction to be executed; until the instruction to be executed is completed, continuing to execute other instructions besides the instruction to be executed.

[0011] According to one embodiment of this disclosure, stopping the execution of other instructions besides the instruction to be executed includes: blocking the first-level dispatch operation of the other instructions and preventing the other instructions from being dispatched to each dispatch queue.

[0012] According to one embodiment of this disclosure, the dispatch queue includes a fixed-point dispatch queue, a floating-point dispatch queue, and a memory access dispatch queue.

[0013] According to one embodiment of this disclosure, continuing to execute other instructions besides the instruction to be executed includes: resuming the first-level dispatch operation of the other instructions and allowing the other instructions to be dispatched to various dispatch queues.

[0014] According to one embodiment of this disclosure, executing the instruction to be executed includes: directly executing the instruction to be executed in the first-level dispatch stage, wherein the instruction to be executed does not enter the dispatch queue and subsequent flow stages.

[0015] According to one embodiment of this disclosure, the step of performing instruction operation on the instruction to be executed based on the instruction type includes: in response to the instruction type of the instruction to be executed being a non-Control and Status Register (CSR) instruction, determining the target dispatch queue corresponding to the non-CSR instruction, and writing the non-CSR instruction into the target dispatch queue.

[0016] To achieve the above objectives, a second aspect of this disclosure provides an instruction execution apparatus, comprising: an identification module for identifying the instruction type of an instruction to be executed after a register renaming pipeline stage; and an execution module for performing instruction operations on the instruction to be executed based on the instruction type.

[0017] To achieve the above objectives, a third aspect of this disclosure provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to implement the instruction execution method as described in the first aspect of this disclosure.

[0018] To achieve the above objectives, a fourth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to implement the instruction execution method as described in the first aspect of this disclosure.

[0019] To achieve the above objectives, a fifth aspect of this disclosure provides a computer program product, including a computer program that, when executed by a processor, implements the instruction execution method as described in the first aspect of this disclosure.

[0020] Therefore, compared to the current technology where all types of instructions need to be sent to the dispatch queue to perform subsequent instruction operations, this solution can improve instruction execution efficiency, reduce resource consumption, and enhance processor flexibility and adaptability by setting different instruction types to correspond to different instruction operations. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of an instruction execution method according to one embodiment of the present disclosure;

[0022] Figure 2 This is a schematic diagram of a RISC-V CSR instruction according to one embodiment of the present disclosure;

[0023] Figure 3 This is a schematic flowchart of a processor pipeline according to one embodiment of the present disclosure;

[0024] Figure 4 This is a schematic diagram of another instruction execution method according to one embodiment of the present disclosure;

[0025] Figure 5 This is a schematic flowchart of another processor pipeline according to one embodiment of the present disclosure;

[0026] Figure 6 This is a schematic diagram of an instruction execution device according to one embodiment of the present disclosure;

[0027] Figure 7 This is a schematic diagram of an electronic device according to one embodiment of the present disclosure. Detailed Implementation

[0028] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0029] The acquisition, storage, use, and processing of data in this disclosed technical solution all comply with the relevant provisions of relevant laws and regulations.

[0030] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0031] In current technology, processor modifications to the Control and Status Register (CSR) must adhere to specific instruction set specifications and hardware access rules. For example, in the RISC-V (Reduced Instruction Set Computing – V) architecture, the specific CSR instructions and execution methods are as follows:

[0032] 1. Atomic read-modify-write operation

[0033] All CSR instructions perform read, modify, and write operations atomically, ensuring data consistency in multi-threaded or interrupt-driven scenarios. For example:

[0034] CSRRW: Writes the source register value to the CSR while simultaneously reading the original CSR value into the destination register;

[0035] CSRRS: Set specific bits of CSR using a mask, while leaving other bits unchanged;

[0036] CSRRC: Clears specific bits of CSR using a mask, leaving other bits unchanged.

[0037] 2. Immediate value operation instructions

[0038] For scenarios involving 5-bit unsigned immediate values, variant instructions such as CSRRWI, CSRRSI, and CSRRCI can be used, where the immediate value is zero-extended to 32 bits before being used in the operation.

[0039] 3. Instruction Format and Operands

[0040] like Figure 2 As shown, RISC-V's CSR instructions include a 12-bit encoded CSR address field (located in bits 31-20 of the instruction), supporting the specification of the target register by register name (e.g., mtvec) or direct number (e.g., 0x305). zimm is the immediate value, rs1 is the source register, and rd is the destination register. Through this mechanism, the processor's state and behavior can be precisely controlled while ensuring atomicity.

[0041] Because CSR instructions have long execution times, requiring two stages of dispatch, issue, and re-execution control and status register operations followed by write-back, they lead to wasted processor hardware resources, such as consuming resources in the dispatch and issue queues. The atomicity requirement of CSR instructions forces frequent pipeline blocking or flushing (hazard handling), causing pipeline bubbles and reducing instructions per cycle (IPC). Since CSR instructions execute out of order, the blocking and flushing processes involve determining which instructions precede and follow the CSR instructions, a costly process.

[0042] To address the aforementioned problems, this disclosure proposes an instruction execution method. Figure 1 This is a schematic diagram of an instruction execution method according to one embodiment of the present disclosure, as shown below. Figure 1 As shown, the instruction execution method includes the following steps:

[0043] S101 identifies the instruction type of the instruction to be executed after the register renaming pipeline stage.

[0044] The instruction execution method of this application embodiment can be applied to the scenario of instruction allocation and execution. The execution subject of the instruction execution in this application embodiment can be the instruction execution device of this application embodiment, which can be installed on an electronic device.

[0045] Pipelining breaks down the instruction execution process into multiple steps, each step performing a specific task, so that multiple instructions can be processed in parallel at different stages.

[0046] In one possible implementation, such as Figure 3 As shown, Figure 3 This is a schematic diagram of a processor pipeline according to one embodiment of the present disclosure. In the processor pipeline, the instruction type of the instruction to be executed is identified in the first-level dispatch stage, and then the corresponding instruction is allocated to the corresponding dispatch queue according to the instruction type. In the processor, after register renaming, the dispatch logic includes two pipeline stages. The first-level dispatch is responsible for classifying instructions and sending them to three types of dispatch queues (fixed-point, floating-point, and memory access). The second-level dispatch is responsible for further dispatching the corresponding type of instruction to different issue queues (IQ) according to different operation types.

[0047] The first-level dispatch includes determining the type of instruction and whether each instruction can proceed to the next level. For control and status register instructions, the operation on the control and status registers is performed directly.

[0048] A dispatch queue is a buffer between the first-level dispatch and the second-level dispatch. Dispatch queues include fixed-point dispatch queues, floating-point dispatch queues, and memory access dispatch queues. The second-level dispatch is responsible for sending instructions from various dispatch queues to different issue queues based on different instruction types and the instruction types accepted by different issue queues.

[0049] The instruction types to be executed typically include, but are not limited to, the following:

[0050] Arithmetic Logic Unit (ALU) instructions: such as basic operation instructions like addition, subtraction, logical AND, and logical OR.

[0051] Branch instructions: Jump instructions used to control program flow, such as conditional jumps and unconditional jumps.

[0052] Memory access instructions: Instructions involving memory read and write operations, such as load and store instructions.

[0053] Floating-point arithmetic instructions: Instructions for performing operations on floating-point numbers, such as floating-point addition and floating-point multiplication.

[0054] Control and Status Register (CSR) instructions: used to read and write the processor's control and status registers to modify the processor's operating state or query the current state.

[0055] Special function instructions: such as system calls, interrupt handling, and related instructions.

[0056] S102, perform instruction operations on the instruction to be executed based on the instruction type.

[0057] In this embodiment, different instruction types may correspond to different instruction operations. This correspondence is pre-designed and can be changed according to actual design needs, without any limitations. For example, instruction operations may include direct execution, sending the instruction to the corresponding dispatch queue, delayed execution, increasing the execution priority, fixed-point arithmetic, floating-point arithmetic, memory access operations, etc.

[0058] Based on instruction type, instruction operations are performed on the instructions to be executed. Compared to the current technology where all types of instructions need to be sent to a dispatch queue to complete subsequent instruction operations, this method has the following advantages:

[0059] 1. Improve instruction execution efficiency

[0060] Directly process specific instruction types: For example, in the case of a CSR instruction, the control and status register operations can be completed directly in the first-level dispatch stage, without placing the instruction in the regular dispatch queue for further processing. This reduces unnecessary queuing time and speeds up the instruction execution process.

[0061] Reduce pipeline latency: By identifying and processing specific types of instructions in advance (such as CSR instructions), delays caused by waiting for other instructions can be avoided, thereby optimizing the efficiency of the entire pipeline.

[0062] 2. Reduce resource consumption

[0063] Saves hardware resources: Instructions that do not need to enter the dispatch queue or launch queue (such as CSR instructions) can be processed and their functions completed directly, which reduces the occupation of these resources and improves the overall system resource utilization efficiency.

[0064] Avoiding pipeline blocking and flushing: Traditionally, to ensure the atomicity of CSR instructions, it may be necessary to block subsequent instructions or flush the pipeline. Processing CSR instructions directly in the first dispatch stage simplifies this process, reduces the need for pipeline blocking and flushing, and lowers processor complexity and power consumption.

[0065] 3. Enhance processor flexibility and adaptability

[0066] Supports efficient processing of multiple instruction types: By classifying and processing instruction types immediately after register renaming, it can more flexibly cope with different types of instruction requirements, such as fixed-point arithmetic, floating-point arithmetic, memory access operations, etc., enabling the processor to better adapt to complex computing tasks.

[0067] Simplify pipeline design: By determining instruction types and processing them at an early stage, the design and management of subsequent pipelines can be simplified, reducing design complexity and improving system stability and reliability.

[0068] 4. Ensure precise control and data consistency

[0069] Maintaining program order correctness: For certain instructions that require a strict program order (such as CSR instructions), processing at the first-level dispatch stage can ensure that these instructions are executed in the correct order, thus maintaining program correctness and data consistency.

[0070] Simplified dependency management: Since CSR instructions typically involve modifications to the processor state, handling them directly at the first dispatch stage makes it easier to manage and resolve potential data dependencies, avoiding complex dependency judgment logic.

[0071] In the above embodiments, instruction operations are performed on the instruction to be executed based on the instruction type, and can also be achieved through... Figure 4 To further explain, the method includes:

[0072] S401, in response to the instruction type of the instruction to be executed being the Control and Status Register (CSR) instruction, executes the instruction to be executed and stops executing other instruction operations except for the instruction to be executed.

[0073] In this invention, the CSR instruction performs control and status register operations after the register renaming pipeline stage, thus completing the CSR instruction execution function. The CSR instruction does not need to enter the dispatch queue, issue queue, or subsequent execution pipeline stages.

[0074] In this disclosure, the instruction to be executed is executed directly in the first-level dispatch stage, and the instruction to be executed does not enter the dispatch queue or subsequent pipeline stages. The CSR execution of this invention is carried out in the first-level dispatch stage, realizing the early execution of CSR instructions, improving the execution efficiency of CSR instructions, and at the same time, CSR instructions no longer occupy the dispatch queue, reservation station and subsequent execution pipeline stages, reducing the resource consumption of CSR instructions.

[0075] To address the hazard (also called dependency) associated with the Control and Status Register (CSR) and ensure the atomicity of CSR instructions, the pipeline needs to be blocked or flushed during CSR instruction execution. CSR instructions run sequentially before first-level dispatch. When a CSR instruction is modified, subsequent instructions are blocked from first-level dispatch, preventing other instructions from being dispatched to their respective dispatch queues until the CSR instruction completes execution.

[0076] Compared to current technology where CSR instructions are executed after being dispatched in two stages and issued from the dispatch queue, this simplifies the blocking logic, further improving processor execution efficiency and reducing processor complexity. Before the first-stage dispatch, the pipeline stages after register renaming are ordered; after entering the dispatch queue, the pipeline stages are out of order. Executing CSR instructions in the first-stage dispatch stage reduces the complexity and efficiency loss caused by the current technology where CSR instructions are executed in out-of-order pipeline stages. This requires the processor to determine which instructions precede and follow the CSR instruction, and then block and refresh the pipeline for the instructions following the CSR instruction.

[0077] For example, such as Figure 5 As shown, Figure 5This is a schematic diagram of another processor pipeline according to one embodiment of the present disclosure. The execution of CSR instructions is advanced to the first-level dispatch stage of the pipeline. That is, after register renaming, control and status register operations are executed directly, without needing to go through the current fixed-point, control and status register dispatch queue (Dispatch Queue), and control and status register issue queue (IQ) to execute control and status register operations. This avoids the occupation of the dispatch queue and issue queue (IQ) by control and status register instructions.

[0078] The first level of dispatch determines the type of instruction after register renaming. If it's a control and status register instruction, the operation on the control and status registers is performed directly. Simultaneously, if a CSR instruction is detected during the first level of dispatch, the processor blocks the first-level dispatch. Instructions following the CSR instruction are no longer dispatched to the dispatch queues (including fixed-point, floating-point, and memory access queues). This blockage prevents the flow of subsequent instructions from the CSR instruction until the current CSR instruction completes its operation.

[0079] S402, until the pending instruction is completed, continue executing other instructions except the pending instruction.

[0080] In this embodiment of the disclosure, after the instruction to be executed is completed, it is necessary to determine the instruction type of other instructions and perform operations based on the instruction operation method in the above embodiment.

[0081] In one possible implementation, if the instruction type of other instructions is not a CSR instruction, the first-level dispatch operation of other instructions is resumed after the instructions to be executed have been completed, and other instructions are allowed to be dispatched to their respective dispatch queues.

[0082] For non-control and status register instructions, they are dispatched according to instruction type to the fixed-point dispatch queue, floating-point dispatch queue, or memory access dispatch queue, waiting to enter the issue queue of each functional unit. Dispatch is completed in two pipeline stages. The first pipeline stage performs the operations for control and status register instructions. For non-control and status register instructions, the first pipeline stage dispatches them according to floating-point, fixed-point, or memory access type. The processor has fixed-point dispatch queues, floating-point dispatch queues, and memory access dispatch queues.

[0083] Corresponding to the instruction execution methods provided in the above embodiments, one embodiment of this disclosure also provides an instruction execution device. Since the instruction execution device provided in this disclosure corresponds to the instruction execution methods provided in the above embodiments, the implementation methods of the above instruction execution methods are also applicable to the instruction execution device provided in this disclosure, and will not be described in detail in the following embodiments.

[0084] Figure 6 Figure 6 is a schematic diagram of an instruction execution device according to one embodiment of the present disclosure. As shown in Figure 6, the instruction execution device 600 includes an identification module 610 and an execution module 620.

[0085] The identification module 610 is used to identify the instruction type of the instruction to be executed after the register renaming pipeline stage.

[0086] The execution module 620 is used to perform instruction operations on the instruction to be executed based on the instruction type.

[0087] According to one embodiment of this disclosure, the instruction operation on the instruction to be executed based on the instruction type includes: in response to the instruction type of the instruction to be executed being a Control and Status Register (CSR) instruction, executing the instruction to be executed and stopping the execution of other instruction operations besides the instruction to be executed; until the instruction to be executed is completed, continuing to execute other instructions besides the instruction to be executed.

[0088] According to one embodiment of this disclosure, stopping the execution of other instructions besides the instruction to be executed includes: blocking the first-level dispatch operation of the other instructions and preventing the other instructions from being dispatched to each dispatch queue.

[0089] According to one embodiment of this disclosure, the dispatch queue includes a fixed-point dispatch queue, a floating-point dispatch queue, and a memory access dispatch queue.

[0090] According to one embodiment of this disclosure, continuing to execute other instructions besides the instruction to be executed includes: resuming the first-level dispatch operation of the other instructions and allowing the other instructions to be dispatched to various dispatch queues.

[0091] According to one embodiment of this disclosure, executing the instruction to be executed includes: directly executing the instruction to be executed in the first-level dispatch stage, wherein the instruction to be executed does not enter the dispatch queue and subsequent flow stages.

[0092] According to one embodiment of this disclosure, the step of performing instruction operation on the instruction to be executed based on the instruction type includes: in response to the instruction type of the instruction to be executed being a non-Control and Status Register (CSR) instruction, determining the target dispatch queue corresponding to the non-CSR instruction, and writing the non-CSR instruction into the target dispatch queue.

[0093] Therefore, compared to the current technology where all types of instructions need to be sent to the dispatch queue to perform subsequent instruction operations, this solution can improve instruction execution efficiency, reduce resource consumption, and enhance processor flexibility and adaptability by setting different instruction types to correspond to different instruction operations.

[0094] To implement the above embodiments, this disclosure also proposes an electronic device 700. Figure 7 This is a schematic diagram of an electronic device according to one embodiment of the present disclosure, such as... Figure 7 As shown, the electronic device 700 includes: a processor 701 and a memory 702 communicatively connected to the processor. The memory 702 stores instructions executable by at least one processor. The instructions are executed by at least one processor 701 to achieve the functions described in this disclosure. Figures 1-5 Instruction execution method of the embodiment.

[0095] To implement the above embodiments, this disclosure also proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to implement the present disclosure. Figures 1-5 Instruction execution method of the embodiment.

[0096] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program, which, when executed by a processor, implements the features of this disclosure. Figures 1-5 Instruction execution method of the embodiment.

[0097] It should be noted that personal information collected from users should be used for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. Furthermore, such collection / sharing should only be conducted after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization that includes authorization of relevant user information before the user uses the function. In addition, any necessary steps must be taken to protect and safeguard access to such personal information data and ensure that others with access to personal information data comply with their privacy policies and procedures.

[0098] This application is intended to provide an implementation scheme for users to selectively prevent the use or access to their personal information data. Specifically, this disclosure is intended to provide hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, risks can be minimized by restricting data collection and deleting data. Furthermore, where applicable, such personal information is de-identified to protect user privacy.

[0099] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0100] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0101] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0102] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that contains, stores, communicates, propagates, or transmits programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0103] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0104] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0105] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0106] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method of instruction execution, the method comprising: The method comprises the following steps: After a register renaming pipeline stage, an instruction type of an instruction to be executed is identified; An instruction operation is performed on the instruction to be executed based on the instruction type; The instruction operation performed on the instruction to be executed based on the instruction type comprises the following steps: In response to the instruction type of the instruction to be executed being a control and status register (CSR) instruction, the instruction to be executed is directly executed in a first dispatch stage, the instruction to be executed does not enter a dispatch queue and a subsequent pipeline stage, and a first dispatch operation of other instructions is blocked, and the other instructions are prevented from being dispatched to respective dispatch queues, the control and status register (CSR) instruction being used for reading and writing control and status registers of a processor to modify a working state of the processor or query a current state; Until the instruction to be executed is executed, the other instructions except the instruction to be executed are continuously executed.

2. The method of claim 1, wherein, The dispatch queue comprises a fixed-point dispatch queue, a floating-point dispatch queue and a memory access dispatch queue.

3. The method according to claim 1 or 2, characterized in that, The continuously executing the other instructions except the instruction to be executed comprises the following steps: The first dispatch operation of the other instructions is resumed, and the other instructions are allowed to be dispatched to the respective dispatch queues.

4. The method of claim 1, wherein, The instruction operation performed on the instruction to be executed based on the instruction type comprises the following steps: In response to the instruction type of the instruction to be executed being a non-control and status register (CSR) instruction, a target dispatch queue corresponding to the non-CSR instruction is determined, and the non-CSR instruction is written into the target dispatch queue.

5. An instruction execution apparatus, characterized by comprising: The method comprises the following steps: An identification module is configured to identify an instruction type of an instruction to be executed after a register renaming pipeline stage; An execution module is configured to perform an instruction operation on the instruction to be executed based on the instruction type; The execution module is specifically configured to: In response to the instruction type of the instruction to be executed being a control and status register (CSR) instruction, the instruction to be executed is directly executed in a first dispatch stage, the instruction to be executed does not enter a dispatch queue and a subsequent pipeline stage, and a first dispatch operation of other instructions is blocked, and the other instructions are prevented from being dispatched to respective dispatch queues, the control and status register (CSR) instruction being used for reading and writing control and status registers of a processor to modify a working state of the processor or query a current state; Until the instruction to be executed is executed, the other instructions except the instruction to be executed are continuously executed.

6. An electronic device, comprising: The method comprises the following steps: A memory and a processor are comprised; 7. A computer readable storage medium characterized in that, The processor runs a program corresponding to executable program code stored in the memory by reading the executable program code, so as to implement the method according to any one of claims 1-4. The computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the processor to implement the method according to any one of claims 1-4.

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