A multi-bus fault injection circuit

Abstract

This invention discloses a multi-bus fault injection circuit, including a control module, a verification module, and a validation module. The verification module includes several verification units. The control module is used to wake up the verification units by feeding back different Put series signals when a node outputs a signal. The same verification unit constructs the node-injected fault code during the first wake-up. After the SAN wakes up for the second time, it verifies the node data on the serial bus at the SAN end. If correct, the data is erased and awaits reconstruction; if incorrect, an Out series signal is fed back to the validation module for indication. Through a distributed, dynamically reconfigurable fault injection method, the configuration can be automatically erased after verification and reconstructed in real time based on the new fault code fed back by the node, realizing mutual testing between any nodes.

Description

Technical Field

[0001] This invention relates to the field of fault injection technology, and in particular to a multi-bus fault injection circuit. Background Technology

[0002] Fault injection, as an active testing technique, assesses a system's behavior under abnormal conditions by artificially introducing faults, effectively verifying the system's fault tolerance, error recovery mechanisms, and overall stability. However, in current hardware bus communication testing practices, the testing process is highly dependent on the resources of the central control node. The entire system must rely on the central control node to complete the injection and response reception of all test nodes. This approach has low scalability, and the test scale is limited by the processing performance limit of the central control node. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention aims to provide a multi-bus fault injection circuit, comprising a control module, a verification module, and a validation module. The verification module includes several validation units. The control module is used to wake up the validation units by feeding back different Put series signals when a node outputs a signal. The same validation unit constructs the node-injected fault code during the first wake-up. After the SAN wakes up for the second time, it verifies the node data on the serial bus at the SAN end. If the data is correct, it is erased and awaits reconstruction. If the data is incorrect, it feeds back Out series signals to the validation module for indication.

[0004] Furthermore, the verification unit includes several resistors, several diodes, several transistors, several field-effect transistors, several inverting inputs, an operational amplifier, and a capacitor. Among the diodes, the collector of transistor Q1 is connected to one end of resistor R1, one end of resistor R5, and one end of resistor R8; its base is connected to the drain of field-effect transistor Q3 and one end of resistor R4. The collector of transistor Q4 is connected to the non-inverting input of operational amplifier U2, one end of resistor R2, and the other end of resistor R4; its base is connected to the other end of resistor R5. The output of operational amplifier U2 is connected to the Out_1 terminal. The input of inverter U3 is connected to diode D. The cathode of transistor 1, the cathode of diode D2, one end of resistor R10, and the output terminal are connected to the gate of MOSFET Q2; the source of MOSFET Q2 is connected to the SAN terminal, and the drain is connected to the gate of MOSFET Q3 and one end of resistor R11; the source of MOSFET Q3 is connected to one end of capacitor C1; the other ends of resistor R1 and resistor R2 are connected to the power supply; the anode of diode D1 is connected to the Put_1 terminal; the anode of diode D2 is connected to the Put_2 terminal; the emitters of transistors Q1 and Q4, the other ends of resistor R10, resistor R11, and capacitor C1 are grounded.

[0005] Furthermore, the circulation control module includes a multiplexing chip. The second, fourth, seventh, and tenth pins of the multiplexing chip U1 are connected to the Put_1, Put_3, Put_5, and Put_7 terminals, respectively. The fifth, sixth, ninth, and eleventh pins are connected to the Put_2, Put_4, Put_6, and Put_8 terminals, respectively. The first pin is connected to the Port terminal, the fourteenth pin is connected to the CLK terminal, the sixteenth pin is connected to the power supply, and the eighth pin is grounded.

[0006] Furthermore, the verification module includes an AND gate, wherein the first and second input pins of the AND gate U4 are connected to the Out_1 and Out_2 terminals respectively, and the fourth and fifth input pins are connected to the Out_3 and Out_4 terminals respectively.

[0007] Furthermore, the control module includes several multiplexed chips. The second, fourth, seventh, tenth, first, fifth, and sixth pins of multiplexed chip U5 are respectively connected to Put_1, Put_3, Put_5, Put_7, Put_9, Put_11, and Put_13 terminals. The ninth and thirteenth pins are connected to the input terminal and Put_15 terminal of inverter U7, and the fourteenth pin is connected to the fourteenth pin and CLK terminal of multiplexed chip U6. The thirteenth pin of multiplexer U6 is connected to the output of inverter U7. The second, fourth, seventh, tenth, first, fifth, sixth, ninth, and eleventh pins are connected to the Put terminal, Put_2 terminal, Put_4 terminal, Put_6 terminal, Put_8 terminal, Put_10 terminal, Put_12 terminal, Put_14 terminal, and Put_15 terminal, respectively. The sixteenth pin of multiplexer U5 and multiplexer U6 is connected to the power supply. The eighth pin of multiplexer U5 and multiplexer U6 is grounded.

[0008] Furthermore, the control module also includes several resistors, one end of resistor R6 is connected to the thirteenth pin of multiplexing chip U1; one end of resistor R7 is connected to the fifteenth pin of multiplexing chip U1; and the other ends of resistor R6 and resistor R7 are grounded.

[0009] Furthermore, the control module also includes several resistors, one end of resistor R13 and one end of resistor R14 are connected to the thirteenth and fifteenth pins of multiplexing chip U5, respectively; one end of resistor R15 and one end of resistor R16 are connected to the thirteenth and fifteenth pins of multiplexing chip U6, respectively; and the other ends of resistors R13, R14, R15, and R16 are grounded.

[0010] Furthermore, the verification unit also includes several resistors, one end of resistor R13 is connected to the power supply, and the other end is connected to the inverting input of operational amplifier U2 and one end of resistor R9; the other end of resistor R9 is grounded.

[0011] Furthermore, it also includes a level conversion module, which is connected in series between the verification module and the bus to convert the node level to a level that the verification module can recognize.

[0012] The beneficial effects of this invention compared to the prior art are:

[0013] This invention utilizes a distributed, dynamically reconfigurable fault injection method to automatically erase configurations after verification and reconstruct them in real time based on new fault codes fed back by nodes, thereby enabling mutual testing between any nodes. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the overall structure of the present invention.

[0016] Figure 2 This is a schematic diagram of the verification unit structure provided by the present invention.

[0017] Figure 3 This is a schematic diagram of the circulation control module structure provided by the present invention.

[0018] Figure 4 This is a schematic diagram of the verification module structure provided by the present invention.

[0019] Figure 5 This is a schematic diagram of another circulation control module provided by the present invention. Detailed Implementation

[0020] To make the objectives and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection specifically claimed by the present invention.

[0021] like Figure 1As shown, this invention discloses a multi-bus fault injection circuit, including a control module, a verification module, and a validation module. The verification module includes several validation units. The control module is used to wake up the validation units by feeding back different Put series signals when the node outputs a signal. The same validation unit constructs the node injection fault code during the first wake-up. After the SAN wakes up for the second time, it verifies the node data on the serial bus at the SAN end. If it is correct, it erases and waits for reconstruction. If it is incorrect, it feeds back Out series signals to the validation module for indication.

[0022] like Figure 2 As shown, specifically, the verification unit includes several resistors, several diodes, several transistors, several field-effect transistors, several inverting inputs, an operational amplifier, and a capacitor. Among the diodes, the collector of transistor Q1 is connected to one end of resistor R1, one end of resistor R5, and one end of resistor R8, while its base is connected to the drain of field-effect transistor Q3 and one end of resistor R4. The collector of transistor Q4 is connected to the non-inverting input of operational amplifier U2, one end of resistor R2, and the other end of resistor R4, while its base is connected to the other end of resistor R5. The output of operational amplifier U2 is connected to the Out_1 terminal. The input of inverter U3 is connected to diodes. The cathodes of diodes D1 and D2, one end of resistor R10, and the output terminal are connected to the gate of MOSFET Q2. The source of MOSFET Q2 is connected to the SAN terminal, and the drain is connected to the gate of MOSFET Q3 and one end of resistor R11. The source of MOSFET Q3 is connected to one end of capacitor C1. The other ends of resistors R1 and R2 are connected to the power supply. The anode of diode D1 is connected to the Put_1 terminal. The anode of diode D2 is connected to the Put_2 terminal. The emitters of transistors Q1 and Q4, the other ends of resistors R10 and R11, and the other end of capacitor C1 are grounded.

[0023] like Figure 3 As shown, specifically, the circulation control module includes a multiplexing chip. The second, fourth, seventh, and tenth pins of the multiplexing chip U1 are connected to the Put_1, Put_3, Put_5, and Put_7 terminals, respectively. The fifth, sixth, ninth, and eleventh pins are connected to the Put_2, Put_4, Put_6, and Put_8 terminals, respectively. The first pin is connected to the Port terminal, the fourteenth pin is connected to the CLK terminal, the sixteenth pin is connected to the power supply, and the eighth pin is grounded.

[0024] like Figure 4 As shown, specifically, the verification module includes an AND gate. The first and second pins of the first input terminal of the AND gate U4 are connected to the Out_1 and Out_2 terminals, respectively, and the fourth and fifth pins of the second input terminal are connected to the Out_3 and Out_4 terminals, respectively.

[0025] like Figure 5As shown, specifically, the cycle control module includes several multiplexed chips. The second, fourth, seventh, tenth, first, fifth, and sixth pins of multiplexed chip U5 are connected to Put_1, Put_3, Put_5, Put_7, Put_9, Put_11, and Put_13 terminals respectively. The ninth and thirteenth pins are connected to the input terminal and Put_15 terminal of inverter U7, and the fourteenth pin is connected to the fourteenth pin and CLK terminal of multiplexed chip U6. The thirteenth pin of multiplexer U6 is connected to the output of inverter U7. The second, fourth, seventh, tenth, first, fifth, sixth, ninth, and eleventh pins are connected to the Put terminal, Put_2 terminal, Put_4 terminal, Put_6 terminal, Put_8 terminal, Put_10 terminal, Put_12 terminal, Put_14 terminal, and Put_15 terminal, respectively. The sixteenth pin of multiplexer U5 and multiplexer U6 is connected to the power supply. The eighth pin of multiplexer U5 and multiplexer U6 is grounded.

[0026] like Figure 3 As shown, specifically, the control module also includes several resistors, one end of resistor R6 is connected to the thirteenth pin of multiplexing chip U1; one end of resistor R7 is connected to the fifteenth pin of multiplexing chip U1; and the other ends of resistor R6 and resistor R7 are grounded.

[0027] like Figure 5 As shown, specifically, the control module also includes several resistors. One end of resistor R13 and one end of resistor R14 are connected to the thirteenth and fifteenth pins of multiplexing chip U5, respectively; one end of resistor R15 and one end of resistor R16 are connected to the thirteenth and fifteenth pins of multiplexing chip U6, respectively; and the other ends of resistors R13, R14, R15, and R16 are grounded.

[0028] like Figure 2 As shown, specifically, the verification unit also includes several resistors. One end of resistor R13 is connected to the power supply, and the other end is connected to the inverting input of operational amplifier U2 and one end of resistor R9; the other end of resistor R9 is grounded.

[0029] Specifically, it also includes a level conversion module, which is connected in series between the verification module and the bus to convert the node level into a level that the verification module can recognize.

[0030] See Figure 1In the node cluster on the bus, when internal nodes send serial data to other nodes for injection, the verification module synchronously receives the data. When the serial data is input, the control module feeds back the control signal to the verification module through the synchronous clock signal CLK. The number of bits in the verification module is composed of the number of verification units. The control module outputs different Put series signals to the verification units in the verification module along with the serial data input and when CLK is high. When the same verification unit receives the Put series signal for the first time, it dynamically constructs the fault code injected from the first node to the second node on the bus, and verifies the data fed back by the second node when it receives the Put series signal for the second time. If the verification is correct, the configuration is erased and the module waits for other nodes to reconstruct and verify again. At the same time, it also feeds back the Out series signal to the verification module. If there is an error, the verification module outputs an indication signal.

[0031] See appendix Figure 2 and attached Figure 3 The CLK of the tracking module is the synchronous clock signal, the Put series is the wake-up signal terminal of the verification unit, and Port is the pending signal; the SAN terminal of the verification module is the serial data input terminal, and the Out series is the parity bit data terminal, with additional... Figure 2Taking the 4-bit control module as an example, assume a fault injection from node A in the bus node cluster to node B, and the data bit corresponding to node B is 1010. At this time, when the CLK synchronization clock signal is high, node A sequentially inputs serial data 1010 to the verification unit and node B. Simultaneously, the multiplexed chip U1, along with the CLK signal input, sequentially changes the Put series signals to wake up the verification unit. When node A finishes inputting 4 bits of data, the multiplexed chip U1 feeds back a Port signal in anticipation, waiting for node B to receive and feed back 1010 to the verification unit. During feedback, the multiplexed chip U1, along with the CLK signal, wakes up the same verification unit for verification. If the data passes... If the signal is normal, the original serial data is erased; otherwise, a corresponding fault code is output to the verification module for indication. After erasure, the data is multiplexed to different nodes, allowing any node to input and output to other nodes. Specifically, the CLK signal is input through pin 14 of the multiplexing chip U1. Pin 3 of the multiplexing chip U1 is the reset pin or initial bit pin. When the first bit of the 4-bit serial data is input, the synchronization clock signal CLK is input as a high-level signal to the multiplexing chip U1. Pin 2 of the multiplexing chip U1 outputs the Put_1 signal, which is then input to the inverter U3 via diode D1 for inversion. The gate and source of the field-effect transistor Q2 are subjected to a negative voltage. When MOSFET Q2 is turned on, the first data from the SAN terminal is input to the subsequent circuit via MOSFET Q2. Assuming the data is 1, the high-level signal is pulled up through the source and drain of MOSFET Q2 and resistor R11, then input to the source of MOSFET Q3. MOSFET Q3 conducts with a positive voltage from the gate to the source. The power supply signal at resistor R2 is fed back to the collector of transistor Q1 through resistor R4, the source and drain of MOSFET Q3, and resistor R8, causing transistor Q1 to saturate. The original power supply from resistor R1 is fed back to the base of transistor Q4 through resistor R5, then loops through the collector and emitter of transistor Q1 to ground, causing transistor Q4 to turn off. The potentials at the terminals of resistors R2 and R4 are pulled up and input to operational amplifier U2. Operational amplifier U2 outputs a signal to Out_1. Resistors R3 and R9 set the initial static point reference voltages of transistors Q4 and Q1. The voltages should be greater than the reference voltages, or they can be configured through the power supply. Assuming the data is 0, the low-level signal is fed back to the source of field-effect transistor Q2. There is no positive voltage between the gate and the source of field-effect transistor Q3, so it is cut off. Transistors Q1 and Q4 are at their initial static operating points. At this time, the base voltages of transistors Q1 and Q4 are close and in an amplified state. The power supply signal at the terminal of resistor R2 is looped back to ground through transistor Q4. The collector of transistor Q4 and the terminal of resistor R2 are at low potentials.When the second data is input, the CLK synchronous clock signal goes high again and is input to the multiplexing chip U1. Pin 2 of the multiplexing chip U1 outputs the Put_3 signal to the second verification unit. The above operation is performed according to the data level. After all four bits of data have been input, pin 1 of the multiplexing chip U1 outputs the Port wait signal, waiting for the corresponding node to respond. When CLK goes high again, the corresponding node inputs the same serial data to the SAN terminal. Simultaneously, the re-input of CLK causes pin 5 of the multiplexing chip U1 to output the Put_2 signal, which is then input to the inverter U3 via diode D2 for inversion, and the field-effect transistor Q2 is turned on again. Assuming the first data of both the node initiating the injection and the node responding to the injection is 1, then MOSFET Q3 will turn on again. The potential at capacitor C1 will be lower than the collector potential of transistor Q1. The voltage at resistor R2 will be input to capacitor C1 through resistor R4 and MOSFET Q3. After being pulled up by capacitor C1, it will be input to the base of transistor Q4 through resistors R8 and R5, turning on transistor Q4. The power signal at resistor R2 will be pulled down through the transistor Q4 circuit, and transistors Q1 and Q4 will return to their static points, cutting off op-amp U2. If the node initiating the injection outputs 1 or 0, and the node responding to the injection outputs 0 or 1, then Out_1 will remain unchanged or, after a transition, output 1.

[0032] Appendix Figure 5 This is an 8-bit 256-1 node control module. The injection method is the same as described above, except that when pin 9 of the multiplexing chip U5 outputs, one path provides a feedback signal to pin 13 of the multiplexing chip U5 for interruption, while the other path is inverted by inverter U7 to start multiplexing chip U6. The interrupt prevents multiplexing chip U5 from resetting due to a fault when CLK inputs a signal again. Simultaneously, when CLK inputs a signal again, pin 1 of multiplexing chip U6 outputs a Port signal. After CLK inputs again, the input signals of other nodes wait for verification by the verification module. When there is a master controller, after verification, the master controller outputs a signal to pins 15 of multiplexing chips U5 and U6. The input signal is used for reset. When used independently, the 11th pin of the multiplexing chip U6 is connected in parallel with the 15th pin of the multiplexing chip U5 and the AND gate U4 for self-reset. The verification module can verify the 8-bit control module by using an 8-input AND gate (not shown in the attached figure). Resistors R6, R7, R13, R14, R15, and R16 are all pull-down resistors. They are used to pull down the signal when there is no upper-level control. The serial bus includes, but is not limited to, SPI, I2C, CAN, etc. The high and low levels can be converted to 5V and 0V by a level conversion module between the verification module and the bus (not shown in the attached figure).

[0033] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No markings in the claims should be construed as limiting the scope of the claims.

Claims

1. A multi-bus fault injection circuit, characterized in that, The system includes a tracking module, a verification module, and a validation module. The verification module comprises several verification units, which are configured to have different bit lengths. When serial data is input, the tracking module feeds back a control signal to the verification module via a synchronous clock signal. The tracking module outputs different Put series signals to the verification units in the verification module as serial data is input and when the clock signal is high. When the same verification unit receives the Put series signal for the first time, it dynamically constructs the fault code injected from the first node to the second node on the bus. When it receives the Put series signal for the second time, it verifies the data fed back by the second node and feeds back an Out signal to the validation module. If the verification is correct, the configuration is erased and the system waits for other nodes to reconstruct and verify again. If there is an error, the validation module outputs an indication signal.

2. The multi-bus fault injection circuit according to claim 1, characterized in that, The verification unit includes several resistors, several diodes, several transistors, several field-effect transistors, several inverting inputs, an operational amplifier, and capacitors. Among the transistors, transistor Q1's collector is connected to one end of resistor R1, one end of resistor R5, and one end of resistor R8; its base is connected to the drain of field-effect transistor Q3 and one end of resistor R4. Transistor Q4's collector is connected to the non-inverting input of operational amplifier U2, one end of resistor R2, and the other end of resistor R4; its base is connected to the other end of resistor R5. The output of operational amplifier U2 is connected to the Out_1 terminal. The input of inverter U3 is connected to the cathode of diode D1. The cathode of diode D2, one end of resistor R10, and the output terminal are connected to the gate of MOSFET Q2; the source of MOSFET Q2 is connected to the SAN terminal, and the drain is connected to the gate of MOSFET Q3 and one end of resistor R11; the source of MOSFET Q3 is connected to one end of capacitor C1; the other ends of resistor R1 and resistor R2 are connected to the power supply; the anode of diode D1 is connected to the Put_1 terminal; the anode of diode D2 is connected to the Put_2 terminal; the emitters of transistors Q1 and Q4, the other ends of resistor R10, resistor R11, and capacitor C1 are grounded.

3. The multi-bus fault injection circuit according to claim 1, characterized in that, The control module includes a multiplexing chip. The second, fourth, seventh, and tenth pins of the multiplexing chip U1 are connected to the Put_1, Put_3, Put_5, and Put_7 terminals, respectively. The fifth, sixth, ninth, and eleventh pins are connected to the Put_2, Put_4, Put_6, and Put_8 terminals, respectively. The first pin is connected to the Port terminal, the fourteenth pin is connected to the CLK terminal, the sixteenth pin is connected to the power supply, and the eighth pin is grounded.

4. The multi-bus fault injection circuit according to claim 1, characterized in that, The verification module includes an AND gate. The first and second pins of the first input terminal of the AND gate U4 are connected to the Out_1 and Out_2 terminals, respectively, and the fourth and fifth pins of the second input terminal are connected to the Out_3 and Out_4 terminals, respectively.

5. The multi-bus fault injection circuit according to claim 1, characterized in that, The control module includes several multiplexed chips. The second, fourth, seventh, tenth, first, fifth, and sixth pins of multiplexed chip U5 are connected to Put_1, Put_3, Put_5, Put_7, Put_9, Put_11, and Put_13 terminals, respectively. The ninth and thirteenth pins are connected to the input terminal and Put_15 terminal of inverter U7, respectively. The fourteenth pin is connected to the fourteenth pin and CLK terminal of multiplexed chip U6. Pin 13 of chip U6 is connected to the output of inverter U7. Pins 2, 4, 7, 10, 1, 5, 6, 9, and 11 are connected to Put, Put_2, Put_4, Put_6, Put_8, Put_10, Put_12, Put_14, and Put_15 respectively. Pin 16 of multiplexer chips U5 and U6 is connected to the power supply. Pin 8 of multiplexer chips U5 and U6 is grounded.

6. The multi-bus fault injection circuit according to claim 3, characterized in that, The control module also includes several resistors, one end of resistor R6 is connected to the thirteenth pin of multiplexing chip U1; one end of resistor R7 is connected to the fifteenth pin of multiplexing chip U1; and the other ends of resistor R6 and resistor R7 are grounded.

7. The multi-bus fault injection circuit according to claim 5, characterized in that, The control module also includes several resistors. One end of resistor R13 and one end of resistor R14 are connected to the thirteenth and fifteenth pins of multiplexing chip U5, respectively; one end of resistor R15 and one end of resistor R16 are connected to the thirteenth and fifteenth pins of multiplexing chip U6, respectively; and the other ends of resistors R13, R14, R15, and R16 are grounded.

8. The multi-bus fault injection circuit according to claim 2, characterized in that, The verification unit also includes several resistors. One end of resistor R13 is connected to the power supply, and the other end is connected to the inverting input of operational amplifier U2 and one end of resistor R9. The other end of resistor R9 is grounded.

9. The multi-bus fault injection circuit according to claim 1, characterized in that, It also includes a level conversion module, which is connected in series between the verification module and the bus to convert the node level to the level that the verification module can recognize.

Images