Semiconductor structure of driving chip

Abstract

The invention relates to the technical field of semiconductor chips, in particular to a semiconductor structure of a driving chip. The semiconductor structure of the driving chip comprises a substrate and at least one first-class isolation layer, the first-class isolation layer is formed on the substrate, and at least one body region is formed on the first isolation layer; semiconductor devices are respectively formed on the substrate and the body region; wherein the first type of isolation layer is configured to be in a suspended state or configured to be in a high-resistance state. According to the semiconductor structure of the driving chip, the load can be prevented from absorbing current from the chip power supply when the load is driven.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip technology, and in particular to a semiconductor structure of a driver chip. Background Art

[0002] In applications such as DC-DC power supply, relay drive, and motor drive, driver chips are often used for driving. Isolation areas are often set up to isolate different devices in the driver chip, and the isolation areas are often configured to be connected to the VDD potential or a specific bias voltage.

[0003] When the load of the driver chip contains a large inductive component, the N-type isolation of the power device inside the driver chip used to drive the load is often designed to be connected to the load output terminal together with the device drain, and the N-type isolation in other areas is designed to be connected to VDD or a specific bias voltage. However, when the driver chip output is in a high-impedance state, due to the freewheeling effect of the inductor, the current on the inductor does not immediately decay to zero, causing the load to draw current from the driver chip for a long time. This will cause the N-type isolation, P-type substrate and other N-type isolation of the power device inside the driver chip to form a parasitic NPN transistor to turn on, directly drawing current from VDD. When the current drawn from VDD exceeds its power supply capacity, it will pull VDD close to the ground voltage, affecting the chip's operating stability and even causing chip logic confusion, resulting in unpredictable results. Summary of the Invention

[0004] In order to address the deficiencies in the prior art, the present application aims to provide a semiconductor structure for a driver chip, which prevents the load from drawing current from the chip power supply when driving the load.

[0005] To achieve the above objectives, the present application provides a semiconductor structure of a driver chip, comprising: substrate, at least one first type isolation layer, wherein the first type isolation layer is formed on the substrate, and at least one body region is formed on the first isolation layer; Semiconductor devices are formed on the substrate and the body region respectively; The first type of isolation layer is configured to be in a suspended state or in a high-impedance state.

[0006] Furthermore, at least two of the first-type isolation layers are connected to each other.

[0007] Furthermore, each of the first-type isolation layers is separated by the substrate.

[0008] Furthermore, the substrate is a P-type substrate, each of the first-type isolation layers is an N-type isolation layer, and the body region is a P-type body region.

[0009] Furthermore, it also includes: a second type of isolation layer, which is formed on the substrate and is ohmically connected to the first isolation layer.

[0010] Furthermore, each of the first-type isolation layers includes any one or a combination of a buried layer, a deep well, and a well.

[0011] To achieve the above objectives, the present application also provides a driver chip that adopts the semiconductor structure of the above driver chip.

[0012] The semiconductor structure of the driver chip provided in the present application configures the first isolation layer to be in a suspended state or a high-impedance state, so that when the load draws current from the semiconductor structure of the driver chip, it does not affect the voltage of the first type of isolation layer before reaching the reverse breakdown voltage of the parasitic diode. This avoids the problem of the load drawing current from VDD due to the isolation layer being connected to VDD, which affects the operation of the semiconductor structure of the driver chip, and improves the robustness of the semiconductor structure of the driver chip.

[0013] Other features and advantages of the present application will be set forth in the following description, and in part will be apparent from the description, or may be learned by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings: Figure 1 A schematic diagram of the semiconductor structure of a conventional driver chip; Figure 2 This is a schematic structural diagram of the semiconductor structure of the driver chip according to Example 1 of the present application; Figure 3 This is a schematic structural diagram of the semiconductor structure of the driver chip according to Example 2 of the present application; Figure 4 This is a schematic structural diagram of the semiconductor structure of the driver chip according to Example 3 of the present application; Figure 5 This is a schematic structural diagram of the semiconductor structure of the driver chip according to Example 4 of the present application; Reference numerals: 100 - substrate, 101 - first type isolation layer, 1011 - first first type isolation layer, 1012 - second first type isolation layer, 102 - body region, 103 - well, 104 - semiconductor device, 105 - parasitic transistor, 106 - wire, 108 - second type isolation layer. DETAILED DESCRIPTION

[0015] The following describes embodiments of the present application in more detail with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of protection of the present application.

[0016] It should be understood that the various steps described in the method embodiments of the present application can be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present application is not limited in this respect.

[0017] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0018] It should be noted that the modifications of "one" and "plurality" mentioned in this application are illustrative rather than restrictive. Those skilled in the art will understand that unless the context clearly indicates otherwise, they should be understood as "one or more." "Plurality" should be understood as two or more.

[0019] Figure 1 This is a schematic diagram of the semiconductor structure of a conventional driver chip, see Figure 1 , which includes a substrate 100, a first first-type isolation region 1011 and a second first-type isolation region 1012, a well 103, and a semiconductor device 104. The first first-type isolation region 1011 is configured to connect to the drain of the semiconductor device formed thereon and to the inductor L1 and the load terminal, while the second first-type isolation region 1012 is configured to connect to the VDD power supply. When the output of the semiconductor structure of the driver chip is in a high-impedance state, due to the freewheeling effect of the inductor L1, the current in the inductor L1 does not immediately decay to zero, causing the load to draw current from the semiconductor structure of the driver chip for a long time. This causes the first first-type isolation region 1011, the second first-type isolation region 1012, and the substrate 100 within the semiconductor structure of the driver chip to form a parasitic transistor that turns on, directly drawing current from the VDD power supply. When the current drawn from the VDD power supply exceeds its power supply capacity, the VDD power supply is pulled close to the ground voltage, affecting the operating stability of the semiconductor structure of the driver chip and even causing chip logic confusion, resulting in unpredictable results.

[0020] To address the above problems, the present application provides a semiconductor structure of a driver chip, which can avoid the formation of parasitic transistors inside the device structure when driving inductive loads, thereby preventing the load from drawing current from the semiconductor structure power supply VDD of the driver chip.

[0021] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0022] Example 1 One embodiment of the present application provides a semiconductor structure of a driver chip. Figure 2 This is a schematic diagram of the semiconductor structure of the driver chip of Example 1 of the present application, which will be referred to below. Figure 2 The semiconductor structure of the driver chip of the present application is described in detail, including: substrate 100, In this embodiment, the substrate 100 is a P-type substrate.

[0023] A first type isolation layer 101 is formed on the substrate 100; In this embodiment, the first type isolation layer 101 is an N-type isolation layer; In this embodiment, the first type isolation layer 101 includes a buried layer and a well.

[0024] In some other embodiments, the first type isolation layer 101 may also include a combination of any N-type doping structures, for example, a combination of an N-type deep well and an N-type well.

[0025] It can be understood that a buried layer refers to a highly doped region formed on a substrate through high-energy ion implantation or diffusion, which is then covered and buried by an epitaxial layer grown on top. A well is a region of a certain depth and doping concentration formed through ion implantation, high-temperature drive-in (annealing), or diffusion. Wells of varying depths are used to meet different isolation and device fabrication requirements.

[0026] The body region 102 is a P-type body region, and two of the body regions 102 are formed on the first type isolation layer 101 .

[0027] Semiconductor devices 104 are formed on the substrate 100 and the body region 102 , respectively.

[0028] The P-type semiconductor device 104 is indirectly formed on the substrate 100 or the body region 102 through the N-type well 103 , and the N-type semiconductor is directly formed on the substrate 100 or the body region 102 .

[0029] In some other embodiments, the substrate is an N-type substrate, the first type isolation layer 101 is a P-type isolation layer, and the body region 102 is an N-type body region.

[0030] It is understandable that different body regions 102 may correspond to different operating voltage domains, and the semiconductor device 104 may be formed in the corresponding body region 102 according to the required operating voltage domain.

[0031] It is understandable that the number of body regions, the type and number of semiconductor devices, etc. can be adaptively set on the substrate 100 and the first type isolation layer 101 according to the actual circuit requirements of the driver chip.

[0032] In this embodiment, the first type isolation layer 101 is configured to be in a suspended state, where the driver chip is not directly connected to an external potential when in use.

[0033] In this embodiment, the voltage of the first type isolation layer 101 is determined by the body region with the highest potential connected to it. After the voltage of the body region decreases, the first type isolation layer 101 will maintain the previous voltage and will not form a parasitic transistor conduction until the reverse bias breakdown voltage of the parasitic diode between the first type isolation layer 101 and the body region is reached. The charge of the first type isolation layer 101 is discharged and the voltage of the first type isolation layer 101 is reduced.

[0034] Example 2 One embodiment of the present application provides a semiconductor structure of a driver chip. Figure 3 This is a schematic diagram of the semiconductor structure of the driver chip of Example 2 of the present application, which will be referred to below. Figure 3 The semiconductor structure of the driver chip of Example 2 of the present application is described in detail: The difference between Example 2 of the present application and Example 1 is that: In this embodiment, two first-type isolation layers are spaced apart on the substrate 100 , namely a first first-type isolation region 1011 and a second first-type isolation region 1012 . The first first-type isolation region 1011 and the second first-type isolation region 1012 are ohmically connected via a wire 106 .

[0035] In some other embodiments, a plurality of first-type isolation layers may be spaced apart on the substrate 100 according to the actual circuit requirements of the semiconductor structure of the driver chip, and two or more first-type isolation layers may be ohmically connected via the wire 106 .

[0036] In some other embodiments, as long as each first-type isolation layer is configured to be in a suspended state or a high-resistance state, the ohmic connection may not be achieved through the wire 106 , but may be simply isolated by the substrate 100 .

[0037] Example 3 One embodiment of the present application provides a semiconductor structure of a driver chip. Figure 4This is a schematic diagram of the semiconductor structure of the driver chip of Example 3 of the present application, which will be referred to below. Figure 4 The semiconductor structure of the driver chip of Example 3 of the present application is described in detail: The difference between Example 3 of the present application and Example 1 is that: In this embodiment, a second type isolation layer 108 is further provided on the substrate 100 . No body region or semiconductor device is formed on the second type isolation layer 108 . The second type isolation layer 108 is ohmically connected to the first type isolation layer 101 via a wire 106 .

[0038] Example 4 One embodiment of the present application provides a semiconductor structure of a driver chip. Figure 5 This is a schematic diagram of the semiconductor structure of the driver chip of Example 4 of the present application, which will be referred to below. Figure 5 The semiconductor structure of the driver chip of Example 4 of the present application is described in detail: The difference between Example 4 of the present application and Example 1 is that: In this embodiment, the first type isolation layer 101 is in a high resistance state after being connected to the bias voltage VB via the resistor Rh.

[0039] It can be understood that, since the first type isolation layer 101 is configured to be in a high resistance state, the bias voltage VB connected thereto does not need to have a driving capability.

[0040] Example 5 One embodiment of the present application provides a driver chip that adopts the semiconductor structure of the above-mentioned driver chip.

[0041] The above description is only a partial embodiment of the present application and an illustration of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in this application is not limited to the technical solutions formed by the specific combination of the above technical features, but also includes other technical solutions formed by any combination of the above technical features or their equivalents without departing from the above disclosed concepts. For example, the above features can be replaced with (but not limited to) technical features with similar functions disclosed in this application.

[0042] In addition, although adopting specific order to describe each operation, this should not be interpreted as requiring these operations to be performed in the specific order shown or in sequential order. Under certain environment, multitasking and parallel processing may be advantageous. Similarly, although comprising some specific implementation details in the above discussion, these should not be interpreted as limiting the scope of the application. Some features described in the context of separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment also can be implemented in multiple embodiments individually or in the mode of any suitable subcombination.

[0043] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A semiconductor structure of a driver chip, characterized in that: include: substrate, at least one first type isolation layer, wherein the first type isolation layer is formed on the substrate, and at least one body region is formed on the first isolation layer; Semiconductor devices are formed on the substrate and the body region respectively; The first type of isolation layer is configured to be in a suspended state or in a high-impedance state.

2. The semiconductor structure of the driver chip according to claim 1, wherein: At least two of the first-type isolation layers are connected to each other.

3. The semiconductor structure of the driver chip according to claim 1, wherein: The first-type isolation layers are separated by the substrate.

4. The semiconductor structure of the driver chip according to claim 1, wherein: The substrate is a P-type substrate, each of the first-type isolation layers is an N-type isolation layer, and the body region is a P-type body region.

5. The semiconductor structure of the driver chip according to claim 1, wherein: Also includes: A second type of isolation layer is formed on the substrate and is ohmically connected to the first isolation layer.

6. The semiconductor structure of the driver chip according to claim 1, wherein: The first type of isolation layer includes any one or a combination of a buried layer, a deep well, and a well.

7. A driver chip, characterized in that: A semiconductor structure of a driver chip according to any one of claims 1 to 6.

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