Semiconductor structure and its preparation method

Abstract

This invention provides a semiconductor structure and a method for fabricating the same. The method includes: providing a semiconductor material layer for forming at least two grooves; forming a first hard mask layer on one side of the semiconductor material layer; etching the first hard mask layer to form at least two openings, the openings defining critical dimensions of the grooves; forming an etching guide structure in the openings, the upper surface of the etching guide structure being higher than the upper surface of the first hard mask layer; forming a dielectric layer covering the first hard mask layer and the etching guide structure, the upper surface of the dielectric layer being flush with the upper surface of the etching guide structure; forming a photoresist layer on the side of the dielectric layer away from the first hard mask layer; exposing the photoresist layer to different depths at corresponding positions of the openings to form photoresist grooves of different depths; and performing a single etching operation on the etching guide structure and the semiconductor material layer based on the photoresist grooves of different depths to form grooves of different depths in the semiconductor material layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] In the semiconductor manufacturing field, it is often necessary to prepare grooves of different depths in semiconductors, and then fill the grooves with materials to further form structures of different depths, such as forming shallow trench isolation (STI) structures of different depths.

[0003] Traditional methods for fabricating dual shallow trench isolation structures of varying depths typically involve two photolithography and two etching steps. Specifically, the first and second trenches are first etched to the same depth. Then, the first trench is covered with photoresist, and the second trench is etched separately to reach a predetermined depth. During this process, the etching mask around the second trench is consumed, while the etching mask around the first trench is preserved due to the protection of the photoresist, creating a height difference in the etching masks. With further etching of the second trench, the opening at the top of the second trench expands further, becoming larger than the opening at the top of the first trench. This results in a significant deviation in the critical dimension (CD) of the dual shallow trench isolation structure, affecting the dimensional control of the active region. Furthermore, the second trench is etched twice, each etching creating a different slope for the trench sidewalls. Typically, the first etching creates a larger slope, while the second etching creates a smaller slope, leading to an undesirable morphology for the second trench.

[0004] Therefore, fabricating grooves of different depths using traditional processes will reduce both the precision and yield of semiconductor structure production. Summary of the Invention

[0005] Therefore, it is necessary to provide a method for fabricating semiconductor structures to address the problems mentioned in the background art, which can at least avoid height differences in etching masks and deviations in critical groove dimensions, thereby improving the accuracy and yield of semiconductor structure production.

[0006] To achieve the above and other related objectives, one aspect of this application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0007] A semiconductor material layer is provided, which is used to form at least two grooves;

[0008] A first hard mask layer is formed on one side of the semiconductor material layer, and the first hard mask layer is etched to form at least two openings, which are used to define the critical dimensions of the groove;

[0009] An etching guide structure is formed in the opening, and the upper surface of the etching guide structure is higher than the upper surface of the first hard mask layer;

[0010] A dielectric layer is formed covering the first hard mask layer and the etching guide structure, with the upper surface of the dielectric layer flush with the upper surface of the etching guide structure;

[0011] A photoresist layer is formed on the side of the dielectric layer away from the first hard mask layer. The photoresist layer is exposed to different depths at the corresponding positions of the opening to form photoresist grooves of different depths.

[0012] The etching guide structure and the semiconductor material layer are etched in one step using photoresist grooves of different depths to form grooves of different depths in the semiconductor material layer.

[0013] In one embodiment, the etching selectivity ratio of the etching guide structure to the first hard mask layer is greater than a preset value, so that the size of the opening in the first hard mask layer remains unchanged when the etching guide structure and the semiconductor material layer are etched in one step.

[0014] In one embodiment, the first hard mask layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride, and the etching guide structure includes at least one of organic dielectric material, spin-coated carbon material, and amorphous carbon.

[0015] In one embodiment, forming an etching guide structure in the opening includes:

[0016] A soft film layer is formed, which covers the first hard mask layer and the opening;

[0017] A second mask layer is formed on the side of the soft film layer opposite to the first hard mask layer, and the second mask layer is patterned based on the position of the opening to form a patterned second mask layer;

[0018] The soft film layer is etched based on the patterned second mask layer to form an etching guide structure, at least a portion of which is located in the opening, and the upper surface of the etching guide structure is higher than the upper surface of the first hard mask layer.

[0019] In one embodiment, exposing the photoresist layer to different depths at corresponding locations of the opening to form photoresist grooves of different depths includes:

[0020] The photoresist layer is exposed based on a halftone mask, wherein the semi-transparent and transparent portions of the halftone mask are located at corresponding positions of at least two openings, so as to form photoresist grooves of different depths in the photoresist layer.

[0021] In one embodiment, performing a single etching of the etching guide structure and the semiconductor material layer based on photoresist grooves of different depths includes:

[0022] A dry etching process is performed, using a first etching gas to etch the etch guide structure until one of the openings in the first hard mask layer exposes the top surface of the semiconductor material layer.

[0023] Continue with the dry etching process, switch to the second etching gas to etch the semiconductor material layer until the grooves of different depths in the semiconductor material layer reach the predetermined depth.

[0024] In one embodiment, the first etching gas includes oxygen, and the second etching gas includes at least one of chlorine-based gas, fluorine-based gas, and bromine-based gas.

[0025] In one embodiment, the semiconductor material layer includes a semiconductor substrate, and grooves of different depths are used to form a double shallow groove isolation structure of different depths.

[0026] In one embodiment, after forming grooves of different depths in the semiconductor material layer, the method further includes the step of removing the dielectric layer to expose the upper surface of the first hard mask layer, the upper surface of the first hard mask layer being flush.

[0027] Another aspect of the present invention protects a semiconductor structure comprising:

[0028] Grooves of different depths are formed according to any of the above semiconductor structure fabrication methods.

[0029] According to the semiconductor structure and its fabrication method provided by the present invention, before forming grooves of different depths in the semiconductor material layer, an opening for defining the critical dimensions of the groove is first formed in the hard mask layer. Then, an etching guide structure penetrating the hard mask layer and the dielectric layer is formed in the opening. A photoresist layer is formed on the etching guide structure. Photoresist grooves of different depths are formed by performing different depth exposures on the photoresist layer. Based on the photoresist grooves of different depths, the etching guide structure and the semiconductor material layer are etched to form grooves of different depths in the semiconductor material layer. This avoids deviations in the critical dimensions of the grooves and avoids height differences in the hard mask layer. The resulting groove sidewalls have uniform morphology, improving the performance of the semiconductor structure and increasing the yield of the semiconductor structure. Attached Figure Description

[0030] To better describe and illustrate embodiments and / or examples of the applications disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, or the best mode of conduct of these applications as currently understood.

[0031] Figure 1 A schematic diagram of a semiconductor structure provided in the prior art;

[0032] Figure 2This is a flowchart illustrating a method for fabricating a semiconductor structure as provided in one embodiment;

[0033] Figure 3A This is a schematic cross-sectional view of the structure obtained after forming an opening in the first mask layer in step S202 of the semiconductor structure fabrication method provided in one embodiment.

[0034] Figure 3B This is a schematic cross-sectional view of the structure obtained after forming a soft film layer and a second mask layer in step S203 of the semiconductor structure fabrication method provided in one embodiment.

[0035] Figure 3C This is a schematic cross-sectional view of the structure obtained after forming the etching guide structure in step S203 of the semiconductor structure fabrication method provided in one embodiment.

[0036] Figure 3D This is a schematic cross-sectional view of the structure obtained after forming a dielectric layer in step S204 of the semiconductor structure fabrication method provided in one embodiment.

[0037] Figure 3E This is a schematic cross-sectional view of the structure obtained after forming photoresist grooves of different depths in step S205 of the semiconductor structure fabrication method provided in one embodiment.

[0038] Figure 3F This is a schematic cross-sectional view of the structure obtained by etching the guide structure in step S206 of the semiconductor structure fabrication method provided in one embodiment.

[0039] Figure 3G This is a schematic cross-sectional view of the structure obtained by etching the semiconductor material layer in step S206 of the semiconductor structure fabrication method provided in one embodiment.

[0040] Figure 3H This is a schematic cross-sectional view of the structure obtained after removing the dielectric layer in a semiconductor structure fabrication method provided in one embodiment.

[0041] Figure 4 This is a cross-sectional schematic diagram of an etching guide structure formed when there is an overlay accuracy problem, as provided in one embodiment.

[0042] Explanation of reference numerals in the attached figures:

[0043] 100. Semiconductor material layer; 101. First groove; 102. Second groove; 103. First dielectric layer; 110. First hard mask layer; 111. First opening; 112. Second opening; 120. Soft film layer; 121. First etching guide structure; 122. Second etching guide structure; 130. Second mask layer; 140. Second dielectric layer; 150. Third hard mask layer; 160. Bottom anti-reflection layer; 170. Photoresist layer; 171. First photoresist groove; 172. Second photoresist groove; 180. Halftone mask; 181. Semi-transparent portion; 182. Transparent portion. Detailed Implementation

[0044] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures). Thus, variations from the illustrated shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of the application.

[0050] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation, the form, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0051] Reference Figure 1As shown, two grooves of different depths were prepared using traditional methods. The etching masks of the two grooves have a height difference. The opening size at the top of the deep groove is larger than that at the top of the shallow groove. The critical dimension (CD) of the two grooves has a large deviation, and the slope of the sidewalls of the deep groove is different.

[0052] To address the above problems, this invention provides a method for fabricating a semiconductor structure, such as... Figure 2 As shown, it includes the following steps:

[0053] Step S201: Provide a semiconductor material layer for forming at least two grooves;

[0054] Step S202: Form a first hard mask layer on one side of the semiconductor material layer, and etch the first hard mask layer to form at least two openings, which are used to define the critical dimensions of the groove;

[0055] Step S203: Form an etching guide structure in the opening, wherein the upper surface of the etching guide structure is higher than the upper surface of the first hard mask layer;

[0056] Step S204: Form a dielectric layer covering the first hard mask layer and the etching guide structure, wherein the upper surface of the dielectric layer is flush with the upper surface of the etching guide structure;

[0057] Step S205: A photoresist layer is formed on the side of the dielectric layer away from the first hard mask layer. The photoresist layer is exposed to different depths at the corresponding positions of the opening to form photoresist grooves of different depths.

[0058] Step S206: Perform a one-time etching of the etching guide structure and the semiconductor material layer based on photoresist grooves of different depths to form grooves of different depths in the semiconductor material layer.

[0059] First, execute step S201, referring to... Figure 3A A semiconductor material layer 100 is provided, which is used to form at least two grooves.

[0060] In one embodiment, the semiconductor material layer 100 includes, but is not limited to, at least one of a substrate and an interlayer dielectric layer. The grooves formed in the substrate can be used to further form shallow trench isolation structures, field oxide structures, etc., and the grooves formed in the interlayer dielectric layer can be used to further form interconnect structures, bonding structures, etc. Specifically, the substrate can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc.

[0061] Next, proceed to step S202, referring to... Figure 3A As shown, a first hard mask layer 110 is formed on one side of the semiconductor material layer 100, and the first hard mask layer 110 is etched to form at least two openings, which are used to define the critical dimensions of the groove.

[0062] In one embodiment, before forming the first hard mask layer 110, a step of forming a first dielectric layer 103 is included. Optionally, the material of the first dielectric layer includes, but is not limited to, silicon oxide (SiO2), and the first dielectric layer 103 can be formed using processes familiar to those skilled in the art, such as thermal oxidation. Next, a first hard mask layer 110 is formed on the first dielectric layer 103. The material of the first hard mask layer 110 includes, but is not limited to, at least one of silicon nitride (SiN), silicon oxide (SiO2), and silicon oxynitride (SiON). Optionally, the first hard mask layer 110 is selected from silicon nitride (SiN), and the first hard mask layer 110 can be formed using processes familiar to those skilled in the art, such as chemical vapor deposition (CVD). Next, a patterned photoresist layer (not shown) is formed on the first hard mask layer 110. The first hard mask layer 110 is etched using the patterned photoresist layer as a mask until the surface of the semiconductor material layer 100 is exposed, so as to form at least two openings in the first hard mask layer 110. Specifically, refer to... Figure 3A As shown, a first opening 111 and a second opening 112 are formed in the first hard mask layer 110. The first opening 111 defines the critical dimension (CD) of the first recess, and the second opening 112 defines the critical dimension of the second recess. Optionally, the critical dimensions of the first and second recesses are the same, therefore the widths of the first opening 111 and the second opening 112 are the same. Furthermore, the thickness of the first hard mask layer 110 is less than the width of the openings. By making the thickness of the first hard mask layer 110 less than the width of the openings, the width of the openings formed in the first hard mask layer 110 is made uniform, and the cross-section of the openings is rectangular, avoiding a situation where the width of the upper part of the opening is greater than the width of the lower part, resulting in an inverted trapezoidal shape.

[0063] Next, proceed to step S203, referring to... Figures 3B to 3C As shown, an etching guide structure is formed in the opening, with the upper surface of the etching guide structure being higher than the upper surface of the first hard mask layer. Exemplarily, forming the etching guide structure in the opening includes: forming a soft film layer covering the first hard mask layer and the opening; forming a second mask layer on the side of the soft film layer opposite to the first hard mask layer; patterning the second mask layer based on the location of the opening to form a patterned second mask layer; and etching the soft film layer based on the patterned second mask layer to form the etching guide structure, at least a portion of which is located in the opening, with the upper surface of the etching guide structure being higher than the upper surface of the first hard mask layer.

[0064] In one embodiment, first refer to Figure 3B As shown, a soft film layer 120 is formed, which covers the first hard mask layer 110 and fills the first opening 111 and the second opening 112. The material of the soft film layer 120 includes, but is not limited to, at least one of organic dielectric layer (ODL), spin-on carbon (SOC), and amorphous carbon. The soft film layer 120 can be formed using coating, spin coating, or other processes familiar to those skilled in the art. Next, a photoresist layer is formed on the soft film layer 120 as a second mask layer 130. Then, the second mask layer 130 is patterned according to the positions of the openings in the first hard mask layer 110. Specifically, the photoresist at the positions corresponding to the openings is retained, while the photoresist at other positions is removed to form a patterned second mask layer 130, as shown below. Figure 3B As shown. Next, the soft film layer 120 is etched using the patterned second mask layer 130 as a mask to form etching guide structures in and above the openings. Specifically, a first etching guide structure 121 is formed in and above the first opening 111, and a second etching guide structure 122 is formed in and above the second opening 112, as shown. Figure 3C As shown.

[0065] In one embodiment, Figure 3C The desired morphology of the etch-guided structure formed according to the above steps is shown. However, in actual processes, there is an overlay (OVL) accuracy issue, resulting in a different morphology of the etch-guided structure. Figure 4 As shown, the top and bottom widths of the etching guide structure are not uniform, with the bottom width being greater than the top width. This results in an angle α between the sidewall of the etching guide structure and the surface of the first mask layer, where Tan(α) = x / y, where x represents the thickness of the soft film layer and y represents the overlap width between the etching guide structure and the first hard mask. Taking a 40nm process as an example, if the overlay clearance (OVL) is 5nm (i.e., y = 5nm), the linewidth dimension (ADI) after the lithography process is 62nm, and the angle α is approximately 87°, yielding x = 954Å. Therefore, controlling the thickness of the soft film layer 120 to above 954Å solves the 5nm OVL problem. Furthermore, setting the thickness of the soft film layer 120 to 2000Å solves OVL problems above 10nm.

[0066] In one embodiment, taking the thickness of the first hard mask layer 110 as 50nm~60nm and the width of the opening formed in the first hard mask as 62nm, the linewidth dimension (ADI) of the etching guide structure after photolithography is 62nm. Optionally, the thickness of the soft film layer 120 is set to 100nm~150nm, and the ratio of the thickness of the soft film layer to the thickness of the first hard mask layer is in the range of 2:1~3:1. Further, the height of the formed etching guide structure is in the range of 150nm~200nm, and the ratio of the height of the etching guide structure to the thickness of the first hard mask layer is in the range of 3:1~4:1.

[0067] Next, proceed to step S204, referring to... Figure 3D As shown, a second dielectric layer 140 is formed covering the first hard mask layer 110 and the etching guide structure, with the upper surface of the second dielectric layer 140 being flush with the upper surface of the etching guide structure.

[0068] In one embodiment, the material of the second dielectric layer 140 includes, but is not limited to, at least one of silicon oxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiON). Optionally, the second dielectric layer 140 is selected as silicon oxide (SiO2), and can be formed using processes familiar to those skilled in the art, such as chemical vapor deposition (CVD). After forming the second dielectric layer 140, chemical mechanical polishing (CMP) is further performed to make the upper surface of the second dielectric layer 140 flush with the upper surface of the etching guide structure, such as... Figure 3D As shown.

[0069] Next, proceed to step S205, referring to... Figure 3E As shown, a photoresist layer 170 is formed on the side of the second dielectric layer 140 away from the first hard mask layer 110. The photoresist layer 170 is exposed to different depths at the corresponding positions of the opening to form photoresist grooves of different depths.

[0070] In one embodiment, before forming a photoresist layer on the second dielectric layer 140, the method further includes the step of sequentially forming a third hard mask layer 150 and a bottom anti-reflection layer 160 on the second dielectric layer 140. The material of the third hard mask layer 150 includes, but is not limited to, at least one of silicon oxynitride (SiON), silicon nitride (SiN), and silicon oxide (SiO2). Optionally, the third hard mask layer 150 is selected as silicon oxynitride (SiON), and can be formed using processes familiar to those skilled in the art, such as chemical vapor deposition (CVD). The material of the bottom anti-reflection layer 160 includes, but is not limited to, amorphous carbon or other organic anti-reflection materials, and can be formed using processes familiar to those skilled in the art, such as coating or spin coating. The photoresist layer 170 includes positive or negative photoresist. Optionally, the photoresist layer 170 uses positive photoresist, and can be formed using processes familiar to those skilled in the art, such as coating or spin coating.

[0071] For example, exposing the photoresist layer to different depths at corresponding positions of the openings to form photoresist grooves of different depths includes: exposing the photoresist layer 170 based on a halftone mask 180, wherein the semi-transparent portion 181 and the transparent portion 182 of the halftone mask 180 are respectively located at corresponding positions of at least two openings, so as to form photoresist grooves of different depths in the photoresist layer 170.

[0072] In one embodiment, refer to Figure 3E As shown, a halftone mask 180 is used as the photomask for the photoresist layer 170. The halftone mask 180 includes at least a semi-transparent portion 181 and a transparent portion 182, which are correspondingly disposed with respect to the openings in the first hard mask layer 110. Next, the halftone mask 180 is used as the photomask for the photoresist layer 170 for exposure at different depths. The photoresist at the semi-transparent portion 181 forms a first photoresist groove 171, the width of which is equal to the width of the first opening 111 and the width of the first etching guide structure 121. The photoresist at the transparent portion 182 forms a second photoresist groove 172, the width of which is equal to the width of the second opening 112 and the width of the second etching guide structure 122. Since the photoresist layer 170 uses a positive photoresist, the depth of the first photoresist groove 171 is less than the depth of the second photoresist groove 172. Figure 3E As shown.

[0073] exist Figure 4In the example shown, when an overlay (OVL) issue causes the bottom width of the etching guide structure to be greater than the top width, the widths of the semi-transparent portion 181 and the transparent portion 182 must be the same as the width of the widest part of the etching guide structure, for example, 72nm.

[0074] Next, proceed to step S206, referring to... Figures 3F to 3H As shown, a single etching process is performed on the etching guide structure and the semiconductor material layer 100 based on photoresist grooves of different depths to form grooves of different depths in the semiconductor material layer 100. Exemplarily, performing a single etching process on the etching guide structure and the semiconductor material layer based on photoresist grooves of different depths includes: performing a dry etching process, using a first etching gas to etch the guiding structure until one of the openings in the first hard mask layer exposes the top surface of the semiconductor material layer; continuing the dry etching process, switching to a second etching gas to etch the semiconductor material layer until the grooves of different depths in the semiconductor material layer reach a predetermined depth.

[0075] In one embodiment, a one-step dry etching process is performed, firstly etching the photoresist layer 170 until the first photoresist recess 171 or the second photoresist recess 172 exposes the top surface of the bottom anti-reflective layer 160. Figure 3E As shown, when the top surface of the bottom anti-reflective layer 160 is exposed in the second photoresist groove 172 without etching, the photoresist layer does not need to be etched. Next, the bottom anti-reflective layer 160 and the third hard mask layer 150 exposed by the second photoresist groove 172 are etched away until the second etching guide structure 122 is exposed.

[0076] Next, oxygen (O2) can be used as the first etching gas to etch the etching guide structure. When a portion of the second etching guide structure 122 is etched away, the top surface of the bottom anti-reflection layer 160 is exposed in the first photoresist groove 171. The etching gas is switched to etch away the bottom anti-reflection layer 160 and the third hard mask layer 150 exposed in the first photoresist groove 171. Then, the first etching gas is switched back to simultaneously etch the first etching guide structure 121 and the second etching guide structure 122 until the second etching guide structure 122 is completely etched, and the second opening 112 exposes the surface of the first dielectric layer 103. (Refer to...) Figure 3F As shown. Then the etching gas is switched to etch away the first dielectric layer 103 exposed by the second opening 112 until the top surface of the semiconductor material layer 100 is exposed. While etching the first etching guide structure 121 and the second etching guide structure 122, the photoresist layer 170, the bottom anti-reflection layer 160 and the third hard mask layer 150 are removed.

[0077] Next, at least one of chlorine-based gas, fluorine-based gas, and bromine-based gas can be used as the second etching gas to etch the semiconductor material layer 100. The chlorine-based gas includes chlorine or carbon tetrachloride, or a combination thereof. The fluorine-based gas includes CF4, CHF3, NF3, SF6, and other commonly used fluorine-containing gases, or a combination thereof. The bromine-based gas is bromine or hydrogen bromide, or a combination thereof. When a portion of the semiconductor material layer 100 is removed, the first etching guide structure 121 is completely removed, exposing the top surface of the first dielectric layer 103. Then, the etching gas is switched to etch and remove the first dielectric layer 103 exposed by the first opening 111. Then, the second etching gas is switched back to simultaneously etch the semiconductor material layer 100 until the grooves in the semiconductor material layer 100 reach a predetermined depth, forming the first groove 101 and the second groove 102. (Refer to...) Figure 3G As shown. The depth of the first groove 101 is less than the depth of the second groove 102. The first groove 101 is a shallow groove, and the second groove 102 is a deep groove.

[0078] In one embodiment, after forming grooves of different depths in the semiconductor material layer 100, the method further includes removing the second dielectric layer 140 to expose the upper surface of the first hard mask layer 110, in order to form Figure 3H The structure shown. The upper surface of the first hard mask layer 110 formed according to this embodiment is flush and the overall thickness is uniform, without any "steps" caused by height differences.

[0079] In one embodiment, it should be noted that the first etching gas has a high etching selectivity for the etching guide structure and the first etching mask layer, which is greater than a preset value. Therefore, when the first etching gas etches the etching guide structure, the size of the opening in the first hard mask layer 110 remains unchanged, that is, the widths of the first opening 111 and the second opening 112 remain unchanged. Thus, the key dimensions for forming the first groove 101 and the second groove 102 in the semiconductor material layer 100 remain unchanged, that is, the top widths of the formed first groove 101 and the second groove 102 are equal. After the etching guide structure is removed by etching, etching guide channels are formed in the second dielectric layer 140 and the first hard mask layer 110. Due to the presence of the etching guide channels, the top width of the groove formed in the semiconductor material layer 100 is the same as or close to the bottom width. Therefore, the slope of the sidewall of the groove formed in the semiconductor material layer 100 is 90° or close to 90°, and the sidewall of the groove is basically perpendicular to the bottom surface, avoiding the sidewall of the groove formed in the semiconductor material layer 100 being tilted or even having different slopes.

[0080] This concludes the introduction of the relevant steps in the semiconductor structure fabrication method according to this embodiment of the invention. It is understood that the semiconductor structure fabrication method of this embodiment includes not only the steps described above, but may also include other necessary steps before, during, or after the above steps, all of which are included within the scope of this manufacturing method.

[0081] The present invention also provides a semiconductor structure, with reference to Figure 3H As shown, it includes:

[0082] Grooves of different depths are formed according to the semiconductor structure fabrication method described above.

[0083] In one embodiment, the semiconductor material layer 100 includes, but is not limited to, at least one of a substrate and an interlayer dielectric layer. The grooves formed in the substrate can be used to further form shallow trench isolation structures, field oxide structures, etc., and the grooves formed in the interlayer dielectric layer can be used to further form interconnect structures, bonding structures, etc. Specifically, the substrate can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc.

[0084] In one embodiment, a first groove 101 and a second groove 102 of different depths are formed in the semiconductor material layer 100, wherein the depth of the first groove 101 is less than the depth of the second groove 102, the first groove 101 is a shallow groove, and the second groove 102 is a deep groove. Furthermore, the critical dimensions of the first groove 101 and the second groove 102 are equal, that is, the top widths of the first groove 101 and the second groove 102 are equal, avoiding critical dimension deviations between the first groove 101 and the second groove 102. The slope of the sidewalls of the first groove 101 and the second groove 102 is 90° or close to 90°, and the sidewalls of the grooves are substantially perpendicular to the bottom surface, avoiding tilting of the groove sidewalls or even different slopes of the sidewalls.

[0085] In one embodiment, a first hard mask layer 110 is formed on one side of the semiconductor material layer 100. The upper surface of the first hard mask layer 110 is flush and the overall thickness is uniform, without any "steps" caused by height differences.

[0086] The specific structure of the semiconductor structure can be referred to in the corresponding section above, and will not be repeated here for the sake of brevity.

[0087] According to the semiconductor structure and its fabrication method provided by the present invention, before forming grooves of different depths in the semiconductor material layer, an opening for defining the critical dimensions of the groove is first formed in the hard mask layer. Then, an etching guide structure penetrating the hard mask layer and the dielectric layer is formed in the opening. A photoresist layer is formed on the etching guide structure. Photoresist grooves of different depths are formed by performing different depth exposures on the photoresist layer. Based on the photoresist grooves of different depths, the etching guide structure and the semiconductor material layer are etched to form grooves of different depths in the semiconductor material layer. This avoids deviations in the critical dimensions of the grooves and avoids height differences in the hard mask layer. The resulting groove sidewalls have uniform morphology, improving the performance of the semiconductor structure and increasing the yield of the semiconductor structure.

[0088] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0089] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A semiconductor material layer is provided, the semiconductor material layer being used to form at least two grooves; A first hard mask layer is formed on one side of the semiconductor material layer, and the first hard mask layer is etched to form at least two openings, the openings being used to define the critical dimensions of the groove; An etching guide structure is formed in the opening, and the upper surface of the etching guide structure is higher than the upper surface of the first hard mask layer; A dielectric layer is formed covering the first hard mask layer and the etching guide structure, wherein the upper surface of the dielectric layer is flush with the upper surface of the etching guide structure; A photoresist layer is formed on the side of the dielectric layer opposite to the first hard mask layer, and the photoresist layer is exposed to different depths at the corresponding positions of the opening to form photoresist grooves of different depths. Based on the photoresist grooves of different depths, the etching guide structure and the semiconductor material layer are etched in one step to form grooves of different depths in the semiconductor material layer; Forming an etching guide structure in the opening includes: A soft film layer is formed, which covers the first hard mask layer and the at least two openings; A second mask layer is formed on the side of the soft film layer opposite to the first hard mask layer, and the second mask layer is patterned based on the position of the opening in the first hard mask layer to form a patterned second mask layer; The soft film layer is etched based on the patterned second mask layer to form the etching guide structure, at least a portion of which is located in the opening, and the upper surface of the etching guide structure is higher than the upper surface of the first hard mask layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching selectivity ratio between the etching guide structure and the first hard mask layer is greater than a preset value, so that the size of the opening in the first hard mask layer remains unchanged when the etching guide structure and the semiconductor material layer are etched in one go.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The first hard mask layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride, and the etching guide structure includes at least one of organic dielectric material, spin-coated carbon material, and amorphous carbon.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the first hard mask layer is less than the width of the opening.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, Exposing the photoresist layer to different depths at corresponding positions of the opening to form photoresist grooves of different depths includes: The photoresist layer is exposed based on a halftone mask, wherein the semi-transparent portion and the transparent portion of the halftone mask are respectively located at corresponding positions of the at least two openings, so as to form photoresist grooves of different depths in the photoresist layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, Performing a single etching operation on the etching guide structure and the semiconductor material layer based on the photoresist grooves of different depths includes: A dry etching process is performed, using a first etching gas to etch the etching guide structure until one of the openings in the first hard mask layer exposes the top surface of the semiconductor material layer; Continue executing the dry etching process, switch to the second etching gas to etch the semiconductor material layer until the grooves of different depths in the semiconductor material layer reach the predetermined depth.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The first etching gas includes oxygen, and the second etching gas includes at least one of chlorine-based gas, fluorine-based gas, and bromine-based gas.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The semiconductor material layer includes a semiconductor substrate, and the grooves of different depths are used to form a double shallow groove isolation structure of different depths.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming grooves of different depths in the semiconductor material layer, the method further includes removing the dielectric layer to expose the upper surface of the first hard mask layer, wherein the upper surface of the first hard mask layer is flush.

10. A semiconductor structure, characterized in that, include: Grooves of different depths are formed by the semiconductor structure fabrication method according to any one of claims 1 to 9.

Images