Novel HBPOP packaging structure and manufacturing method thereof

Abstract

The invention discloses a novel HBPOP packaging structure and a manufacturing method, and relates to the technical field of chip packaging, the novel HBPOP packaging structure is used for packaging a chip, the novel HBPOP packaging structure comprises an upper packaging substrate, the upper packaging substrate is used for mounting the chip, and the upper packaging substrate and the chip form a plastic packaging structure; and the redistribution layer is formed on the plastic package structure and is close to the plastic package layer of the chip. A lower packaging substrate in an original HBPOP packaging structure is replaced by the redistribution layer, the plastic packaging layer of the plastic packaging chip is packaged again, the packaging process of the HBPOP packaging structure can be simplified, the preparation process of the redistribution layer is simple compared with the manufacturing process of the lower packaging substrate, therefore, the preparation of the lower packaging substrate is not needed, and the cost is reduced. The preparation cost of the lower packaging substrate during packaging can be reduced, the manufacturing time consumption of the HBPOP packaging structure can be greatly reduced, the lower packaging substrate is replaced by the redistribution layer, the overall thickness of the HBPOP packaging structure can be reduced, and the thermal warping condition can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a novel HBPOP packaging structure and a manufacturing method. Background Art

[0002] High-Bandwidth Package-on-Package (HBPOP) is a three-dimensional packaging technology widely used in mobile devices, high-performance computing, and artificial intelligence. HBPOP achieves high bandwidth and high-performance computing capabilities by vertically stacking multiple package structures.

[0003] In the prior art, the HBPOP packaging structure is usually produced by independently producing the upper and lower packaging structures, and then packaging the upper plate, lower plate and chip together. For example, the Chinese patent with the announcement number "CN116705727A" discloses a high-bandwidth stacked packaging HBPoP structure, which includes a first packaging substrate formed of silicon and / or ceramic materials and a second packaging structure arranged above the first packaging structure.

[0004] However, in the packaging structure in the prior art, both the upper plate and the lower plate need to be produced independently, resulting in a relatively time-consuming manufacturing process.

[0005] Therefore, how to reduce the manufacturing time of the HBPOP packaging structure has become a technical problem that needs to be solved urgently. Summary of the Invention

[0006] The technical problem solved by the present invention is that the production of the HBPOP packaging structure in the prior art takes a long time.

[0007] To solve the above technical problems, the present invention provides the following technical solutions: a new HBPOP packaging structure for packaging chips, comprising: an upper packaging substrate, the upper packaging substrate being used to mount the chip, the upper packaging substrate and the chip forming a plastic packaging structure; a redistribution layer, a plastic packaging layer formed on the plastic packaging structure close to the chip.

[0008] As a preferred solution of the novel HBPOP packaging structure described in the present invention, deep blind holes are formed on the surface of the plastic package structure close to the chip, copper is electroplated in the deep blind holes, and the electroplated copper forms a fan-out structure relative to the chip.

[0009] As a preferred solution of the novel HBPOP packaging structure described in the present invention, the thickness of the upper packaging substrate is greater than 0.04 mm.

[0010] As a preferred solution of the novel HBPOP packaging structure described in the present invention, the novel HBPOP packaging structure has two redistribution layers stacked one above the other.

[0011] As a preferred solution of the novel HBPOP packaging structure described in the present invention, the line width and spacing of the redistribution layer are both between 1 μm and 10 μm.

[0012] The present invention also provides the following technical solution: a method for preparing a novel HBPOP packaging structure, used to prepare the novel HBPOP packaging structure as described in any of the above embodiments, the preparation method comprising: preparing an upper packaging substrate; mounting a chip on the upper packaging substrate; filling the upper packaging substrate with bottom filling glue; plastic-sealing the upper packaging substrate with the chip mounted thereon to obtain a plastic-sealed structure; fabricating interconnection circuits on the surface of the plastic-sealed layer close to the chip on the plastic-sealed structure to form a redistribution layer; and cutting the plastic-sealed structure with the redistribution layer formed thereon to obtain the novel HBPOP packaging structure.

[0013] As a preferred embodiment of the preparation method of the present invention, before interconnection circuits are fabricated on the surface of the plastic encapsulation layer of the plastic encapsulation structure close to the chip to form a redistribution layer, the preparation method further comprises: forming deep blind holes on the surface of the plastic encapsulation layer of the plastic encapsulation structure close to the chip by laser lithography; and electroplating copper in the deep blind holes, wherein the electroplated copper forms a fan-out structure relative to the chip.

[0014] As a preferred embodiment of the preparation method described in the present invention, the production of the upper packaging substrate includes: laser drilling on the core layer of the substrate; coating dry film photoresist on the core layer of the substrate after laser drilling, and forming a circuit pattern through exposure and development; electroplating copper in the exposed area subjected to exposure and development to form a conductive circuit and fill the hole; coating the core layer of the substrate after electroplating with solder mask ink to cover the non-soldering area; gold plating the pads and contact points of the circuit pattern, and coating the non-soldering pads and non-contact point areas in the core layer of the substrate with an organic solder mask.

[0015] As a preferred embodiment of the preparation method of the present invention, before cutting the plastic package structure with the redistribution layer to obtain the novel HBPOP packaging structure, the preparation method further comprises: making interconnection lines on the surface of the redistribution layer to form the redistribution layer again.

[0016] As a preferred solution of the preparation method of the present invention, the line width and spacing of the redistribution layer are both between 1 μm and 10 μm.

[0017] The beneficial effect of the present invention is that the plastic packaging layer of the plastic-sealed chip is re-packaged by replacing the lower packaging substrate with a redistribution layer, which can simplify the packaging process and thus reduce the time consumption for manufacturing the HBPOP packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference symbols are used throughout the drawings to represent the same components. In the drawings: Figure 1 A schematic diagram of the basic structure of a novel HBPOP packaging structure provided by one embodiment of the present invention; Figure 2 A schematic diagram of the basic structure of a HBPOP packaging structure in the prior art provided by one embodiment of the present invention; Figure 3 A schematic diagram of the basic process of a method for preparing a novel HBPOP packaging structure provided by one embodiment of the present invention.

[0019] The reference numerals are as follows: 1. New HBPOP packaging structure; 11. Upper package substrate; 12. Redistribution layer; 13. Chip; 14. Deep blind via; 15. Electroplated copper; 2. Original HBPOP packaging structure; 21. Upper package substrate; 22. Lower package substrate; 23. Chip; 24. Solder ball. DETAILED DESCRIPTION

[0020] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0021] Example 1, with reference to Figure 1 , which is an embodiment of the present invention, provides a new HBPOP packaging structure 1 for packaging a chip 13, including: an upper packaging substrate 11, the upper packaging substrate 11 is used to mount the chip 13, and the upper packaging substrate 11 and the chip 13 form a plastic packaging structure; a redistribution layer 12, a plastic packaging layer formed on the plastic packaging structure near the chip 13.

[0022] Among them, the production process of the upper packaging substrate 11 in the new HBPOP packaging structure 1 and the original HBPOP packaging structure 2 is consistent. Since the thicker lower packaging substrate 22 is replaced by the redistribution layer 12 in the new HBPOP packaging structure 1, the thickness of the upper packaging substrate 11 in the new HBPOP packaging structure 1 can be thicker than the thickness of the upper packaging substrate 21 in the original HBPOP packaging structure 2. For example, the substrate thickness of the upper packaging substrate 21 in the original HBPOP packaging structure 2 is 0.04 mm, and the thickness of the entire upper packaging substrate 21 after packaging can reach 0.1 mm. The substrate thickness of the upper packaging substrate 11 in the new HBPOP packaging structure 1 can be 0.06 mm, and the thickness of the entire upper packaging substrate 11 after packaging can reach 0.12 mm.

[0023] Chip 13 is an IC chip (Integrated Circuit Chip). An IC chip is an integrated circuit formed by placing a large number of microelectronic components (transistors, resistors, capacitors, etc.) on a plastic substrate to form a chip. IC chips include wafer chips and packaged chips. The corresponding IC chip production line consists of two parts: a wafer production line and a packaging production line.

[0024] The Redistribution Layer (RDL) is a technology used to optimize signal routing and increase contact density, and is widely used in semiconductor packaging and integrated circuit design. It deposits metal layers and corresponding dielectric layers on the chip surface to form metal conductors and redesigns I / O ports to new, more spacious areas, creating a surface array layout.

[0025] The preparation method of the novel HBPOP packaging structure 1 is as follows: Figure 3 As shown, it includes: S110, making an upper packaging substrate 11; S120, mounting a chip 13 on the upper packaging substrate 11; S130, filling the upper packaging substrate 11 with bottom filling glue; S140, plastic-sealing the upper packaging substrate 11 with the chip 13 mounted thereon to obtain a plastic-sealed structure; S150, making interconnection lines on the surface of the plastic-sealed layer close to the chip 13 on the plastic-sealed structure to form a redistribution layer 12; S160, cutting the plastic-sealed structure with the redistribution layer 12 to obtain a new HBPOP packaging structure 1.

[0026] Among them, when manufacturing the upper package substrate 11, S110 usually includes material sending, laser drilling, image transfer + electroplating, solder mask and surface treatment processes in sequence.

[0027] Among them, the specific process of material distribution is to prepare the core layer of the substrate. The core layer of the substrate is usually a thin plate clad with copper on both sides, which serves as a carrier for subsequent processes. Specifically, the substrate material with material model HL832NS can be used as the core layer of the substrate. Among them, HL832NS is a high-performance organic substrate material, such as the ABF (Ajinomoto Build-up Film) substrate of Japan Ajinomoto Co., Ltd., which has a low dielectric constant (Dk≈3.3) and low dissipation factor (Df≈0.002), and is suitable for high-frequency and high-speed signal transmission.

[0028] The typical aperture of laser drilling is 20μm, and the whole board is processed without segmentation. Specifically, UV laser or CO2 laser can be used to drill microholes on the substrate, such as blind holes and through holes, for interlayer interconnection. Preferably, the hole wall roughness during laser drilling can be set to less than 1μm to ensure the quality of subsequent electroplating. The alignment accuracy of laser drilling is within ±5μm to ensure the conduction reliability during multi-layer stacking.

[0029] Image transfer + electroplating: RD-3025 dry film photoresist is coated on the core layer of the substrate. A circuit pattern is formed through exposure and development. The circuit pattern includes lines and pads. During photolithography, the lithography accuracy must be below 5μm to support fine lines. Copper is then electroplated in the exposed area with a thickness of 15μm to form conductive lines and fill the holes. The 15μm copper thickness can provide low resistance (R≈0.1Ω / cm²), which is suitable for high current applications. The large-size substrate can be divided into four small panels to improve process efficiency. For example, a large-size 600mm×600mm substrate can be divided into four small panels of 300mm×300mm. The four-split design can reduce material waste and lower costs.

[0030] For solder mask, PSR-800_AUS_SR1 solder mask ink (green or black) can be applied to cover the non-soldering area. The thickness of the solder mask ink is controlled at 12.5μm±2μm. The solder mask ink is evenly applied to ensure the accuracy of the solder window, protect the circuit and insulate it, improve chemical corrosion resistance and mechanical strength, and prevent solder overflow from causing short circuits. The core layer of the substrate can be cut into strips, such as 300mm×50mm, to facilitate subsequent ball planting and placement.

[0031] Surface treatments include gold plating and OSP (Organic Solderability Preservative). The gold plating process involves electroless nickel (Ni) and immersion gold (Au). The thickness of electroless nickel is 3–5μm, and the thickness of immersion gold is 0.05–0.1μm. These processes are used to plate pads and contacts with gold, providing oxidation resistance and high reliability, making the gold-plated layer suitable for high-frequency signals with low resistance and low insertion loss. OSP, or organic solderability preservative (OSP), is applied to non-gold-plated areas to prevent copper oxidation and maintain solderability. The coating thickness of OSP is typically 0.2–0.5μm. OSP is low-cost, environmentally friendly, and compatible with lead-free soldering processes.

[0032] The novel HBPOP packaging structure 1 has fewer steps and simpler processes during preparation, and the manufacturing process of the redistribution layer 12 is very simple.

[0033] However, for Figure 2 The manufacturing method of the HBPOP package structure 2 in the prior art includes: S201, manufacturing the bottom substrate (such as an organic substrate or a ceramic substrate), that is, Figure 2 The lower package substrate 22 shown in the figure is formed into a circuit by etching or printing process; S202, the chip 23 is mounted on the lower package substrate 22 by adhesive or solder; S203, the bottom filling glue (such as epoxy resin) is filled to protect the solder joints and enhance the mechanical strength; S204, the top substrate, that is, Figure 2 The upper package substrate 21 in the circuit is also formed with circuits. S205: Solder balls (such as solder balls 24) are implanted on the surface of the upper substrate for subsequent electrical connection during stacking. S206: The large upper substrate is cut into individual smaller substrate units. S207: The upper substrate is stacked onto the lower substrate and aligned and secured using solder balls. S208: Heating is performed to melt the solder balls, achieving electrical connection between the upper and lower substrates. S209: The entire structure is encapsulated with epoxy molding compound to protect the chip 23 and circuitry. S210: The encapsulated substrate is cut into individual packages. The production of the original HBPOP package structure 2 not only involves many additional steps, but also requires a more complex lower substrate fabrication process than the redistribution layer 12. Specifically, the lower substrate fabrication process includes material preparation, image transfer and electroplating, lamination, laser drilling, board removal, etching, solder masking, surface treatment, and ball implantation.

[0034] When the original HBPOP package structure 2 is manufactured, the upper package substrate 21 and the lower package substrate 22 are usually manufactured separately, and then the upper package substrate 21, the lower package substrate 22 and the chip 23 are packaged. The steps of manufacturing the upper package substrate 11 include S111-S115. Specifically, S111, laser drilling is performed on the substrate core layer; S112, dry film photoresist is applied to the laser-drilled substrate core layer, and a circuit pattern is formed through exposure and development; S113, copper 15 is electroplated in the exposed area after exposure and development to form a conductive circuit and fill the hole; S114, solder mask ink is applied to the substrate core layer after electroplating to cover the non-soldering area; S115, gold is plated on the pads and contact points of the circuit pattern, and organic solder mask is applied to the non-pad and non-contact point areas in the substrate core layer.

[0035] It can be seen from this that the production process of the lower substrate is the most tedious step in the production process of the original HBPOP packaging structure 2. The present application uses the redistribution layer 12 to replace the lower packaging substrate 22 to re-encapsulate the plastic layer of the plastic-encapsulated chip, which can simplify the S201-S210 to the S110-S160 packaging process, and the preparation process of the redistribution layer 12 is simpler than the preparation process of the lower packaging substrate 22. Therefore, the present application does not need to prepare the lower packaging substrate 22, which can greatly reduce the production time of the HBPOP packaging structure.

[0036] The present application simplifies the manufacturing process of the HBPOP packaging structure and, by replacing the lower packaging substrate 22 with the redistribution layer 12 , can reduce the overall thickness of the HBPOP packaging structure, reduce thermal warpage, and reduce costs.

[0037] Furthermore, since the lower packaging substrate 22 is replaced by the redistribution layer 12, the redistribution layer 12 is formed on the surface of the plastic packaging layer of the plastic packaging structure, and the redistribution layer 12 is thinner than the lower packaging substrate 22, the overall thickness of the new HBPOP packaging structure 1 is thinner than the traditional 2. Therefore, the thickness of the upper packaging substrate 11 and the chip 13 can be increased. The thicker upper packaging substrate 11 is less likely to deform or jam during the assembly and manufacturing process, thereby improving the production yield. The thicker chip 13 can reduce the resistance when current passes through, and has a higher computing power, especially in power applications, which helps to improve efficiency and reduce energy loss. In addition, the redistribution layer 12 can shorten the signal transmission path, reduce delay, and improve the efficiency of high-frequency signal transmission; reduce crosstalk between signal layers, and improve signal quality.

[0038] That is, in terms of process flow, the original process needs to independently produce the upper packaging substrate 21 and the lower packaging substrate 22, and stack the upper packaging substrate 21 and the lower packaging substrate 22. These three independent steps involve more than twenty processes. Specifically, the upper packaging substrate 21 involves S111-S115, and the production process of the lower packaging substrate 22 requires at least ten processes. Stacking also involves the process flow of S201-S210. Therefore, the process is extremely complex, tedious and time-consuming. The existing process involves steps S110-S160, and S111-S115, about ten processes. Therefore, in terms of process flow, 50% of the operation links can be reduced, which greatly saves packaging time.

[0039] In terms of cost, Figure 3 The preparation method shown can eliminate the substrate material and solder balls of a layer of lower packaging substrate 22, and the copper wire material utilization rate of the redistribution layer 12 is higher, and its material cost is lower; and its equipment cost can also be reduced, and the frequency of use of substrate stacking and reflow soldering equipment can be reduced to reduce the frequency of use of the equipment, thereby reducing the cost of use of the equipment.

[0040] In terms of yield rate, Figure 3 The preparation method shown can avoid alignment errors during the stacking process, such as offset and tilt. In addition, due to the different thermal stress conditions of the upper package substrate 21 and the lower package substrate 22 during chip packaging in the original production process, thermal warping may occur around the packaged chip. Figure 3 The manufacturing method shown can avoid the thermal warping caused by different thermal stresses, so that the yield rate in actual production can be increased by at least 5%.

[0041] In terms of chip quality, HBPOP requires high-density interconnection to support high bandwidth, such as the integration of HBM memory and logic chips, such as Figure 3 The new HBPOP produced by the preparation method shown can be directly wired on the plastic layer based on RDL technology, achieving shorter signal paths and lower parasitic effects to meet high-bandwidth requirements, thereby improving the quality of chip packaging.

[0042] Preferably, the thickness of the upper package substrate 11 is greater than 0.04 mm, and may be 0.06 mm.

[0043] Preferably, the line width and spacing of the redistribution layer 12 are both between 1μm and 10μm, and the line width spacing of the redistribution layer 12 is between 1 / 1-10 / 10μm, where 1 / 1-10 / 10 means that the line width and spacing are the same width, and both are between 1μm and 10μm; the redistribution layer 12 adopts semiconductor-grade photolithography technology, and accurately controls the line width through photomasks and chemical electroplating, while traditional substrates rely on mechanical etching or printing, and the accuracy is naturally limited; therefore, the redistribution layer 12 can produce 1μm-level lines (traditional substrates are usually ≥10μm) and smaller spacing, and the spacing between adjacent lines can be reduced to 1μm, reducing signal crosstalk, which is suitable for high-frequency and high-speed signal transmission (such as 5G, AI chips); and, multi-layer high-density interconnection (such as TSV+silicon interposer) can be achieved through photolithography, while traditional substrate multi-layer stacking is costly and prone to warping.

[0044] Therefore, preferably, the novel HBPOP package structure 1 has two redistribution layers 12 stacked one above the other.

[0045] Furthermore, while the upper and lower packaging substrates 21 and 22 of the original HBPOP package structure 2 are electrically connected via solder balls 24, the new HBPOP package structure 1 of this application can be configured to provide electrical connectivity via copper. Specifically, a deep blind via 14 is formed on the surface of the plastic package structure near the chip 13. Copper 15 is electroplated within the deep blind via 14, forming a fan-out structure relative to the chip 13. Fan-out packaging is an integrated circuit packaging technology primarily used to integrate multiple transistors or other electronic components into a single packaged device and provide signal input and output connections. It typically does not require a substrate and directly fans out the die to the chip bump layer via a redistribution layer 12 (RDL), effectively improving circuit density, performance, and reliability. Electroplated copper, when used as an electrical conductive medium, has a resistivity of only approximately 1 / 6 that of tin. Therefore, using it as a conductive medium to the RDL layer on the surface of the plastic package structure near the chip 13 can form a fan-out structure.

[0046] That is, before S150, the preparation method also includes: S141, forming a deep blind hole 14 on the surface of the plastic packaging layer close to the chip 13 on the plastic packaging structure by laser; S142, electroplating copper 15 in the deep blind hole 14, and the electroplated copper 15 forms a fan-out structure relative to the chip 13.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0048] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0049] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0050] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0051] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0052] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0053] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A new HBPOP packaging structure, characterized in that: Used for packaging chips, including: An upper packaging substrate, the upper packaging substrate is used to mount the chip, and the upper packaging substrate and the chip form a plastic packaging structure; The redistribution layer is formed on the plastic packaging structure and close to the chip.

2. The novel HBPOP packaging structure according to claim 1, characterized in that: A deep blind hole is formed on the surface of the plastic package structure close to the chip. Copper is electroplated in the deep blind hole, and the electroplated copper forms a fan-out structure relative to the chip.

3. The novel HBPOP packaging structure according to claim 1, characterized in that: The thickness of the upper packaging substrate is greater than 0.04 mm.

4. The novel HBPOP packaging structure according to claim 1, wherein: The novel HBPOP packaging structure has two redistribution layers stacked one above the other.

5. The novel HBPOP packaging structure according to claim 1, characterized in that: The line width and spacing of the redistribution layer are both between 1 μm and 10 μm.

6. A method for preparing a novel HBPOP packaging structure, characterized in that: For preparing the novel HBPOP packaging structure according to any one of claims 1 to 5, the preparation method comprises: Making an upper package substrate; Mounting the chip on the upper packaging substrate; Filling the upper packaging substrate with bottom filling glue; Plastic-sealing the upper package substrate on which the chip is mounted to obtain a plastic-sealed structure; Fabricating interconnection circuits on the surface of the plastic packaging layer close to the chip on the plastic packaging structure to form a redistribution layer; The plastic package structure formed with the redistribution layer is cut to obtain a novel HBPOP packaging structure.

7. The preparation method according to claim 6, wherein Before forming a redistribution layer by fabricating interconnection circuits on the surface of the plastic packaging structure close to the chip, the preparation method further comprises: forming a deep blind hole on the surface of the plastic packaging layer close to the chip on the plastic packaging structure by laser; Copper is electroplated in the deep blind vias, and the electroplated copper forms a fan-out structure relative to the chip.

8. The preparation method according to claim 6, wherein The manufacturing of the upper packaging substrate includes: Laser drilling is performed on the core layer of the substrate; Coating dry film photoresist on the core layer of the substrate after laser drilling, and forming circuit patterns through exposure and development; Electroplating copper in the exposed area for exposure and development to form conductive circuits and fill in the holes; Apply solder mask ink to the core layer of the electroplated substrate to cover the non-soldering area; The pads and contact points of the circuit pattern are gold-plated, and the non-pad and non-contact point areas in the core layer of the substrate are coated with an organic solderability film.

9. The preparation method according to claim 6, wherein Before cutting the plastic package structure with the redistribution layer to obtain the novel HBPOP packaging structure, the preparation method further includes: Interconnection lines are fabricated on the surface of the redistribution layer to form a redistribution layer again.

10. The preparation method according to claim 6, wherein The line width and spacing of the redistribution layer are both between 1 μm and 10 μm.

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