Multi-chip semiconductor structure for improving performance of storage device
By adopting a stepped stacking design and multi-channel transmission channel in a multi-chip semiconductor structure, the heat dissipation problem is solved and the data transmission efficiency and stability of the storage device are improved.
Patent Information
- Application Number
- CN202510683958.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-26
- Publication Date
- 2025-08-26
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
It is difficult to effectively disperse heat in multi-chip semiconductor structures, resulting in a problem of degradation of data transmission efficiency and overheating and damage to storage particles.
The step-stacked memory chip design is adopted, combining the silicon interposer layer and conductive parts for stacking interconnection, and a multi-channel transmission channel is established through the first bonding line, the second bonding line and the composite bonding line, and heat dissipation is performed with the hollow step channel.
It improves the data transmission efficiency of storage devices, prevents the formation of hot spots, and improves operating stability and life.
Smart Images
Figure CN120545288A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a multi-chip semiconductor structure for improving the performance of storage devices. Background Art
[0002] Multi-Chip Package (MCP) is a technology that integrates multiple chips into a single package. MCP integrates multiple semiconductor chips (such as logic chips, memory chips, RF chips, etc.) by vertically stacking them together to achieve higher integration and performance. Multi-chip semiconductors are packaged directly by vertically stacking chips, and are interconnected through silicon interposers and conductive parts. Although this design improves integration, it also makes it difficult to effectively disperse heat, easily forming local hotspots, resulting in reduced data transmission efficiency and even damaging storage particles in the event of overheating. Summary of the Invention
[0003] (1) Purpose of the invention In order to solve the technical problems existing in the background technology, the present invention proposes a multi-chip semiconductor structure for improving the performance of storage devices, which has the characteristics of diverse storage chip connection methods and multi-channel data transmission to improve the performance of storage devices.
[0004] (2) Technical solution To solve the above technical problems, the present invention provides a multi-chip semiconductor structure for improving the performance of a storage device, wherein the packaging mechanism includes a packaging substrate, on which at least one logic chip is arranged; The first storage module includes a plurality of storage chips arranged on the logic chip in a stepped stack, and a silicon interposer is formed at the bottom of each storage chip; The connection mechanism includes a first bonding wire, a second bonding wire, a conductive member, and a composite bonding wire, wherein the exposed portion of the stepped stack is connected by the first bonding wire and the second bonding wire, and the vertically stacked portion is connected by the conductive member; The second storage module has the same structure as the first storage module, and the first bonding wire and the second bonding wire exposed in the second storage module are both connected by the composite bonding wire; The heat dissipation mechanism includes an upper stepped channel arranged on one side of the first bonding wire and a lower stepped channel arranged on one side of the second bonding wire. The upper stepped channel and the lower stepped channel are externally encapsulated with heat-conducting encapsulation material.
[0005] Preferably, the memory chip includes a first memory chip, a second memory chip and a third memory chip; The exposed storage particles of the first storage chip, the second storage chip and the third storage chip are connected by the first bonding wire and the second bonding wire. The first bonding wire is set on the upper part of the storage particle, and the second bonding wire is set on the lower part of the storage particle.
[0006] Preferably, the first storage chip and the second storage chip establish a one-to-two transmission channel through the first bonding wire or the second bonding wire; The second storage chip and the third storage chip establish a second or third transmission channel through the first bonding wire or the second bonding wire; The first memory chip and the third memory chip establish a three-way transmission channel through the first bonding wire or the second bonding wire; The first memory chip, the second memory chip, and the third memory chip establish a one-two-three transmission channel through the first bonding wire or the second bonding wire.
[0007] Preferably, the second memory module includes a fourth memory chip, a fifth memory chip, and a sixth memory chip arranged in a stair-like manner above the third memory chip, wherein exposed portions of the stair-stacked portions of the fourth memory chip, the fifth memory chip, and the sixth memory chip are connected by the first bonding wire and the second bonding wire, and vertically stacked portions are connected by the conductive member; The first bonding wire and the second bonding wire on the first storage module and the second storage module are both connected through the composite bonding wire.
[0008] Preferably, a four-transmission channel is established between the first memory chip and the fourth memory chip via the first bonding wire and the composite bonding wire; A two-to-five transmission channel is established between the second memory chip and the fifth memory chip via the first bonding wire and the composite bonding wire; A three-to-six transmission channel is established between the third memory chip and the sixth memory chip via the first bonding wire and the composite bonding wire; One, two, three, four, five, and six transmission channels are established between the first memory chip, the second memory chip, the third memory chip, the fourth memory chip, the fifth memory chip, and the sixth memory chip through the first bonding wire and the composite bonding wire.
[0009] Preferably, the composite bonding wire is an L-shaped structure, and the distances between the composite bonding wire and the two first bonding wires or the two second bonding wires are the same.
[0010] Preferably, the corners of the upper step channel and the lower step channel are the same as the bending angles of the first bonding wire, the second bonding wire and the composite bonding wire, the distance between the two points is the same, the upper step channel and the lower step channel are both hollow structures, and both are connected to the logic chip and the packaging substrate respectively.
[0011] Preferably, two logic chips are arranged on the packaging substrate, and the two logic chips are connected by a logic chip bonding wire running through the middle of the packaging substrate.
[0012] Preferably, when there are two groups of logic chips, one of the logic chips is provided with a combined first storage module and a second storage module, and the other logic chip is provided with a combined third storage module and a fourth storage module; The third storage module and the fourth storage module are connected via the same connection mechanism.
[0013] Preferably, the packaging mechanism further comprises a packaging cover plate, a partition frame for separating the cavity is provided between the packaging cover plate and the packaging substrate, and a detachable expansion module is provided between the packaging cover plate and the combination of the first storage module and the second storage module.
[0014] The above technical solution of the present invention has the following beneficial technical effects: 1. Compared with storage particles with vertically stacked single transmission channels, the transmission efficiency of storage particles with dual transmission channels established by step-stacked conductive parts and bonding wires is effectively improved. They can act as high-performance transmission particles, increasing the content of high-performance transmission particles in a storage module. When multiple storage modules continue to be combined, the amount of high-performance transmission particles can continue to increase, thereby improving the performance of the storage device.
[0015] 2. A hollow stepped channel is set up for gas to pass through the overall packaging structure for internal heat dissipation. Combined with the stepped stacking design, the external exposure of each layer of chip storage particles is increased, and the heat exchange area is increased to improve the heat dissipation performance. It prevents the internal storage particles from accumulating heat to form hot spots due to the use of vertical stacking, reduces the possibility of storage particles being affected by hot spots and being damaged by overheating, and improves the operating stability and service life of semiconductors after multi-chip combination. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a structural schematic diagram of the present invention; Figure 2 It is an enlarged schematic diagram of the cross-sectional structure of the present invention; Figure 3 It is a schematic diagram of the planar structure of the present invention; Figure 4 Schematic diagram of the combined structure of the first storage module and the second storage module of the present invention; Figure 5 It is a schematic structural diagram of the heat dissipation mechanism of the present invention; Figure 6 Schematic diagram of the logic chip assembly structure of the present invention; Figure 7 This is a schematic diagram of the three-dimensional structure of the logic chip assembly of the present invention; Figure 8 This is a schematic diagram of the logic chip assembly packaging structure of the present invention; Figure 9 It is a schematic diagram of the three-dimensional structure of the logic chip combination package of the present invention.
[0017] Reference numerals: 1. Package substrate; 2. Logic chip; 21. Logic chip bonding wire; 3. Silicon interposer; 41. First memory chip; 42. Second memory chip; 43. Third memory chip; 51. First bonding wire; 52. Second bonding wire; 53. Conductive member; 54. Composite bonding wire; 61. Fourth memory chip; 62. Fifth memory chip; 63. Sixth memory chip; 71. Upper step channel; 72. Lower step channel; 73. Thermally conductive packaging material; 81. Package cover; 82. Partition frame; 83. Extension module. DETAILED DESCRIPTION
[0018] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention.
[0019] like Figure 1-5 As shown, the present invention proposes a multi-chip semiconductor structure for improving the performance of a storage device, wherein the packaging mechanism includes a packaging substrate 1, on which at least one logic chip 2 is arranged; The first storage module includes several storage chips arranged on the logic chip 2, namely, a first storage chip 41, a second storage chip 42 and a third storage chip 43. A silicon interposer 3 is formed on the bottom of each of the three storage chips and the chips are stacked in a stepped manner. The connection mechanism includes a first bonding wire 51, a second bonding wire 52, a conductive member 53 and a composite bonding wire 54. The exposed portion of the stepped stack is connected by the first bonding wire 51 and the second bonding wire 52, and the vertically stacked portion is connected by the conductive member 53. The second storage module has the same structure as the first storage module, and the exposed first bonding wires 51 and second bonding wires 52 of the second storage module are connected by a composite bonding wire 54; The heat dissipation mechanism includes an upper stepped channel 71 provided on one side of the first bonding wire 51 and a lower stepped channel 72 provided on one side of the second bonding wire 52 . The upper stepped channel 71 and the lower stepped channel 72 are encapsulated with a heat conductive encapsulation material 73 .
[0020] It should be noted that the exposed storage particles of the first storage chip 41, the second storage chip 42 and the third storage chip 43 are connected by the first bonding wire 51 and the second bonding wire 52. The first bonding wire 51 is set at the upper part of the storage particle, and the second bonding wire 52 is set at the lower part of the storage particle. The exposed storage particles are connected through multiple groups of first bonding wires 51 and second bonding wires 52. The first bonding wires 51 and the second bonding wires 52 can replace the conductive parts 53 for connection in the exposed area, and the bonding wires can be used to establish transmission channels between the storage particles.
[0021] In one embodiment, after the first memory chip 41 , the second memory chip 42 , and the third memory chip 43 are connected via the first bonding wire 51 , the second bonding wire 52 , and the conductive member 53 of the connection mechanism, the number of memory chips on each of the first memory chip 41 , the second memory chip 42 , and the third memory chip 43 is (10*10), and the total number of memory chips after connection should be (30*10). In the stepped stack, the memory cell portion (18*10) of the first memory module is connected vertically only by the conductive member 53. The exposed portion of the stepped stack is connected to the attachment position by the conductive member 53 and is also connected by the first bonding wire 51 and the second bonding wire 52. The total number of memory cells used to establish dual-channel transmission is (12*10). Compared with vertically stacked single-transmission channel storage particles, dual-transmission channel storage particles have significantly improved transmission efficiency and can serve as high-performance transmission particles. The content of high-performance transmission particles in a storage module is increased. When multiple storage modules are combined, the amount of high-performance transmission particles can be further increased, thereby improving the performance of the storage device.
[0022] As an example, the first memory chip 41 and the second memory chip 42 establish a one-two transmission channel through the first bonding wire 51 or the second bonding wire 52 ; The second storage chip 42 and the third storage chip 43 establish a second or third transmission channel through the first bonding wire 51 or the second bonding wire 52; The first memory chip 41 and the third memory chip 43 establish a three-way transmission channel through the first bonding wire 51 or the second bonding wire 52; The first memory chip 41 , the second memory chip 42 and the third memory chip 43 establish a one-two-three transmission channel through the first bonding wire 51 or the second bonding wire 52 .
[0023] It should be noted that the significance of adding a new transmission channel is to add a data transmission path in addition to the conductive member 53 .
[0024] like Figure 4 As shown, the second memory module includes a fourth memory chip 61, a fifth memory chip 62, and a sixth memory chip 63 arranged in a stair-like manner above the third memory chip 43. The exposed portions of the stair-stacked fourth memory chip 61, the fifth memory chip 62, and the sixth memory chip 63 are connected by a first bonding wire 51 and a second bonding wire 52, and the vertically stacked portions are connected by a conductive member 53. The first bonding wire 51 and the second bonding wire 52 on the first storage module and the second storage module are both connected through a composite bonding wire 54 .
[0025] In one embodiment, in order to improve the performance of the storage device, the total amount of storage particles (60*10) is increased by combining the first storage module and the second storage module. In the stepped stack, the first storage module and the second storage module are only connected by the conductive member 53 in the vertical stacking of the storage particles (18*10). In addition to being connected to the attachment position through the conductive member 53, the exposed part of the stepped stack is also connected by the first bonding wire 51 and the second bonding wire 52. The total amount of storage particles for dual-channel transmission is (42*10), which can meet the needs of higher performance storage devices.
[0026] As an example: A four-way transmission channel is established between the first memory chip 41 and the fourth memory chip 61 via the first bonding wire 51 and the composite bonding wire 54 ; A two-to-five transmission channel is established between the second memory chip 42 and the fifth memory chip 62 via the first bonding wire 51 and the composite bonding wire 54 ; A three-to-six transmission channel is established between the third memory chip 43 and the sixth memory chip 63 via the first bonding wire 51 and the composite bonding wire 54; One, two, three, four, five, and six transmission channels are established between the first memory chip 41 , the second memory chip 42 , the third memory chip 43 and the fourth memory chip 61 , the fifth memory chip 62 , and the sixth memory chip 63 via the first bonding wires 51 and the composite bonding wires 54 .
[0027] It can be understood that after being connected through the first bonding wire 51, the second bonding wire 52 and the composite bonding wire 54, some storage particles of the stepped structure cooperate with the conductive parts 53 in the original silicon interposer 3 to become storage particles with dual transmission channels (high-performance transmission particles).
[0028] In order to ensure the stability of data transmission, further, the composite bonding wire 54 is an L-shaped structure, and the distances between the composite bonding wire 54 and the two first bonding wires 51 or the two second bonding wires 52 are the same.
[0029] like Figure 5 As shown, the corners of the upper step channel 71 and the lower step channel 72 are the same as the bending angles of the first bonding wire 51, the second bonding wire 52 and the composite bonding wire 54, and the distance between the two points is the same. The upper step channel 71 and the lower step channel 72 are both hollow structures, and both are connected to the logic chip 2 and the packaging substrate 1 respectively, for internal heat dissipation of gas through the overall packaging structure. With the design of step stacking, the external exposure of the storage particles of each layer of chips is increased, the heat exchange area is increased to improve the heat dissipation performance, and the vertical stacking is prevented from causing the internal storage particles to accumulate heat to form a hot spot area, reducing the possibility of overheating and damage of the storage particles due to the hot spot area, thereby improving the operating stability and service life of the semiconductor after the multi-chip combination.
[0030] like Figure 6-9 As shown, two logic chips 2 are set on the packaging substrate 1, and the two logic chips 2 are connected by a logic chip bonding wire 21 that runs through the middle of the packaging substrate 1. The logic chips 2 are connected by signals through the logic chip bonding wire 21 to perform interactive control of the storage modules on the two logic chips 2.
[0031] When there are two logic chips 2, one logic chip 2 is provided with a combined first storage module and a second storage module, and the other logic chip 2 is provided with a combined third storage module and a fourth storage module; The third storage module and the fourth storage module are connected via the same connection mechanism.
[0032] In one embodiment, when a logic chip 2 is already provided with a combined first storage module and second storage module, continuing to integrate a third storage module thereon will not effectively improve the storage performance and will increase the volume of the multi-chip semiconductor. Therefore, a logic chip 2 is added on one side, and the same stepped stacking design is adopted, that is, a combination of the third storage module and the fourth storage module, to horizontally expand the total amount of storage particles and improve the performance of the storage device through hardware improvements.
[0033] In one embodiment, the packaging mechanism also includes a packaging cover 81, and the packaging cover 81 and the packaging substrate 1 are used for the upper and lower packaging respectively. A partition frame 82 for separating the cavities is arranged between the packaging cover 81 and the packaging substrate 1, and is supported by an insulating rigid material (such as FR4 or ceramic) to form a dual-cavity structure for independent arrangement of storage particles in each cavity, while providing a certain degree of thermal insulation protection. A detachable expansion module 83 is arranged between the packaging cover 81 and the combination of the first storage module and the second storage module. After the extension module 83 is disassembled, functional chips other than the storage chip can be installed for functional expansion, and an improved sub-packaging unit is reserved to break through the limitations of the traditional fixed packaging architecture.
[0034] It should be understood that the above-described specific embodiments of the present invention are merely illustrative or illustrative of the principles of the present invention and do not constitute limitations of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included within the scope of protection of the present invention. In addition, the appended claims are intended to cover all variations and modifications that fall within the scope and metes and bounds of the appended claims, or equivalents thereof.
Claims
1. A multi-chip semiconductor structure for improving the performance of a storage device, characterized in that: The packaging mechanism comprises a packaging substrate (1), on which at least one logic chip (2) is arranged; The first storage module comprises a plurality of storage chips arranged on the logic chip (2), which are stacked in a stepped manner, and a silicon interposer (3) is formed at the bottom of each storage chip; The connection mechanism includes a first bonding wire (51), a second bonding wire (52), a conductive member (53) and a composite bonding wire (54), wherein the exposed portion of the stepped stack is connected via the first bonding wire (51) and the second bonding wire (52), and the vertically stacked portion is connected via the conductive member (53); The second storage module has the same structure as the first storage module, and the first bonding wire (51) and the second bonding wire (52) exposed on both are connected via the composite bonding wire (54); The heat dissipation mechanism comprises an upper stepped channel (71) arranged on one side of the first bonding wire (51) and a lower stepped channel (72) arranged on one side of the second bonding wire (52), wherein the upper stepped channel (71) and the lower stepped channel (72) are externally encapsulated with a heat-conducting encapsulation material (73).
2. The multi-chip semiconductor structure for improving storage device performance according to claim 1, wherein: The memory chip includes a first memory chip (41), a second memory chip (42), and a third memory chip (43); The exposed storage particles of the first storage chip (41), the second storage chip (42) and the third storage chip (43) are connected via the first bonding wire (51) and the second bonding wire (52), wherein the first bonding wire (51) is arranged on the upper part of the storage particle and the second bonding wire (52) is arranged on the lower part of the storage particle.
3. The multi-chip semiconductor structure for improving storage device performance according to claim 2, wherein: The first storage chip (41) and the second storage chip (42) establish a one-to-two transmission channel via the first bonding wire (51) or the second bonding wire (52); The second storage chip (42) and the third storage chip (43) establish a second-third transmission channel via the first bonding wire (51) or the second bonding wire (52); The first memory chip (41) and the third memory chip (43) establish a three-way transmission channel via the first bonding wire (51) or the second bonding wire (52); The first memory chip (41), the second memory chip (42), and the third memory chip (43) establish a one-two-three transmission channel via the first bonding wire (51) or the second bonding wire (52).
4. The multi-chip semiconductor structure for improving storage device performance according to claim 1, wherein: The second storage module comprises a fourth storage chip (61), a fifth storage chip (62) and a sixth storage chip (63) arranged in a stair-like manner above the third storage chip (43), wherein exposed portions of the stair-stacked layers of the fourth storage chip (61), the fifth storage chip (62) and the sixth storage chip (63) are connected via the first bonding wire (51) and the second bonding wire (52), and vertically stacked portions are connected via the conductive member (53); The first bonding wire (51) and the second bonding wire (52) on the first storage module and the second storage module are both connected via the composite bonding wire (54).
5. The multi-chip semiconductor structure for improving storage device performance according to claim 4, wherein: A four-way transmission channel is established between the first memory chip (41) and the fourth memory chip (61) via the first bonding wire (51) and the composite bonding wire (54); A two-to-five transmission channel is established between the second storage chip (42) and the fifth storage chip (62) via the first bonding wire (51) and the composite bonding wire (54); A three-to-six transmission channel is established between the third storage chip (43) and the sixth storage chip (63) via the first bonding wire (51) and the composite bonding wire (54); One, two, three, four, five, and six transmission channels are established between the first memory chip (41), the second memory chip (42), the third memory chip (43), the fourth memory chip (61), the fifth memory chip (62), and the sixth memory chip (63) via the first bonding wire (51) and the composite bonding wire (54).
6. The multi-chip semiconductor structure for improving storage device performance according to claim 1, wherein: The composite bonding wire (54) is an L-shaped structure, and the distances between the composite bonding wire (54) and the two first bonding wires (51) or the two second bonding wires (52) are the same.
7. The multi-chip semiconductor structure for improving storage device performance according to claim 1, wherein: The corners of the upper step channel (71) and the lower step channel (72) are the same as the bending angles of the first bonding wire (51), the second bonding wire (52) and the composite bonding wire (54), and the distance between the two points is the same. The upper step channel (71) and the lower step channel (72) are both hollow structures, and are respectively connected to the logic chip (2) and the packaging substrate (1).
8. The multi-chip semiconductor structure for improving storage device performance according to claim 1, wherein: Two logic chips (2) are arranged on the packaging substrate (1), and the two logic chips (2) are connected via a logic chip bonding wire (21) that passes through the middle of the packaging substrate (1).
9. The multi-chip semiconductor structure for improving storage device performance according to claim 1, wherein: When there are two groups of logic chips (2), one of the logic chips (2) is provided with a combined first storage module and a second storage module, and the other logic chip (2) is provided with a combined third storage module and a fourth storage module; The third storage module and the fourth storage module are connected via the same connection mechanism.
10. The multi-chip semiconductor structure for improving storage device performance according to claim 1, wherein: The packaging mechanism further comprises a packaging cover plate (81), a partition frame (82) for separating the cavities is provided between the packaging cover plate (81) and the packaging substrate (1), and a detachable expansion module (83) is provided between the packaging cover plate (81) and the combination of the first storage module and the second storage module.