An open-loop residual amplifier and electronic equipment for PSAR ADC

Abstract

The present invention discloses an open-loop residual amplifier and electronic equipment for PSAR ADC. The first circuit unit of the open-loop residual amplifier of the present invention comprises a two-stage structure consisting of a first super source follower structure and an NMOS tube M7. The negative output terminal Voutn Also through a resistor R 21 Connected to the intermediate voltage VCM; the second circuit unit includes a two-stage structure consisting of a second super source follower structure and a PMOS tube M5, the second super source follower structure includes an NMOS tube M11, a PMOS tube M9, a resistor R 12 , current source I XN and current source I YN The present invention aims to solve the problem of the influence caused by the jitter of the open-loop residual amplifier control clock, avoid the mutual restriction of gain and bandwidth in the design for use in higher-speed PSAR ADCs, and improve the linearity of the residual amplifier input transconductance.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an open-loop residual amplifier and electronic equipment for a PSAR ADC. Background Art

[0002] A pipelined serial-to-parallel converter (PSAR ADC) consists of a multi-stage serial-to-analog-to-digital converter (SAR ADC) and a residual amplifier (RA). The residual amplifier amplifies the residual voltage from the previous SAR ADC stage and forwards it to the next SAR ADC stage for conversion, thereby improving the resolution of a single-stage SAR ADC. Pipeline ADCs have a higher number of bits per stage, resulting in a smaller residual voltage. Therefore, a higher-gain residual amplifier is required for amplification. Furthermore, as process technology shrinks and ADC speeds increase, the time available for the residual amplifier to amplify the signal becomes increasingly limited. Traditional closed-loop residual amplifiers, due to their negative feedback structure, maintain reliable linearity under varying conditions. However, its voltage buildup is a negative exponential growth. Taking a 5+5-bit pipelined serial-to-parallel converter as an example, the residual amplifier needs to achieve a gain of 32 times, and the voltage buildup to the corresponding accuracy requires a bandwidth of more than 1GHz. The power consumption is enormous. As the speed of the analog-to-digital converter increases, the closed-loop structure gradually fails to meet the requirements. The open-loop residual amplifier with an open-loop structure can significantly reduce power consumption and increase speed. However, it is difficult to maintain good linearity under different PVT (power, voltage and operating temperature). The current open-loop residual amplifier working principles are mainly divided into dynamic integration type (output voltage is not fully built) and Gm_R type (output voltage is fully built). Lin J and Vaz B proposed two different structures of dynamic integration type residual amplifiers in 2011 and 2017 respectively. Although the two structures are different, in essence, both structures use the relatively fixed slew rate stage in the initial stage of voltage buildup to achieve amplification. At the same time, both structures ensure the stability of the common mode of the output voltage. However, the gain expression of the dynamic integration type open-loop residual amplifier is different from that of g m / C L and T amp The product of g m is the transconductance, C L is the load capacitance, T amp is the RC time constant, due to the transconductance g mDynamically integrating open-loop residual amplifiers (Gm_R) have always been plagued by nonlinearity caused by input voltage, and jitter in the amplification time can also introduce noise into the entire system. For Gm_R open-loop residual amplifiers, setting an excessively small output resistor to increase speed reduces the residual amplifier's gain, effectively increasing the input transistor transconductance to boost gain. However, excessively large input transistors introduce significant parasitic capacitance, and the nonlinearity of transconductance can significantly impact gain. The strong dependence of gain on resistance severely impacts the gain of residual amplifiers with this structure, particularly under various conditions (power, voltage, and operating temperature). Summary of the Invention

[0003] Technical problem to be solved by the present invention: In response to the above-mentioned problems in the prior art, an open-loop residual amplifier and electronic equipment for a PSAR ADC are provided. The present invention aims to solve the problem of the impact caused by jitter of the open-loop residual amplifier control clock, avoid the mutual constraint of gain and bandwidth in the design to facilitate the use of higher-speed PSAR ADCs, and improve the linearity of the residual amplifier input transconductance.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] An open-loop residual amplifier for a PSAR ADC includes a first circuit unit and a second circuit unit. The first circuit unit includes a two-stage structure consisting of a first super source follower structure and an NMOS transistor M7. The first super source follower structure includes a PMOS transistor M1, an NMOS transistor M3, a resistor R 11 , current source I XP and current source I YP , current source I XP , PMOS tube M1, current source I YP The gate of the PMOS tube M1 is connected to the negative input terminal V in , the source of PMOS tube M1 passes through resistor R 11 The drain of the NMOS tube M3 is connected to the drain of the PMOS tube M1, the drain of the NMOS tube M3 and the gate of the NMOS tube M7 are connected to the ground, and the drain of the NMOS tube M7 is connected to the negative output terminal V outn , and the negative output terminal V outn Also through a resistor R 21 Connected to the intermediate voltage VCM, the intermediate voltage VCM is the negative input terminal V in and the positive input terminal V ip The second circuit unit comprises a two-stage structure consisting of a second super source follower structure and a PMOS tube M5, the second super source follower structure includes an NMOS tube M11, a PMOS tube M9, a resistor R12 , current source I XN and current source I YN , current source I YN , NMOS tube M11, current source I XN The gate of NMOS tube M11 is connected to the negative input terminal V in , the source of NMOS tube M11 passes through resistor R 12 The drain of the NMOS tube M11 is connected to the gate of the PMOS tube M9 and the gate of the PMOS tube M5. The source of the PMOS tube M9 and the PMOS tube M5 is connected to the power supply. The drain of the PMOS tube M5 is connected to the negative output terminal V outn .

[0006] Optionally, the MOS tube width-to-length ratio of the NMOS tube M7 is K times that of the NMOS tube M3, and the MOS tube width-to-length ratio of the PMOS tube M5 is K times that of the PMOS tube M9, where K is the negative output terminal V outn Relative negative input terminal V in The relative voltage amplification factor.

[0007] Optionally, a third circuit unit and a fourth circuit unit are further included. The third circuit unit includes a two-stage structure consisting of a third super source follower structure and an NMOS tube M8. The third super source follower structure includes a PMOS tube M2, an NMOS tube M4, a resistor R 13 , current source I XP and current source I YP , current source I XP , PMOS tube M2, current source I YP The gate of the PMOS tube M2 is connected to the positive input terminal V ip , the source of PMOS tube M2 passes through resistor R 13 The drain of the PMOS tube M2 is connected to the gates of the NMOS tubes M4 and M8. The sources of the NMOS tubes M4 and M8 are grounded. The drain of the NMOS tube M8 is connected to the positive output terminal V outp , and the positive output terminal V outp Also through a resistor R 22 Connected to the intermediate voltage VCM; the fourth circuit unit includes a two-stage structure consisting of a fourth super source follower structure and a PMOS tube M6, the fourth super source follower structure includes an NMOS tube M12, a PMOS tube M10, a resistor R 14 , current source I XN and current source I YN , current source I YN , NMOS tube M12, current source IXN The gate of NMOS tube M12 is connected to the positive input terminal V ip , the source of NMOS tube M12 passes through resistor R 14 The drain of the NMOS tube M12 is connected to the gate of the PMOS tube M10 and the gate of the PMOS tube M6. The source of the PMOS tube M10 and the PMOS tube M6 is connected to the power supply. The drain of the PMOS tube M6 is connected to the positive output terminal V outp .

[0008] Optionally, a resistor R is connected between the sources of the PMOS transistors M1 and M2. 01 A resistor R is connected between the source of the PMOS tube M10 and the NMOS tube M12. 02 .

[0009] In addition, the present invention also provides an electronic device, including an analog-to-digital converter based on a pipeline serial-to-parallel converter composed of a multi-stage serial-to-parallel conversion-analog-to-digital converter and a residual amplifier, wherein the residual amplifier is the open-loop residual amplifier for the PSAR ADC.

[0010] Compared with the prior art, the present invention can achieve the following beneficial effects: 1. The open-loop residual amplifier of the present invention adopts a voltage complete establishment structure, which avoids the influence of the jitter of the control clock existing in the dynamic integration structure and solves the problem of the influence caused by the jitter of the control clock of the open-loop residual amplifier. 2. In order to improve the speed of the residual amplifier and make the voltage establishment as fast as possible, the output of the open-loop residual amplifier of the present invention is connected through a resistor R 21 Connected to the intermediate voltage VCM output resistance equal to R 21 , which can be adjusted according to application needs. 3. The open-loop residual amplifier of the present invention has a two-stage structure, which can achieve a wider gain range. 4. The open-loop residual amplifier of the present invention improves the SSF (Super Source Follower) structure so that the gain is related to the width-to-length ratio of the MOS tube and the resistor ratio, and the resistor and MOS tube are matched to make the gain still maintain good stability under different PVT (power, voltage and operating temperature), avoiding the mutual constraints of gain and bandwidth in the design for use in higher-speed PSAR ADCs, and improving the linearity of the residual amplifier input transconductance. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Schematic diagram of the circuit structure of an open-loop residual amplifier in an embodiment of the present invention.

[0012] Figure 2 Schematic diagram of the circuit structure of the first circuit unit in an embodiment of the present invention.

[0013] Figure 3 Schematic diagram of the static analysis circuit structure of the first circuit unit in an embodiment of the present invention.

[0014] Figure 4 Schematic diagram of the dynamic analysis circuit structure of the first circuit unit in an embodiment of the present invention.

[0015] Figure 5 Schematic diagram of the circuit structure of the first super source follower structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The open-loop residual amplifier for a PSAR ADC employs a Super Source Follower (SSF) structure to stabilize the transconductance of the input transistor. The same resistor matching is used to stabilize gain variations under varying PVT conditions. To facilitate a better understanding of the technical solutions of the present invention, the following detailed description is provided in conjunction with the accompanying drawings illustrating embodiments of the present invention.

[0017] like Figure 1 As shown, the open-loop residual amplifier for PSAR ADC in this embodiment includes a first circuit unit and a second circuit unit. The first circuit unit includes a two-stage structure consisting of a first super source follower structure and an NMOS transistor M7. The first super source follower structure includes a PMOS transistor M1, an NMOS transistor M3, a resistor R 11 , current source I XP and current source I YP , current source I XP , PMOS tube M1, current source I YP The gate of the PMOS tube M1 is connected to the negative input terminal V in , the source of PMOS tube M1 passes through resistor R 11 The drain of the NMOS tube M3 is connected to the drain of the PMOS tube M1, the drain of the NMOS tube M3 and the gate of the NMOS tube M7 are connected to the ground, and the drain of the NMOS tube M7 is connected to the negative output terminal V outn , and the negative output terminal V outn Also through a resistor R 21 Connected to the intermediate voltage VCM (so that the output node is connected through the parallel resistor R 21 Make the output static voltage stable near VCM), the intermediate voltage VCM is the negative input terminal V in and the positive input terminal V ipThe second circuit unit comprises a two-stage structure consisting of a second super source follower structure and a PMOS tube M5, the second super source follower structure includes an NMOS tube M11, a PMOS tube M9, a resistor R 12 , current source I XN and current source I YN , current source I YN , NMOS tube M11, current source I XN The gate of NMOS tube M11 is connected to the negative input terminal V in , the source of NMOS tube M11 passes through resistor R 12 The drain of the NMOS tube M11 is connected to the gate of the PMOS tube M9 and the gate of the PMOS tube M5. The source of the PMOS tube M9 and the PMOS tube M5 is connected to the power supply. The drain of the PMOS tube M5 is connected to the negative output terminal V outn .

[0018] like Figure 1 As shown, in this embodiment, the MOS tube width-to-length ratio of the NMOS tube M7 is K times that of the NMOS tube M3, and the MOS tube width-to-length ratio of the PMOS tube M5 is K times that of the PMOS tube M9, where K is the negative output terminal V outn Relative negative input terminal V in The relative voltage amplification factor.

[0019] like Figure 1 As shown, this embodiment further includes a third circuit unit and a fourth circuit unit. The third circuit unit includes a two-stage structure consisting of a third super source follower structure and an NMOS transistor M8. The third super source follower structure includes a PMOS transistor M2, an NMOS transistor M4, a resistor R 13 , current source I XP and current source I YP , current source I XP , PMOS tube M2, current source I YP The gate of the PMOS tube M2 is connected to the positive input terminal V ip , the source of PMOS tube M2 passes through resistor R 13 The drain of the PMOS tube M2 is connected to the gates of the NMOS tubes M4 and M8. The sources of the NMOS tubes M4 and M8 are grounded. The drain of the NMOS tube M8 is connected to the positive output terminal V outp , and the positive output terminal V outp Also through a resistor R 22Connected to the intermediate voltage VCM; the fourth circuit unit includes a two-stage structure consisting of a fourth super source follower structure and a PMOS tube M6, the fourth super source follower structure includes an NMOS tube M12, a PMOS tube M10, a resistor R 14 , current source I XN and current source I YN , current source I YN , NMOS tube M12, current source I XN The gate of NMOS tube M12 is connected to the positive input terminal V ip , the source of NMOS tube M12 passes through resistor R 14 The drain of the NMOS tube M12 is connected to the gate of the PMOS tube M10 and the gate of the PMOS tube M6. The source of the PMOS tube M10 and the PMOS tube M6 is connected to the power supply. The drain of the PMOS tube M6 is connected to the positive output terminal V outp .

[0020] like Figure 1 As shown, in this embodiment, a resistor R is connected between the sources of the PMOS tube M1 and the PMOS tube M2. 01 A resistor R is connected between the source of the PMOS tube M10 and the NMOS tube M12. 02 .

[0021] The following will be Figure 2 The operating principle of the open-loop residual amplifier of this embodiment is described using the first circuit unit as an example. When the residual amplifier begins operating, because the PMOS transistor M1 and the NMOS transistor M3 are located in an SSF structure (a first super source follower structure), the loop gain causes node X to always follow the input voltage.

[0022] First, perform static analysis. Figure 3 This is a schematic diagram of the static analysis circuit structure of the first circuit unit in this embodiment. 01 The circuits at both ends are symmetrical. Under static working condition, the resistance R 01 No current will flow. Therefore, the current flowing through the resistor R 11 The current is equal to I X -I Y The voltage at node Z is:

[0023] ,

[0024] in, is the voltage at node Z, is the voltage of node X, is the current of node X, is the current at the Y node, is the resistor R11 ~R 14 Since the NMOS tube M3 and NMOS tube M7 share the same gate voltage, when the negative output terminal Voutn Output voltage V out When the static voltage of the Z node is consistent, the NMOS transistor M7 can better replicate the current of the NMOS transistor M3. 21 Connected to the output node, since the output impedance of NMOS tube M7 is much greater than the resistor R 21 , so that the output static voltage is equal to the intermediate voltage VCM.

[0025] Perform dynamic analysis based on static analysis. Figure 4 This is a schematic diagram of the dynamic analysis circuit structure of the first circuit unit in this embodiment. 01 The voltages at both ends change in opposite directions, so the resistor R 01 The middle node is regarded as AC ground, and the equivalent resistance R0' in single-side analysis is R0'=R0 / 2. Among them, R0 is the resistance R 01 and resistor R 02 and resistance value; if the SSF loop gain of the first super source follower structure is infinite, then:

[0026] ,

[0027] in, is the voltage increment of the X node, The voltage difference generated by the first super source follower structure will produce a current change on the equivalent resistor R0'. When the channel length modulation effect is not considered, the impedance of the node Y is infinite, and the excess current on the equivalent resistor R0' will only flow from the resistor R 11 Flowing upward. Then:

[0028] ,

[0029] ,

[0030] in, is the excess current on the equivalent resistor R0', From the resistor R 11 The current flowing out, is the voltage increment at node Z. Considering that an excessively large resistor ratio will cause the static voltage at node Z to be too low, using it as an output point will limit the voltage swing of the residual amplifier. The added NMOS transistor M7 can further amplify the signal. At this time, the voltage increment at node Y is:

[0031] ,

[0032] in, is the voltage increment at the Y node, is the transconductance of NMOS tube M3, is the output impedance of the Z node. The drain static voltage of the NMOS tube M3 is controlled to be consistent with that of the NMOS tube M7 as much as possible, thereby controlling the drain-source voltage difference V DS The effect on transconductance is the same. Assuming that the width-to-length ratio of the NMOS tube M7 is K times that of the NMOS tube M3, the amplification is achieved:

[0033] ,

[0034] in, is the positive output voltage increment, is the transconductance of NMOS tube M7, is the resistor R 21 and resistor R 22 In practice, due to the resistance R 01 and R 02 The loop gain will be greatly attenuated if there is a load effect. Figure 5 The open-loop gain of the disconnected loop is shown as for:

[0035] ,

[0036] in, is the transconductance of the PMOS tube M1, is the output impedance of the PMOS tube M1 from the drain, for and The parallel resistance value.

[0037] The loop gain and closed-loop gain are:

[0038] ,

[0039] ,

[0040] in, is the closed-loop feedback coefficient, is the closed-loop gain.

[0041] The actual open-loop residual amplifier unilateral gain A is:

[0042]

[0043] in, is the transconductance of the PMOS tube M2.

[0044] Since the second stage of the open-loop residual amplifier is a Class AB structure (Class A and B amplifier structure), the transconductance of the PMOS tube M5 will be superimposed with the NMOS tube M7 for amplification. The final open-loop residual amplifier gain is for:

[0045]

[0046] in, is the closed-loop gain of the NMOS tube input, is the closed-loop gain of the PMOS transistor input. Due to the existence of the SSF loop in the first super source follower structure, although changes in transconductance will cause changes in open-loop gain under different PVT conditions, as long as the loop gain is much greater than 1, the impact on the closed-loop gain is very weak. For example, when PVT changes cause the open-loop gain A0 to change by ΔA0, then:

[0047] ,

[0048] ,

[0049] in, The actual gain of the op amp is affected by PVT. for Changes caused by PVT, for Changes caused by PVT.

[0050] To verify the open-loop residual amplifier for a PSAR ADC in this embodiment, simulations were conducted with a power supply voltage of 1.8V, an input voltage range of -20mV to 20mV, and a load capacitance of 150fF. The results are as follows: the residual amplifier achieved a -3dB bandwidth of 1.57GHz, power consumption of 5.55mW, and an open-loop gain of 16.2. The SFDR (spurious-free dynamic range) of the open-loop residual amplifier in this embodiment was simulated under different PVT (power, voltage, and operating temperature) conditions, and the results are shown in Table 1.

[0051] Table 1: Simulation results of performance parameters of the open-loop residual amplifier of this embodiment

[0052]

[0053] In Table 1, SS represents a combination of slow NMOS and slow PMOS, FF represents a combination of fast NMOS and fast PMOS, and TT represents a combination of typical NMOS and typical PMOS. As shown in Table 1, under different PVTs (power, voltage, and operating temperature), the SFDR of the open-loop residual amplifier of this embodiment varies from 53.0 to 62.2 dB, meeting the linearity requirement of at least 7 bits.

[0054] In summary, the open-loop residual amplifier for PSAR ADC in this embodiment adopts a voltage complete settling structure, which avoids the influence of control clock jitter existing in the dynamic integration structure. In order to improve the speed of the residual amplifier and make the voltage settling as fast as possible, the output resistance of the open-loop residual amplifier for PSAR ADC in this embodiment is equal to R 21 / R 22 , which can be adjusted according to application needs. The open-loop residual amplifier proposed in this embodiment for a PSAR ADC features a two-stage Class AB structure, enabling a wider gain range. This open-loop residual amplifier for a PSAR ADC employs an improved SSF structure based on resistor matching to stabilize output gain, making the gain dependent on the MOS transistor aspect ratio and resistor ratio. Matching the resistors and MOS transistors ensures good gain stability across various PVT (power, voltage, and operating temperature) conditions.

[0055] In addition, this embodiment also provides an electronic device, including an analog-to-digital converter based on a pipeline serial-to-parallel converter composed of a multi-stage serial-to-parallel conversion-analog-to-digital converter and a residual amplifier, wherein the residual amplifier is the open-loop residual amplifier for the PSAR ADC described above in this embodiment.

[0056] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. An open-loop residual amplifier for a PSAR ADC, characterized in that: The first circuit unit includes a two-stage structure consisting of a first super source follower structure and an NMOS tube M7. The first super source follower structure includes a PMOS tube M1, an NMOS tube M3, a resistor R 11 , current source I XP and current source I YP , the power supply passes through the current source I XP , PMOS tube M1, current source I YP Then the ground GND is connected, and the gate of the PMOS tube M1 is connected to the negative input terminal V in , the source of PMOS tube M1 passes through resistor R 11 The drain of the NMOS tube M3 is connected to the drain of the PMOS tube M1, the drain of the NMOS tube M3 and the gate of the NMOS tube M7 are connected to the ground, and the drain of the NMOS tube M7 is connected to the negative output terminal V outn , and the negative output terminal V outn Also through a resistor R 21 Connected to the intermediate voltage VCM, the intermediate voltage VCM is the negative input terminal V in and the positive input terminal V ip The second circuit unit comprises a two-stage structure consisting of a second super source follower structure and a PMOS tube M5, the second super source follower structure includes an NMOS tube M11, a PMOS tube M9, a resistor R 12 , current source I XN and current source I YN , the power supply passes through the current source I YN , NMOS tube M11, current source I XN Then the ground GND is connected, and the gate of NMOS tube M11 is connected to the negative input terminal V in , the source of NMOS tube M11 passes through resistor R 12 The drain of the NMOS tube M11 is connected to the gate of the PMOS tube M9 and the gate of the PMOS tube M5. The source of the PMOS tube M9 and the PMOS tube M5 is connected to the power supply. The drain of the PMOS tube M5 is connected to the negative output terminal V outn The PSAR ADC refers to an analog-to-digital converter based on a pipeline serial-to-parallel converter, and the analog-to-digital converter based on a pipeline serial-to-parallel converter is composed of a multi-stage serial-to-parallel conversion-analog-to-digital converter and a residual amplifier.

2. The open-loop residual amplifier for PSAR ADC according to claim 1, wherein The width-to-length ratio of the NMOS tube M7 is K times that of the NMOS tube M3, and the width-to-length ratio of the PMOS tube M5 is K times that of the PMOS tube M9, where K is the negative output terminal V outn Relative negative input terminal V in The relative voltage amplification factor.

3. The open-loop residual amplifier for PSAR ADC according to claim 2, wherein: The third circuit unit includes a two-stage structure consisting of a third super source follower structure and an NMOS tube M8, and the third super source follower structure includes a PMOS tube M2, an NMOS tube M4, a resistor R 13 , current source I XP and current source I YP , the power supply passes through the current source I XP , PMOS tube M2, current source I YP Then the ground GND is connected, and the gate of the PMOS tube M2 is connected to the positive input terminal V ip , the source of PMOS tube M2 passes through resistor R 13 The drain of the PMOS tube M2 is connected to the gates of the NMOS tubes M4 and M8. The sources of the NMOS tubes M4 and M8 are grounded. The drain of the NMOS tube M8 is connected to the positive output terminal V outp , and the positive output terminal V outp Also through a resistor R 22 Connected to the intermediate voltage VCM; the fourth circuit unit includes a two-stage structure consisting of a fourth super source follower structure and a PMOS tube M6, the fourth super source follower structure includes an NMOS tube M12, a PMOS tube M10, a resistor R 14 , current source I XN and current source I YN , the power supply passes through the current source I YN , NMOS tube M12, current source I XN Then the ground GND is connected, and the gate of NMOS tube M12 is connected to the positive input terminal V ip , the source of NMOS tube M12 passes through resistor R 14 The drain of the NMOS tube M12 is connected to the gate of the PMOS tube M10 and the gate of the PMOS tube M6. The source of the PMOS tube M10 and the PMOS tube M6 is connected to the power supply. The drain of the PMOS tube M6 is connected to the positive output terminal V outp .

4. The open-loop residual amplifier for PSAR ADC according to claim 3, wherein: A resistor R is connected between the sources of the PMOS tubes M1 and M2. 01 A resistor R is connected between the source of the PMOS tube M10 and the NMOS tube M12. 02 .

5. An electronic device comprising an analog-to-digital converter based on a pipeline serial-to-parallel converter, comprising a multi-stage serial-to-parallel converter and a residual amplifier, wherein: The residual amplifier is an open-loop residual amplifier for a PSAR ADC according to any one of claims 1 to 4.

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