Three-dimensional structure of polar memory chalcogenide

Abstract

The invention relates to a three-dimensional structure of polar memory chalcogenide. The present disclosure also relates to a memory device having a three-dimensional array of nodes configured on a semiconductor substrate. Each respective node in the array has a selector transistor; and a memory cell, the memory cell comprising: a first conductive material layer configured as a first electrode terminal, the first electrode terminal being connected to the selector transistor; a second conductive material layer configured as a second electrode terminal; and a chalcogenide alloy layer that is sandwiched between the first electrode terminal and the second electrode terminal. The chalcogenide alloy comprises a ternary indium-arsenic-selenium material or a ternary indium-arsenic-tellurium material, and the material is deposited by using an atomic layer deposition technology.

Description

[0001] Related applications

[0002] This application claims priority to provisional U.S. patent application serial number 63 / 557,106, filed on February 23, 2024, the entire disclosure of which is hereby incorporated by reference herein. Technical Field

[0003] At least some embodiments disclosed herein relate generally to three-dimensional memory array structures, and more particularly, but not limited to, memory array structures using memory cells implemented with chalcogenide alloys. Background Art

[0004] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Typically, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices.

[0005] A memory device may include a memory integrated circuit having an array of one or more memory cells formed on an integrated circuit die of semiconductor material. A memory cell is the smallest unit of memory that can be used or operated individually for storing data. Typically, a memory cell can store one or more data bits.

[0006] Different types of memory cells have been developed for memory integrated circuits, such as random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), NOR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), flash memory, etc.

[0007] Some integrated circuit memory cells are volatile and require power to maintain the data stored in the cell. Examples of volatile memory include dynamic random access memory (DRAM) and static random access memory (SRAM).

[0008] Some integrated circuit memory cells are non-volatile and can retain stored data even when power is not supplied. Examples of non-volatile memory include flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electronically erasable programmable read-only memory (EEPROM). Flash memory includes NAND-type flash memory or NOR-type flash memory. NAND-type memory cells are based on NAND logic gates; and NOR-type memory cells are based on NOR logic gates.

[0009] Integrated circuit memory cells can be programmed to store data by applying a voltage or voltage pattern to the memory cell during a program / write operation. The program / write operation sets the memory cell to a state corresponding to the data being programmed / stored into the memory cell. The data stored in the memory cell can be retrieved during a read operation by examining the state of the memory cell. For example, a read operation can determine the state of the memory cell by applying a voltage and determining whether the memory cell becomes conductive. Summary of the Invention

[0010] In one aspect, the present disclosure provides a memory device comprising: a three-dimensional node array, the array being configured on a semiconductor substrate, each corresponding node in the array having: a selector transistor; and a memory cell, the memory cell having: a first conductive material layer, the first conductive material layer being configured as a first electrode terminal of the memory cell, the first electrode terminal being connected to the selector transistor; a second conductive material layer, the second conductive material layer being configured as a second electrode terminal of the memory cell; and a chalcogenide alloy layer, the layer being sandwiched between the first electrode terminal and the second electrode terminal.

[0011] In another aspect, the present disclosure provides a device comprising: a controller; a bit line driver, the bit line driver being controlled by the controller; a word line driver, the word line driver being controlled by the controller; a digit line driver, the digit line driver being controlled by the controller; and a three-dimensional node array, the array being configured on a semiconductor substrate, the nodes in the array having: a selector transistor; and a memory cell, the memory cell having: a first conductive material layer, the first conductive material layer being configured as a first electrode terminal of the memory cell, the first electrode terminal being connected to the selector transistor; a second conductive material layer , the second conductive material layer is configured as the second electrode terminal of the memory cell; and a chalcogenide alloy layer, the layer being sandwiched between the first electrode terminal and the second electrode terminal; and a digit line, the digit line being connected to one of the digit line drivers; a thin film transistor, the thin film transistor having a source-drain channel and a gate; wherein the gate of the selector transistor is connected to one of the bit line drivers; wherein the second electrode terminal of the memory cell is connected to the digit line through the source-drain channel of the thin film transistor; and wherein the gate of the thin film transistor is connected to one of the word line drivers.

[0012] In another aspect, the present disclosure provides a method comprising: configuring memory cells in a three-dimensional node array, each corresponding node in the array comprising: a selector transistor; and a memory cell having a chalcogenide alloy layer sandwiched between a first electrode terminal and a second electrode terminal of the memory cell; connecting the gate of the selector transistor to a bit line; connecting the first electrode terminal to ground through a source-drain channel of the selector transistor; connecting the gate of a thin film transistor coupled between the second electrode terminal and a digital line to a word line; connecting the bit line to a bit line driver, the bit line driver being controlled by a controller; connecting the word line to a word line driver, the word line driver being controlled by the controller; and connecting the digital line to a digital line driver, the digital line driver being controlled by the controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Embodiments are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which like references indicate similar elements.

[0014] Figure 1 A three-dimensional structure of a memory according to one embodiment is shown.

[0015] Figure 2 A node containing memory cells in a memory array is shown according to one embodiment.

[0016] Figure 3A 、 3B , 4 and 5 show examples of memory cells configured in a node according to some embodiments.

[0017] Figure 6 The structure of two adjacent node stacks located in a vertical plane is shown according to one embodiment.

[0018] Figure 7 A circuit representation of two adjacent node stacks arranged in a three-dimensional array is shown according to one embodiment.

[0019] Figure 8 A memory device configured with a controller and voltage drivers to program and read memory cells in a three-dimensional array is shown according to one embodiment.

[0020] Figure 9 Shown are bit line drivers and word line drivers connected to select memory cells arranged in a three-dimensional array according to one embodiment.

[0021] Figure 10 An example computing system with memory cells arranged in a three-dimensional array is shown according to one embodiment.

[0022] Figure 11 A method for accessing memory cells in a three-dimensional array according to one embodiment is shown. DETAILED DESCRIPTION

[0023] At least one embodiment disclosed herein provides a high-density memory cell array implemented using a chalcogenide alloy, such as a ternary indium-arsenic-selenide material or a ternary indium-arsenic-tellurium material. For example, the memory cells can be configured in a three-dimensional node array. Each node in the array is configured to have a transistor and a memory cell, wherein the memory cell has a chalcogenide alloy sandwiched between a top electrode terminal (e.g., a first electrode terminal) and a bottom electrode terminal (e.g., a second electrode terminal). The drain of the transistor can be connected to the bottom electrode terminal of the memory cell. A set of horizontal conductive plates is configured in the array to connect bit line signals to the gates of the transistors configured in the three-dimensional node array. Two sets of vertical conductive pillars are configured in the array. One set of vertical conductive pillars is connected to the sources of the transistors configured in the three-dimensional node array; and the other set of vertical conductive pillars is connected to the top electrode terminals of the memory cells configured in the three-dimensional node array. Thus, each node is connected between two vertical pillars, one vertical pillar in each of the two sets, as discussed further below.

[0024] Figure 1 A three-dimensional structure of a memory according to one embodiment is shown.

[0025] exist Figure 1 , horizontal nodes (eg, 101, 102 in one layer; 103, 104 in another layer) are stacked in a vertical direction (eg, along the Z-axis).

[0026] Each node (eg, 101, 102, 103, or 104) in the three-dimensional array contains a transistor and a memory cell (eg, Figures 2 to 5 ). The gate of the transistor in the node (e.g., 101, 102, 103, or 104) is connected to a conductive plate (e.g., 111, 112, 113, or 114) configured to extend in a first horizontal direction (e.g., along the X-axis).

[0027] The conductive plate (e.g., 111, 112, 113, or 114) is configured to carry a voltage that controls the selection of a row of nodes, wherein the gates of transistors in the nodes of the row are connected to the same conductive plate (e.g., 111, 112, 113, or 114). The nodes of the row are arranged in a horizontal layer in the same direction as the conductive plate (e.g., 111, 112, 113, or 114) (e.g., in the same direction as the conductive plate (e.g., 111, 112, 113, or 114) Figure 1 Extending in the first horizontal direction of the X-axis.

[0028] Figure 1 Two adjacent node stacks extending in a second horizontal direction (e.g., along the Y-axis) in a vertical slice of a three-dimensional array are shown. Each node stack (e.g., 101, 103 in one stack; or 102, 104 in another stack) is configured between and connected to two vertical conductive pillars (e.g., 121 and 123 for one stack; or 123 and 125 for the other stack). Two adjacent stacks can share a common vertical conductive pillar (e.g., 123).

[0029] like Figure 1 The illustrated structure of two stacked nodes (e.g., 101, 103 in one stack and 102, 104 in the other stack) can be repeated in a second horizontal direction (e.g., along the Y-axis) to form a vertical slice of nodes extending in the second horizontal direction (e.g., along the Y-axis). This structure of vertical slices of nodes can be further repeated in the first horizontal direction to provide multiple vertical slices of nodes in a three-dimensional array.

[0030] exist Figure 1Node stacks extending in a second horizontal direction (e.g., along the Y-axis) in a vertical slice may be numbered consecutively for ease of reference. Odd-numbered stacks (e.g., having odd-numbered nodes 101, 103) and even-numbered stacks (e.g., having even-numbered nodes 102, 104) are connected to a common vertical column 123 disposed between the two stacks and thus share the common vertical column.

[0031] The drain of the transistor in the odd-numbered node (eg, 101) is connected to the bottom electrode terminal of the memory cell in the odd-numbered node (eg, 101) (eg, Figure 3A and Figure 3B As shown). The source of the transistor in the odd-numbered node (e.g., 101) is connected to a pillar 121 called an S pillar because the S pillar is closer to the source of the transistor than to the drain of the transistor. The top electrode terminal of the memory cell in the odd-numbered node (e.g., 101) is connected to a pillar 123 called a D pillar (e.g., Figure 3A and Figure 3B ) connection because the D-pillar is closer to the drain of the transistor than to the source of the transistor.

[0032] Similarly, the drain of the transistor in the even-numbered node (e.g., 102) is connected to the bottom electrode terminal of the memory cell in the even-numbered node (e.g., 102). The source of the transistor in the even-numbered node (e.g., 102) is connected to the S-pillar 125. The top electrode terminal of the memory cell in the even-numbered node (e.g., 102) is connected to the D-pillar 123.

[0033] When an additional odd-numbered stack is added to the right side of an even-numbered stack (e.g., even nodes 102, 104), the additional odd-numbered stack and the even-numbered stack (e.g., even nodes 102, 104) can be connected to a common S-pillar 125 configured between the two stacks and thereby share the common S-pillar.

[0034] Similarly, when an additional even-numbered stack is added to the left side of an odd-numbered stack (e.g., odd nodes 101, 103), the additional even-numbered stack and the odd-numbered stack (e.g., odd nodes 101, 103) can be connected to a common S-pillar 121 configured between the two stacks and thereby share the common S-pillar.

[0035] In some embodiments, the S pillars (e.g., 121, 125) are connected to ground (or biased to another voltage); and the D pillars (e.g., 123) arranged in the vertical slice are connected to a group of thin film transistors (TFTs) controlled by word lines to implement word line selection (e.g., as shown in FIG. Figure 6 shown).

[0036] For example, thin film transistors (TFTs) (e.g. Figure 6 The drain (or source) of the thin film transistor (TFT) can be connected to the D column (e.g., 151) in the vertical slice; the source (or drain) of the thin film transistor (TFT) can be connected to the digital line for detecting the current passing through the D column (e.g., 123); and the gate of the thin film transistor (TFT) is connected to the word line extending horizontally parallel to the vertical slice of the node.

[0037] The horizontal plates (eg, 111 , 112 , 113 , 114 ) may be connected to bit lines to enable bit line selection.

[0038] Thus, each memory cell in the three-dimensional array of nodes (eg, 101, 102, 103, or 104) can be selectively addressed by activating the bit lines and word lines.

[0039] For example, when a voltage applied to the bit line is sufficient to turn on a transistor connected to a horizontal plate (e.g., 111) connected to the bit line, and when a voltage applied to the word line 127 is sufficient to turn on a thin-film transistor (e.g., 151) connected to the word line 127, activating the thin-film transistor (e.g., 151) in the vertical slice connected to the word line 127 and activating the transistor in the node (e.g., 101) of the row connected to the horizontal plate (e.g., 111) connects the row and the node 101 in the vertical slice between a voltage applied to the S-pillar 121 (e.g., ground) and a voltage applied to the digit line 129. The voltage difference between the digit line 129 and the S-pillar 121 can be configured to program a memory cell in the node 101 to a state representative of data stored in the memory cell and / or to check the state of the memory and thereby retrieve data from the memory cell.

[0040] When the voltage on the horizontal plate (eg, 113) is insufficient to turn on the transistor connected to the plate (eg, 113), the transistor connected to the plate (eg, 113) isolates the row of memory cells from their S-pillars (eg, 121).

[0041] Similarly, when the voltage on word line 127 is insufficient to turn on the thin film transistor (e.g., 151) connected to word line 127, the thin film transistor (e.g., 151) isolates the D column (e.g., 123) from the digital line (e.g., 129) and thereby isolates the memory cells connected thereto in the vertical slice (e.g., in nodes 101, 103; 102, 104) from the digital line (e.g., 129).

[0042] Thus, selectively applying voltages to word lines and bit lines can selectively address memory cells in a three-dimensional array of nodes (eg, 101, 103; 102, 104) for read and write operations.

[0043] Each node (e.g., 101, 102, 103, or 104) in the three-dimensional array can be represented as follows: Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 4 and / or Figure 5 The method shown in FIG.

[0044] Figure 2 1 shows a node containing memory cells in a memory array according to one embodiment. For example, Figure 1 The representative nodes 101 and 102 in the three-dimensional array can be Figure 2 The method shown in FIG.

[0045] exist Figure 2 In FIG. 1 , the odd-numbered node 101 has a memory cell 141 and a selector transistor 131 that connects the S column 121 to the D column 123 via the memory cell 141 (eg, in FIG. 1 ). Figure 1 For example, when odd plates 111 have a voltage that turns off selector transistor 131, the source-drain channel of selector transistor 131 is closed to prevent memory cell 141 from experiencing the voltage difference driven between S pillar 121 and D pillar 123.

[0046] When the odd plate 111 has a voltage that turns on the selector transistor 131, the source-drain channel of the selector transistor 131 is opened, so that the voltage difference driven between the S pillar 121 and the D pillar 123 is applied to the memory cell 141. If the applied voltage difference is higher than the threshold voltage of the memory cell 141, a current greater than a predetermined threshold value can flow between the S pillar 121 and the D pillar 123 through the odd node 101. If the applied voltage difference is lower than the threshold voltage of the memory cell 141, a small amount of leakage can flow between the S pillar 121 and the D pillar 123 through the odd node 101. Thus, by sensing the magnitude of the current passing through the D pillar 123, the state of the threshold voltage of the memory cell 141 can be checked to determine whether data is programmed into the memory cell 141 in a read operation for retrieval of the data.

[0047] Similarly, the even-numbered node 102 has a memory cell 142 and a selector transistor 132 that connects the S column 125 to the D column 123 through the memory cell 142 (eg, at Figure 1). When the even plates 112 have a voltage that turns off the selector transistor 132, the memory cell 142 does not experience the voltage differential driven between the S pillar 125 and the D pillar 123. When the even plates 112 have a voltage that turns on the selector transistor 132, the memory cell 142 experiences a voltage differential driven between the S pillar 125 and the D pillar 123. The voltage differential can be applied to program the memory cell 142 to a certain state and thereby store data represented by the state in the memory cell 142, or to check the state of the memory cell 142 to retrieve the data programmed into the memory cell 142.

[0048] Memory cells 141 and 142 may be selectively addressed by selectively turning selector transistors 131 and 132 on or off using different bit line signals applied to different horizontal plates 111 and 112 .

[0049] Figure 2 The memory cells 141 and 142 in may have Figure 3A and Figure 3B The structure of the memory cell 141 is shown in FIG.

[0050] Figure 3A Memory cells configured in a node are shown according to one embodiment.

[0051] exist Figure 3A In the example, odd nodes 101 (e.g., Figure 1 and / or Figure 2 ) has a plurality of material layers stacked in a vertical direction (e.g., along the Z axis) to form a memory cell 141. The selector transistor 131 is configured to have a horizontal source-drain channel extending from the S pillar 121 (e.g., Figure 1 and / or Figure 2 101 ) is connected to the bottom electrode terminal 155 of the memory cell 141. The top electrode terminal 151 is connected to the D-pillar 123. The gate of the selector transistor 131 is connected to and controlled by the odd-numbered plate 111 disposed above the node 101. A chalcogenide alloy 153 is disposed between the top electrode terminal 151 and the bottom electrode terminal 155 to form the memory cell 141.

[0052] In some embodiments, odd-numbered nodes 101 are simplified to have dynamic random access memory (DRAM) cells when an isolation material is deposited between the top electrode terminal 151 and the bottom electrode terminal 155 of the memory cell 141 instead of forming a chalcogenide alloy 153 in the memory cell 141. In some embodiments, odd-numbered nodes 101 are simplified to have ferroelectric random access memory (FeRAM) cells when a ferroelectric material is deposited between the top electrode terminal 151 and the bottom electrode terminal 155 of the memory cell 141 instead of forming a chalcogenide alloy 153 in the memory cell 141. Thus, a manufacturing facility can switch between producing three-dimensional chalcogenide memory cells, three-dimensional DRAM cells, and / or three-dimensional FeRAM cells with minimal adjustments in the placement of materials between the top electrode terminal 151 and the bottom electrode terminal 155.

[0053] Figure 3A A configuration is shown in which the source-drain channel of transistor 131 is connected between one electrode terminal 155 of memory cell 141 and S pillar 121, with D pillar 123 connected to the other electrode terminal 151 of memory cell 141. Alternatively, the source-drain channel of transistor 131 may be connected between one electrode terminal 155 of memory cell 141 and D pillar 123, with S pillar 121 connected to the other electrode terminal 151 of memory cell 141.

[0054] Figure 3A An example of an odd node 101 is shown. An even node 102 (e.g., Figure 1 and / or Figure 2 ) can be formed in a similar manner. Figure 3A An example is shown in which the electrode terminals 151 and 155 and the chalcogenide alloy 153 are stacked along the Z axis. For example, the first conductive material layer is configured as the first electrode terminal (e.g., 155) of the memory cell 141, in which case the first electrode terminal (e.g., 155) is connected to the selector transistor 131; the second conductive material layer is configured as the second electrode terminal (e.g., 151) of the memory cell 141, in which case the second electrode terminal (e.g., 151) is connected to the pillar 123; and the chalcogenide alloy 153 layer is sandwiched between the first electrode terminal (e.g., 155) and the second electrode terminal (e.g., 151). In another embodiment, the electrode terminals 151 and 155 and the chalcogenide alloy 153 layer are stacked along the Y axis, as shown in FIG. Figure 3B shown.

[0055] In some embodiments, the chalcogenide alloy 153 of the memory cell 141 is Figure 4The ternary indium-arsenic-selenium material 157 in the embodiment of the present invention is deposited using an atomic layer deposition (ALD) technique or another technique (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD)). Figure 4 An example is shown in which the electrode terminals 151 and 155 and the indium-arsenic-selenium material 157 are stacked along the Z axis. In another embodiment, the layers of the electrode terminals 151 and 155 and the indium-arsenic-selenium material 157 are stacked in the same manner as in FIG. Figure 3B . In some embodiments, the indium-arsenic-selenium material 157 can be replaced with a storage element, a doped compound, a chalcogenide material, or other alloys, including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples of storage elements, a chalcogenide material primarily composed of selenium (Se), arsenic (As), and germanium (Ge) can be referred to as a SAG alloy. In some examples of storage elements, a SAG alloy can also include silicon (Si), and such a chalcogenide material can be referred to as a SiSAG alloy. In some examples of storage elements, a SAG alloy can include silicon (Si) or indium (In), or a combination thereof, and such a chalcogenide material can be referred to as a SiSAG alloy or an InSAG alloy, respectively, or a combination thereof. In some examples of storage elements, a chalcogenide alloy can include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0056] In some embodiments, the chalcogenide alloy 153 of the memory cell 141 is a ternary indium-arsenic-tellurium material 159, such as Figure 5 As shown, the layer is deposited using an atomic layer deposition (ALD) technique or another technique (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD)). Figure 5 An example is shown in which the electrode terminals 151 and 155 and the indium-arsenic-tellurium material 159 are stacked along the Z axis. In another embodiment, the layers of the electrode terminals 151 and 155 and the indium-arsenic-tellurium material 159 are stacked in the same manner as in FIG. Figure 3B. In some embodiments, the indium-arsenic-tellurium material 159 can be replaced with a storage element, a doped compound, a chalcogenide material, or other alloys, including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples of storage elements, a chalcogenide material primarily composed of selenium (Se), arsenic (As), and germanium (Ge) can be referred to as a SAG alloy. In some examples of storage elements, a SAG alloy can also include silicon (Si), and such a chalcogenide material can be referred to as a SiSAG alloy. In some examples of storage elements, a SAG alloy can include silicon (Si) or indium (In), or a combination thereof, and such a chalcogenide material can be referred to as a SiSAG alloy or an InSAG alloy, respectively, or a combination thereof. In some examples of storage elements, a chalcogenide alloy can include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0057] When the chalcogenide alloy is deposited using atomic layer deposition (ALD) or physical vapor deposition (PVD) (to be positioned between terminals 151 and 155), memory cell 141 can have a polarity-induced threshold window. This memory cell 141 can be programmed with a low programming current (e.g., less than 50 mA, such as approximately 40 mA) and can have good endurance (e.g., enduring more than 10,000 programming cycles). This memory cell 141 can be programmed to have different threshold voltages for voltages applied to the memory cell 141 with different polarities. When selenium in the chalcogenide alloy 153 is replaced with tellurium, the alloy band gap can be further reduced, which reduces both the set threshold voltage and the reset threshold voltage. The set threshold voltage is the threshold voltage of the memory cell 141 that is programmed to indicate a set state (e.g., a bit value of one stored in the memory cell 141), and the reset threshold voltage is the threshold voltage of the memory cell 141 that is programmed to indicate a reset state (e.g., a bit value of zero stored in the memory cell 141). For example, the difference between the set threshold voltage and the reset threshold voltage may be referred to as a threshold window.

[0058] Figure 6 The structure of two adjacent node stacks located in a vertical plane is shown according to one embodiment.

[0059] exist Figure 6In the example, odd-numbered stacks of odd-numbered nodes (e.g., 101, 103) are arranged in a vertical direction (e.g., along the Z axis); and even-numbered stacks of even-numbered nodes (e.g., 102, 104) are arranged next to odd-numbered stacks. For example, the three-dimensional structure of nodes (e.g., 101, 103; 102, 104) can be arranged in a manner similar to Figure 1 Configure in a similar manner as shown in .

[0060] Adjacent node layers (eg, 101 and 103 ) stacked in a vertical direction (eg, along the Z-axis) may be separated by a dielectric region layer disposed on a substrate of the semiconductor device.

[0061] Each node in the stack (e.g., 101, 102, 103, or 104) can be connected to Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 4 and / or Figure 5 1 is configured with a selector transistor (eg, 131 ) and a memory cell (eg, 141 ) in a manner similar to that shown in .

[0062] exist Figure 6 In the embodiment, D pillar 123 is connected to digit line 129 through thin film transistor 151, which is formed through word line 127. Conductive word line 127 surrounds thin film transistor 151 to control the gate of thin film transistor 151. The source-drain channel of thin film transistor 151 connects or disconnects the D pillar from digit line 129 based on the voltage applied to word line 127.

[0063] For example, when a voltage applied to word line 127 turns on thin film transistor 151, the source-drain channel of thin film transistor 151 connects D column 123 to digit line 129. When a voltage applied to word line 127 turns off thin film transistor 151, the source-drain channel of thin film transistor 151 disconnects D column 123 from digit line 129.

[0064] Thus, word line 127 and a group of thin film transistors (eg, 151 ) arranged thereon can selectively connect a group of digit lines (eg, 129 ) to D-pillars (eg, 123 ) arranged in a vertical slice of a three-dimensional node array.

[0065] The digit line 129 may extend in the X-axis (perpendicular to the Y-axis and the Z-axis). A row of D pillars (eg, 123 ) arranged in parallel with the digit line 129 in a vertical plane may be connected to the same digit line 129 .

[0066] The S-pillars (e.g., 121, 125) are connected to ground (or biased at another voltage). The digit line (e.g., 129) can be connected to a voltage driver and a current sensor to drive the voltage on the D-pillar (e.g., 123) and sense the magnitude of the current passing through the D-pillar (e.g., 123) to the digit line (e.g., 129).

[0067] For example, a voltage driver connected to digital line 129 can be instructed to drive a voltage higher than ground (or the bias voltage of S pillars 121, 125) to apply a voltage at a positive polarity; and a voltage driver connected to digital line 129 can be instructed to drive a voltage lower than ground (or the bias voltage of S pillars 121, 125) to apply a voltage at a negative polarity.

[0068] With chalcogenide alloy 153 (for example, Figure 4 Indium-arsenic-selenium 157 or Figure 5 A memory cell (e.g., 141 or 142) having an indium-arsenic-tellurium 159 (IATF 159) in a first polarity (e.g., positive polarity) can have different threshold voltages of different magnitudes at different polarities. Making the threshold voltage at a first polarity (e.g., positive polarity) greater than the threshold voltage at a second polarity (e.g., negative polarity) can be used to indicate that the memory cell (e.g., 141 or 142) is in a set state (e.g., to store a bit value of one); and making the threshold voltage at the first polarity (e.g., positive polarity) less than the threshold voltage at the second polarity (e.g., negative polarity) can be used to indicate that the memory cell (e.g., 141 or 142) is in a reset state (e.g., to store a bit value of zero). For example, during a write operation, applying a voltage at a first polarity can cause the cell to have a first threshold voltage (e.g., a set threshold voltage); and applying a voltage at a second polarity can cause the cell to have a second threshold voltage (e.g., a reset threshold voltage), which is higher than the first (set) threshold voltage when the threshold voltage of the cell is read at the first polarity after the write pulse. Similarly, during a write operation, applying a voltage at a first polarity may cause the cell to have a first threshold voltage (e.g., a reset threshold voltage); and applying a voltage at a second polarity may cause the cell to have a second threshold voltage (e.g., a set threshold voltage), and when the threshold voltage of the cell is read at the second polarity after the write pulse, the second threshold voltage is lower than the first (reset) threshold voltage.

[0069] Figure 7 A circuit representation of two adjacent node stacks arranged in a three-dimensional array is shown according to one embodiment.

[0070] exist Figure 7 In the stacking of two memory cells (e.g., 141, 143; 142, 144) (e.g., Figure 1 and / or Figure 61 and 125) are connected between the D-pillar 123 and the S-pillars 121 and 125 via selector transistors (e.g., 131, 133; 132, 134). The S-pillar is biased at ground (or another voltage). The D-pillar 123 can be connected to a current sensor and a voltage driver via a thin-film transistor 151. The gate of transistor 151 is controlled by a word line 127.

[0071] When the voltage on word line 127 turns on transistor 151, a voltage driven by the voltage driver is applied to D pillar 123; and the current passing through D pillar 123 can be sensed, measured and / or detected by the current sensor to determine whether the voltage difference between D pillar 123 and S pillars 121 and 125 is higher than a threshold.

[0072] When the voltage on word line 127 turns off transistor 151 , D column 123 is isolated from the current sensor and voltage driver.

[0073] Digital line 129 can be configured as a horizontal plate extending in the same direction (e.g., along the X-axis) as the odd-numbered plates (e.g., 111, 113) and the even-numbered plates (e.g., 112, 114). The D-pillars (e.g., 123) arranged above digit line 129 can each be connected to the same digit line 129 via a corresponding thin-film transistor (e.g., 151) controlled by a corresponding word line (e.g., 127). Thus, a row of D-pillars (e.g., 123) connected to digit line 129 can share the same current sensor and the same voltage driver.

[0074] Odd plates (e.g., 111, 113) and even plates (e.g., 112, 114) can be connected to separate bit lines. A memory cell (e.g., 141) in the array can be addressed by activating a bit line (e.g., connected to odd plate 111) and a word line (e.g., 127) to program the memory cell to store data and to determine the state of the memory cell (e.g., 141) to retrieve data stored in the memory cell (e.g., 141).

[0075] Figure 8 A memory device 230 is shown configured with a controller 231 and voltage drivers (eg, 237 , 235 ) to program and read memory cells in a three-dimensional array, according to one embodiment.

[0076] For example, Figure 8 The memory cell array 233 in the embodiment may be arranged in Figure 1 and a representative memory cell 201 in the memory cell array 233 may have Figure 3A 、 Figure 3B 、 Figure 4 or Figure 5The structure of the memory cell 141 in the node 101 in FIG.

[0077] Figure 8 The memory device 230 includes a controller 231 that operates a bit line driver 237 and a word line driver 235 to address individual memory cells (e.g., 201) in the array 233 for access, such as programming the addressed / selected memory cells to store data in a write operation, and checking the state of the addressed / selected memory cells to determine the data programmed into the memory cells in a read operation.

[0078] Memory device 230 includes a digit line driver and a current sensor 239. When addressing memory cell 201 for a write operation, the digit line driver may apply one or more voltage pulses to program memory cell 201 with a state representative of the data to be written into memory cell 201.

[0079] When addressing a memory cell 201 for a read operation, the digit line driver may apply one or more voltages to check the state of the memory cell 201. The controller 231 uses a current sensor to determine whether the addressed memory cell 201 is in a conductive state or a non-conductive state based on the magnitude / level of the current passing through the memory cell 201.

[0080] For example, each memory cell (eg, 201) in array 233 can be selected / addressed for access by a voltage driven by a pair of bit line drivers 247 and word line drivers 245, as shown in FIG. Figure 9 shown.

[0081] Figure 9 2 shows a bit line driver 247 and a word line driver 245, which are connected to select the memory cell 201 configured in a three-dimensional array according to one embodiment. Figure 1 Memory cells in a three-dimensional node array are shown in FIG.

[0082] exist Figure 9 In FIG. 2 , the bit line driver 247, the word line driver 245, the current sensor 259 and the digit line driver 249 are controlled by the controller 231. Figure 8 The controller 231 of the memory device 230 of FIG. The current sensor 259 can be used to determine the magnitude of the current in the digit line 255 driven by the digit line driver 249 .

[0083] The memory cells 201 may be arranged in a three-dimensional array (eg, Figure 1The node also includes a selector transistor 251 for selecting the memory cell 201 by a bit line voltage driven on line 241 by a bit line driver 247. For example, line 241 can be connected to a horizontal plate (e.g., 111, 112, 113, or 114) configured above the node in a three-dimensional array (e.g., Figure 1 (as shown) connections.

[0084] The source-drain channel of selector transistor 251 is connected between a reference voltage (eg, ground or another voltage) and one terminal of memory cell 201. The gate of selector transistor 251 is connected to line 241 to receive a bitline voltage driven by bitline driver 247.

[0085] Another terminal of the memory cell 201 is connected to a common line 243 (eg, Figure 1 A bit line voltage driven by a bit line driver 247 is connected to control selection / deselection of the memory cell 201 among the group of memory cells sharing the line 243.

[0086] The line 243 common to the memory cells of the group (eg, 201) is driven by a word line driver 245 (eg, Figure 6 and Figure 7 The source-drain channel of transistor 253, which is controlled by a word line 127 shown in FIG. 2 , is connected to digit line 255. A word line voltage from word line driver 245 selectively turns transistor 253 on or off.

[0087] When word line driver 245 and bit line driver 247 turn on transistors 253 and 251, respectively, memory cell 201 is connected between a reference voltage (e.g., ground or another voltage) and a voltage driven on digit line 255 by digit line driver 249. Memory cell 201 is thereby selected / addressed for read / write access.

[0088] When word line driver 245 turns off transistor 253 or bit line driver 247 turns off transistor 251 (or both), respectively, memory cell 201 is disconnected from the voltage difference between a reference voltage (e.g., ground or another voltage) and the voltage driven on digit line 255 by digit line driver 249. Thus, memory cell 201 is deselected or not addressed for read / write access.

[0089] For example, when the memory cell 201 is selected / addressed, the digit line driver 249 may apply a voltage higher than a reference voltage (e.g., ground or another voltage) to apply a voltage difference of positive polarity to the memory cell 201. The memory cell 201 may have a threshold voltage in the positive polarity. When the voltage difference of positive polarity applied to the memory cell 201 is less than the threshold voltage in the positive polarity, the memory cell 201 is substantially non-conductive (e.g., a current passing through the memory cell 201 is less than the threshold voltage). When the voltage difference of positive polarity applied to the memory cell 201 is greater than the threshold voltage in the positive polarity, the memory cell 201 is substantially conductive (e.g., a current passing through the memory cell 201 is greater than the threshold voltage in the positive polarity).

[0090] For example, when the memory cell 201 is selected / addressed, the digit line driver 249 may apply a voltage lower than a reference voltage (e.g., ground or another voltage) to apply a voltage difference of negative polarity to the memory cell 201. The memory cell 201 may have a threshold voltage at negative polarity. When the voltage difference of negative polarity applied to the memory cell 201 is less than the threshold voltage at negative polarity, the memory cell 201 is substantially non-conductive (e.g., a current passing through the memory cell 201 is less than the threshold voltage). When the voltage difference of negative polarity applied to the memory cell 201 is greater than the threshold voltage at negative polarity, the memory cell 201 is substantially conductive (e.g., a current passing through the memory cell 201 is greater than the threshold voltage at negative polarity).

[0091] The difference between the threshold voltage after a programming pulse at negative polarity and the threshold voltage after a programming pulse at positive polarity represents the polarity-induced threshold window of the memory cell 201. A large polarity-induced threshold window allows the state of the memory cell 201 to be detected reliably.

[0092] During a write operation, the controller 231 can instruct the digit line driver 249 to apply one or more voltage pulses to change the threshold voltage of the memory cell 201. For example, the memory cell 201 can be programmed so that the threshold voltage in negative polarity is less than the threshold voltage in positive polarity to represent one state (e.g., representing a bit value of one stored in the memory cell 201); and the memory cell 201 can be programmed so that the threshold voltage in negative polarity is greater than the threshold voltage in positive polarity to represent another state (e.g., representing a bit value of zero stored in the memory cell 201). The threshold window allows the memory cell to be read using a variety of techniques; and thus, it is not necessary to read the memory cell in both polarities to determine the state of the memory cell and, therefore, the data stored in the memory cell.

[0093] The bit line voltage driven by the bit line driver 247 can be connected to the selector transistors (e.g., 251, 257) of a row of memory cells (e.g., 201, 202). The memory cells (e.g., 201, 202) of the row can be arranged in different vertical slices of the three-dimensional node array and connected to a common horizontal plate (e.g., 111). Different memory cells (e.g., 201, 202) are connected to different D-pillars (e.g., 123), which are controlled by different word lines (e.g., 127) running in the corresponding vertical slices. The selection / addressing of the memory cells (e.g., 201, 202) in the row is controlled by different word lines. Since the memory cells in a row (e.g., 201, 202) are selected / addressed one at a time, the D columns connected to the memory cells in the row (e.g., 201, 202) can be connected to the same digital line 255 driven by the same digital line driver 249 through separate transistors (e.g., 253) controlled by separate word line drivers (e.g., 245).

[0094] Figure 10 FIG. 1 shows a configuration of a plurality of layers in a three-dimensional array (eg, Figure 1 An example computing system with memory cells in a node array (shown in FIG).

[0095] Figure 10 The example computing system includes a host system 310 and a memory subsystem 301. A group of memory cells (e.g., configured in conjunction with Figures 1 to 9 3D array nodes discussed above).

[0096] For example, memory cells 327 in memory device 323 may be configured in Figure 1 and Figure 6 In the three-dimensional node array in Figures 2 to 5 The local media controller 325 can be like Figure 8 and Figure 9 The voltage driver 333 is used as in the controller 231 to apply the bit line voltage, the word line voltage and the digit line voltage.

[0097] Memory subsystem 301 may include media such as one or more volatile memory devices (eg, memory device 321 ), one or more non-volatile memory devices (eg, memory device 323 ), or a combination of such memory devices.

[0098] The memory subsystem 301 can be a storage device, a memory module, or a mixture of a storage device and a memory module. Typically, examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0099] The computing system can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or networked business device), or such a computing device that includes memory and processing devices.

[0100] The computing system may include a host system 310 coupled to one or more memory subsystems 301 . Figure 10 An example of a host system 310 coupled to a memory subsystem 301 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0101] The host system 310 may include a processor chipset (e.g., processing device 311) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 313) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 310 uses the memory subsystem 301, for example, to write data to the memory subsystem 301 and read data from the memory subsystem 301.

[0102] The host system 310 can be coupled to the memory subsystem 301 via a physical host interface 309. Examples of the physical host interface 309 include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Serial Attached SCSI (SAS) interface, a Double Data Rate (DDR) memory bus interface, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), a Double Data Rate (DDR) interface, a Low Power Double Data Rate (LPDDR) interface, or any other interface. The physical host interface 309 can be used to transfer data between the host system 310 and the memory subsystem 301. When the memory subsystem 301 is coupled to the host system 310 via the PCIe interface, the host system 310 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 323). The physical host interface 309 may provide an interface for passing control, address, data, and other signals between the memory subsystem 301 and the host system 310 . Figure 10 Memory subsystem 301 is shown as an example. Generally, host system 310 can access multiple memory subsystems through the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0103] The processing device 311 of the host system 310 can be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some examples, the controller 313 can be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 313 controls communications via a bus coupled between the host system 310 and the memory subsystem 301. Generally, the controller 313 can send commands or requests to the memory subsystem 301 to obtain desired access to the memory devices 323, 321. The controller 313 can further include interface circuitry for communicating with the memory subsystem 301. The interface circuitry can convert responses received from the memory subsystem 301 into information for the host system 310.

[0104] The controller 313 of the host system 310 can communicate with the controller 303 of the memory subsystem 301 to perform operations such as reading data, writing data, or erasing data at the memory devices 323 and 321, as well as other such operations. In some cases, the controller 313 is integrated into the same package as the processing device 311. In other cases, the controller 313 is separate from the package of the processing device 311. The controller 313 and / or the processing device 311 can include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 313 and / or the processing device 311 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0105] The memory devices 323, 321 may include any combination of different types of non-volatile memory components and / or volatile memory components. Volatile memory devices (e.g., memory device 321) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0106] Some examples of non-volatile memory components include negative-and (or NOT AND) (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0107] Each memory device in the memory device 323 may include one or more memory cell arrays. One type of memory cell (e.g., single-level cell (SLC)) may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), and quintuple-level cell (PLC) may store multiple bits per cell. In some embodiments, each memory device in the memory device 323 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination of such memory cells. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of a memory cell. The memory cells of the memory device 323 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. With some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0108] Although non-volatile memory devices such as 3D cross-point and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, the memory device 323 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0109] The memory subsystem controller 303 (or, for simplicity, the controller 303) can communicate with the memory device 323 to perform operations such as reading data, writing data, or erasing data, as well as other such operations, at the memory device 323 (e.g., in response to commands dispatched by the controller 313 on a command bus). The controller 303 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller 303 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0110] The controller 303 may include a processing device 307 (processor) configured to execute instructions stored in the local memory 305. In the example shown, the local memory 305 of the controller 303 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 301, including handling communications between the memory subsystem 301 and the host system 310.

[0111] In some embodiments, local memory 305 may include memory registers that store memory pointers, retrieved data, etc. Local memory 305 may also include read-only memory (ROM) for storing microcode. Figure 10 The example memory subsystem 301 in FIG. 3 is shown as including a controller 303, but in another embodiment of the present disclosure, the memory subsystem 301 does not include a controller 303 and may instead rely on external control (e.g., provided by an external host or a processor or controller separate from the memory subsystem).

[0112] Typically, the controller 303 can receive commands or operations from the host system 310 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 323. The controller 303 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 323. The controller 303 can further include a host interface circuit system for communicating with the host system 310 via a physical host interface. The host interface circuit system can convert commands received from the host system into command instructions for accessing the memory device 323 and can convert responses associated with the memory device 323 into information for the host system 310.

[0113] The memory subsystem 301 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 301 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the controller 303 and decode the addresses to access the memory device 323.

[0114] In some embodiments, the memory device 323 includes a local media controller 325 that operates in conjunction with the memory subsystem controller 303 to perform operations on one or more memory cells of the memory device 323. An external controller (e.g., the memory subsystem controller 303) can externally manage the memory device 323 (e.g., perform media management operations on the memory device 323). In some embodiments, the memory device 323 is a managed memory device, which is a raw memory device that is combined with a local controller (e.g., the local media controller 325) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0115] Figure 11 A method for accessing a three-dimensional array (such as the one described above) according to one embodiment is shown. Figures 1 to 10 Method for memory cells in the array discussed).

[0116] At block 401, Figure 11 The method includes configuring memory cells in a three-dimensional node array (e.g., 101, 103; 102, 104) of a memory device 230. Each corresponding node (e.g., 101 or 102) in the array includes: a selector transistor (e.g., 131 or 132); and a memory cell (e.g., 141 or 142) having a chalcogenide alloy (e.g., 153) layer sandwiched between a first electrode terminal (e.g., 155) and a second electrode terminal (e.g., 151) of the memory cell (e.g., 141).

[0117] For example, a node may have a structure such that when the chalcogenide alloy 153 is replaced with an isolation material, the corresponding node becomes a dynamic random access memory cell. For example, a node may have a structure such that when the chalcogenide alloy 153 is replaced with a ferroelectric material, the corresponding node becomes a ferroelectric random access memory (FeRAM) cell. Thus, a manufacturing facility can advantageously be configured to easily switch between producing memory chips having non-volatile memory cells that can be programmed to have a polarity-induced threshold window, producing memory chips having volatile dynamic random access memory cells, and / or producing memory chips having ferroelectric random access memory cells.

[0118] For example, the method may include using atomic layer deposition techniques to deposit a chalcogenide alloy 153 including a ternary indium-arsenic-selenium material 157 or a ternary indium-arsenic-tellurium material 159. In some embodiments, the chalcogenide alloy 153 may be replaced with a doped ternary compound (e.g., the primary three species of silicon (Si) doped from selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and indium (In)).

[0119] At block 403 , the method includes connecting the gate of a selector transistor (eg, 131 ) to a bit line (eg, through a horizontal plate 111 disposed above node 101 ).

[0120] At block 405 , the method includes connecting a first electrode terminal (eg, 155 ) to ground (eg, through a vertical pillar 121 proximate to the node 101 ) through a source-drain channel of a selector transistor (eg, 131 ).

[0121] At box 407, the method includes connecting the gate of the thin film transistor (e.g., 151) to the word line (e.g., 127), wherein the thin film transistor (e.g., 151) is electrically coupled between the second electrode terminal (e.g., 151) and the digit line (e.g., 129) (e.g., through the vertical column 123).

[0122] At block 409 , the method includes connecting the bit lines to a bit line driver 247 controlled by a controller 231 of the memory device 230 .

[0123] At block 411 , the method includes connecting a word line to a word line driver 245 controlled by a controller 231 .

[0124] At block 413 , the method includes connecting the digit line 129 to a digit line driver 249 controlled by the controller 231 .

[0125] For example, the method may further include: selecting a memory cell (e.g., 141 or 201) through a controller 231, wherein the controller controls a bit line driver 247 to drive a voltage for turning on a selector transistor (e.g., 131), and controls a word line driver 245 to drive a voltage for turning on a thin film transistor (e.g., 253 or 151).

[0126] After selecting / addressing a memory cell (e.g., 141 or 201) using the bit line driver 247 and the word line driver 245, the method may further include programming the memory cell (e.g., 141 or 201) to have a polarity-induced threshold window by controlling the digital line driver 249 to allow a current of less than 50 μA to flow through the memory cell (e.g., 141 or 201).

[0127] In one embodiment, an example machine of a computer system is shown within which an instruction set for causing the machine to perform any one or more of the methods discussed herein may be executed. In some embodiments, the computer system may correspond to a host system that includes, is coupled to, or utilizes a memory subsystem or may be used to perform the operations described herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet, or a combination thereof. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0128] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge, a network-attached storage facility, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by the machine. In addition, while a single machine is shown, the term "machine" should also be taken to include any collection of machines that individually or jointly execute an instruction set (or multiple instruction sets) to perform any one or more of the methodologies discussed herein.

[0129] An example computer system includes processing devices that communicate with each other via a bus (which may include multiple buses), a main memory (e.g., read-only memory (ROM); flash memory; dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system.

[0130] The processing device represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device is configured to execute instructions for performing the operations and steps discussed herein. The computer system may further include a network interface device for communicating over a network.

[0131] The data storage system may include a machine-readable medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions or software that embodies any one or more of the methods or functions described herein. During execution of the instructions by the computer system, the instructions may also reside completely or at least partially in the main memory and / or the processing device, with the main memory and the processing device also constituting the machine-readable storage medium. The machine-readable medium, data storage system, or main memory may correspond to a memory subsystem.

[0132] In one embodiment, the instructions include instructions for implementing functions corresponding to the operations described above. Although the machine-readable medium shown in the example embodiment is a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more instruction sets. The term "machine-readable storage medium" should also be taken to include any medium that can store or encode an instruction set for execution by a machine and causes the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0133] Some portions of the foregoing detailed description have been presented in the form of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are commonly used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. Typically, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common usage reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0134] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the computer system's registers and memories and transforms it into other data represented in a similar manner as physical quantities within the computer system's memories or registers or other such information storage systems.

[0135] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0136] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used together with programs according to the teachings herein, or it can be demonstrated that it is convenient to construct a more specialized device for performing the method. The structure for various of these systems will be as described in the following description to reveal. In addition, the present disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of the present disclosure as described herein.

[0137] The present disclosure may be provided in the form of a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. Machine-readable media includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, machine-readable (e.g., computer-readable) media includes machine (e.g., computer) readable storage media, such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0138] In this specification, various functions and operations are described as being performed by computer instructions or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that the meaning of such expressions is that the functions are generated by one or more controllers or processors such as microprocessors executing computer instructions. Alternatively or in combination, dedicated circuit systems can be used with or without software instructions, such as using application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs) to implement functions and operations. Hard-wired circuit systems can be used to implement embodiments in the absence of software instructions or in combination with software instructions. Therefore, the technology is neither limited to any specific combination of hardware circuit systems and software, nor to any specific source of instructions executed by the data processing system.

[0139] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments. It will be apparent that various modifications may be made to the described embodiments without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. The description and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory device comprising: A three-dimensional node array, the array being configured on a semiconductor substrate, each corresponding node in the array having: selector transistor; as well as A memory cell, the memory cell having: a first conductive material layer, the first conductive material layer being configured as a first electrode terminal of the memory cell, the first electrode terminal being connected to the selector transistor; a second conductive material layer, wherein the second conductive material layer is configured as a second electrode terminal of the memory cell; as well as A chalcogenide alloy layer is interposed between the first electrode terminal and the second electrode terminal.

2. The memory device of claim 1 , wherein the chalcogenide alloy comprises a ternary indium-arsenic-selenium material or a ternary indium-arsenic-tellurium material; and The memory cell can be programmed to have a polarity-induced threshold window by a current less than 50 μA.

3. The memory device of claim 2, wherein the chalcogenide alloy is deposited by atomic layer deposition or physical vapor deposition; and The three-dimensional node array includes: first nodes, the first nodes being stacked in a first direction; and a second node, the second node being stacked in the first direction and arranged next to the first node in a slice of nodes extending along the first direction and the second direction; wherein the memory device includes a conductive pillar extending in the first direction and arranged between the first node and the second node; and Each of the first node and the second node has an electrode terminal, and the electrode terminal is connected to the conductive column.

4. The memory device of claim 3 , wherein the conductive pillar is a first conductive pillar; and the memory device further comprises: a second conductive pillar extending in parallel with the first conductive pillar, wherein each of the first nodes has a source-drain channel, and the source-drain channel connects a memory cell between the first conductive pillar and the second conductive pillar; A plurality of horizontal plates extending in a third direction, wherein each of the horizontal plates is connected to a gate of a selector transistor in one of the first nodes.

5. The memory device of claim 4 , further comprising: a word line, the word line being parallel to the slice and extending in the second direction; a number line extending in the third direction, the third direction being perpendicular to the slice; as well as a thin film transistor, wherein the thin film transistor is formed through the word line, and the thin film transistor has: a gate connected to the word line; a source-drain channel configured to connect the conductive pillar to the digit line; a plurality of bit line drivers, the plurality of bit line drivers being connected to the plurality of horizontal plates respectively; a word line driver connected to the word line; as well as A digit line driver is connected to the digit line.

6. An apparatus comprising: Controller; a bit line driver, the bit line driver being controlled by the controller; a word line driver, the word line driver being controlled by the controller; a digital line driver, the digital line driver being controlled by the controller; A three-dimensional node array, wherein the array is configured on a semiconductor substrate, and the nodes in the array have: selector transistor; as well as A memory cell, the memory cell having: a first conductive material layer, the first conductive material layer being configured as a first electrode terminal of the memory cell, the first electrode terminal being connected to the selector transistor; a second conductive material layer, wherein the second conductive material layer is configured as a second electrode terminal of the memory cell; as well as a chalcogenide alloy layer, the layer being interposed between the first electrode terminal and the second electrode terminal; as well as a digit line connected to one of the digit line drivers; as well as a thin film transistor having a source-drain channel and a gate; wherein a gate of the selector transistor is connected to one of the bit line drivers; wherein the second electrode terminal of the memory cell is connected to the digit line through the source-drain channel of the thin film transistor; and The gate of the thin film transistor is connected to one of the word line drivers.

7. The apparatus of claim 6, wherein the chalcogenide alloy comprises a ternary indium-arsenic-selenium material or a ternary indium-arsenic-tellurium material, the material being deposited by an atomic layer deposition technique; and The memory cell can be programmed to have a polarity-induced threshold window by a current less than 50 μA.

8. A method comprising: The memory cells are arranged in a three-dimensional node array, each corresponding node in the array comprising: a selector transistor; and a memory cell having a chalcogenide alloy layer sandwiched between a first electrode terminal and a second electrode terminal of the memory cell; connecting the gate of the selector transistor to a bit line; connecting the first electrode terminal to ground through the source-drain channel of the selector transistor; connecting a gate of a thin film transistor coupled between the second electrode terminal and the digit line to a word line; connecting the bit line to a bit line driver controlled by a controller; connecting the word line to a word line driver controlled by the controller; The digit line is connected to a digit line driver, which is controlled by the controller.

9. The method according to claim 8, further comprising: The chalcogenide alloy is deposited using an atomic layer deposition technique, and the chalcogenide alloy includes a ternary indium-arsenic-selenium material or a ternary indium-arsenic-tellurium material.

10. The method according to claim 9, further comprising: selecting the memory cell by controlling the bit line driver to drive a voltage for turning on the selector transistor, and controlling the word line driver to drive a voltage for turning on the thin film transistor; and The memory cell is programmed to have a polarity-induced threshold window by controlling the digit line driver to cause a current of less than 50 μA to flow through the memory cell.

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