Vertical field effect transistor stray capacitance acquisition method and test structure
By obtaining the gate and top source and drain parasitic capacitors CGT, gate and bottom source and drain parasitic capacitors CGB of the vertical field effect transistor, the problem of capacitance cannot be accurately extracted in the prior art, and the precise characterization and performance improvement of the vertical field effect transistor is achieved.
Patent Information
- Application Number
- CN202410214502.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-27
- Publication Date
- 2025-08-29
AI Technical Summary
The prior art cannot accurately extract the gate and top source and drain parasitic capacitances of vertical field effect transistors, as well as gate and bottom source and drain parasitic capacitances, resulting in the inability to effectively monitor the manufacturing process and optimize the device structure.
A method and a test structure are provided, through a capacitance measuring device, the sum of the gate and top source and drain parasitic capacitors CGT, the gate and bottom source and drain parasitic capacitors CGB and the gate and channel capacitors CGC are obtained by a capacitance measuring device, and the CGB and CGT are calculated using the contact structure to connect the power supply and the ground structure.
Accurate acquisition of parasitic capacitance of vertical field effect transistors is achieved, and device characterization accuracy is improved, which helps manufacturing process monitoring and device structure optimization, improves working speed and reduces power consumption.
Smart Images
Figure CN120559338A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for obtaining parasitic capacitance of a vertical field effect transistor and a test structure. Background Art
[0002] Vertical-Transport Nanosheet FETs (VTFETs) are seen as promising devices that can overcome the limitations of existing lateral transport field-effect transistors (e.g., planar MOSFETs and FinFETs), and have enormous potential for application at process nodes of 3nm and below. They offer excellent performance in terms of power consumption, area, and subthreshold characteristics.
[0003] The gate-source / drain parasitic capacitance of a VTFET directly affects the system's operating speed and power consumption. Reducing this parasitic capacitance helps improve operating speed and reduce power consumption. Extracting the effective parasitic parameters of each device component and accurately characterizing the device is crucial for monitoring the manufacturing process, optimizing device structure design, and building models.
[0004] Currently, the gate-source / drain capacitance extraction structures for lateral transport field-effect transistors are relatively mature. Due to manufacturing process limitations, their gate-source / drain capacitances can be roughly considered equal, each half the gate-channel capacitance. However, the top and bottom source / drain regions of VTFET devices are asymmetrical, with different capacitances, requiring separate extraction. Existing gate-source / drain capacitance measurement structures and methods for lateral transport field-effect transistors cannot be applied to VTFETs. Currently, no measurement structures or methods exist specifically for VTFET gate-source / drain capacitance extraction.
[0005] Therefore, it is necessary to provide a technical solution that can accurately obtain the gate and top source-drain parasitic capacitance of a vertical field effect transistor and the gate and bottom source-drain parasitic capacitance of a vertical field effect transistor. Summary of the Invention
[0006] The present application provides a method and test structure for obtaining the parasitic capacitance of a vertical field effect transistor, which can accurately obtain the parasitic capacitance C of the gate and top source-drain of the vertical field effect transistor. GT And the gate and bottom source-drain parasitic capacitance C of the vertical field effect transistor GB .
[0007] One aspect of the present application provides a method for obtaining parasitic capacitance of a vertical field effect transistor, comprising: obtaining the parasitic capacitance C of the gate and top source-drain of the vertical field effect transistor GT , gate and bottom source-drain parasitic capacitance C GB and the gate and channel capacitance C GCThe sum of C0; Get the gate and top source-drain parasitic capacitance C of the vertical field effect transistor GT and the gate and channel capacitance C GC The sum of C1, the gate and bottom source-drain parasitic capacitance C of the vertical field effect transistor is obtained. GB and the gate and channel capacitance C GC The sum of C2; Get C according to C0 and C1 GB And obtain C according to C0 and C2 GT .
[0008] In some embodiments of the present application, the method for obtaining the C0 includes: providing the vertical field effect transistor, obtaining the C0 through a capacitance measuring device, the vertical field effect transistor including: a semiconductor substrate, a bottom source and drain formed in the semiconductor substrate, and a fin formed on the surface of the semiconductor substrate and located above the bottom source and drain; an insulating isolation layer, located on the surface of the semiconductor substrate on both sides of the fin; a gate, located on the sidewalls of the fin and the surface of the insulating isolation layer; a top source and drain, located on the top of the fin; an interlayer dielectric layer, covering the semiconductor substrate, the gate and the top source and drain; a first contact structure, a second contact structure and a third contact structure, penetrating the interlayer dielectric layer and electrically connecting the bottom source and drain, the top source and drain and the gate, respectively.
[0009] In some embodiments of the present application, when obtaining C0 by a capacitance measuring device, the first contact structure and the second contact structure are grounded and the third contact structure is connected to an AC power supply, and the measurement value of the capacitance measuring device is C0.
[0010] In some embodiments of the present application, the C1 is obtained through a first measurement structure, which includes: a semiconductor substrate, a fin being formed on the surface of the semiconductor substrate; an insulating isolation layer, located on the surface of the semiconductor substrate on both sides of the fin; a gate, located on the sidewalls of the fin and the surface of the insulating isolation layer; a top source and drain, located on the top of the fin; an interlayer dielectric layer, covering the semiconductor substrate, the gate and the top source and drain; a first contact structure, a second contact structure and a third contact structure, which penetrate the interlayer dielectric layer and are electrically connected to the semiconductor substrate, the top source and drain and the gate, respectively.
[0011] In some embodiments of the present application, the method for obtaining the C1 includes: grounding the first contact structure and the second contact structure and connecting the third contact structure to an AC power supply, and measuring the C1 using a capacitance measuring device.
[0012] In some embodiments of the present application, C2 is obtained through a second measurement structure, which includes: a semiconductor substrate, a bottom source and drain formed in the semiconductor substrate, and a fin formed on the surface of the semiconductor substrate and located above the bottom source and drain; an insulating isolation layer, located on the surface of the semiconductor substrate on both sides of the fin; a gate, located on the sidewalls of the fin and the surface of the insulating isolation layer; a secondary fin, located on the top of the fin; an interlayer dielectric layer, covering the semiconductor substrate, the gate and the fin; a first contact structure, a second contact structure and a third contact structure, which penetrate the interlayer dielectric layer and are electrically connected to the bottom source and drain, the secondary fin and the gate, respectively.
[0013] In some embodiments of the present application, the method for obtaining C2 includes: grounding the first contact structure and the second contact structure and connecting the third contact structure to an AC power supply, and measuring C2 using a capacitance measuring device.
[0014] In some embodiments of the present application, the first measurement structure and the vertical field effect transistor are formed by the same process, and have the same structure except that the first measurement structure does not include a bottom source and drain.
[0015] In some embodiments of the present application, the second measurement structure and the vertical field effect transistor are formed by the same process, and have the same structure as the vertical field effect transistor except that the secondary fins in the second measurement structure replace the top source and drain in the vertical field effect transistor.
[0016] In some embodiments of the present application, C is obtained according to C0 and C1. GB The method is: C GB = C0-C1; Get C according to C0 and C2 GT The method is: C GT =C0-C2.
[0017] Another aspect of the present application also provides a test structure for obtaining the parasitic capacitance of a vertical field effect transistor, comprising: a vertical field effect transistor, comprising: a semiconductor substrate, a bottom source and drain formed in the semiconductor substrate, and a fin formed on the surface of the semiconductor substrate and located above the bottom source and drain; an insulating isolation layer, located on the surface of the semiconductor substrate on both sides of the fin; a gate, located on the sidewalls of the fin and the surface of the insulating isolation layer; a top source and drain, located on the top of the fin; an interlayer dielectric layer, covering the semiconductor substrate, the gate and the top source and drain; a first contact structure, a second contact structure and a third contact structure, penetrating the interlayer dielectric layer and electrically connecting the bottom source and drain, the top source and drain and the gate respectively; a first measurement structure, comprising: a semiconductor substrate, a fin formed on the surface of the semiconductor substrate; an insulating isolation layer, located on the surface of the semiconductor substrate on both sides of the fin; a gate, located on the sidewalls of the fin and the surface of the insulating isolation layer; a top source and drain, located on the top of the fin; The sidewalls of the fin and the surface of the insulating isolation layer; the top source and drain are located on the top of the fin; the interlayer dielectric layer covers the semiconductor substrate, the gate and the top source and drain; the first contact structure, the second contact structure and the third contact structure penetrate the interlayer dielectric layer and are electrically connected to the semiconductor substrate, the top source and drain and the gate respectively; the second measurement structure includes: a semiconductor substrate, a bottom source and drain are formed in the semiconductor substrate, and a fin located above the bottom source and drain is formed on the surface of the semiconductor substrate; the insulating isolation layer is located on the surface of the semiconductor substrate on both sides of the fin; the gate is located on the sidewalls of the fin and the surface of the insulating isolation layer; the auxiliary fin is located on the top of the fin; the interlayer dielectric layer covers the semiconductor substrate, the gate and the fin; the first contact structure, the second contact structure and the third contact structure penetrate the interlayer dielectric layer and are electrically connected to the bottom source and drain, the auxiliary fin and the gate respectively.
[0018] In some embodiments of the present application, the first measurement structure and the vertical field effect transistor are formed by the same process, and have the same structure except that the first measurement structure does not include a bottom source and drain.
[0019] In some embodiments of the present application, the second measurement structure and the vertical field effect transistor are formed by the same process, and have the same structure as the vertical field effect transistor except that the secondary fins in the second measurement structure replace the top source and drain in the vertical field effect transistor.
[0020] The present application provides a method and test structure for obtaining the parasitic capacitance of a vertical field effect transistor, which can accurately obtain the parasitic capacitance C of the gate and top source-drain of the vertical field effect transistor. GT And the gate and bottom source-drain parasitic capacitance C of the vertical field effect transistor GB . BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The following figures describe in detail exemplary embodiments disclosed in this application. Like reference numerals denote similar structures throughout the several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are provided for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0022] in:
[0023] Figure 1 This is a flow chart of a method for obtaining parasitic capacitance of a vertical field effect transistor according to an embodiment of the present application;
[0024] Figure 2 A schematic structural diagram of a vertical field effect transistor in a method for obtaining parasitic capacitance of a vertical field effect transistor according to an embodiment of the present application;
[0025] Figure 3 This is a schematic structural diagram of a first measurement structure in a method for obtaining parasitic capacitance of a vertical field effect transistor according to an embodiment of the present application;
[0026] Figure 4 This is a structural schematic diagram of a second measurement structure in a method for obtaining parasitic capacitance of a vertical field effect transistor according to an embodiment of the present application. DETAILED DESCRIPTION
[0027] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.
[0028] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.
[0029] Figure 1 This is a flow chart of a method for obtaining parasitic capacitance of a vertical field effect transistor according to an embodiment of the present application. The following describes in detail a method for obtaining parasitic capacitance of a vertical field effect transistor according to an embodiment of the present application in conjunction with the accompanying drawings.
[0030] This application provides a method for obtaining the parasitic capacitance of a vertical field effect transistor, referring to Figure 1 Shown, including:
[0031] Step S1: Obtain the gate and top source-drain parasitic capacitance C of the vertical field effect transistor GT , gate and bottom source-drain parasitic capacitance C GB and the gate and channel capacitance C GC The sum of C0;
[0032] Step S2: Obtain the gate and top source-drain parasitic capacitance C of the vertical field effect transistor GT and the gate and channel capacitance C GC The sum of C1;
[0033] Step S3: Obtain the gate and bottom source-drain parasitic capacitance C of the vertical field effect transistor GB and the gate and channel capacitance C GC The sum of C2;
[0034] Step S4: Obtain C according to C0 and C1 GB And obtain C according to C0 and C2 GT .
[0035] In some embodiments of the present application, C is obtained according to C0 and C1. GB The method is: C GB = C0-C1; Get C according to C0 and C2 GT The method is: C GT =C0-C2. Specifically, C0=C GT +C GB +C GC , C1=C GT +C GC , C2=C GB +C GC , C can be obtained based on the measurement results C0, C1, and C2 by simple calculation. GB and C GT .
[0036] The following further details how to obtain C0, C1, and C2 in the technical solution of this application.
[0037] Figure 2 Schematic diagram of the structure of a vertical field effect transistor 100 in a method for obtaining parasitic capacitance of a vertical field effect transistor according to an embodiment of the present application.
[0038] refer to Figure 1 and Figure 2 As shown, step S1, obtaining the parasitic capacitance C of the gate 150 and the top source and drain 160 of the vertical field effect transistor 100 GT , gate 150 and bottom source drain 120 parasitic capacitance C GBand the parasitic capacitance C between the gate 150 and the channel (the fin 130 acts as a channel) GC The vertical field effect transistor 100 includes: a semiconductor substrate 110, in which a bottom source and drain 120 is formed, and a fin 130 is formed on the surface of the semiconductor substrate 110 and located above the bottom source and drain 120; an insulating isolation layer 140, located on the surface of the semiconductor substrate 110 on both sides of the fin 130; a gate 150, located on the sidewalls of the fin 130 and on the surface of the insulating isolation layer 140; a top source and drain 160, located on the top of the fin 130; an interlayer dielectric layer 170, covering the semiconductor substrate 110, the gate 150, and the top source and drain 160; a first contact structure 181, a second contact structure 182, and a third contact structure 183, which penetrate the interlayer dielectric layer 170 and are electrically connected to the bottom source and drain 120, the top source and drain 160, and the gate 150, respectively.
[0039] In some embodiments of the present application, the vertical field-effect transistor 100 is used as a standard measurement structure for measuring parasitic capacitance. The vertical field-effect transistor 100 can be any structure that requires parasitic capacitance measurement. The embodiments of the present application only use the most basic vertical field-effect transistor structure including a source, a drain, and a gate as an example for description.
[0040] In some embodiments of the present application, the present application provides a method for obtaining parasitic capacitance of a vertical field effect transistor, and the vertical field effect transistor may include a basic structure and various variant structures based on the vertical field effect transistor. As a standard measurement structure, the vertical field effect transistor 100 is formed using the same manufacturing process as the various vertical field effect transistor structures that need to be measured for parasitic capacitance, and the structure is exactly the same, including the size, positional relationship, etc. of each structure. Further, the vertical field effect transistor 100 as the standard measurement structure can be produced in the same batch as the vertical field effect transistor structure that needs to be measured for parasitic capacitance. Further, the vertical field effect transistor 100 as the standard measurement structure can be directly sampled from the vertical field effect transistor structure that needs to be measured for parasitic capacitance. In this way, the error between the vertical field effect transistor 100 as the standard measurement structure and the vertical field effect transistor structure that needs to be measured for parasitic capacitance can be minimized or even eliminated, so that the measurement result of the vertical field effect transistor 100 as the standard measurement structure can represent the measurement result of the vertical field effect transistor structure that needs to be measured for parasitic capacitance.
[0041] It should be noted that the specific formation process, detailed structure and dimension data of the vertical field effect transistor 100 as a standard measurement structure are completely referenced to the vertical field effect transistor structure requiring parasitic capacitance measurement, and therefore will not be repeated here.
[0042] In some embodiments of the present application, the method for obtaining C0 includes: providing the vertical field-effect transistor 100 and obtaining C0 using a capacitance measuring device. The capacitance measuring device can be any capacitance measuring device commonly used in the semiconductor field and is not described in detail herein. The method of directly measuring a semiconductor device using a capacitance measuring device in the technical solution of the present application is a method well known to those skilled in the art and is not described in detail herein.
[0043] In some embodiments of the present application, when obtaining C0 by a capacitance measuring device, the first contact structure 181 and the second contact structure 182 are grounded and the third contact structure 183 is connected to an AC power supply, and the measurement value of the capacitance measuring device is C0.
[0044] Figure 3 Schematic diagram of the structure of the first measurement structure 200 in a method for obtaining parasitic capacitance of a vertical field effect transistor according to an embodiment of the present application.
[0045] Continue to refer Figure 1 As shown, in step S2, the parasitic capacitance C of the gate 150 and the top source-drain 160 of the vertical field effect transistor 100 is obtained. GT and the gate 150 and channel parasitic capacitance C GC The sum of C1.
[0046] In some embodiments of the present application, the C1 is obtained by the first measurement structure 200, referring to Figure 3 As shown, the first measurement structure 200 includes: a semiconductor substrate 210, with a fin 230 formed on the surface of the semiconductor substrate 210; an insulating isolation layer 240, located on the surface of the semiconductor substrate 210 on both sides of the fin 230; a gate 250, located on the sidewalls of the fin 230 and on the surface of the insulating isolation layer 240; a top source and drain 260, located on the top of the fin 230; an interlayer dielectric layer 270, covering the semiconductor substrate 210, the gate 250 and the top source and drain 260; a first contact structure 281, a second contact structure 282 and a third contact structure 283, which penetrate the interlayer dielectric layer 270 and are electrically connected to the semiconductor substrate 210, the top source and drain 260 and the gate 250 respectively.
[0047] In some embodiments of the present application, the first measurement structure 200 and the vertical field-effect transistor 100 are formed using the same process. Except for the fact that the first measurement structure 200 does not include a bottom source and drain, the structures of the first measurement structure 200 and the vertical field-effect transistor 100 are identical, including the dimensions and positional relationships of the various structures. This minimizes or even eliminates the error between the vertical field-effect transistor 100 (which serves as a standard measurement structure) and the first measurement structure 200, ensuring that the measurement results of the first measurement structure 200 are representative of the measurement results of the vertical field-effect transistor 100 (which serves as a standard measurement structure).
[0048] In some embodiments of the present application, a method for obtaining C1 includes grounding the first contact structure 281 and the second contact structure 282 of the first measurement structure 200 and connecting the third contact structure 283 to an AC power source, and measuring C1 using a capacitance measuring device. Although C1 in the first measurement structure 200 is directly measured here, the measurement result of the first measurement structure 200 can represent the measurement result of the vertical field effect transistor 100 as a standard measurement structure. Therefore, C1 in the first measurement structure 200 can be equivalent to C1 of the vertical field effect transistor 100.
[0049] Figure 4 Schematic diagram of the structure of the second measurement structure 300 in a method for obtaining parasitic capacitance of a vertical field effect transistor according to an embodiment of the present application.
[0050] Continue to refer Figure 1 As shown, in step S3, the parasitic capacitance C of the gate 150 and the bottom source and drain 120 of the vertical field effect transistor 100 is obtained. GB and the gate 150 and channel parasitic capacitance C GC The sum of C2.
[0051] In some embodiments of the present application, the C2 is obtained by the second measurement structure 300, referring to Figure 4As shown, the second measurement structure 300 includes: a semiconductor substrate 310, in which a bottom source and drain 320 is formed, and a fin 330 is formed on the surface of the semiconductor substrate 310 and located above the bottom source and drain 320; an insulating isolation layer 340, located on the surface of the semiconductor substrate 310 on both sides of the fin 330; a gate 350, located on the sidewalls of the fin 330 and on the surface of the insulating isolation layer 340; an auxiliary fin 360, located on the top of the fin 330; an interlayer dielectric layer 370, covering the semiconductor substrate 310, the gate 350 and the fin 330; a first contact structure 381, a second contact structure 382 and a third contact structure 383, which penetrate the interlayer dielectric layer 370 and are electrically connected to the bottom source and drain 320, the auxiliary fin 360 and the gate 350 respectively.
[0052] In some embodiments of the present application, the second measurement structure 300 and the vertical field-effect transistor 100 are formed using the same process. Except for the sub-fin 360 in the second measurement structure 300 replacing the top source and drain 160 in the vertical field-effect transistor 100, the second measurement structure 300 and the vertical field-effect transistor 100 are identical in structure, including the dimensions and positional relationships of the various structures. This minimizes or even eliminates the error between the vertical field-effect transistor 100 (as a standard measurement structure) and the second measurement structure 300, ensuring that the measurement results of the second measurement structure 300 are representative of the measurement results of the vertical field-effect transistor 100 (as a standard measurement structure). Specifically, the difference between the sub-fin 360 and the top source and drain 160 is that, although both are epitaxially grown from fins, the top source and drain 160 are doped with either P-type or N-type doping, depending on whether they are source or drain, while the sub-fin 360, like the fin 330, may be undoped.
[0053] In some embodiments of the present application, a method for obtaining C2 includes grounding the first contact structure 381 and the second contact structure 382 in the second measurement structure 300 and connecting the third contact structure 383 to an AC power source, and measuring C2 using a capacitance measurement device. Although C2 in the second measurement structure 300 is directly measured here, the measurement result of the second measurement structure 300 can represent the measurement result of the vertical field effect transistor 100 as a standard measurement structure. Therefore, C2 in the second measurement structure 300 can be equivalent to C2 of the vertical field effect transistor 100.
[0054] In some embodiments of the present application, the order of obtaining C0, C1 and C2 can be arbitrary, that is, the order of step S1, step S2 and step S3 is not limited.
[0055] In the technical solution of the present application, in order to extract the parasitic capacitance data of a vertical field effect transistor for which parasitic capacitance data is required, the gate and top source-drain parasitic capacitance C of the vertical field effect transistor is directly measured by using the vertical field effect transistor 100 as a standard measurement structure. GT , gate and bottom source-drain parasitic capacitance C GB and the gate and channel capacitance C GC The sum of C0. Then, C0=C GT +C GB +C GC Since the vertical field effect transistor 100 as the standard measurement structure and the vertical field effect transistor for which parasitic capacitance data needs to be obtained are formed using the same manufacturing process and have exactly the same structure, the measurement result of the vertical field effect transistor 100 as the standard measurement structure can represent the measurement result of the vertical field effect transistor for which parasitic capacitance data needs to be obtained.
[0056] In addition, the parasitic capacitance C of the gate and the top source-drain in the first measurement structure is directly measured by the first measurement structure 200. GT and the gate and channel capacitance C GC The sum C1 of the first measurement structure 200 and the vertical field-effect transistor 100 is obtained by the same process. With the exception that the first measurement structure 200 does not include a bottom source and drain, the first measurement structure 200 and the vertical field-effect transistor 100 have identical structures, including the dimensions and positional relationships of the various structures. Therefore, the measurement results of the first measurement structure 200 can represent the measurement results of the vertical field-effect transistor 100 as a standard measurement structure.
[0057] In addition, the gate and bottom source-drain parasitic capacitance C in the third measurement structure 300 is directly measured by the third measurement structure 300. GB and the gate and channel capacitance C GC Since the second measurement structure 300 and the vertical field effect transistor 100 are formed using the same process, except that the secondary fins 360 in the second measurement structure 300 replace the top source and drain 160 in the vertical field effect transistor 100, the second measurement structure 300 and the vertical field effect transistor 100 have the same structure, including the size and positional relationship of each structure. Therefore, the measurement result of the second measurement structure 300 can represent the measurement result of the vertical field effect transistor 100 as a standard measurement structure.
[0058] In the technical solution of the present application, C0 of the vertical field effect transistor 100 is obtained based on step S1, C1 of the first test structure 200 (equivalent to C1 of the vertical field effect transistor 100) is obtained based on step S2, C2 of the second test structure 300 (equivalent to C2 of the vertical field effect transistor 100) is obtained based on step S3, and finally C0, C1, C2 of the vertical field effect transistor 100 and step S4 are used to obtain C2 of the vertical field effect transistor 100. GT and C GB The measurement result of the vertical field effect transistor 100 can be equivalent to the measurement result of the vertical field effect transistor for which parasitic capacitance data needs to be obtained. Therefore, the C GT and C GB This is equivalent to the C of the vertical field effect transistor for which parasitic capacitance data needs to be obtained. GT and C GB .
[0059] In summary, this application provides a method for obtaining the parasitic capacitance of a vertical field effect transistor, which can accurately obtain the gate and top source-drain parasitic capacitance C of the vertical field effect transistor. GT And the gate and bottom source-drain parasitic capacitance C of the vertical field effect transistor GB .
[0060] An embodiment of the present application further provides a test structure for obtaining the parasitic capacitance of a vertical field effect transistor, comprising: Figure 2 The vertical field effect transistor 100 shown in FIG. 1 includes: a semiconductor substrate 110, wherein a bottom source and drain 120 is formed in the semiconductor substrate 110, and a fin 130 is formed on the surface of the semiconductor substrate 110 and located above the bottom source and drain 120; an insulating isolation layer 140 located on the surface of the semiconductor substrate 110 on both sides of the fin 130; a gate 150 located on the sidewalls of the fin 130 and on the surface of the insulating isolation layer 140; a top source and drain 160 located on the top of the fin 130; an interlayer dielectric layer 170 covering the semiconductor substrate 110, the gate 150, and the top source and drain 160; a first contact structure 181, a second contact structure 182, and a third contact structure 183 penetrating the interlayer dielectric layer 170 and electrically connecting the bottom source and drain 120, the top source and drain 160, and the gate 150, respectively; Figure 3The first measurement structure 200 shown in FIG. 1 includes: a semiconductor substrate 210 having a fin 230 formed on its surface; an insulating isolation layer 240 located on the surface of the semiconductor substrate 210 on both sides of the fin 230; a gate 250 located on the sidewalls of the fin 230 and on the surface of the insulating isolation layer 240; a top source and drain 260 located on top of the fin 230; an interlayer dielectric layer 270 covering the semiconductor substrate 210, the gate 250, and the top source and drain 260; a first contact structure 281, a second contact structure 282, and a third contact structure 283 extending through the interlayer dielectric layer 270 and electrically connecting the semiconductor substrate 210, the top source and drain 260, and the gate 250, respectively. Figure 4 The second measurement structure 300 shown in FIG. 3 includes: a semiconductor substrate 310 having a bottom source and drain 320 formed therein, and a fin 330 formed on the surface of the semiconductor substrate 310 and located above the bottom source and drain 320; an insulating isolation layer 340 located on the surface of the semiconductor substrate 310 on both sides of the fin 330; a gate 350 located on the sidewalls of the fin 330 and on the surface of the insulating isolation layer 340; a secondary fin 360 located on the top of the fin 330; an interlayer dielectric layer 370 covering the semiconductor substrate 310, the gate 350, and the fin 330; a first contact structure 381, a second contact structure 382, and a third contact structure 383 extending through the interlayer dielectric layer 370 and electrically connecting the bottom source and drain 320, the secondary fin 360, and the gate 350, respectively.
[0061] In some embodiments of the present application, the vertical field-effect transistor 100 is used as a standard measurement structure for measuring parasitic capacitance. The vertical field-effect transistor 100 can be any structure that requires parasitic capacitance measurement. The embodiments of the present application only use the most basic vertical field-effect transistor structure including a source, a drain, and a gate as an example for description.
[0062] In some embodiments of the present application, the test structure described in the present application is used to apply Figure 1A method for obtaining parasitic capacitance of a vertical field effect transistor is shown, and the vertical field effect transistor can include a basic structure and various variant structures based on the vertical field effect transistor. As a standard measurement structure, the vertical field effect transistor 100 is formed using the same manufacturing process as the various vertical field effect transistor structures that need to be measured for parasitic capacitance, and the structure is exactly the same, including the size, positional relationship, etc. of each structure. Further, the vertical field effect transistor 100 as the standard measurement structure can be produced in the same batch as the vertical field effect transistor structure that needs to be measured for parasitic capacitance. Further, the vertical field effect transistor 100 as the standard measurement structure can be directly sampled from the vertical field effect transistor structure that needs to be measured for parasitic capacitance. In this way, the error between the vertical field effect transistor 100 as the standard measurement structure and the vertical field effect transistor structure that needs to be measured for parasitic capacitance can be minimized or even eliminated, so that the measurement result of the vertical field effect transistor 100 as the standard measurement structure can represent the measurement result of the vertical field effect transistor structure that needs to be measured for parasitic capacitance.
[0063] It should be noted that the specific formation process, detailed structure and dimension data of the vertical field effect transistor 100 as a standard measurement structure are completely referenced to the vertical field effect transistor structure requiring parasitic capacitance measurement, and therefore will not be repeated here.
[0064] In some embodiments of the present application, the first measurement structure 200 and the vertical field-effect transistor 100 are formed using the same process. Except for the fact that the first measurement structure 200 does not include a bottom source and drain, the structures of the first measurement structure 200 and the vertical field-effect transistor 100 are identical, including the dimensions and positional relationships of the various structures. This minimizes or even eliminates the error between the vertical field-effect transistor 100 (which serves as a standard measurement structure) and the first measurement structure 200, ensuring that the measurement results of the first measurement structure 200 are representative of the measurement results of the vertical field-effect transistor 100 (which serves as a standard measurement structure).
[0065] In some embodiments of the present application, the second measurement structure 300 and the vertical field-effect transistor 100 are formed using the same process. Except for the sub-fin 360 in the second measurement structure 300 replacing the top source and drain 160 in the vertical field-effect transistor 100, the second measurement structure 300 and the vertical field-effect transistor 100 are identical in structure, including the dimensions and positional relationships of the various structures. This minimizes or even eliminates the error between the vertical field-effect transistor 100 (as a standard measurement structure) and the second measurement structure 300, ensuring that the measurement results of the second measurement structure 300 are representative of the measurement results of the vertical field-effect transistor 100 (as a standard measurement structure). Specifically, the difference between the sub-fin 360 and the top source and drain 160 is that, although both are epitaxially grown from fins, the top source and drain 160 are doped with either P-type or N-type doping, depending on whether they are source or drain, while the sub-fin 360, like the fin 330, may be undoped.
[0066] The present application provides a method and test structure for obtaining the parasitic capacitance of a vertical field effect transistor, which can accurately obtain the parasitic capacitance C of the gate and top source-drain of the vertical field effect transistor. GT And the gate and bottom source-drain parasitic capacitance C of the vertical field effect transistor GB .
[0067] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.
[0068] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may also be present.
[0069] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" indicates that there are no intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0070] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.
[0071] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.
Claims
1. A method for obtaining parasitic capacitance of a vertical field effect transistor, characterized in that: include: Get the gate and top source-drain parasitic capacitance C of the vertical field effect transistor GT , gate and bottom source-drain parasitic capacitance C GB and the gate and channel capacitance C GC The sum of C0; Get the gate and top source-drain parasitic capacitance C of the vertical field effect transistor GT and the gate and channel capacitance C GC The sum of C1, the gate and bottom source-drain parasitic capacitance C of the vertical field effect transistor is obtained. GB and the gate and channel capacitance C GC The sum of C2; Get C based on C0 and C1 GB And obtain C according to C0 and C2 GT .
2. The acquisition method according to claim 1, wherein: The method for obtaining the C0 includes: providing the vertical field effect transistor, obtaining the C0 by using a capacitance measuring device, the vertical field effect transistor including: a semiconductor substrate, a bottom source and drain formed in the semiconductor substrate, and a fin formed on the surface of the semiconductor substrate and located above the bottom source and drain; an insulating isolation layer located on the surface of the semiconductor substrate on both sides of the fin; a gate located on the sidewalls of the fin and on the surface of the insulating isolation layer; a top source and drain located on the top of the fin; an interlayer dielectric layer covering the semiconductor substrate, the gate, and the top source and drain; a first contact structure, a second contact structure, and a third contact structure penetrating the interlayer dielectric layer and electrically connecting the bottom source and drain, the top source and drain, and the gate, respectively.
3. The acquisition method according to claim 2, wherein: When obtaining C0 through a capacitance measuring device, the first contact structure and the second contact structure are grounded and the third contact structure is connected to an AC power supply. The measurement value of the capacitance measuring device is C0.
4. The acquisition method according to claim 2, wherein: The C1 is obtained through a first measurement structure, which includes: a semiconductor substrate, a fin formed on the surface of the semiconductor substrate; an insulating isolation layer, located on the surface of the semiconductor substrate on both sides of the fin; a gate, located on the sidewalls of the fin and the surface of the insulating isolation layer; a top source and drain, located on the top of the fin; an interlayer dielectric layer, covering the semiconductor substrate, the gate and the top source and drain; a first contact structure, a second contact structure and a third contact structure, which penetrate the interlayer dielectric layer and are electrically connected to the semiconductor substrate, the top source and drain and the gate, respectively.
5. The acquisition method according to claim 4, wherein: The method for obtaining the C1 includes: grounding the first contact structure and the second contact structure and connecting the third contact structure to an AC power supply, and measuring the C1 using a capacitance measuring device.
6. The acquisition method according to claim 2, wherein: The C2 is obtained through a second measurement structure, where the second measurement structure includes: a semiconductor substrate, in which a bottom source and drain are formed, and a fin is formed on the surface of the semiconductor substrate and is located above the bottom source and drain; an insulating isolation layer is located on the surface of the semiconductor substrate on both sides of the fin; a gate is located on the sidewalls of the fin and on the surface of the insulating isolation layer; a secondary fin is located on the top of the fin; an interlayer dielectric layer covers the semiconductor substrate, the gate and the fin; a first contact structure, a second contact structure and a third contact structure penetrate the interlayer dielectric layer and are electrically connected to the bottom source and drain, the secondary fin and the gate, respectively.
7. The acquisition method according to claim 6, characterized in that: The method for obtaining the C2 includes: grounding the first contact structure and the second contact structure and connecting the third contact structure to an AC power supply, and measuring the C2 using a capacitance measuring device.
8. The acquisition method according to claim 4, wherein: The first measurement structure and the vertical field effect transistor are formed using the same process. Except that the first measurement structure does not include a bottom source and drain, the first measurement structure and the vertical field effect transistor have the same structure.
9. The acquisition method according to claim 6, wherein: The second measurement structure and the vertical field effect transistor are formed by the same process. Except that the auxiliary fins in the second measurement structure replace the top source and drain in the vertical field effect transistor, the second measurement structure and the vertical field effect transistor have the same structure.
10. The acquisition method according to claim 1, wherein: Get C based on C0 and C1 GB The method is: C GB = C0-C1; Get C according to C0 and C2 GT The method is: C GT =C0-C2.
11. A test structure for obtaining the parasitic capacitance of a vertical field effect transistor, characterized in that: include: A vertical field-effect transistor comprises: a semiconductor substrate, a bottom source and drain formed in the semiconductor substrate, a fin formed on the surface of the semiconductor substrate and located above the bottom source and drain; an insulating isolation layer located on the surface of the semiconductor substrate on both sides of the fin; a gate located on the sidewalls of the fin and on the surface of the insulating isolation layer; a top source and drain located on top of the fin; an interlayer dielectric layer covering the semiconductor substrate, the gate, and the top source and drain; a first contact structure, a second contact structure, and a third contact structure penetrating the interlayer dielectric layer and electrically connecting the bottom source and drain, the top source and drain, and the gate, respectively; The first measurement structure includes: a semiconductor substrate having a fin formed on its surface; an insulating isolation layer located on the surface of the semiconductor substrate on both sides of the fin; a gate located on the sidewalls of the fin and on the surface of the insulating isolation layer; a top source and drain located on top of the fin; an interlayer dielectric layer covering the semiconductor substrate, the gate, and the top source and drain; a first contact structure, a second contact structure, and a third contact structure penetrating the interlayer dielectric layer and electrically connecting the semiconductor substrate, the top source and drain, and the gate, respectively; The second measurement structure includes: a semiconductor substrate, in which a bottom source and drain are formed, and a fin is formed on the surface of the semiconductor substrate and is located above the bottom source and drain; an insulating isolation layer is located on the surface of the semiconductor substrate on both sides of the fin; a gate is located on the sidewalls of the fin and on the surface of the insulating isolation layer; a secondary fin is located on the top of the fin; an interlayer dielectric layer covers the semiconductor substrate, the gate and the fin; a first contact structure, a second contact structure and a third contact structure penetrate the interlayer dielectric layer and are electrically connected to the bottom source and drain, the secondary fin and the gate respectively.
12. The test structure according to claim 11, wherein: The first measurement structure and the vertical field effect transistor are formed using the same process. Except that the first measurement structure does not include a bottom source and drain, the first measurement structure and the vertical field effect transistor have the same structure.
13. The test structure according to claim 11, wherein: The second measurement structure and the vertical field effect transistor are formed by the same process. Except that the auxiliary fins in the second measurement structure replace the top source and drain in the vertical field effect transistor, the second measurement structure and the vertical field effect transistor have the same structure.