Self-starting ultra-low power consumption and low temperature drift resistance-free band-gap reference voltage source

Abstract

The invention discloses a self-starting ultra-low power consumption and low temperature drift resistance-free band-gap reference voltage source, and belongs to the field of CMOS integrated circuit design. The band-gap reference voltage source is composed of a self-starting circuit, a nanometer ampere current reference circuit, a bipolar transistor and five sets of proportional-absolute temperature voltage generating circuits. The circuit does not use a resistor and only comprises an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a bipolar transistor. In a nanometer ampere current reference circuit, an MOSFET resistor working in a deep linear area is adopted to replace a resistor, other MOSFETs all work in a sub-threshold area, and low power consumption is achieved. The circuit adopts a positive temperature coefficient provided by a cascaded proportional-absolute temperature voltage generation circuit to counteract a negative temperature coefficient provided by a bipolar transistor, so that low-temperature-drift band-gap reference voltage output is realized.

Description

Technical Field

[0001] The present invention belongs to the field of CMOS integrated circuit design, and in particular relates to a self-starting, ultra-low power consumption, low temperature drift, and resistance-free bandgap reference voltage source. Background Art

[0002] Bandgap reference voltage sources play a vital role in modern integrated circuits. They are key components of analog, digital, and mixed-signal circuits, providing a stable reference voltage for circuit modules such as digital-to-analog converters (DACs), phase-locked loops (PLLs), analog-to-digital converters (ADCs), and low-dropout regulators (LDOs). With the maturity of CMOS technology, CMOS bandgap references have become increasingly popular in large-scale integration systems (LSIs) due to their high integration density, low power consumption, low temperature coefficient, and strong immunity to power supply noise.

[0003] However, traditional bandgap reference (BGR) structures have been limited by high operating voltages and significant power consumption. To meet the stringent requirements of modern integrated circuits for low power consumption, low voltage, and high precision, researchers have conducted extensive and in-depth research on CMOS bandgap reference circuits. Although some BGR circuits have been developed, their power consumption remains generally above the nanowatt level, with no significant reductions achieved. A key factor is the use of resistors. In most reference circuit designs, resistors are used to generate current or voltage to adjust the temperature characteristics of the output reference voltage. When using medium resistance values, sufficient current must be supplied to ensure proper operation of the resistors, which limits power consumption reduction. Using high resistance values ​​to reduce current consumption results in the resistors occupying a larger silicon area, increasing manufacturing costs. Therefore, effectively reducing power consumption and area cost while maintaining circuit performance is a major challenge in current CMOS bandgap reference circuit research.

[0004] In recent years, researchers have proposed novel resistor-free voltage reference circuits capable of operating at nanowatt power levels. Their output reference voltage is primarily based on the threshold voltage of MOSFETs. However, these circuits are not suitable for use as voltage reference circuits because the threshold voltage varies with manufacturing process variations.

[0005] Resistor-free, low-power, low-drift, all-CMOS bandgap reference circuits are becoming a new trend in integrated circuit design due to their energy-saving, stable, and cost-effective features. By eliminating resistors, they reduce power consumption and temperature drift, minimizing chip area and manufacturing costs. Compatible with existing CMOS processes, these circuits are easy to integrate and are suitable for large-scale integrated circuit systems with high power consumption and stability requirements.

[0006] The Chinese patent publication number is "CN117348674A," and its title is "A Low-Power Subthreshold Bandgap Reference Circuit with a Full CMOS Structure." This invention proposes a low-power subthreshold bandgap reference circuit with a full CMOS structure. By generating a subthreshold current, the entire circuit operates in the subthreshold region, and the gate-source voltage of a MOS transistor operating in the subthreshold region is used to provide a negative temperature coefficient voltage. However, this invention uses resistors, which have a large temperature coefficient and may cause the reference voltage to fluctuate with temperature. The precision and long-term stability of resistors are inferior to those of other components (such as transistors), which can reduce the output precision and long-term reliability of the reference circuit. Summary of the Invention

[0007] In order to solve the problem of large temperature coefficient of resistance, which causes reference voltage to fluctuate with temperature, and to achieve the ultra-low power consumption requirement of bandgap reference, this paper proposes a self-starting, ultra-low power consumption, and low-temperature drift bandgap reference voltage source.

[0008] The present invention provides a self-starting, ultra-low power consumption, low temperature drift, and resistance-free bandgap reference voltage source, comprising: a self-starting circuit, a nanoampere current reference circuit, and a voltage generating circuit; the self-starting circuit is connected to the nanoampere current reference circuit; the nanoampere current reference circuit is connected to the voltage generating circuit; the self-starting circuit is used to implement a self-starting mechanism and generate a starting signal and a bias voltage; the nanoampere current reference circuit uses two MOSFETs operating in a deep linear region to replace the function of a resistor, thereby reducing power consumption while generating a reference current; the voltage generating circuit uses multiple groups of cascaded PTAT circuits to offset the negative temperature coefficient generated by bipolar transistors, thereby obtaining a reference voltage that does not change with temperature.

[0009] Furthermore, the self-starting circuit includes a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M12, and a PMOS transistor M13; the sources of the PMOS transistor M1, the PMOS transistor M2, the PMOS transistor M12, and the PMOS transistor M13 are all connected to the AVDD power supply;

[0010] The gate of the PMOS transistor M1 is connected to the gates of the PMOS transistors M12 and M13 as an output branch EN, the drain of the PMOS transistor M1 is connected to the drain and gate of the NMOS transistor M3; the source of the NMOS transistor M3 is connected to the drain and gate of the NMOS transistor M5; the source of the NMOS transistor M5 is connected to the drain and gate of the NMOS transistor M7; the source of the NMOS transistor M7 is connected to the drain and gate of the NMOS transistor M9; the source of the NMOS transistor M9 is connected to the AVSS ground, and the gate of the NMOS transistor M9 is connected to the gate of the NMOS transistor M10 and the gate of the NMOS transistor M17 respectively;

[0011] The drain of the PMOS transistor M2 is connected to the source of the PMOS transistor M4; the drain of the PMOS transistor M4 is connected to the source of the PMOS transistor M6; the drain of the PMOS transistor M6 is connected to the source of the PMOS transistor M8; the drain of the PMOS transistor M8 is respectively connected to the drain of the NMOS transistor M10 and the gate of the NMOS transistor M11; the source of the NMOS transistor M10 and the source of the NMOS transistor M11 are connected to the AVSS ground; the drain of the NMOS transistor M11 is connected to the input start signal EN; the PMOS transistors M2, M4, M6, and M8 constitute a group of continuously conducting PMOS transistors, and their gates are all connected to the AVSS ground;

[0012] The drain of the PMOS transistor M12 is connected to the source of the PMOS transistor M14; the drain of the PMOS transistor M14 is connected to the source of the PMOS transistor M16 and the gate of the PMOS transistor M15; the drain of the PMOS transistor M16 is connected to the drain of the NMOS transistor M17; the source of the NMOS transistor M17 is connected to the AVSS ground;

[0013] The drain of the PMOS tube M13 is connected to the source of the PMOS tube M15; the drain of the PMOS tube M15 is connected to the nanoampere current reference circuit and the voltage generating circuit as an output branch VN1; the gates of the PMOS tubes M14 and M16 are connected to the nanoampere current reference circuit as output branches VP1.

[0014] Furthermore, the nanoampere current reference circuit includes a PMOS transistor M19 and a PMOS transistor M20 operating in a deep linear region and a PMOS transistor 18 and an NMOS transistor 25 operating in a subthreshold region;

[0015] The source of the PMOS tube M18 is connected to the AVDD power supply, the gate of the PMOS tube M18 is connected to the input start signal EN, and the drain of the PMOS tube M18 is respectively connected to the source of the PMOS tube M19, the PMOS tube M21, the PMOS tube M20, and the PMOS tube M29; the gate and drain of the PMOS tube M21 are connected together, respectively connected to the gate of the PMOS tube M22, the gate of the PMOS tube M29, and the source of the PMOS tube M23, and connected to the voltage generating circuit as the output branch VBIAS1; the gate and drain of the PMOS tube M23 are connected together, respectively connected to The gate of the PMOS transistor M24 and the drain of the NMOS transistor M25 are connected to the voltage generating circuit as an output branch VBIAS2; the gate of the NMOS transistor M25 is respectively connected to the gate and drain of the NMOS transistor M26 and the gate of the NMOS transistor M34, and the source of the NMOS transistor M25 is connected to the drain of the NMOS transistor M27; the source of the NMOS transistor M27 is connected to the AVSS ground, and the gate of the NMOS transistor M27 is respectively connected to the gate and drain of the NMOS transistor M28, the source of the NMOS transistor M26, and the gate of the NMOS transistor M37, and is connected to the voltage generating circuit as an output branch VN1;

[0016] The drain of the PMOS transistor M19 is connected to the source of the PMOS transistor M22. The gate of the PMOS transistor M19 is respectively connected to the gate and drain of the PMOS transistor M30, the drain of the NMOS transistor M32, and the input branch VP1. The drain of the PMOS transistor M22 is connected to the source of the PMOS transistor M24. The source of the NMOS transistor M28 is connected to the AVSS ground.

[0017] The drain of the PMOS transistor M29 is respectively connected to the source of the PMOS transistor M30 and the source of the PMOS transistor M31; the drain of the PMOS transistor M31 is respectively connected to the drain and gate of the NMOS transistor M33 and the gate of the NMOS transistor M32; the gate of the PMOS transistor M31 is respectively connected to the drain and gate of the PMOS transistor M29 and the drain of the NMOS transistor M34; the source of the NMOS transistor M32 is connected to the drain of the NMOS transistor M35; the source of M33 is respectively connected to the gate and drain of the NMOS transistor M36 and the gate of the NMOS transistor M35; the gate of the NMOS transistor M35 is respectively connected to the drain and gate of the NMOS transistor M36 and the source of the NMOS transistor M33; the source of the NMOS transistor M35 is connected to the AVSS ground; the source of the NMOS transistor M36 is connected to the AVSS ground; the source of the NMOS transistor M34 is connected to the drain of the NMOS transistor M37; the source of the NMOS transistor M37 is connected to the AVSS ground.

[0018] Furthermore, the voltage generating circuit includes a voltage dividing branch and six groups of cascade-connected PTAT circuits, and the output branch of the last stage PTAT is VREF;

[0019] The source of the PMOS tube M38 is connected to the AVDD power supply, the gate of the PMOS tube M38 is connected to the input start signal EN, and the drain of the PMOS tube M38 is respectively connected to the source of the PMOS tube M39 and 6 groups of PTAT circuits; the gate of the PMOS tube M39 is connected to the input branch VBIAS1, and the drain of the PMOS tube M39 is connected to the source of the PMOS tube M40; the gate of the PMOS tube M40 is connected to the input branch VBIAS2, and the drain of the PMOS tube M40 is respectively connected to the emitter of the NPN tube Q1 and the output branch VBE of the PTAT circuit; the base and collector of the NPN bipolar transistor Q1 are connected to the AVSS ground.

[0020] Furthermore, the PTAT circuit includes a PMOS transistor M41 and a PMOS transistor M42;

[0021] The source of the PMOS tube M41 is connected to the drain of M38, the gate and drain of the PMOS tube M41 are connected together, and are respectively connected to the gate of M42 and the source of the PMOS tube M43; the source of the PMOS tube M42 is connected to the drain of M38, and the drain of the PMOS tube M42 is connected to the source of the PMOS tube M44; the gate and drain of the PMOS tube M43 are connected together, and are respectively connected to the gate of the PMOS tube M44 and the drain of the NMOS tube M45; the drain of the PMOS tube M44 is respectively connected to the gate of the PMOS tube M44 and the drain of the NMOS tube M45. The gate and drain of the NMOS transistor M46 are connected and serve as the first output branch of the PTAT circuit; the gate of the NMOS transistor M45 is connected to the output branch VBE of the voltage divider and serves as the first input branch of the PTAT circuit; the source of the NMOS transistor M45 and the source of the NMOS transistor M46 are connected to the drain of the NMOS transistor M47; the gate of the NMOS transistor M47 is connected to the input branch VN1 and serves as the second input branch of the PTAT circuit; the source of the NMOS transistor M47 is connected to the AVSS ground.

[0022] Furthermore, the self-starting, ultra-low power consumption, low temperature drift, and resistance-free bandgap reference voltage source generates a reference current of:

[0023]

[0024] Among them, μC OX K M19 is the current gain of M19, K Mi is the aspect ratio of Mi (K 31 >K 30 ,K 22 >K 21 ), μ is the electron mobility; C OX is the gate oxide capacitance; η is the subthreshold slope factor; V T =(kB T / q) is the thermal voltage, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge; I0 is the subthreshold current exponential factor.

[0025] Furthermore, it is characterized in that the self-starting ultra-low power consumption, low temperature drift and resistance-free bandgap reference voltage source outputs a reference voltage of:

[0026]

[0027] V BE =V BGR -γT

[0028]

[0029] Among them, V BE is the bipolar transistor voltage; V BGR is the bandgap voltage of silicon; γ is V BE The temperature coefficient of; N is the number of groups of PTAT circuit; is the total gate voltage; K Dj is the width-to-length ratio of the differential pair.

[0030] Furthermore, the temperature coefficient of the self-starting, ultra-low power consumption, low temperature drift, and resistance-free bandgap reference voltage source is:

[0031]

[0032] Where, ΔV REF is the change in the reference voltage within the temperature range; ΔT is the temperature range; Average (ΔV REF ) is the average value of the reference voltage within the varying temperature range.

[0033] The beneficial effects of the present invention are:

[0034] The self-starting ultra-low power consumption and low temperature drift bandgap reference voltage source provided by the present invention realizes a self-starting process when a circuit is powered on.

[0035] The self-starting, ultra-low power consumption, low-temperature drift bandgap reference voltage source provided by the present invention realizes low-temperature drift of the circuit.

[0036] The self-starting, ultra-low power consumption, low temperature drift bandgap reference voltage source provided by the present invention optimizes the PTAT circuit in a cascade manner.

[0037] The self-starting ultra-low power consumption and low temperature drift bandgap reference voltage source provided by the present invention realizes ultra-low power consumption of the circuit.

[0038] The self-starting, ultra-low power consumption, low temperature drift bandgap reference voltage source provided by the present invention is suitable for use in low dropout linear regulators (LDOs) and many other electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is the circuit schematic diagram of a self-starting, ultra-low power, low-temperature drift, resistor-free bandgap reference voltage source.

[0040] Figure 2 Schematic diagram of the self-starting circuit;

[0041] Figure 3 This is the schematic diagram of the nanoampere current reference circuit;

[0042] Figure 4 This is the schematic diagram of the voltage generator circuit;

[0043] Figure 5 This is the schematic diagram of the PTAT circuit;

[0044] Figure 6 Schematic diagram of simulation of the output voltage temperature coefficient of the circuit of the present invention. DETAILED DESCRIPTION

[0045] The present invention will be further described below with reference to the accompanying drawings.

[0046] In order to achieve the ultra-low power consumption requirement of the bandgap reference, this paper proposes a self-starting, ultra-low power consumption, and low temperature drift bandgap reference voltage source.

[0047] The circuit structure of the present invention is as follows Figure 1 As shown, the circuit is composed of a self-starting circuit, a nanoampere current reference circuit, a bipolar transistor, and six proportional-to-absolute temperature (PTAT) voltage generation circuits. The circuit proposed by the present invention does not use resistors and only includes MOSFETs and a bipolar transistor.

[0048] like Figure 2 As shown, in one embodiment of the present invention, the self-starting circuit includes:

[0049] The source of the PMOS tube M1 is connected to the AVDD power supply;

[0050] The gate of M1 is connected to the gates of PMOS tubes M12 and M13 respectively as output branches EN;

[0051] The drain of M1 is connected to the gate and drain of NMOS tube M3;

[0052] The source of M3 is connected to the gate and drain of NMOS tube M5;

[0053] The source of M5 is connected to the gate and drain of NMOS tube M7;

[0054] The source of M7 is connected to the gate and drain of NMOS tube M9;

[0055] The gate of M9 is connected to the gates of NMOS transistors M10 and M17 respectively;

[0056] The source of M9 is connected to AVSS ground;

[0057] The source of the PMOS tube M2 is connected to the AVDD power supply;

[0058] The drain of M2 is connected to the source of PMOS tube M4;

[0059] The drain of M4 is connected to the source of PMOS tube M6;

[0060] The drain of M6 is connected to the source of PMOS tube M8;

[0061] The drain of M8 is connected to the drain of NMOS tube M10 and the gate of NMOS tube M11 respectively;

[0062] The sources of M10 and M11 are connected to AVSS ground;

[0063] The gates of M2, M4, M6, and M8 are connected to AVSS ground;

[0064] The source of M12 is connected to the AVDD power supply;

[0065] The drain of M12 is connected to the source of PMOS tube M14;

[0066] The drain of M14 is connected to the source of PMOS tube M16 and the gate of PMOS tube M15 respectively;

[0067] The drain of M16 is connected to the drain of M17;

[0068] The source of M17 is connected to AVSS ground;

[0069] The source of M13 is connected to the AVDD power supply;

[0070] The drain of M13 is connected to the source of M15;

[0071] The drain of M15 serves as the output branch VN1;

[0072] The gates of M14 and M16 serve as the output branch VP1;

[0073] When the circuit is inactive, no current flows through the M12 and M13 branches, and their gate voltages remain high. Simultaneously, since the current mirror M9 and the current mirrors M10 and M17 are not conducting, no current flows through these components. Meanwhile, M2, M4, M6, and M8 form a group of continuously conducting PMOS transistors, providing charging current to M11, thereby increasing its gate voltage. Once M11's gate voltage exceeds its threshold voltage, M11 turns on, lowering the gate voltages of M12 and M13, causing them to conduct. This process provides bias voltages VN1 and VP1 for subsequent circuits, thus implementing the bandgap reference circuit's self-starting mechanism.

[0074] like Figure 3 As shown, in one embodiment of the present invention, the nanoampere current reference circuit includes:

[0075] The source of the PMOS tube M18 is connected to the AVDD power supply;

[0076] The gate of M18 is connected to input a start signal EN;

[0077] The drain of M18 is connected to the sources of PMOS tubes M19, M20, M21 and M29 respectively;

[0078] The gate of M19 is connected to the gate and drain of the PMOS tube M30 and the drain of the NMOS tube M32 respectively;

[0079] The drain of M19 is connected to the source of PMOS tube M22;

[0080] The gate and drain of the M20 are connected together, and are respectively connected to the gate of the PMOS tube M31 and the drain of the NMOS tube M34;

[0081] The gate and drain of M21 are connected together, and are respectively connected to the gates of PMOS transistors M22 and M29 and the source of PMOS transistor M23, and serve as the output branch VBIAS1;

[0082] The drain of M22 is connected to the source of PMOS tube M24;

[0083] The gate and source of M23 are connected together, and are respectively connected to the gate of M24 and the drain of NMOS tube M25, and serve as the output branch VBIAS2;

[0084] The gate of M25 is connected to the gate and drain of NMOS transistor M26 and the gate of NMOS transistor M34 respectively;

[0085] The source of M25 is connected to the drain of NMOS tube M27;

[0086] The gate of M27 is respectively connected to the gate and drain of NMOS transistor M28, the source of M26 and the gate of NMOS transistor M37, and serves as an output branch VN1;

[0087] The source of M27 is connected to AVSS ground;

[0088] The source of M28 is connected to AVSS ground;

[0089] The drain of M29 is connected to the sources of M30 and M31;

[0090] The drain of M31 is connected to the gate and drain of NMOS tube M33 and the gate of M32 respectively;

[0091] The gate of the MOS transistor M31 is connected to the drain and gate of the PMOS transistor M29 and the drain of the NMOS transistor M34 respectively;

[0092] The source of M32 is connected to the drain of NMOS tube M35;

[0093] The source of M33 is connected to the gate and drain of NMOS tube M36 and the gate of M35 respectively;

[0094] The source of M35 is connected to AVSS ground;

[0095] The gate of the NMOS transistor M35 is connected to the drain and gate of the NMOS transistor M36 and the source of the NMOS transistor M33 respectively;

[0096] The source of M36 is connected to AVSS ground;

[0097] The source of M34 is connected to the drain of M37;

[0098] The source of M37 is connected to the AVSS ground.

[0099] like Figure 4 As shown, in one embodiment of the present invention, the voltage divider circuit includes:

[0100] The source of the PMOS tube M38 is connected to the AVDD power supply;

[0101] The gate of M38 is connected to input a start signal EN;

[0102] The drain of M38 is connected to the source of PMOS tube M39 and 6 groups of PTAT respectively;

[0103] The gate of M39 is connected to the input branch VBIAS1;

[0104] The drain of M39 is connected to the source of PMOS tube M40;

[0105] The gate of M40 is connected to the input branch VBIAS2;

[0106] The drain of M40 is connected to the emitter of NPN transistor Q1 and the output branch VBE of the PTAT circuit respectively;

[0107] The base and collector of Q1 are connected to AVSS ground.

[0108] One set of PTAT circuits includes:

[0109] The source of the PMOS tube M41 is connected to the drain of M38;

[0110] The source of the PMOS tube M42 is connected to the drain of M38;

[0111] The gate and drain of M41 are connected together, and are respectively connected to the gate of M42 and the source of PMOS tube M43;

[0112] The drain of M42 is connected to the source of PMOS tube M44;

[0113] The gate and drain of M43 are connected together, and are respectively connected to the gate of the PMOS tube M44 and the drain of the NMOS tube M45;

[0114] The gate of M45 is connected to the output branch VBE of the voltage divider, which is also the input branch of the PTAT circuit.

[0115] The drain of M44 is connected to the gate and drain of NMOS transistor M46 respectively, and serves as the output branch 1 of PTAT;

[0116] The sources of M45 and M46 are connected to the drain of NMOS tube M47;

[0117] The gate of M47 is connected to the input branch VN1, which is also the second input branch of the PTAT circuit;

[0118] The source of M47 is connected to the AVSS ground.

[0119] This voltage generator consists of a voltage divider circuit and six PTATs connected in cascade, with the output branch of the last PTAT being VREF.

[0120] The working principle of the present invention is:

[0121] First, the self-starting circuit generates a starting signal and a bias voltage to control the switch of the circuit.

[0122] exist Figure 2In the circuit diagram, when the circuit is not started, no current flows through branches M12 and M13, so their gate voltages are high. No current flows through current mirror M9 and current mirrors M10 and M17. M2, M4, M6, and M8 are a group of normally-on PMOS transistors, whose current is used to charge M11, increasing its gate voltage. When the threshold voltage of M11 is exceeded, M11 turns on, lowering the gate voltages of M12 and M13, turning them on and providing bias voltages VN1 and VP1 for subsequent circuits, thus achieving the self-startup process of the bandgap reference circuit.

[0123] exist Figure 3 In traditional current reference circuits, the use of resistors has many problems, such as the need to provide sufficient current to ensure the normal operation of the resistors, which limits the reduction of power consumption, or the use of high resistance values ​​can reduce the current, but will increase the silicon area and increase the manufacturing cost. The current reference circuit designed in this embodiment is innovative. It does not use resistors and only contains MOSFETs and a bipolar transistor, which reduces power consumption, temperature drift, chip area and manufacturing cost. The nanoampere current reference circuit consists of a bias voltage circuit, a PTAT voltage generator and a current source circuit. The NMOS transistor generates current and the PMOS transistor copies the current. In the circuit, MOS resistors (M19, M20) working in the deep linear region are used to replace the role of the resistor, and the remaining MOSFETs all work in the subthreshold region, achieving low power consumption. The bias voltage signal VN1 output by the startup circuit is input, so that the branch composed of the PMOS tubes M21, M23 and the NMOS tubes M25, M27 forms a current mirror, which copies the current to other branches. The gate-drain voltage of the M21 and M23 is output to the voltage divider circuit to generate V BE Voltage.

[0124] Using the same size MOS resistor and transistor pair, and working in the subthreshold region of the MOS transistor, when its drain-source voltage VDS is higher than 0.1V, its subthreshold current I sub It can be expressed as

[0125]

[0126] Where I0 is the subthreshold current index factor, V T =(k B T / q) is the thermal voltage, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, and η is the subthreshold slope factor;

[0127] In this circuit, the reference current I REF Mainly determined by the gate-source voltage V of the MOS resistor GS and drain-source voltage V DSThe PMOS transistors M19 and M20 act as MOS resistors and operate in the deep linear region, while all other MOSFETs operate in the subthreshold region. The gate length W and gate width L of M19 and M20 are identical, and they are biased at the same current. The PTAT voltage generator adds a voltage to the gate-source voltage of M19 to increase the gate-source voltage of M20. The difference in their gate-source voltages forces the MOS resistor M19 to operate in the deep linear region. The current value of the MOS resistor is as follows:

[0128] I REF =μC OX K 19 (V GS19 -V TH )V DS19

[0129] Among them, μC OX K M19 is the current gain of PMOS tube M19, K Mi is the aspect ratio of Mi (K 31 >K 30 ,K 22 >K 21 ), μ is the electron mobility; C OX is the gate oxide capacitance; V GSi is the gate-source voltage;

[0130] according to Figure 3 It can be seen that the voltage V GS19 =(V GS20 -V GS31 +V GS30 ) and V DS19 =(V GS21 -V GS22 ) can be expressed as:

[0131] V GS19 =V GS20 +ηV T ln(K 31 / K 30 )

[0132] V DS19 =ηV T ln(K 22 / K 21 )

[0133] According to the above formula, the circuit generates a reference current:

[0134]

[0135] Using MOS resistors M19, M20 and transistors of the same size makes their threshold voltages close to each other, thereby alleviating the impact of their mismatch because the generated current value is robust to process variations.

[0136] exist Figure 4 In the figure, the nanoampere current reference circuit generates a nanoampere level reference current that is copied to the voltage divider circuit through a current mirror. The NPN bipolar transistor receives the current of the nanoampere current reference circuit and generates a base-emitter voltage, which is expressed as:

[0137]

[0138] Among them, I S is the saturation current of the NPN bipolar transistor.

[0139] Because the V BE It shows a negative temperature coefficient, so the above formula can be simplified to

[0140] V BE =V BGR -γT

[0141] Where V BGR is the bandgap voltage of silicon; γ is V BE Temperature coefficient.

[0142] Because V BE The PTAT circuit has a negative temperature coefficient, while the PTAT circuit has a positive temperature coefficient, which can be used to offset the bipolar transistor V BE The bias current of the NPN bipolar transistor also determines its accuracy. The bias current is generated by a nanoampere current reference circuit, and the resulting current has little effect on threshold voltage variations, minimizing current variations. Consequently, the effects of bias current variations can also be minimized.

[0143] The PTAT circuit exhibits a positive temperature coefficient, such as Figure 5 The figure shows the basic working principle of the PTAT circuit. It consists of a differential pair with a tail current source. When all MOSFETs operate in the subthreshold region, the gate voltage difference of the circuit is

[0144]

[0145] Among them, K D1 and K D2 Corresponding to the width-to-length ratio of the differential pair, K M1 and K M2 Corresponding to Figure 5 The width-to-length ratio of the tube, so the PTAT voltage can be D1 K M2 / KD2 K M1 >1 is generated.

[0146] As mentioned above, Figure 5 The PTAT circuit in the circuit has a positive temperature coefficient. In order to offset the transistor V BE Negative temperature coefficient is generated. K is required D1 K M2 / K D2 K M1 The value of is large, so a larger area is required, which is inconvenient. Therefore, the present invention adopts many groups of PTAT circuits and cascades them to offset the transistor V BE The generated negative temperature coefficient can obtain sufficient PTAT voltage.

[0147] When the PTAT circuits are connected in cascade, the total gate voltage can be expressed as

[0148]

[0149] Where N is the number of PTAT circuit groups. D2j-1 K M2j / K D2j K M2j-1 The ratio is a multiplication relationship, so it can replace the large-area PTAT circuit to offset the transistor V BE Resulting in a negative temperature coefficient.

[0150] The final bandgap reference voltage can also be expressed as

[0151]

[0152] Therefore, the width-to-length ratio of the transistors in the N and PTAT circuits is appropriately adjusted to offset the positive temperature coefficient of the transistor V by the N group of PTAT circuits. BE The negative temperature coefficient generated can achieve low-temperature drift bandgap reference voltage output.

[0153] Figure 6 This is a simulation diagram of the output voltage temperature coefficient of the circuit of the present invention.

[0154]

[0155] Where, ΔV REF is the change in the reference voltage within the temperature range; ΔT is the temperature range; Average (ΔV REF ) is the average value of the reference voltage within the varying temperature range.

[0156] Calculation shows that the temperature coefficient of the circuit of the present invention is 5.69 PPM.

[0157] The final output reference voltage V REF The voltage is 1.2V and the static power consumption is 210nW.

[0158] In summary, the present invention provides a self-starting, ultra-low-power, low-temperature drift bandgap reference voltage source circuit. The present invention is applicable to digital-to-analog converters (DACs), phase-locked loops (PLLs), analog-to-digital converters (ADCs), low-dropout linear regulators (LDOs), and many other electronic devices.

[0159] It should be noted that although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention. Therefore, the present invention is not limited to the above-mentioned specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A self-starting, ultra-low power consumption, low temperature drift, resistor-free bandgap reference voltage source, characterized in that: include: Self-starting circuit, nanoampere current reference circuit and voltage generating circuit; The self-starting circuit is connected to a nanoampere current reference circuit; The nanoampere current reference circuit is connected to the voltage generating circuit; The self-starting circuit is used to implement a self-starting mechanism and generate a starting signal and a bias voltage. The nanoampere current reference circuit uses two MOSFETs operating in a deep linear region to replace the resistor, reducing power consumption while generating a reference current. The voltage generation circuit uses multiple sets of cascaded PTAT circuits to offset the negative temperature coefficient generated by bipolar transistors and obtain a reference voltage that does not change with temperature.

2. The self-starting, ultra-low power consumption, low temperature drift, resistor-free bandgap reference voltage source according to claim 1, characterized in that: The self-starting circuit includes a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M12, and a PMOS transistor M13; the sources of the PMOS transistor M1, the PMOS transistor M2, the PMOS transistor M12, and the PMOS transistor M13 are all connected to the AVDD power supply; The gate of the PMOS transistor M1 is connected to the gates of the PMOS transistors M12 and M13 as an output branch EN, the drain of the PMOS transistor M1 is connected to the drain and gate of the NMOS transistor M3; the source of the NMOS transistor M3 is connected to the drain and gate of the NMOS transistor M5; the source of the NMOS transistor M5 is connected to the drain and gate of the NMOS transistor M7; the source of the NMOS transistor M7 is connected to the drain and gate of the NMOS transistor M9; the source of the NMOS transistor M9 is connected to the AVSS ground, and the gate of the NMOS transistor M9 is connected to the gate of the NMOS transistor M10 and the gate of the NMOS transistor M17 respectively; The drain of the PMOS transistor M2 is connected to the source of the PMOS transistor M4; the drain of the PMOS transistor M4 is connected to the source of the PMOS transistor M6; the drain of the PMOS transistor M6 is connected to the source of the PMOS transistor M8; the drain of the PMOS transistor M8 is respectively connected to the drain of the NMOS transistor M10 and the gate of the NMOS transistor M11; the source of the NMOS transistor M10 and the source of the NMOS transistor M11 are connected to the AVSS ground; the drain of the NMOS transistor M11 is connected to the input start signal EN; the PMOS transistors M2, M4, M6, and M8 constitute a group of continuously conducting PMOS transistors, and their gates are all connected to the AVSS ground; The drain of the PMOS transistor M12 is connected to the source of the PMOS transistor M14; the drain of the PMOS transistor M14 is connected to the source of the PMOS transistor M16 and the gate of the PMOS transistor M15; the drain of the PMOS transistor M16 is connected to the drain of the NMOS transistor M17; the source of the NMOS transistor M17 is connected to the AVSS ground; The drain of the PMOS tube M13 is connected to the source of the PMOS tube M15; the drain of the PMOS tube M15 is connected to the nanoampere current reference circuit and the voltage generating circuit as an output branch VN1; the gates of the PMOS tubes M14 and M16 are connected to the nanoampere current reference circuit as output branches VP1.

3. The self-starting, ultra-low power consumption, low temperature drift, resistor-free bandgap reference voltage source according to claim 1, characterized in that: The nanoampere current reference circuit includes a PMOS transistor M19 and a PMOS transistor M20 operating in a deep linear region, and a PMOS transistor M18 and an NMOS transistor M25 operating in a subthreshold region. The source of the PMOS tube M18 is connected to the AVDD power supply, the gate of the PMOS tube M18 is connected to the input start signal EN, and the drain of the PMOS tube M18 is respectively connected to the source of the PMOS tube M19, the PMOS tube M21, the PMOS tube M20, and the PMOS tube M29; the gate and drain of the PMOS tube M21 are connected together, respectively connected to the gate of the PMOS tube M22, the gate of the PMOS tube M29, and the source of the PMOS tube M23, and connected to the voltage generating circuit as the output branch VBIAS1; the gate and drain of the PMOS tube M23 are connected together, respectively connected to The gate of the PMOS transistor M24 and the drain of the NMOS transistor M25 are connected to the voltage generating circuit as an output branch VBIAS2; the gate of the NMOS transistor M25 is respectively connected to the gate and drain of the NMOS transistor M26 and the gate of the NMOS transistor M34, and the source of the NMOS transistor M25 is connected to the drain of the NMOS transistor M27; the source of the NMOS transistor M27 is connected to the AVSS ground, and the gate of the NMOS transistor M27 is respectively connected to the gate and drain of the NMOS transistor M28, the source of the NMOS transistor M26, and the gate of the NMOS transistor M37, and is connected to the voltage generating circuit as an output branch VN1; The drain of the PMOS transistor M19 is connected to the source of the PMOS transistor M22. The gate of the PMOS transistor M19 is connected to the gate and drain of the PMOS transistor M30, the drain of the NMOS transistor M32, and the input branch VP1. The drain of the PMOS transistor M22 is connected to the source of the PMOS transistor M24. The source of the NMOS transistor M28 is connected to the AVSS ground; The drain of the PMOS transistor M29 is respectively connected to the source of the PMOS transistor M30 and the source of the PMOS transistor M31; the drain of the PMOS transistor M31 is respectively connected to the drain and gate of the NMOS transistor M33 and the gate of the NMOS transistor M32; the gate of the PMOS transistor M31 is respectively connected to the drain and gate of the PMOS transistor M29 and the drain of the NMOS transistor M34; the source of the NMOS transistor M32 is connected to the drain of the NMOS transistor M35; the source of M33 is respectively connected to the gate and drain of the NMOS transistor M36 and the gate of the NMOS transistor M35; the gate of the NMOS transistor M35 is respectively connected to the drain and gate of the NMOS transistor M36 and the source of the NMOS transistor M33; the source of the NMOS transistor M35 is connected to the AVSS ground; the source of the NMOS transistor M36 is connected to the AVSS ground; the source of the NMOS transistor M34 is connected to the drain of the NMOS transistor M37; the source of the NMOS transistor M37 is connected to the AVSS ground.

4. The self-starting, ultra-low power consumption, low temperature drift, resistor-free bandgap reference voltage source according to claim 1, characterized in that: The voltage generating circuit includes a voltage dividing branch and six groups of cascade-connected PTAT circuits, and the output branch of the last stage PTAT is VREF; The source of the PMOS tube M38 is connected to the AVDD power supply, the gate of the PMOS tube M38 is connected to the input start signal EN, and the drain of the PMOS tube M38 is respectively connected to the source of the PMOS tube M39 and 6 groups of PTAT circuits; the gate of the PMOS tube M39 is connected to the input branch VBIAS1, and the drain of the PMOS tube M39 is connected to the source of the PMOS tube M40; the gate of the PMOS tube M40 is connected to the input branch VBIAS2, and the drain of the PMOS tube M40 is respectively connected to the emitter of the NPN tube Q1 and the output branch VBE of the PTAT circuit; the base and collector of the NPN bipolar transistor Q1 are connected to the AVSS ground.

5. The self-starting, ultra-low power consumption, low temperature drift, resistor-free bandgap reference voltage source according to claim 4, characterized in that: The PTAT circuit includes a PMOS tube M41 and a PMOS tube M42; The source of the PMOS tube M41 is connected to the drain of M38, the gate and drain of the PMOS tube M41 are connected together, and are respectively connected to the gate of M42 and the source of the PMOS tube M43; the source of the PMOS tube M42 is connected to the drain of M38, and the drain of the PMOS tube M42 is connected to the source of the PMOS tube M44; the gate and drain of the PMOS tube M43 are connected together, and are respectively connected to the gate of the PMOS tube M44 and the drain of the NMOS tube M45; the drain of the PMOS tube M44 is respectively connected to the gate of the PMOS tube M44 and the drain of the NMOS tube M45. The gate and drain of the NMOS transistor M46 are connected and serve as the first output branch of the PTAT circuit; the gate of the NMOS transistor M45 is connected to the output branch VBE of the voltage divider and serves as the first input branch of the PTAT circuit; the source of the NMOS transistor M45 and the source of the NMOS transistor M46 are connected to the drain of the NMOS transistor M47; the gate of the NMOS transistor M47 is connected to the input branch VN1 and serves as the second input branch of the PTAT circuit; the source of the NMOS transistor M47 is connected to the AVSS ground.

6. The self-starting, ultra-low power consumption, low temperature drift, resistor-free bandgap reference voltage source according to claim 1, characterized in that: The self-starting, ultra-low power consumption, low temperature drift, and resistor-free bandgap reference voltage source generates a reference current of: Among them, μC OX K M19 is the current gain of M19, K Mi is the aspect ratio of Mi (K 31 >K 30 ,K 22 >K 21 ), μ is the electron mobility; C OX is the gate oxide capacitance; η is the subthreshold slope factor; V T =(k B T / q) is the thermal voltage, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge; I0 is the subthreshold current exponential factor.

7. The self-starting, ultra-low power consumption, low temperature drift, resistor-free bandgap reference voltage source according to claim 1, characterized in that: The output reference voltage of the self-starting, ultra-low power consumption, low temperature drift, and resistor-free bandgap reference voltage source is: In BE =V BGR -γT Among them, V BE is the bipolar transistor voltage; V BGR is the bandgap voltage of silicon; γ is V BE The temperature coefficient of; N is the number of groups of PTAT circuit; is the total gate voltage; K Dj is the width-to-length ratio of the differential pair.

8. The self-starting, ultra-low power consumption, low temperature drift, resistor-free bandgap reference voltage source according to claim 1, characterized in that: The temperature coefficient of the self-starting, ultra-low power consumption, low temperature drift, resistor-free bandgap reference voltage source is: Where, ΔV REF is the change in the reference voltage within the temperature range; ΔT is the temperature range; Average (ΔV REF ) is the average value of the reference voltage within the varying temperature range.

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