Semiconductor structure and forming method thereof
By using hybrid bonding technology in the semiconductor structure, the peeling layer and substrate are removed to form a structure of metal interconnection devices and traditional silicon-based devices, solving the problems of complex and high cost in traditional processes and achieving a high integration and low cost semiconductor structure.
Patent Information
- Application Number
- CN202410218670.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-27
- Publication Date
- 2025-08-29
AI Technical Summary
The traditional metal interconnect structure has complex processes and high costs, which is difficult to meet the needs of high-integration 3D chips, and the traditional bonding technology has high costs and complex processes.
Using hybrid bonding technology, a release layer is formed on the first substrate. After bonding, the release layer and substrate are removed to form a structure between a metal interconnection device and a traditional silicon-based device, simplifying the process flow and avoiding the through-silicon process.
A highly integrated semiconductor structure is realized, process flow is simplified, costs are reduced, and compatibility and performance are improved.
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Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink, and the density of device interconnections continues to increase. Traditional silicon-based structures and metal interconnect structures are becoming increasingly diverse, especially with the emergence of multiple metal devices in the metal layer. Due to the increasing process requirements and complexity of metal devices, traditional metal interconnect structures, which typically form a dielectric layer on a substrate and metal interconnect lines within the dielectric layer, are gradually becoming unsuitable for the development of metal device technology. They are difficult to process, have complex process flows, and face increasing compatibility challenges. In the future, they will not be able to meet the needs of process development.
[0003] To address these issues, hybrid bonding technology can be used to bond traditional silicon-based devices to metal interconnects. Currently, after wafer-to-wafer bonding, through-silicon vias (TSVs) are typically opened on the back of the bonded wafers to further connect the circuits. However, traditional substrate-based bonding technology is costly and complex for metal device bonding.
[0004] Therefore, there is an urgent need to provide a semiconductor structure and a method for forming the same, which can form a structure in which traditional silicon-based devices are only connected to metal interconnect devices, so as to form a highly integrated 3D chip structure with simple process, high compatibility and lower cost. Summary of the Invention
[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can form a structure in which traditional silicon-based devices are only connected to metal interconnect devices, so as to form a highly integrated 3D chip structure with simple process, high compatibility and lower cost.
[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a first substrate; forming a peeling layer on the first substrate; forming a first interconnection layer on the surface of the peeling layer, the interconnection layer including a peeling surface in contact with the peeling layer; providing a second wafer; bonding the first substrate to the second wafer so that the first interconnection layer is in contact with the surface of the second wafer; after bonding the first substrate to the second wafer, removing the peeling layer and the first substrate to expose the peeling surface; and forming a liner layer located within the first interconnection layer on the peeling surface.
[0007] Optionally, before forming the stripping layer on the first substrate, the method further includes: forming a buffer layer on the surface of the first substrate.
[0008] Optionally, the method of forming the lift-off layer on the first substrate includes at least one of a chemical vapor deposition process, a physical vapor deposition process and an atomic layer deposition process.
[0009] Optionally, the material of the peeling layer includes silicon carbide.
[0010] Optionally, the peeling layer has a thickness of 1000 angstroms to 1500 angstroms.
[0011] Optionally, the release layer and the first substrate are removed by applying a mechanical force to the release layer.
[0012] Optionally, the magnitude of the applied mechanical force is 10N to 50N.
[0013] Optionally, the peeling layer and the first substrate are removed by heat treating the peeling layer.
[0014] Optionally, the heat treatment temperature is 300°C to 1000°C.
[0015] Optionally, the first interconnection layer includes a first dielectric layer and a first electrical interconnection structure located in the first dielectric layer.
[0016] Optionally, after removing the stripping layer and the first substrate, the method further includes: etching to remove the stripping layer remaining on the first dielectric layer; and performing a planarization process on the first dielectric layer.
[0017] Optionally, the second wafer includes a second substrate and a device layer located on the second substrate. After the first substrate is bonded to the second wafer, the first electrical interconnection structure is electrically connected to the device layer.
[0018] Optionally, the device layer includes a device structure located on the second substrate, a second dielectric layer located on the device structure, and a second electrical interconnection structure located in the second dielectric layer, wherein the second electrical interconnection structure is electrically connected to the device structure.
[0019] Optionally, after the first substrate is bonded to the second wafer, the first electrical interconnection structure and the second electrical interconnection structure are electrically connected.
[0020] Optionally, the method for forming the liner layer includes: etching the first dielectric layer to form an opening in the first dielectric layer, wherein the opening exposes a portion of the first electrical interconnection structure; and forming the liner layer in the opening.
[0021] Correspondingly, the present invention also provides a semiconductor structure, including: a second wafer, the second wafer including a second substrate and a device layer located on the second substrate; a first interconnection layer, the first interconnection layer is bonded to the second wafer, and the first interconnection layer is in contact with the surface of the second wafer; and a liner layer, the liner layer is located in the first interconnection layer.
[0022] Optionally, the first interconnection layer includes a first dielectric layer and a first electrical interconnection structure located in the first dielectric layer, and the liner layer is connected to the first electrical interconnection structure.
[0023] Optionally, the device layer includes a device structure located on the second substrate, a second dielectric layer located on the device structure, and a second electrical interconnection structure located in the second dielectric layer, wherein the second electrical interconnection structure is connected to the device structure.
[0024] Optionally, after the first interconnect layer is bonded to the second wafer, the first electrical interconnect structure and the second electrical interconnect structure are connected.
[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0026] The method for forming a semiconductor structure provided by the present technical solution can form a structure in which a metal interconnect device is bonded to a traditional silicon-based device. By providing a peeling layer on the first substrate, after the first substrate is bonded to the second wafer, the first substrate is removed by removing the peeling layer. There is no need to perform process flows such as wafer thinning and etching the substrate to form through holes, which simplifies the process flow and can form a highly integrated semiconductor structure with high compatibility and lower cost.
[0027] The semiconductor structure provided by this technical solution includes a first interconnect layer and a second wafer bonded to each other, and a liner layer located within the first interconnect layer. The liner layer does not require a through-silicon via (TSV) process, resulting in a simple structure that helps improve the integration and performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figures 1 to 9 It is a structural schematic diagram corresponding to each step of the semiconductor structure formation process in one embodiment of the present invention. DETAILED DESCRIPTION
[0029] As described in the background technology, with the continuous development of semiconductor technology, metal interconnect structures are becoming more and more complex. Compared with the traditional stacking method to form metal interconnect structures, hybrid bonding technology can be used to bond metal interconnect devices to traditional silicon-based devices. The current bonding process usually includes a substrate. When forming the interconnect structure, silicon vias are opened on the back of the bonded wafer, and the circuit connection is further realized through silicon via technology. However, due to the micron-level depth of the silicon via, the area occupied by the silicon via on the wafer surface is large, resulting in poor integration of the semiconductor structure. At the same time, the formation of silicon vias also increases the process difficulty and the complexity of the process flow.
[0030] To address the above-mentioned issues, an embodiment of the present invention provides a semiconductor structure and a method for forming the same. A first substrate and a second wafer to be bonded are provided, wherein the first substrate has a peeling layer. After the first substrate and the second wafer are bonded, the peeling layer is removed, thereby removing the first substrate above the peeling layer. When an interconnection structure is subsequently required, an opening is directly formed within the first dielectric layer to expose the first electrical interconnection structure. A liner layer is then formed within the opening. The liner layer can be used to subsequently connect other circuits. The technical solution provided by the present invention eliminates the need to etch the substrate to form a through hole and then form a liner layer. This simplifies the process and is beneficial for improving the integration of the semiconductor structure. Furthermore, the removed first substrate is intact and can be reused, which is beneficial for saving materials.
[0031] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0032] Figures 1 to 9 It is a structural schematic diagram corresponding to each step of the semiconductor structure formation process in one embodiment of the present invention.
[0033] Providing a first wafer, specifically providing the first wafer includes: referring to Figure 1 , providing a first substrate 100.
[0034] In this embodiment, the material of the first substrate 100 is silicon; in other embodiments, the material of the first substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.
[0035] After providing the first substrate 100 , a peeling layer is formed on the first substrate 100 .
[0036] refer to Figure 2 In this embodiment, before forming the peeling layer, a buffer layer 101 is first formed on the surface of the first substrate 100 .
[0037] In this embodiment, the buffer layer 101 is used to increase the adhesion between the release layer and the first substrate 100 .
[0038] In this embodiment, the buffer layer 101 is made of silicon dioxide.
[0039] Continue to refer Figure 2 , a peeling layer 102 is formed on the surface of the buffer layer 101.
[0040] In this embodiment, the material of the peeling layer 102 is silicon carbide; in other embodiments, the material of the peeling layer 102 may also be other brittle materials or materials that are prone to phase change.
[0041] The peeling layer 102 is made of a brittle material, which is easily broken under external influences and has poor adhesion to other material layers. After the first wafer and the second wafer are bonded, the peeling layer located between the first substrate 100 and the first dielectric layer is broken, thereby separating the first substrate 100 and the first dielectric layer. The first substrate 100 can be removed as a whole without affecting reuse, which is beneficial to saving materials and costs.
[0042] The peeling layer 102 is made of a material that is easy to undergo phase change and can undergo phase change under heat treatment, for example, from solid to liquid, gas, etc., so that the peeling layer can be peeled off.
[0043] The method of forming the lift-off layer 102 includes at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.
[0044] The thickness of the peeling layer 102 is 1000 to 1500 angstroms. The thickness of the peeling layer 102 should not be too thick, as this will make subsequent removal of the peeling layer 102 more difficult. The thickness of the peeling layer 102 should not be too thin, as this will make the peeling layer 102 too fragile and likely break before bonding is completed, preventing the normal process steps.
[0045] A first interconnection layer is formed on the surface of the peeling layer 102 , wherein the first interconnection layer includes a peeling surface in contact with the peeling layer 102 .
[0046] In this embodiment, the first interconnection layer includes a first dielectric layer and a first electrical interconnection structure located in the first dielectric layer. Specifically, the surface of the first dielectric layer in contact with the peeling layer 102 is a peeling surface.
[0047] refer to Figure 3 A first dielectric layer 103 is formed on the peeling layer 102 , and the first dielectric layer 103 is used for electrical insulation between first electrical interconnection layers formed subsequently.
[0048] The method of forming the first dielectric layer 103 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
[0049] The material of the first dielectric layer 103 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first dielectric layer 103 is silicon oxide.
[0050] refer to Figure 4 , forming a first electrical interconnection structure in the first dielectric layer 103 .
[0051] In this embodiment, the first electrical interconnection structure includes several first conductive layers 104 and first conductive plugs 105 connecting the first conductive layers 104 .
[0052] In this embodiment, the first conductive layer 104 has a three-layer structure. In other embodiments, the number of layers of the first conductive layer 104 can be adjusted according to actual circuit design requirements, so there is no requirement for the number of layers of the first conductive layer 104 .
[0053] The material of the first conductive layer includes metal, and the metal includes one or more combinations of copper, aluminum, tungsten, nickel, and tantalum.
[0054] Continue to refer Figure 4 In this embodiment, the first wafer includes a first surface 100a and a second surface 100b opposite to each other. The first substrate 100 is close to the first surface 100a, and the second surface 100b is used for bonding with the second wafer. Figure 5 , providing a second wafer, wherein the second wafer includes a third surface 200a and a fourth surface 200b opposite to each other, and the fourth surface 200b is used for bonding with the first wafer.
[0055] Continue to refer Figure 5 The second wafer includes: a second substrate 200 and a device layer located on the second substrate 200, and the second substrate 200 is close to the side of the third surface 200a.
[0056] In this embodiment, the device layer includes: a device structure 201, wherein the device structure 201 is located on the second substrate 200; a second dielectric layer 202, wherein the second dielectric layer 202 is located on the device structure 201; and a second electrical interconnection structure, wherein the second electrical interconnection structure is located in the second dielectric layer 202 and is electrically connected to the device structure 201.
[0057] In this embodiment, after the first substrate 100 is bonded to the second wafer, the first electrical interconnection structure is electrically connected to the second electrical interconnection structure.
[0058] In this embodiment, the material of the second substrate 200 is silicon; in other embodiments, the material of the second substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.
[0059] The device structure 201 includes one or more combinations of transistors, diodes, triodes, capacitors, inductors, and conductive structures. Therefore, the specific structure of the device structure 201 is not required.
[0060] The material of the second dielectric layer 202 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, and silicon carbonitride oxynitride. In this embodiment, the material of the second dielectric layer 202 is silicon oxide.
[0061] In this embodiment, the second dielectric layer 202 is used for electrical insulation between the device structure 201 and the second electrical interconnection structure.
[0062] In this embodiment, the second electrical interconnection structure includes a plurality of second conductive layers 203 and second conductive plugs 204 connecting the second conductive layers 203 .
[0063] The number of the second conductive layer 203 can be adjusted according to actual circuit design requirements, so there is no requirement for the number of the second conductive layer 203. In this embodiment, different second conductive layers 203 are electrically interconnected through second conductive plugs 204 according to actual circuit design requirements.
[0064] refer to Figure 6 , bonding is performed with the second surface 100b of the first wafer facing the fourth surface 200b of the second wafer.
[0065] In this embodiment, hybrid bonding is used to achieve bonding between the first wafer and the second wafer.
[0066] In this embodiment, after the first wafer and the second wafer are bonded, the second electrical interconnection structure is electrically connected to the first electrical interconnection structure.
[0067] refer to Figure 7 , remove the peeling layer 102 and the first substrate 100.
[0068] In this embodiment, the peeling layer 102 is mainly removed, and the first substrate 100 is bonded to the peeling layer 102 via the buffer layer 101 , so when the peeling layer 102 is removed, the first substrate 100 is removed along with the peeling layer 102 .
[0069] Since the peeling layer 102 is made of a brittle material, in this embodiment, a mechanical force is applied to the peeling layer 102 to remove the peeling layer 102 .
[0070] The magnitude of the applied mechanical force is 10 N to 50 N. The applied mechanical force cannot be too large, otherwise it will easily damage other device layers; nor can it be too small, otherwise it will not be able to break the peeling layer 102.
[0071] In other embodiments, the peeling layer 102 may be removed by heat treatment, where the material of the peeling layer undergoes a phase change through heat treatment, thereby removing the peeling layer.
[0072] When heat treatment is used, the temperature is between 300° C. and 1000° C. The temperature and duration of the heat treatment should not be too high or too long, otherwise other semiconductor structures may be adversely affected. The temperature and duration of the heat treatment should not be too low or too short, otherwise the peeling layer 102 may not be broken.
[0073] like Figure 7 As shown, after the peeling layer 102 and the first substrate 100 are removed, a portion of the peeling layer 102 remains on the peeling surface of the first dielectric layer 103 .
[0074] refer to Figure 8 , remove the remaining peeling layer 102, and planarize the peeling surface of the first dielectric layer 103.
[0075] In this embodiment, a dry etching process is used to remove the remaining peeling layer 102 ; in other embodiments, a wet etching process or a mixed process of dry and wet etching may also be used to remove the remaining peeling layer 102 .
[0076] After removing the remaining peeling layer 102 , in this embodiment, a chemical mechanical polishing process is used to planarize the first dielectric layer 103 .
[0077] refer to Figure 9 , an opening (not marked in the figure) is formed in the first dielectric layer 103, wherein the opening exposes a portion of the topmost first conductive layer 104; and a liner layer 106 is formed in the opening.
[0078] The pad layer 106 is used to connect the first conductive layer 104 with other circuits.
[0079] The material of the liner layer 106 includes metal, and the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum. In this embodiment, the material of the liner layer 106 is aluminum.
[0080] Correspondingly, an embodiment of the present invention further provides a semiconductor structure.
[0081] refer to Figure 9The semiconductor structure includes: a second wafer, the second wafer includes a second substrate 200 and a device layer located on the second substrate 200; a first interconnection layer, the first interconnection layer is bonded to the second wafer, and the first interconnection layer is in contact with the surface of the second wafer; a liner layer 106, and the liner layer 106 is located in the first interconnection layer.
[0082] The first interconnection layer includes a first dielectric layer 103 and a first electrical interconnection structure located in the first dielectric layer 103 , and the liner layer 106 is connected to the first electrical interconnection structure.
[0083] In this embodiment, the first electrical interconnection structure includes several first conductive layers 104 and first conductive plugs 105 connecting the first conductive layers 104 .
[0084] In this embodiment, the first conductive layer 104 has a three-layer structure. In other embodiments, the number of layers of the first conductive layer 104 can be adjusted according to actual circuit design requirements, so there is no requirement for the number of layers of the first conductive layer 104 .
[0085] The device layer includes a device structure 201 located on the second substrate 200 , a second dielectric layer 202 located on the device structure 201 , and a second electrical interconnection structure located in the second dielectric layer 202 , wherein the second electrical interconnection structure is connected to the device structure 201 .
[0086] The device structure 201 includes one or more combinations of transistors, diodes, triodes, capacitors, inductors, and conductive structures. Therefore, the specific structure of the device structure 201 is not required.
[0087] After the first interconnect layer is bonded to the second wafer, the first electrical interconnect structure and the second electrical interconnect structure are connected.
[0088] In this embodiment, the second electrical interconnection structure includes a plurality of second conductive layers 203 and second conductive plugs 204 connecting the second conductive layers 203 .
[0089] The number of layers of the second conductive layer 203 can be adjusted according to actual circuit design requirements, so there is no requirement for the number of layers of the second conductive layer 203 .
[0090] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a first substrate; forming a peeling layer on the first substrate; forming a first interconnection layer on the surface of the peeling layer, wherein the first interconnection layer includes a peeling surface in contact with the peeling layer; providing a second wafer; bonding the first substrate to the second wafer so that the first interconnect layer contacts the surface of the second wafer; After bonding the first substrate to the second wafer, removing the peeling layer and the first substrate to expose the peeling surface; A liner layer is formed on the peeling surface within the first interconnect layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the peeling layer on the first substrate, the method further includes: forming a buffer layer on the surface of the first substrate.
3. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming the lift-off layer on the first substrate includes at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.
4. The method for forming a semiconductor structure according to claim 1, wherein: The material of the lift-off layer includes silicon carbide.
5. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the peeling layer is 1000 angstroms to 1500 angstroms.
6. The method for forming a semiconductor structure according to claim 1, wherein: The peeling layer and the first substrate are removed by applying a mechanical force to the peeling layer.
7. The method for forming a semiconductor structure according to claim 6, wherein: The magnitude of the applied mechanical force is 10N to 50N.
8. The method for forming a semiconductor structure according to claim 1, wherein: The peeling layer and the first substrate are removed by heat treating the peeling layer.
9. The method for forming a semiconductor structure according to claim 8, wherein: The temperature of the heat treatment is 300°C to 1000°C.
10. The method for forming a semiconductor structure according to claim 1, wherein: The first interconnect layer includes a first dielectric layer and a first electrical interconnect structure located in the first dielectric layer.
11. The method for forming a semiconductor structure according to claim 10, wherein: After removing the stripping layer and the first substrate, the method further includes: etching to remove the stripping layer remaining on the first dielectric layer; and performing a planarization process on the first dielectric layer.
12. The method for forming a semiconductor structure according to claim 10, wherein: The second wafer includes a second substrate and a device layer located on the second substrate. After the first substrate and the second wafer are bonded, the first electrical interconnection structure is electrically connected to the device layer.
13. The method for forming a semiconductor structure according to claim 12, wherein: The device layer includes a device structure located on the second substrate, a second dielectric layer located on the device structure, and a second electrical interconnection structure located in the second dielectric layer, wherein the second electrical interconnection structure is electrically connected to the device structure.
14. The method for forming a semiconductor structure according to claim 13, wherein: After the first substrate is bonded to the second wafer, the first electrical interconnection structure and the second electrical interconnection structure are electrically connected.
15. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the liner layer includes: etching the first dielectric layer to form an opening in the first dielectric layer, wherein the opening exposes a portion of the first electrical interconnection structure; and forming the liner layer in the opening.
16. A semiconductor structure, characterized in that include: a second wafer, the second wafer comprising a second substrate and a device layer located on the second substrate; a first interconnect layer, the first interconnect layer being bonded to the second wafer, the first interconnect layer being in contact with a surface of the second wafer; A liner layer is located in the first interconnect layer.
17. The semiconductor structure according to claim 16, wherein: The first interconnection layer includes a first dielectric layer and a first electrical interconnection structure located in the first dielectric layer, and the liner layer is connected to the first electrical interconnection structure.
18. The semiconductor structure according to claim 17, wherein: The device layer includes a device structure located on the second substrate, a second dielectric layer located on the device structure, and a second electrical interconnection structure located in the second dielectric layer, wherein the second electrical interconnection structure is connected to the device structure.
19. The semiconductor structure according to claim 18, wherein: After the first interconnect layer is bonded to the second wafer, the first electrical interconnect structure and the second electrical interconnect structure are connected.