Overvoltage surge suppression circuit and method for airborne direct-current power supply

Abstract

The invention discloses an airborne DC power supply overvoltage surge suppression circuit and method, the overvoltage surge suppression circuit comprises a power MOSFET, a control chip, a voltage sampling feedback circuit, a delay turn-off circuit and a surge current suppression circuit, the input end of the control chip is connected to the power supply input end, and the output end of the control chip is connected to the grid electrode of the power MOSFET; the voltage sampling feedback circuit is used for detecting output voltage and feeding back the output voltage to an FB pin of the control chip; the delay turn-off circuit is used for setting delay turn-off time in an overvoltage surge period; the surge current suppression circuit comprises a current sampling resistor R1 connected in a power loop in series and a large-resistance resistor connected to a grid electrode of the power MOSFET in parallel, the normal working condition efficiency is improved by more than 15% compared with that of a traditional scheme, the output voltage is stable (30V + / -2%) in the overvoltage period, and 200W is continuously output.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply protection, and more particularly to an airborne direct current power supply overvoltage surge suppression circuit and method. Background Art

[0002] In the general DC power supply design process, for the suppression of surge voltage, although the peak voltage value is relatively high, the time is short and the energy is small, which can be achieved by using a simple voltage clamping circuit, such as using transient voltage suppression diodes, varistors and other pressure-sensitive components to achieve voltage clamping. Of course, Buck-Boost circuits can also be used.

[0003] However, the overvoltage surge curves for airborne DC power supplies are Curves 1 and 2 as specified in GJB181-1986. These curves require 28V-powered electronic devices to withstand an 80V, 50ms overvoltage surge. These surges are high in voltage and long in duration. Using traditional varistor devices with a load at the power supply output can damage the input fuse, causing the power supply to malfunction during the overvoltage surge. While a buck-boost circuit can ensure output voltage stability during surges, it cannot meet the requirements of specialized applications, such as those requiring the output voltage to track the input voltage and requiring high conversion efficiency within the normal input voltage range. Summary of the Invention

[0004] The purpose of the present invention is to provide an airborne DC power supply overvoltage surge suppression circuit and method to solve the problems raised in the above background technology.

[0005] To achieve the above objectives, the present invention is implemented through the following technical means:

[0006] An airborne DC power supply overvoltage surge suppression circuit, comprising:

[0007] A power MOSFET (Q1) is connected between the power input terminal (28VI+) and the output terminal (28VO+) and is used to switch between the on, amplification, or off state according to the drive signal;

[0008] A control chip U1, whose input terminal is connected to the power input terminal and whose output terminal is connected to the gate of the power MOSFET;

[0009] A voltage sampling feedback circuit is used to detect the output voltage and feed it back to the FB pin of the control chip;

[0010] A time-delayed shutdown circuit, comprising a capacitor C5 connected to the TMR lead of the control chip, for setting a delayed shutdown time during an overvoltage surge;

[0011] The inrush current suppression circuit includes a current sampling resistor R1 connected in series in the power loop and a large resistance resistor connected in parallel to the gate of the power MOSFET;

[0012] The control chip U1 dynamically adjusts the working state of the power MOSFET according to the input voltage:

[0013] When the input voltage is ≤28V, the power MOSFET is controlled to be fully turned on, so that the output voltage follows the input voltage;

[0014] When the input voltage exceeds the set threshold, the power MOSFET is adjusted to the amplified state, the output voltage is clamped to the preset value, and the delayed shutdown logic is activated;

[0015] At the moment the power is turned on, the inrush current is limited by the inrush current suppression circuit.

[0016] Furthermore, the power dissipation (PD) of the power MOSFET (Q1) is ≥200W, and the safe operating area (SOA) meets the energy absorption requirement under 80V / 50ms surge conditions.

[0017] Furthermore, the capacitance of the capacitor C5 in the delayed shutdown circuit is 10 μF-100 μF, corresponding to a delayed shutdown time of 50 ms-500 ms.

[0018] Furthermore, the voltage sampling feedback circuit sets the clamping voltage value to 30V±5% through a voltage-dividing resistor network.

[0019] Furthermore, it also includes an input reverse connection protection circuit, which adopts a fast recovery diode or a back-to-back MOSFET structure.

[0020] Furthermore, the control chip U1 automatically resets the power MOSFET to the on state after the overvoltage surge ends.

[0021] A method for suppressing overvoltage surges of an airborne DC power supply comprises the following steps:

[0022] Detect the input voltage. If it is within the normal range ≤ 28V, control the power MOSFET to be fully turned on so that the output voltage follows the input voltage.

[0023] When the input voltage is detected to be over 80V, the power MOSFET is adjusted to the amplification state, the output voltage is clamped to the preset value, and the delay timer is started;

[0024] If the overvoltage lasts for 50ms, the power MOSFET is turned off to protect the circuit.

[0025] When the power supply starts, the inrush current is limited by the current sampling resistor R1 and the gate parallel resistor.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The efficiency of the present invention under normal working conditions is improved by more than 15% compared with the traditional solution. The output voltage is stable (30V±2%) during overvoltage, and the continuous output is 200W. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of the principle of an embodiment of the present invention;

[0029] Figure 2 The present invention discloses an 80V overvoltage surge suppression circuit for an airborne 28V input DC power supply. DETAILED DESCRIPTION

[0030] The following detailed description of the embodiments of the technical solution of this application is provided in conjunction with the accompanying drawings. The following embodiments and drawings are intended only to more clearly illustrate the technical solution of this application and are therefore provided as examples only and are not intended to limit the scope of protection of this application. The accompanying drawings schematically illustrate only the parts relevant to the technical solution of this application and do not represent the actual structure of the product.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0032] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are used only to distinguish different objects and should not be understood as indicating or implying relative importance or implicitly indicating the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two), similarly, "multiple groups" refers to more than two (including two), and "multiple pieces" refers to more than two (including two).

[0033] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0034] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0035] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limiting the embodiments of the present application.

[0036] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0037] In the general DC power supply design process, for the suppression of surge voltage, although the peak voltage value is relatively high, the time is short and the energy is small, which can be achieved by using a simple voltage clamping circuit, such as using transient voltage suppression diodes, varistors and other pressure-sensitive components to achieve voltage clamping. Of course, Buck-Boost circuits can also be used.

[0038] However, for airborne DC power supplies, the overvoltage surge curves are curves 1 and 2 specified in GJB181-1986. This requires that 28V-powered electronic equipment withstand an 80V, 50ms overvoltage surge. This surge voltage is high and lasts for a long time. Using traditional varistor devices with a load at the power output can damage the fuse at the input, causing the power supply to malfunction during the overvoltage surge. If a buck-boost circuit is used, while it can ensure output voltage stability during surges, it cannot meet the needs of some special application scenarios, such as those requiring the output voltage to follow the input voltage and requiring high conversion efficiency within the normal voltage input range. A TVS diode (such as the SMBJ80A) experiences a junction temperature rise of 200°C under a 50ms surge, causing permanent damage. The junction capacitance (>2000pF) of a varistor (such as the 14D820K) causes a reverse recovery current peak of 50A or higher. Consequently, the efficiency of the buck-boost circuit drops to 88%-92% at a 200W load, and input voltage tracking is no longer possible.

[0039] In this embodiment, an airborne DC power supply overvoltage surge suppression circuit includes:

[0040] A power MOSFET (Q1) is connected between the power input terminal (28VI+) and the output terminal (28VO+) and is used to switch between the on, amplification, or off state according to the drive signal;

[0041] A control chip U1, whose input terminal is connected to the power input terminal and whose output terminal is connected to the gate of the power MOSFET;

[0042] A voltage sampling feedback circuit is used to detect the output voltage and feed it back to the FB pin of the control chip;

[0043] A time-delayed shutdown circuit, comprising a capacitor C5 connected to the TMR lead of the control chip, for setting a delayed shutdown time during an overvoltage surge;

[0044] The inrush current suppression circuit includes a current sampling resistor R1 connected in series in the power loop and a large resistance resistor connected in parallel to the gate of the power MOSFET;

[0045] The control chip U1 dynamically adjusts the working state of the power MOSFET according to the input voltage:

[0046] When the input voltage is ≤28V, the power MOSFET is controlled to be fully turned on, so that the output voltage follows the input voltage;

[0047] When the input voltage exceeds the set threshold, the power MOSFET is adjusted to the amplified state, the output voltage is clamped to the preset value, and the delayed shutdown logic is activated;

[0048] At the moment the power is turned on, the inrush current is limited by the inrush current suppression circuit.

[0049] The working principle of the airborne DC power supply overvoltage surge suppression circuit of the present invention is as follows:

[0050] When normal voltage is input: the control chip U1 makes the power MOSFET Q1 fully turned on, supplying power to the load with extremely low power loss, the MOSFET is fully turned on (voltage drop < 0.1V), and the efficiency is > 99%;

[0051] During overvoltage surge: the control chip U1 adjusts the gate drive voltage of Q1 so that it operates in the amplification region, absorbs the surge energy, and clamps the output voltage to the set value. The MOSFET operates in the amplification region, absorbs the surge energy and clamps the output;

[0052] Inrush current suppression: The capacitor C5 is charged by the current source inside the control chip U1, the power circuit is shut down later, and the inrush current when the power supply starts is suppressed. The protection time window is set by the capacitor C5 on the TMR pin.

[0053] During an 80V overvoltage surge, the present invention can clamp the output voltage to a set value to ensure load safety. When the input voltage is lower than the clamping voltage set value, the output voltage is guaranteed to track the input voltage, thereby improving energy efficiency. The present invention integrates input reverse connection protection and surge current suppression functions to improve the reliability and adaptability of the onboard power supply. The circuit structure is simple, with few components, making it easy to design and use.

[0054] Furthermore, the power dissipation (PD) of the power MOSFET (Q1) is ≥200W, and the safe operating area (SOA) meets the energy absorption requirement under 80V / 50ms surge conditions.

[0055] Furthermore, the capacitance of the capacitor C5 in the delayed shutdown circuit is 10 μF-100 μF, corresponding to a delayed shutdown time of 50 ms-500 ms.

[0056] Furthermore, the voltage sampling feedback circuit sets the clamping voltage value to 30V±5% through a voltage-dividing resistor network.

[0057] Furthermore, it also includes an input reverse connection protection circuit, which adopts a fast recovery diode or a back-to-back MOSFET structure.

[0058] Furthermore, the control chip U1 automatically resets the power MOSFET to the on state after the overvoltage surge ends.

[0059] A method for suppressing overvoltage surges of an airborne DC power supply comprises the following steps:

[0060] Detect the input voltage. If it is within the normal range (≤28V), control the power MOSFET to be fully turned on so that the output voltage follows the input voltage.

[0061] When the input voltage is detected to be over 80V, the power MOSFET is adjusted to the amplification state, the output voltage is clamped to the preset value, and the delay timer is started;

[0062] If the overvoltage lasts for 50ms, the power MOSFET is turned off to protect the circuit.

[0063] When the power supply starts, the inrush current is limited by the current sampling resistor R1 and the gate parallel resistor.

[0064] See also Figure 2 , the present invention discloses an 80V overvoltage surge suppression circuit for an airborne 28V input DC power supply;

[0065] In the power input section, 28VI+ is the positive input power supply, and 28VG is the negative input power supply. The positive input power supply terminal 28VI+ is directly connected to one end of resistor R7 and also to one end of the series voltage divider circuit formed by R2 and R3. The other end of R7 is connected to one end of the bidirectional trigger diode D3, and the other end of D3 is connected to the negative input power supply terminal 28VG.

[0066] Chip U1 related connections

[0067] Power supply pin: Pin 14 (VCC) is connected to the power supply to provide operating voltage for the chip.

[0068] Ground pin: Pin 10 (GND) is connected to the negative terminal of the input power supply 28VG to provide a ground reference for the chip.

[0069] Feedback pin: Pin 1 (FB) is connected to the series voltage divider circuit composed of R5 and R10. The connection point of R5 and R10 is also connected to the output voltage terminal 28VO+ through R6, which is used to detect the output voltage and feed it back to the chip to achieve voltage regulation control.

[0070] Output pin: Pin 2 (OUT) is connected to one end of resistor R4, and the other end of R4 is connected to the gate (G pole) of power tube Q2, which is used to output a control signal to drive Q2.

[0071] Detection pin: Pin 3 (SENSE) is connected to one end of resistor R1, and the other end of R1 is connected to the output voltage terminal 28VO+ for detecting output current or other related parameters.

[0072] Low-end gate drive pin: Pin 4 (DGATE) is connected to the gate (G pole) of the power tube Q2 to drive Q2 on and off.

[0073] Source pin: Pin 5 (SOURCE) is connected to the source (S pole) of the power tube Q2 and serves as the reference point for the source signal of the power tube.

[0074] High-side gate drive pin: Pin 6 (HGATE) is connected to the gate (G pole) of the power tube Q1 to drive Q1 on and off.

[0075] Shutdown pin: Pin 7 (SHDN) is connected to one end of resistor R14, and the other end of R14 is connected to the circuit composed of R8, D2 and R9, which can receive an external signal to control the shutdown state of the chip.

[0076] Undervoltage Detection Pin: Pin 8 (UV) is connected to a circuit consisting of R2, R3, V2, and V3, which detects if the input voltage is undervoltage. The junction of R2 and R3 is also connected to the anode of Zener diode V2. The cathode of V2 is connected to the anode of V3, and the cathode of V3 is connected to the negative terminal of the input power supply, 28VG.

[0077] Overvoltage detection pin: Pin 9 (OV) is connected to the circuit consisting of R12, R16, C3, and C4, which detects whether the input voltage is overvoltage. The junction of R12 and R16 is also connected to one end of C3 and C4, and the other end of C3 and C4 is connected to the negative terminal of the input power supply 28VG.

[0078] Fault output pin: Pin 11 (FLT) is connected to the circuit composed of R13, R15, R17 and D4, which can output a fault signal when a fault occurs in the circuit.

[0079] Enable output pin: Pin 12 (ENOUT) is connected to the relevant circuit and is used to output the enable signal.

[0080] Timer pin: Pin 13 (TMR) is connected to one end of capacitor C5, and the other end of C5 is connected to the negative terminal of the input power supply 28VG, which is used to set the internal timer parameters of the chip.

[0081] Power tube part

[0082] Power transistors Q1 and Q2 are N-channel MOSFETs. Q1's drain (D) is connected to the positive input power supply, 28VI+, and its source (S) is connected to Q2's drain (D). Q2's source (S) is connected to the negative output voltage, 28VG. The gates (G) of Q1 and Q2 are driven by pins 6 (HGATE) and 4 (DGATE) of chip U1, respectively. A Zener diode V1 and resistor RP1 are connected between Q1's source and gate to protect and regulate Q1's gate-to-source voltage.

[0083] Output section

[0084] 28VO+ is the positive terminal of the output power supply, and 28VG is the negative terminal of the output power supply. The output end is connected to a voltage divider circuit consisting of resistors R11, R13, R15, and R17. A diode D1 is also connected to protect the output circuit.

[0085] Other component connections

[0086] Capacitors C1 and C2 are connected in parallel across the circuit consisting of R8, D2, and R9 to act as a filter.

[0087] Capacitors C3 and C4 are connected in parallel with resistors R16 and R19 respectively to filter and stabilize the input voltage detection circuit.

[0088] The specific embodiments disclosed in the present invention fall within the scope of protection of the claims of the present invention, and are the specific lower implementation scope of the characteristic part of the present invention. The protection content of the specific embodiments is merely an explanation of the protection scope of the claims of the present invention. The protection scope of the present invention is not limited to the protection content of the specific embodiments, and the protection content of the specific embodiments should not be understood as a limitation on the protection scope of the claims of the present invention.

[0089] The product structure connection relationships that fall within the scope of protection of the present invention shall fall within the protection content of the present invention; without departing from the protection essence of the present invention, conventional technical improvements to the structure of product components, such as improvements to the partial structure of the product in the specific embodiment of the present invention, shall also fall within the protection essence of the present invention.

[0090] The above description is merely illustrative of certain exemplary embodiments of the present invention. It goes without saying that those skilled in the art will be able to modify the described embodiments in various ways without departing from the scope of the present invention. Therefore, the above description is illustrative in nature and should not be construed as limiting the scope of the claims.

[0091] Unless otherwise defined, all academic and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0092] In case of conflict, the definitions in this specification shall prevail.

[0093] Unless otherwise indicated, all percentages, parts, ratios, etc. are by weight.

[0094] When a numerical value or a range of numerical values, a preferred range or a series of lower preferred values ​​and upper preferred values ​​is given, it should be understood that any range formed by any pair of numerical values ​​of any smaller range limit or preferred value and any larger range limit or preferred value is specifically disclosed, regardless of whether the range is disclosed separately. Unless otherwise stated, where a numerical range is described in this specification, the range is intended to include the range endpoints and all integers and fractions within the range.

[0095] When the term "about" or "around" is used in describing a value or an end-point of a range, the disclosure should include the specific value or end-point referred to.

[0096] The use of "a" and "an / kind" to describe elements of the present invention is only for convenience and to give a general view of the present invention. Unless otherwise clearly stated, the description should be understood to include one / kind or at least one / kind.

Claims

1. An airborne DC power supply overvoltage surge suppression circuit, characterized by: include: A power MOSFET (Q1) is connected between the power input terminal (28VI+) and the output terminal (28VO+) and is used to switch between the on, amplification, or off state according to the drive signal; A control chip U1, whose input terminal is connected to the power input terminal and whose output terminal is connected to the gate of the power MOSFET; A voltage sampling feedback circuit is used to detect the output voltage and feed it back to the FB pin of the control chip; A time-delayed shutdown circuit, comprising a capacitor C5 connected to the TMR lead of the control chip, for setting a delayed shutdown time during an overvoltage surge; The inrush current suppression circuit includes a current sampling resistor R1 connected in series in the power loop and a large resistance resistor connected in parallel to the gate of the power MOSFET; The control chip U1 dynamically adjusts the working state of the power MOSFET according to the input voltage: When the input voltage is ≤28V, the power MOSFET is controlled to be fully turned on, so that the output voltage follows the input voltage; When the input voltage exceeds the set threshold, the power MOSFET is adjusted to the amplified state, the output voltage is clamped to the preset value, and the delayed shutdown logic is activated; At the moment the power is turned on, the inrush current is limited by the inrush current suppression circuit.

2. The airborne DC power supply overvoltage surge suppression circuit according to claim 1, characterized in that: The power dissipation power (PD) of the power MOSFET (Q1) is ≥200W, and the safe operating area (SOA) meets the energy absorption requirement under 80V / 50ms surge conditions.

3. The airborne DC power supply overvoltage surge suppression circuit according to claim 1, characterized in that: The capacitance of the capacitor C5 in the delayed shutdown circuit is 10 μF-100 μF, corresponding to a delayed shutdown time of 50 ms-500 ms.

4. The airborne DC power supply overvoltage surge suppression circuit according to claim 1, characterized in that: The voltage sampling feedback circuit sets the clamping voltage value to 30V±5% through a voltage-dividing resistor network.

5. The airborne DC power supply overvoltage surge suppression circuit according to claim 1, characterized in that: It also includes an input reverse polarity protection circuit that uses a fast recovery diode or back-to-back MOSFET structure.

6. The airborne DC power supply overvoltage surge suppression circuit according to claim 1, characterized in that: The control chip U1 automatically resets the power MOSFET to the on state after the overvoltage surge ends.

7. A method for suppressing overvoltage surges in an airborne DC power supply, characterized in that: Detect the input voltage. If it is within the normal range ≤ 28V, control the power MOSFET to be fully turned on so that the output voltage follows the input voltage. When the input voltage is detected to be over 80V, the power MOSFET is adjusted to the amplification state, the output voltage is clamped to the preset value, and the delay timer is started; If the overvoltage lasts for 50ms, the power MOSFET is turned off to protect the circuit. When the power supply starts, the inrush current is limited by the current sampling resistor R1 and the gate parallel resistor.

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