Frequency-locked loop circuit with high power supply rejection ratio and low swing and its control method

Abstract

This invention relates to the field of integrated circuit design, specifically disclosing a frequency-locked loop circuit and its control method with high power supply rejection ratio and low swing drive. By employing a low-dropout linear regulator to provide an independent power supply to the voltage-controlled oscillator (VCO) at a voltage lower than the main power supply voltage, a dual optimization effect is achieved: Firstly, the clean power supply provided by the low-dropout linear regulator effectively isolates the interference of main power supply noise on the VCO, thus significantly enhancing the circuit's power supply noise suppression capability and greatly reducing the jitter of the output clock signal; secondly, by allowing and dynamically adjusting the operating voltage of the VCO to optimize within a lower range that meets performance requirements based on its real-time load, on-demand power supply is achieved, thereby minimizing its dynamic power consumption without reducing output quality and improving the overall circuit's energy efficiency under different load conditions.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a frequency-locked loop circuit with high power supply rejection ratio and low swing drive, and its control method. Background Technology

[0002] Frequency-locked loops (FLLs) and phase-locked loops (PLLs) are core modules in clock generation circuits. However, the performance of these circuits, especially their internal voltage-controlled oscillator (VCO), is susceptible to power supply noise. In some traditional designs, the VCO is directly powered by the system mains power supply (VDD). This approach causes power supply noise to be directly coupled to the VCO's output frequency, resulting in clock signal jitter and affecting system stability.

[0003] To mitigate the impact of power supply noise on VCO performance, several solutions have been proposed in the prior art:

[0004] The first approach is to use a global low-dropout linear regulator to provide low-noise power to the entire frequency-locked loop or phase-locked loop. While this method can suppress some power supply noise to a certain extent, it does not solve the problem that the VCO needs to operate at the full swing of VDD, resulting in still relatively high VCO drive power consumption. Furthermore, the global low-dropout linear regulator cannot completely isolate the coupling effect of local power supply noise generated by the digital modules in the loop on the VCO.

[0005] Another approach is to add an RC filter to the VCO's power path for isolation. While this method can suppress some high-frequency noise, the resistors in the RC filter introduce an additional voltage drop. To compensate for this voltage drop and maintain the VCO's required frequency tuning range, it may be necessary to increase the VCO's operating voltage, which could potentially increase power consumption. Furthermore, RC filters typically have limited ability to suppress low-frequency power supply noise.

[0006] Another approach is to use a differential VCO. The common-mode rejection characteristics of differential signals can theoretically offset some of the power supply noise, improving noise suppression performance. However, differential VCOs typically require more complex frequency tuning circuitry, such as large-scale capacitor arrays, which leads to a significant increase in chip area. Furthermore, device mismatch in the differential structure may introduce new nonlinear errors, affecting VCO performance.

[0007] Besides the impact of power supply noise on the VCO, the techniques used to generate feedback current in the feedback loop may also have shortcomings. For example, when a charge pump based on a switched capacitor generates feedback current, overlapping control clock signals may introduce charge injection errors, which can limit the final locking accuracy of the loop. Summary of the Invention

[0008] The purpose of this invention is to provide a frequency-locked loop circuit and its control method with high power supply rejection ratio and low swing drive, which solves the defects of voltage-controlled oscillators such as high power consumption and susceptibility to power supply noise coupling interference.

[0009] This invention discloses a frequency-locked loop circuit with high power supply rejection ratio and low swing drive, comprising: a current comparator for comparing a reference current and a feedback current, and generating an error current signal based on the comparison result;

[0010] A loop filter is used to generate a control voltage based on the error current signal;

[0011] A low-dropout linear regulator is used to dynamically adjust the operating voltage of the voltage-controlled oscillator (VCO) according to the load current of the VCO; wherein the operating voltage is lower than the main power supply voltage received by the low-dropout linear regulator.

[0012] The voltage-controlled oscillator includes: a bias voltage supply unit, an odd number of cascaded delay units, and an output buffer;

[0013] The bias voltage providing unit provides a bias voltage for each of the delay cascade units based on the control voltage;

[0014] Multiple delay cascade units are connected in series, with the output of the last delay cascade unit outputting a first voltage signal; wherein, the delay cascade unit is used to logically invert the voltage inside the voltage-controlled oscillator and apply a transmission delay regulated by the control voltage;

[0015] The first voltage signal is buffered by the output buffer to generate the output clock signal.

[0016] Furthermore, the current comparator includes: a first operational amplifier, a second operational amplifier, a first resistor, a first capacitor, a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor;

[0017] The non-inverting input of the first operational amplifier is connected to a first reference voltage;

[0018] The gate of the first PMOS transistor is connected to the output terminal of the first operational amplifier, the source is connected to the main power supply voltage, and the drain is connected to the inverting input terminal of the first operational amplifier. The drain of the first PMOS transistor is also grounded through a first resistor.

[0019] The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source is connected to the reference current, and a comparator node is formed at the drain.

[0020] The non-inverting input of the second operational amplifier is connected to a second reference voltage;

[0021] The gate of the first NMOS transistor is connected to the output of the second operational amplifier, the drain is connected to the comparator node, and the source is connected to the inverting input of the second operational amplifier. The source of the first NMOS transistor is also grounded through the first capacitor.

[0022] Furthermore, it also includes a feedback circuit, which is used to generate the feedback current based on the output clock signal.

[0023] Furthermore, the feedback circuit includes:

[0024] The frequency divider divides the output clock signal to generate a frequency-divided clock signal.

[0025] The first level converter performs voltage domain conversion on the frequency-divided clock signal;

[0026] The non-overlapping clock generation circuit generates a non-overlapping clock signal based on the frequency-divided clock signal after voltage domain conversion;

[0027] A switching network generates the feedback current based on the non-overlapping clock signal and the second reference voltage.

[0028] Furthermore, the switch network includes: a second capacitor, a third capacitor, a first switch, a second switch, a third switch, and a fourth switch;

[0029] One end of the first switch and the second switch are connected to the source of the first NMOS transistor, and the other end are respectively connected to one end of the second capacitor and one end of the third capacitor. The other ends of the second capacitor and the third capacitor are both connected to ground. The first switch and the second switch are controlled by a first clock signal and a second clock signal, respectively.

[0030] The third switch is connected between one end of the second capacitor and ground, and is controlled by the second clock signal;

[0031] The fourth switch is connected between one end of the third capacitor and ground, and is controlled by the first clock signal.

[0032] Furthermore, the loop filter includes: a fourth capacitor and a second resistor;

[0033] One end of the fourth capacitor is connected to the comparison node, and the other end is grounded through the second resistor.

[0034] Furthermore, the bias voltage providing unit includes: a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, and a third NMOS transistor;

[0035] The gate of the third PMOS transistor is connected to a low-level enable signal, and the gate of the second NMOS transistor is connected to a high-level enable signal.

[0036] The source and drain of the third PMOS transistor are connected to the drain and source of the second NMOS transistor, respectively, forming a first connection node and a second connection node.

[0037] The source of the fourth PMOS transistor is connected to the operating voltage, the drain is connected to the first connection node, and the gate is connected to the bias voltage input terminal of the delay cascade unit and the drain of the fourth PMOS transistor.

[0038] The source of the third NMOS transistor is grounded, its gate is connected to the control voltage, and its drain is connected to the second connection node.

[0039] Furthermore, the delay cascade unit includes: a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor;

[0040] The source of the fifth PMOS transistor is connected to the operating voltage, the gate is connected to the output terminal of the bias voltage providing unit to receive the bias voltage, and the drain is connected to the source of the sixth PMOS transistor.

[0041] The node where the gate of the sixth PMOS transistor is connected to the gate of the fourth NMOS transistor is connected to the output of another delay cascade unit.

[0042] The node where the drain of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor is connected to the input terminal of another delay cascade unit.

[0043] The source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the control voltage, and the source of the fifth NMOS transistor is grounded.

[0044] Furthermore, the output buffer includes an even number of inverters connected in series, with the last inverter outputting the output clock signal.

[0045] Furthermore, the low-dropout linear regulator includes: a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a fifth capacitor, and a sixth capacitor;

[0046] The source of the eighth PMOS transistor is connected to the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor is grounded through a second current source, and the gate of the eighth PMOS transistor is connected to a fourth reference voltage; the source of the seventh PMOS transistor is connected to the power supply voltage, and the gate of the seventh PMOS transistor is connected between a first current source and the drain of the sixth NMOS transistor; the operating voltage is output at the third connection node where the source of the eighth PMOS transistor and the drain of the seventh PMOS transistor are connected.

[0047] The drain of the sixth NMOS transistor is connected to the first current source; the gate is connected to the third reference voltage; the source is connected to one end of the fifth capacitor; one end of the fifth capacitor is also connected to the first current source; the other end of the fifth capacitor is connected to the third connection node.

[0048] One end of the sixth capacitor is connected to the third connection node, and the other end is grounded.

[0049] Furthermore, it also includes a second level converter that converts the output clock signal into a system clock output signal.

[0050] On the other hand, the present invention also discloses a frequency-locked loop method with high power supply rejection ratio and low swing drive, the method comprising:

[0051] Compare the reference current with the feedback current, and generate an error current signal based on the comparison result;

[0052] A control voltage is generated based on the error current signal;

[0053] A working voltage lower than the main power supply voltage is generated based on the main power supply voltage;

[0054] Under the operating voltage, an output clock signal is generated based on the control voltage.

[0055] Compared with the prior art, the present invention has at least the following technical effects:

[0056] This invention, using a closed-loop architecture consisting of a current comparator and a loop filter, introduces a dedicated low-dropout linear regulator (LDL-RCS) for independent power supply to the internal voltage-controlled oscillator (VCO), thus achieving comprehensive optimization from power supply to the signal link. The clean power supply provided by the LDL-RCS, combined with the VCO's high power supply rejection ratio (PSRR), significantly reduces clock jitter. Furthermore, its dynamic voltage adjustment based on the load greatly optimizes power consumption. In addition, the bias voltage supply unit within the VCO converts the main control voltage into a precise bias for an odd number of cascaded delay units, enabling fine-tuning of the propagation delay of each inverting stage for high-precision frequency control. This generates a stable clock with strong driving capability and effectively isolates the core frequency of the oscillator from interference caused by changes in the back-end load. This contributes to the circuit ultimately generating a stable clock signal with high quality, low power consumption, and low jitter. Attached Figure Description

[0057] Figure 1 This is a schematic block diagram of the frequency-locked loop circuit with high power supply rejection ratio and low swing drive in Embodiment 1 of the present invention;

[0058] Figure 2 This is a schematic diagram of the current comparator, loop filter, and switching network in Embodiment 1 of the present invention;

[0059] Figure 3 This is a schematic diagram of the voltage-controlled oscillator in Embodiment 1 of the present invention;

[0060] Figure 4 This is a schematic diagram of the low-dropout linear regulator in Embodiment 1 of the present invention;

[0061] Figure 5 This is a simplified flowchart illustrating the frequency-locked loop circuit control method with high power supply rejection ratio and low swing in Embodiment 2 of the present invention. Detailed Implementation

[0062] The high power supply rejection ratio and low swing drive frequency-locked loop circuit and its control method of the present invention will be described in detail below with reference to the schematic diagram, which shows the preferred embodiments of the present invention. It should be noted that the following description is intended to enable those skilled in the art to understand and implement the present invention, and is for illustration rather than limiting the scope of the present invention. Those skilled in the art should understand that, based on the teachings of this specification, various modifications, equivalent substitutions, or improvements can be made to the specific embodiments described, without departing from the core spirit and principles of the present invention. For example, technical features in different embodiments can be cross-combined to form new technical solutions. As long as no technical contradictions are created, these variations and combinations should fall within the scope of protection claimed by the present invention.

[0063] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0064] Example 1

[0065] Please refer to Figures 1-4 This invention discloses a frequency-locked loop circuit with high power supply rejection ratio and low swing drive, comprising:

[0066] A current comparator compares the reference current IEF with the feedback current IDN and generates an error current signal based on the comparison result. A loop filter generates a control voltage Vctrl based on the error current signal. A low-dropout linear regulator dynamically adjusts the operating voltage VDD_VCO of the voltage-controlled oscillator (VCO) according to the load current of the VCO; wherein the operating voltage VDD_VCO is lower than the main power supply voltage VDD received by the VCO. The VCO generates the output clock signal CLK_VCO based on the control voltage Vctrl. A voltage-controlled oscillator (VCO) includes: a bias voltage providing unit, an odd number of delay cascade units, and an output buffer; the bias voltage providing unit provides a bias voltage to each delay cascade unit based on the control voltage Vctrl; the multiple delay cascade units are connected in series, with the output of the last delay cascade unit outputting a first voltage signal; wherein, the delay cascade units are used to logically invert the voltage inside the VCO and apply a transmission delay regulated by the control voltage; the first voltage signal is buffered by the output buffer to generate an output clock signal CLK_VCO.

[0067] In this embodiment, within a closed-loop architecture consisting of a current comparator and a loop filter, a dedicated low-dropout linear regulator is introduced to independently power the internal voltage-controlled oscillator (VCO), thereby achieving comprehensive optimization from power supply to the signal link. The clean power supply provided by the low-dropout linear regulator, combined with the high power supply rejection ratio (PSRR) of the VCO itself, significantly reduces clock jitter. Simultaneously, its ability to dynamically adjust voltage according to the load greatly optimizes power consumption. Furthermore, the bias voltage supply unit within the VCO converts the main control voltage into a precise bias for an odd number of cascaded delay units. This allows for fine-tuning of the propagation delay of each inverting stage to achieve high-precision frequency control, generating a stable clock with strong driving capability, and effectively isolating the core frequency of the oscillator from interference caused by changes in the back-end load. This contributes to the circuit ultimately generating a stable clock signal with high quality, low power consumption, and low jitter characteristics.

[0068] Specifically, with a power supply ripple injection of 100mVpp, the frequency jitter amplitude of the voltage-controlled oscillator (VCO) using the aforementioned high power supply rejection ratio and low swing drive loop circuit is reduced to 16.1% of that of the traditional direct-supply architecture (i.e., an improvement of 6.2 times); the operating voltage VDD_VCO of the VCO is reduced from the original main power supply voltage VDD of 2.8V to 2.2V, the swing drive power consumption is reduced, and the measured total power consumption is reduced by 35%.

[0069] Furthermore, the current comparator includes: a first operational amplifier U1, a second operational amplifier U2, a first resistor R1, a first capacitor C1, a first PMOS transistor MP1, a second PMOS transistor MP2, and a first NMOS transistor MN1.

[0070] The non-inverting input of the first operational amplifier U1 is connected to the first reference voltage VREF1.

[0071] The gate of the first PMOS transistor MP1 is connected to the output terminal of the first operational amplifier U1, the source is connected to the main power supply voltage, and the drain is connected to the inverting input terminal of the first operational amplifier U1. The drain of the first PMOS transistor MP1 is also grounded through the first resistor R1.

[0072] The gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1, the source is connected to the reference current, and a comparator node is formed at the drain.

[0073] The non-inverting input of the second operational amplifier U2 is connected to the second reference voltage VREF2.

[0074] The gate of the first NMOS transistor MN1 is connected to the output terminal of the second operational amplifier U2, the drain is connected to the comparator node, and the source is connected to the inverting input terminal of the second operational amplifier U2. The source of the first NMOS transistor MN1 is also grounded through the first capacitor C1.

[0075] In this embodiment, the current comparator is capable of linearly mapping the first reference voltage VREF1 to the reference current IREF.

[0076] in, VREF1 is the value of the first reference voltage, IREF is the value of the reference current, and R1 is the resistance value of the first resistor.

[0077] Next, based on the width-to-length ratio coefficient of the first PMOS transistor MP1 and the second PMOS transistor MP2... Achieving current mirroring, thereby enabling the generation ratio of the MP2 branch of the second PMOS transistor to be... reference current .

[0078] in, ;

[0079] The aspect ratio of the second PMOS transistor MP2 is... The aspect ratio of the first PMOS transistor MP1 is... This is the proportionality coefficient.

[0080] The feedback current IDN is generated by the periodic charging and discharging of the first capacitor C1 driven by the non-overlapping clocks CLKN and CLKP, and satisfies... .

[0081] Where C1 is the capacitance of the first capacitor C1, VREF2 is the magnitude of the second reference voltage, and fb is the feedback frequency (fb=fout / N, where N is the frequency division ratio and fout is the output frequency).

[0082] When the system is in steady state, the current balance condition must be satisfied. When IDN is equal to the frequency, the output frequency expression is derived by combining the frequency relationship formula: ,in This expression indicates that fout is only related to the scaling factor. The frequency division ratio N and the process constant of the first capacitor C1 are related, while they are decoupled from the power supply voltage VDD and the reference voltage VREF1. This characteristic makes the output frequency fout highly robust to process deviations, power supply fluctuations, and temperature variations (PVT).

[0083] Furthermore, this embodiment also includes a feedback circuit, which generates the feedback current IDN based on the output clock signal CLK_VCO. This completes the closed-loop detection and compensation of the frequency error.

[0084] Specifically, the feedback circuit includes:

[0085] The frequency divider divides the output clock signal CLK_VCO to generate the divided clock signal CLK_DIV.

[0086] The first level converter performs voltage domain conversion on the frequency-divided clock signal CLK_DIV.

[0087] The non-overlapping clock generation circuit generates a non-overlapping clock signal based on the frequency-divided clock signal CLK_DIV after voltage domain conversion.

[0088] A switching network generates the feedback current IDN based on the non-overlapping clock signals CLKN and CLKP and the second reference voltage VREF2.

[0089] Specifically, the voltage-controlled oscillator (VCO) generates an output clock signal CLK_VCO. CLK_VCO synchronously drives a frequency divider to generate a divided clock signal CLK_DIV. The divided clock signal CLK_DIV is then level-converted by a first voltage converter and fed into a non-overlapping clock generation circuit. This circuit ultimately generates complementary non-overlapping clock signals, namely the first clock signal CLKN and the second clock signal CLKP (frequency fb = fout / N, where N is the division ratio). The first clock signal CLKN and the second clock signal CLKP control the switched capacitor network in a non-overlapping manner, generating a feedback current IDN through the charge pump effect, thus completing closed-loop detection and compensation of the frequency error.

[0090] In this embodiment, the switch network includes: a second capacitor C2, a third capacitor C3, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4.

[0091] Specifically, one end of the first switch S1 and the second switch S2 are connected to the source of the first NMOS transistor MN1, and the other end is connected to one end of the second capacitor C2 and one end of the third capacitor C3, respectively. The other ends of the second capacitor C2 and the third capacitor C3 are both connected to ground. The first switch S1 and the second switch S2 are controlled by the first clock signal CLKN and the second clock signal CLKP, respectively.

[0092] The third switch S3 is connected between one end of the second capacitor C2 and ground, and is controlled by the second clock signal CLKP.

[0093] The fourth switch S4 is connected between one end of the third capacitor C3 and ground, and is controlled by the first clock signal CLKN.

[0094] In this embodiment, the switching network uses two complementary, non-overlapping clock signals (first clock signal CLKN and second clock signal CLKP) to control the switches, alternately operating the two capacitors (second capacitor C2 and third capacitor C3) to extract a certain average current from the input terminal (the point connected to the first switch S1 and the second switch S2, i.e., the source of the NMOS transistor, with a voltage of approximately VREF2). This average current is the feedback current IDN.

[0095] Furthermore, the loop filter includes: a fourth capacitor C4 and a second resistor R2.

[0096] Specifically, one end of the fourth capacitor C4 is connected to the comparison node, and the other end is grounded through the second resistor R2.

[0097] In this embodiment, after receiving the error current signal from the current comparator, the loop filter removes high-frequency noise and pulses through low-pass filtering, and converts the error current into a relatively smooth control voltage Vctrl through integration. This control voltage Vctrl is then used to adjust the output frequency of the voltage-controlled oscillator to obtain a high-performance phase-locked loop.

[0098] In this embodiment, the bias voltage providing unit includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a second NMOS transistor MN2, and a third NMOS transistor MN3.

[0099] Specifically, the gate of the third PMOS transistor MP3 is connected to a low-level enable signal ENB, and the gate of the second NMOS transistor MN2 is connected to a high-level enable signal ENI. The source and drain of the third PMOS transistor MP3 are connected to the drain and source of the second NMOS transistor MN2, respectively, forming a first connection node and a second connection node. The source of the fourth PMOS transistor MP4 is connected to the operating voltage VDD_VCO, the drain is connected to the first connection node, and the gate is connected to the bias voltage input terminal and the drain of the delay cascade unit. The source of the third NMOS transistor MN3 is grounded, the gate is connected to the control voltage Vctrl, and the drain is connected to the second connection node.

[0100] In this embodiment, the third NMOS transistor MN3 is used to set the current flowing through the bias branch. When the circuit is enabled, the transmission switch, which is formed by the parallel connection of the third PMOS transistor MP3 and the second NMOS transistor MN2, is turned on. At this time, the current set by the third NMOS transistor MN3 can flow through the turned-on switch to the fourth PMOS transistor MP4, establishing a stable bias voltage on the gate of the fourth PMOS transistor MP4. This voltage is then provided to the delay cascade unit as a bias voltage. When the enable signal is invalid, the transmission switch is turned off, cutting off the bias current path, thereby preventing the generation of the bias voltage and achieving the purpose of disabling the oscillator.

[0101] Furthermore, in this embodiment, the delay cascade unit includes: a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5.

[0102] Specifically, the source of the fifth PMOS transistor MP5 is connected to the operating voltage VDD_VCO, its gate is connected to the output of the bias voltage providing unit to receive the bias voltage, and its drain is connected to the source of the sixth PMOS transistor MP6. The node where the gate of the sixth PMOS transistor MP6 is connected to the gate of the fourth NMOS transistor MN4 is connected to the output of another delay cascade unit. The node where the drain of the sixth PMOS transistor MP6 is connected to the drain of the fourth NMOS transistor MN4 is connected to the input of another delay cascade unit. The source of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5, the gate of the fifth NMOS transistor MN5 is connected to the control voltage Vctrl, and the source of the fifth NMOS transistor MN5 is grounded.

[0103] In one specific embodiment, the number of delay cascade units is three. Of course, those skilled in the art can choose the number of delay cascade units based on design decisions regarding the target frequency, phase noise requirements, power budget, area constraints, and matching with other loop parameters. For example, five or seven units are possible; no specific limitation is made here.

[0104] In this embodiment, by controlling the effect of voltage Vctrl on the transconductance characteristics of the fifth NMOS transistor MN5 inside the voltage-controlled oscillator, the voltage change is effectively converted into control of the current flowing through the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5. This controlled current then affects the discharge rate of the output node of each delay cascade unit, adjusting the signal transmission delay time through each delay cascade unit (a larger current results in a shorter delay, and vice versa). Since the frequency of the entire oscillator is inversely proportional to the total delay time of the signal completing one loop, by controlling voltage Vctrl to adjust the unit delay, precise modulation of the oscillator output frequency can ultimately be achieved.

[0105] Furthermore, the output buffer includes an even number of inverters NG connected in series, with the last inverter NG outputting the output clock signal CLK_VCO.

[0106] In one specific embodiment, the number of inverters NG is two, which satisfies the requirement of in-phase buffering. Those skilled in the art can weigh the ratio of the load to be driven to the output capability of the preceding stage, combined with factors such as delay, power consumption, and area, and for example, the number could also be four, six, etc., without specific limitations here.

[0107] In this embodiment, the output buffer can effectively shape the original signal from the oscillator core, outputting a clock signal CLK_VCO with steeper edges and a waveform closer to an ideal square wave, thereby enabling the subsequent system to operate stably, reliably, and at high speed.

[0108] The low-dropout linear regulator includes: a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a sixth NMOS transistor MN6, a fifth capacitor C5, and a sixth capacitor C6.

[0109] Specifically, the source of the eighth PMOS transistor MP8 is connected to the drain of the seventh PMOS transistor MP7, the drain of the eighth PMOS transistor MP8 is grounded through the second current source I2, and the gate of the eighth PMOS transistor MP8 is connected to the third reference voltage VB2; the source of the seventh PMOS transistor MP7 is connected to the main power supply voltage VDD, and the gate of the seventh PMOS transistor MP7 is connected between the first current source I1 and the drain of the sixth NMOS transistor MN6; the third connection node connecting the source of the eighth PMOS transistor MP8 and the drain of the seventh PMOS transistor MP7 outputs the operating voltage VDD_VCO.

[0110] The drain of the sixth NMOS transistor MN6 is connected to the first current source I1; the gate is connected to the fourth reference voltage VB1, and the source is connected to one end of the fifth capacitor C5. One end of the fifth capacitor C5 is also connected to the first current source I1; the other end of the fifth capacitor C5 is connected to the third connection node.

[0111] One end of the sixth capacitor C6 is connected to the third connection node, and the other end is grounded.

[0112] Please refer to Figure 4 In this embodiment, the low-dropout linear regulator employs Miller compensation. Through the dynamic response of the seventh PMOS transistor MP7 and the pole separation design of the fifth capacitor C5, the dominant pole is placed at the internal node Y, simultaneously pushing the poles of nodes X and Z (the third connection node) outside the unity-gain bandwidth. The sixth capacitor C6, as the output voltage regulator, effectively absorbs ripple, thereby improving the phase stability of the low-dropout linear regulator. Furthermore, this embodiment uses a separate low-dropout linear regulator to power the voltage-controlled oscillator (VCO), decoupling the operating voltage VDD_VCO from the main power supply voltage VDD. This effectively suppresses power supply noise affecting the gate voltage of the MOS transistors in the VCO, thereby suppressing output frequency jitter.

[0113] Furthermore, this embodiment also includes a second level converter, which is used to convert the output clock signal CLK_VCO into a system clock output signal, which can be used as a clock output provided to the outside by the frequency-locked loop circuit.

[0114] Example 2

[0115] Please refer to Figure 5This embodiment discloses a frequency-locked loop method with high power supply rejection ratio and low swing drive, which is implemented using the frequency-locked loop circuit with high power supply rejection ratio and low swing drive disclosed in Embodiment 1. The method includes the following steps:

[0116] S1. Compare the reference current IREF with the feedback current IDN, and generate an error current signal based on the comparison result;

[0117] S2. Generate a control voltage Vctrl based on the error current signal;

[0118] S3. Generate an operating voltage VDD_VCO that is lower than the main power supply voltage VDD based on the main power supply voltage VDD;

[0119] S4. Under the operating voltage VDD_VCO, generate the output clock signal CLK_VCO based on the control voltage Vctrl.

[0120] It is understood that the technical effects achievable by the high power supply rejection ratio and low swing drive frequency lock loop method disclosed in this embodiment are the same as those achievable by the high power supply rejection ratio and low swing drive frequency lock loop circuit disclosed in Embodiment 1, and will not be repeated here.

[0121] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A frequency-locked loop circuit with high power supply rejection ratio and low swing, characterized in that, include: A current comparator is used to compare a reference current with a feedback current and generate an error current signal based on the comparison result. A loop filter is used to generate a control voltage based on the error current signal; A low-dropout linear regulator is used to dynamically adjust the operating voltage of a voltage-controlled oscillator (VCO) based on the load current of the VCO; wherein the operating voltage is lower than the main power supply voltage received by the low-dropout linear regulator. The voltage-controlled oscillator includes: a bias voltage supply unit, an odd number of cascaded delay units, and an output buffer; The bias voltage providing unit provides a bias voltage for each of the delay cascade units based on the control voltage; Multiple delay cascade units are connected in series, with the output of the last delay cascade unit outputting a first voltage signal; wherein, the delay cascade unit is used to logically invert the voltage inside the voltage-controlled oscillator and apply a transmission delay regulated by the control voltage; The first voltage signal is buffered by the output buffer to generate an output clock signal; The low-dropout linear regulator includes: a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a fifth capacitor, and a sixth capacitor; The source of the eighth PMOS transistor is connected to the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor is grounded through a second current source, and the gate of the eighth PMOS transistor is connected to a fourth reference voltage; the source of the seventh PMOS transistor is connected to the power supply voltage, and the gate of the seventh PMOS transistor is connected between a first current source and the drain of the sixth NMOS transistor; the operating voltage is output at the third connection node where the source of the eighth PMOS transistor and the drain of the seventh PMOS transistor are connected. The drain of the sixth NMOS transistor is connected to the first current source; the gate is connected to the third reference voltage; the source is connected to one end of the fifth capacitor; one end of the fifth capacitor is also connected to the first current source; the other end of the fifth capacitor is connected to the third connection node. One end of the sixth capacitor is connected to the third connection node, and the other end is grounded.

2. The frequency-locked loop circuit with high power supply rejection ratio and low swing drive as described in claim 1, characterized in that, The current comparator includes: a first operational amplifier, a second operational amplifier, a first resistor, a first capacitor, a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; The non-inverting input of the first operational amplifier is connected to a first reference voltage; The gate of the first PMOS transistor is connected to the output terminal of the first operational amplifier, the source is connected to the main power supply voltage, and the drain is connected to the inverting input terminal of the first operational amplifier. The drain of the first PMOS transistor is also grounded through a first resistor. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source is connected to the reference current, and a comparator node is formed at the drain. The non-inverting input of the second operational amplifier is connected to a second reference voltage; The gate of the first NMOS transistor is connected to the output of the second operational amplifier, the drain is connected to the comparator node, and the source is connected to the inverting input of the second operational amplifier. The source of the first NMOS transistor is also grounded through the first capacitor.

3. The frequency-locked loop circuit with high power supply rejection ratio and low swing as described in claim 2, characterized in that, It also includes a feedback circuit, which generates a feedback current based on the output clock signal.

4. The frequency-locked loop circuit with high power supply rejection ratio and low swing drive as described in claim 3, characterized in that, The feedback circuit includes: The frequency divider divides the output clock signal to generate a frequency-divided clock signal. The first level converter performs voltage domain conversion on the frequency-divided clock signal; The non-overlapping clock generation circuit generates a non-overlapping clock signal based on the frequency-divided clock signal after voltage domain conversion; A switching network generates the feedback current based on the non-overlapping clock signal and the second reference voltage.

5. The frequency-locked loop circuit with high power supply rejection ratio and low swing drive as described in claim 4, characterized in that, The switching network includes: a second capacitor, a third capacitor, a first switch, a second switch, a third switch, and a fourth switch; One end of the first switch and the second switch are connected to the source of the first NMOS transistor, and the other end are respectively connected to one end of the second capacitor and one end of the third capacitor. The other ends of the second capacitor and the third capacitor are both connected to ground. The first switch and the second switch are controlled by a first clock signal and a second clock signal, respectively. The third switch is connected between one end of the second capacitor and ground, and is controlled by the second clock signal; The fourth switch is connected between one end of the third capacitor and ground, and is controlled by the first clock signal.

6. The frequency-locked loop circuit with high power supply rejection ratio and low swing as described in claim 2, characterized in that, The loop filter includes: a fourth capacitor and a second resistor; One end of the fourth capacitor is connected to the comparison node, and the other end is grounded through the second resistor.

7. The frequency-locked loop circuit with high power supply rejection ratio and low swing as described in claim 1, characterized in that, The bias voltage providing unit includes: a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, and a third NMOS transistor; The gate of the third PMOS transistor is connected to a low-level enable signal, and the gate of the second NMOS transistor is connected to a high-level enable signal. The source and drain of the third PMOS transistor are connected to the drain and source of the second NMOS transistor, respectively, forming a first connection node and a second connection node. The source of the fourth PMOS transistor is connected to the operating voltage, the drain is connected to the first connection node, and the gate is connected to the bias voltage input terminal of the delay cascade unit and the drain of the fourth PMOS transistor. The source of the third NMOS transistor is grounded, its gate is connected to the control voltage, and its drain is connected to the second connection node.

8. The frequency-locked loop circuit with high power supply rejection ratio and low swing drive as described in claim 1, characterized in that, The delay cascade unit includes: a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The source of the fifth PMOS transistor is connected to the operating voltage, the gate is connected to the output terminal of the bias voltage providing unit to receive the bias voltage, and the drain is connected to the source of the sixth PMOS transistor. The node where the gate of the sixth PMOS transistor is connected to the gate of the fourth NMOS transistor is connected to the output of another delay cascade unit. The node where the drain of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor is connected to the input terminal of another delay cascade unit. The source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the control voltage, and the source of the fifth NMOS transistor is grounded.

9. The frequency-locked loop circuit with high power supply rejection ratio and low swing as described in claim 1, characterized in that, The output buffer includes an even number of inverters connected in series, with the last inverter outputting the output clock signal.

10. The frequency-locked loop circuit with high power supply rejection ratio and low swing drive as described in claim 1, characterized in that, Also includes: The second level converter converts the output clock signal into a system clock output signal.

11. A frequency-locked loop control method with high power supply rejection ratio and low swing drive, employing a frequency-locked loop circuit with high power supply rejection ratio and low swing drive as described in any one of claims 1-10, characterized in that, The method includes: Compare the reference current with the feedback current, and generate an error current signal based on the comparison result; A control voltage is generated based on the error current signal; A working voltage lower than the main power supply voltage is generated based on the main power supply voltage; Under the operating voltage, an output clock signal is generated based on the control voltage.

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