Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first nanostructure channel region and a second nanostructure channel region disposed on a substrate, a first source / drain region and a second source / drain region disposed adjacent to the first nanostructure channel region and the second nanostructure channel region; and a first gate structure and a second gate structure surrounding the first nanostructure channel region and the second nanostructure channel region. Each of the first gate structure and the second gate structure includes an outer gate portion and an inner gate portion. The semiconductor device also includes a first internal gate spacer disposed along a sidewall of the internal gate portion of the first gate structure and a second internal gate spacer disposed along a sidewall of the internal gate portion of the second gate structure. The first internal gate spacer includes a first doped dielectric layer, and the second internal gate spacer includes a second doped dielectric layer different from the first doped dielectric layer.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As semiconductor technology advances, there is an ever-increasing demand for higher memory capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and gate-all-around field effect transistors (GAA FETs). This shrinkage increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] Some embodiments of the present application provide a semiconductor device, comprising: a substrate; a first nanostructure channel region and a second nanostructure channel region, arranged on the substrate, wherein each of the first nanostructure channel region and the second nanostructure channel region includes a core channel region and an extended channel region; a first source / drain region and a second source / drain region, respectively arranged adjacent to the first nanostructure channel region and the second nanostructure channel region; a first gate structure and a second gate structure, respectively surrounding the first nanostructure channel region and the second nanostructure channel region, wherein each of the first gate structure and the second gate structure includes an external gate portion and an internal gate portion; a first internal gate spacer, arranged along a sidewall of the internal gate portion of the first gate structure, wherein the first internal gate spacer includes a first doped dielectric layer; and a second internal gate spacer, arranged along a sidewall of the internal gate portion of the second gate structure, wherein the second internal gate spacer includes a second doped dielectric layer different from the first doped dielectric layer.

[0004] Other embodiments of the present application provide a semiconductor device, comprising: a substrate; a first nanostructure channel region, arranged on a first portion of the substrate; a second nanostructure channel region, arranged on the first nanostructure channel region; a first dielectric layer, arranged between the first nanostructure channel region and the second nanostructure channel region; a first gate structure and a second gate structure, surrounding the first nanostructure channel region and the second nanostructure channel region, respectively; a first internal gate spacer, arranged along the sidewall of the first gate structure and on the top surface of the first nanostructure channel region, wherein the first internal gate spacer includes a first doped dielectric layer; and a second internal gate spacer, arranged along the sidewall of the second gate structure and on the bottom surface of the second nanostructure channel region, wherein the second internal gate spacer includes a second doped dielectric layer different from the first doped dielectric layer.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a nanostructure layer on a substrate; forming a nanostructure sacrificial layer on the nanostructure layer; forming a polysilicon layer on the nanostructure sacrificial layer; forming an external gate spacer on the nanostructure sacrificial layer; etching the nanostructure sacrificial layer to form an internal gate spacer opening; depositing a doped liner layer in the internal gate spacer opening; depositing a filling layer on the doped liner layer; forming a source / drain region adjacent to the doped layer and the filling layer; and replacing the polysilicon layer and the nanostructure sacrificial layer with a gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the disclosed embodiments are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1 An isometric view of a semiconductor device having a gate spacer structure is shown in accordance with some embodiments.

[0008] Figures 2A to 8A 、 Figures 28A to 31A 、 Figures 2B to 8B and Figures 28B to 31B Different cross-sectional views of a semiconductor device having a gate spacer structure according to some embodiments are shown.

[0009] Figures 2C to 2J Device characteristics of a semiconductor device having a gate spacer structure according to some embodiments are shown.

[0010] Figure 9A An isometric view of another semiconductor device having a gate spacer structure is shown in accordance with some embodiments.

[0011] Figure 9B and Figure 9C Different cross-sectional views of another semiconductor device having a gate spacer structure according to some embodiments are shown.

[0012] Figure 10 is a flow chart of a method for fabricating a semiconductor device having a gate spacer structure according to some embodiments.

[0013] Figures 11 to 16 、 17A to 20A and Figures 17B to 20B Cross-sectional views of a semiconductor device having a gate spacer structure at various stages of its fabrication process are shown according to some embodiments.

[0014] Figure 21 is a flow chart of a method for fabricating another semiconductor device having a gate spacer structure according to some embodiments.

[0015] Figures 22 to 27 Cross-sectional views of another semiconductor device having a gate spacer structure at various stages of its fabrication process are shown in accordance with some embodiments.

[0016] Illustrative embodiments will now be described with reference to the accompanying drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact with each other. As used herein, forming a first component on a second component means that the first component is directly in contact with the second component. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0018] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0019] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "exemplary embodiment," etc. indicate that the described embodiment may include a particular component, structure, or characteristic, but every embodiment may not necessarily include the particular component, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular component, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such component, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0020] It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the phraseology or terminology of this specification will be interpreted by those skilled in the relevant art in light of the teachings herein.

[0021] In some embodiments, the terms "about" and "substantially" can indicate a value of a given amount that varies within 5-20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" can refer to a percentage of a value as interpreted by one skilled in the relevant art in view of the teachings herein.

[0022] The GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. The double patterning or multiple patterning processes can combine photolithography and self-aligned processes, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0023] A GAA FET may include a base structure (also referred to as a "sheet base" and a "fin base") disposed on a substrate, a stack of nanostructure channel regions disposed on the base structure, and a gate structure surrounding each of the nanostructure channel regions. Each gate structure may include an external gate portion and an internal gate portion. The external gate portion may be disposed on the topmost nanostructure channel region in the nanostructure channel region stack. The internal gate portion may be disposed between adjacent nanostructure channel regions. A GAA FET may also include an external gate spacer and an internal gate spacer. The external gate spacer may be disposed on the sidewalls of the external gate portion. The internal gate spacer may be disposed on the sidewalls of the internal gate portion and between adjacent nanostructure channel regions. Some of the challenges in manufacturing a GAA FET are implementing a doping process on the nanostructure channel region and minimizing variations in dopant concentration between nanostructure channel regions in the nanostructure channel region stack. Variations in dopant concentration between nanostructure channel regions may result in poor FET performance.

[0024] To address the aforementioned challenges, embodiments of the present disclosure provide exemplary GAA FETs with internal gate spacers that eliminate the complexity of doping nanostructured channel regions and minimize variations in dopant concentration between nanostructured channel regions. In some embodiments, each nanostructured channel region may include a core channel region and extended channel regions located on either side of the core channel region 208Ac, and the nanostructured channel regions may be undoped. The top and bottom surfaces of the extended channel regions may be in contact with the internal gate spacers.

[0025] In some embodiments, each of the internal gate spacers may include a doped dielectric layer, such as a doped silicon oxide (SiO2) layer, a doped silicon nitride (SiN) layer, a doped silicon oxynitride (SiON) layer, a doped silicon oxycarbide (SiOC) layer, a doped silicon oxycarbonitride (SiOCN) layer, and any other suitable doped dielectric layer. In some embodiments, the doped dielectric layer may include a dopant, such as aluminum (Al), antimony (Sb), phosphorus (P), chlorine (Cl), fluorine (F), bromine (Br), boron (B), zinc (Zn), magnesium (Mg), germanium (Ge), bismuth (Bi), indium (In), gallium (Ga), and combinations thereof. The dopant in the internal gate spacer may provide a doping effect in the extended channel region by inducing charge carriers (e.g., electrons or holes) in the extended channel region. The induced charge carriers may reduce the resistance in the nanostructured channel region and improve the drive current through the nanostructured channel region. Thus, in the presence of a dopant in the internal gate spacer, the nanostructured channel region may have the same doping effect as in the absence of a dopant in the nanostructured channel region. Thus, the need to dope the nanostructure channel region by ion implantation, by in-situ doping epitaxy, by dopant diffusion, or by any other doping method may be eliminated, and the complexity of manufacturing the semiconductor device 100 may be reduced.

[0026] Figure 1 An isometric view of a semiconductor device 100 with FETs 102A and 102B according to some embodiments is shown. In some embodiments, FETs 102A and 102B may represent GAA FETs. In some embodiments, FETs 102A and 102B may both be p-type FETs or n-type FETs, or may be one of each conductivity type. Figures 2A to 8A and Figures 28A to 31A FET 102A is shown along Figure 1 Different cross-sectional views of line AA. Figures 2B to 8B and Figures 28B to 31B FET 102B is shown along Figure 1 Different cross-sectional views of line BB. Figures 2A to 8A 、 Figures 28A to 31A 、 Figures 2B to 8B and Figures 28B to 31B Shown with no Figure 1 A cross-sectional view of additional structures is shown in FIG. Figure 1 、 Figures 2A to 8A 、 Figures 28A to 31A 、 Figures 2B to 8B and Figures 28B to 31B Discussions of elements with the same annotation apply to each other unless otherwise mentioned.

[0027] The semiconductor device 100 may be formed on a substrate 104, wherein the FETs 102A and 102B are formed on different regions of the substrate 104. There may be other FETs and / or structures (e.g., isolation structures) between the FETs 102A and 102B formed on the substrate 104. In some embodiments, the substrate 104 may be a semiconductor material such as silicon (Si), Ge, silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and combinations thereof. In addition, the substrate 104 may be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). The semiconductor device 100 may also include a shallow trench isolation (STI) region 105 disposed on the substrate 104. In some embodiments, the STI region 105 may include an insulating material such as SiO2, SiN, SiON, SiOC, SiOCN, silicon carbon nitride (SiCN), and silicon germanium oxide (SiGeO2). x ).

[0028] refer to Figure 1 and Figure 2A In some embodiments, the FET 102A may include: (i) a fin-shaped base structure 106A (also referred to as a "sheet base 106A" or a "fin base 106A") disposed on the substrate 104; (ii) a nanostructure channel region 208A disposed on the base structure 106A; (iii) an S / D region 110A disposed adjacent to the nanostructure channel region 208A; (iv) a gate structure 112A surrounding the nanostructure channel region 208A; (v) an external gate spacer 114A; (vi) an internal gate spacer 216A; (vii) an etch stop layer (ESL) 118A disposed directly on the S / D region 110A; (viii) an interlayer dielectric (ILD) layer 120A disposed directly on the ESL 118A; and (ix) a contact structure 122A disposed on the S / D region 110A.

[0029] Similarly, reference Figure 1 and Figure 2BIn some embodiments, the FET 102B may include: (i) a fin-shaped base structure 106B (also referred to as a "sheet base 106B" or "fin base 106B") disposed on the substrate 104; (ii) a nanostructured channel region 208B disposed on the base structure 106B; (iii) an S / D region 110B disposed adjacent to the nanostructured channel region 208B; (iv) a gate structure 112B surrounding the nanostructured channel region 208B; (v) an external gate spacer 114B; (vi) an internal gate spacer 216B; (vii) an ESL 118B disposed directly on the S / D region 110B; (viii) an ILD layer 120B disposed directly on the ESL 118B; and (ix) a contact structure 122B disposed on the S / D region 110B. In some embodiments, the base structures 106A and 106B may include a material similar to that of the substrate 104. Base structures 106A and 106B may have elongated sides extending along the X-axis.

[0030] refer to Figure 2A and Figure 2B In some embodiments, nanostructured channel regions 208A and 208B may be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructured shapes. As used herein, the term "nanostructure" defines a structure, layer, and / or region as having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm. Nanostructured channel regions 208A and 208B may include a semiconductor material similar to or different from substrate 104. In some embodiments, nanostructured channel regions 208A and 208B may include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), III-V semiconductor compounds, or other suitable semiconductor materials.

[0031] In some embodiments, the nanostructured channel regions 208A and 208B can be undoped. In some embodiments, the nanostructured channel regions 208A and 208B can be unintentionally doped with dopants diffused from the outer gate spacers 114A and 114B and / or the inner gate spacers 216A and 216B, as described in detail below. The concentration of these unintentional dopants in the nanostructured channel regions 208A and 208B can be less than about 5 atomic percent. In some embodiments, each of the nanostructured channel regions 208A and 208B can have a thickness along the Z-axis of about 3 nm to about 15 nm. Although three nanostructured channel regions 208A are shown below each gate structure 112A and three nanostructured channel regions 208B are shown below each gate structure 112B, the FETs 102A and 102B can have any number of nanostructured channel regions 208A and 208B. Although rectangular cross-sections of the nanostructured channel regions 208A and 208B are shown, the nanostructured channel regions 208A and 208B may have cross-sections of other geometric shapes (eg, circular, elliptical, triangular, or polygonal).

[0032] In some embodiments, each nanostructure channel region 208A can have a core channel region 208Ac and extended channel regions 208Ae located on either side of the core channel region 208Ac. Similarly, in some embodiments, each nanostructure channel region 208B can have a core channel region 208Bc and extended channel regions 208Be located on either side of the core channel region 208Bc. In some embodiments, the core channel regions 208Ac and 208Bc: (i) can be disposed below and in physical contact with the gate structures 112A and 112B, respectively; (ii) can overlap the gate structures 112A and 112B, respectively, along a vertical direction (e.g., the Z-axis) perpendicular to the top surfaces of the nanostructure channel regions 208A and 208B; and (iii) can not overlap the outer gate spacers 114A and 114B and the inner gate spacers 216A and 216B along the Z-axis.

[0033] In some embodiments, the extended channel regions 208Ae and 208Be: (i) may be disposed below and in physical contact with the external gate spacers 114A and 114B, respectively; (ii) may be disposed on and in physical contact with the internal gate spacers 216A and 216B, respectively; (iii) may be located between adjacent internal gate spacers 216A and between adjacent internal gate spacers 216B, respectively; (iv) may overlap with the internal gate spacers 216A and 216B, respectively, along the Z-axis; and (v) may not overlap with the gate structures 112A and 112B, respectively, along the Z-axis.

[0034] refer to Figure 1 、 Figure 2A and Figure 2B In some embodiments, the S / D regions 110A and 110B may include an epitaxially grown semiconductor material (such as Si) and an n-type dopant (such as phosphorus and other suitable n-type dopants for n-type FETs 102A and / or 102B). The S / D regions 110A and 110B may include an epitaxially grown semiconductor material (such as Si and SiGe) and a p-type dopant (such as boron and other suitable p-type dopants for p-type FETs 102A and / or 102B). Each of the S / D regions 110A and 110B may be referred to as a source or a drain, individually or collectively depending on the context.

[0035] refer to Figure 2A and Figure 2B In some embodiments, each gate structure 112A can have an outer gate portion 213A and an inner gate portion 215A. Similarly, in some embodiments, each gate structure 112B can have an outer gate portion 213B and an inner gate portion 215B. In some embodiments, the outer gate portions 213A and 213B can be disposed on and in physical contact with the topmost nanostructure channel regions 208A and 208B, respectively. In some embodiments, the inner gate portion 215A can be disposed between adjacent nanostructure channel regions 208A and between adjacent inner gate spacers 216A. Similarly, in some embodiments, the inner gate portion 215B can be disposed between adjacent nanostructure channel regions 208B and between adjacent inner gate spacers 216B.

[0036] Each of the gate structures 112A and 112B may be a multi-layer structure and may include: (i) an interfacial oxide (IL) layer 226; (ii) a high-k (HK) gate dielectric layer 228; and (iii) a conductive layer 230. In some embodiments, the IL layer 226 may be disposed directly on the topmost nanostructure channel regions 208A and 208B. In some embodiments, the IL layer 226 may include SiO2, SiGeO x or germanium oxide (GeO x ) and may have a thickness of about 1 nm to about 20 nm. In some embodiments, the HK gate dielectric layer 228 may be disposed directly on the IL layer 226 and may include a high-k dielectric material such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). In some embodiments, the sidewalls of the IL layer 226 and the HK gate oxide layer 228 may contact the sidewalls of the external gate spacers 114A and 114B.

[0037] In some embodiments, the conductive layer 230 may be disposed on the HK gate dielectric layer 228 and may be a multi-layer structure. For simplicity, the different layers of the conductive layer 230 are not shown. In some embodiments, the conductive layer 230 may include a work function metal (WFM) layer disposed on the HK gate dielectric layer 230 and a gate metal fill layer disposed on the WFM layer. In some embodiments, the WFM layer may include a Ti-based or Ta-based nitride or alloy that is substantially free of Al (e.g., Al-free), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium-gold (Ti-Au) alloy, titanium-copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum-gold (Ta-Au) alloy, and tantalum copper (Ta-Cu). In some embodiments, the WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials. In some embodiments, the gate metal fill layer may include a suitable conductive material, such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0038] refer to Figure 2A and Figure 2BThe external gate spacers 114A and 114B can electrically isolate the external gate portions 213A and 213B from the adjacent S / D regions 110A and 110B and from the adjacent contact structures 222A and 222B. In some embodiments, the external gate spacers 114A and 114B can be disposed directly on the topmost nanostructure channel regions 208A and 208B, respectively. In some embodiments, the external gate spacers 114A and 114B can include an undoped dielectric layer, such as an undoped SiO2 layer, an undoped SiN layer, an undoped SiON layer, an undoped SiOC layer, an undoped SiCN layer, an undoped SiOCN layer, and any other suitable undoped dielectric layer.

[0039] The internal gate spacers 216A and 216B can electrically isolate the internal gate portions 215A and 215B from the adjacent S / D regions 110A and 110B. In some embodiments, each of the internal gate spacers 216A and 216B can have a height H1 of about 3 nm to about 20 nm and a thickness T1 of about 1 nm to about 10 nm. Within these ranges of height H1 and thickness T1, the internal gate spacers 216A and 216B can provide sufficient electrical isolation of the internal gate portions 215A and 215B from the adjacent S / D regions 110A and 110B without compromising device size and manufacturing cost.

[0040] In some embodiments, each of the internal gate spacers 216A and 216B may include a doped dielectric layer, such as a doped SiO2 layer, a doped SiN layer, a doped SiON layer, a doped SiOC layer, a doped SiOCN layer, and any other suitable doped dielectric layer. In some embodiments, the doped dielectric layer may include dopants such as Al, Sb, P, Cl, F, Br, B, Zn, Mg, Ge, Bi, In, Ga, and combinations thereof. The dopants in the internal gate spacers 216A and 216B may provide a doping effect in the extended channel regions 208Ae and 208Be, respectively, by inducing charge carriers (e.g., electrons or holes) in the extended channel regions 208Ae and 208Be. The induced charge carriers may reduce the resistance in the nanostructured channel regions 208A and 208B and improve the drive current through the nanostructured channel regions 208A and 208B. Thus, in the presence of dopants in the internal gate spacers 216A and 216B, the nanostructured channel regions 208A and 208B can have the effect of doping in the absence of dopants in the nanostructured channel regions 208A and 208B. Therefore, the need to dope the nanostructured channel regions 208A and 208B by ion implantation, by in-situ doping epitaxy, by dopant diffusion, or by any other doping method can be eliminated, and the complexity of manufacturing the semiconductor device 100 can be reduced.

[0041] In some embodiments, the doped dielectric layer of the inner gate spacers 216A and 216B may have a dielectric constant of about 5×10 18 to about 5×10 20 atoms / cm 3 The dopant concentration is about 5×10 18 atoms / cm 3 Below a dopant concentration of about 5×10 20 atoms / cm 3 Above a dopant concentration of , short channel effects may be induced in FETs 102A and 102B.

[0042] Figures 2C to 2F shows an example of a Figure 2A The lines CC and Figure 2B Different dopant concentration distribution along line DD. Figure 2B The dopant concentration profile along line DD is similar to that along Figure 2A In some embodiments, the dopant concentration distribution along line CC is Figure 2A The lines CC and Figure 2B The dopant concentration of line DD across each of the inner gate spacers 216A and 216B may be substantially constant, as Figure 2C In some embodiments, the dopant concentration near the interface between the internal gate spacer 216A and the internal gate portion 215A can be higher than the dopant concentration near the interface between the internal gate spacer 216A and the S / D region 110A. Similarly, in some embodiments, the dopant concentration near the interface between the internal gate spacer 216B and the internal gate portion 215B can be higher than the dopant concentration near the interface between the internal gate spacer 216B and the S / D region 110B. In some embodiments, along Figure 2A The concentration profile of the dopant in the inner gate spacer 216A along line CC may have a decreasing slope from the interface between the inner gate spacer 216A and the inner gate portion 215A to the interface between the inner gate spacer 216A and the S / D region 110A. Similarly, in some embodiments, along line CC Figure 2B A concentration profile of the dopant in the inner gate spacer 216B of line DD may have a decreasing slope from an interface between the inner gate spacer 216B and the inner gate portion 215B to an interface between the inner gate spacer 216B and the S / D region 110B.

[0043] In some embodiments, along Figure 2A The dopant concentration profile of line CC may have: (i) a decreasing slope from the interface between the internal gate spacer 216A and the internal gate portion 215A to the position x1 in the internal gate spacer 216A, as shown in FIG. Figure 2D (ii) a substantially constant distribution from the interface between the internal gate spacer 216A and the internal gate portion 215A to a position x2 in the internal gate spacer 216A and a decreasing slope from the position x2 to the position x3 in the internal gate spacer 216A, as shown in FIG. Figure 2E and (iii) a reduced gradient distribution from the interface between the internal gate spacer 216A and the internal gate portion 215A to the position x4 in the internal gate spacer 216A, as shown in FIG. Figure 2F As shown in .

[0044] Figures 2G to 2J shows an example of a Figure 2A The line FF and Figure 2B The different dopant concentration distribution along line GG. Figure 2B The dopant concentration profile along line GG is similar to that along Figure 2A In some embodiments, the dopant concentration distribution along line FF is Figure 2A The line FF and Figure 2B The dopant concentration of line GG across each of the inner gate spacers 216A and 216B may be substantially constant, as Figure 2G In some embodiments, along Figure 2A The dopant concentration profile of line FF may have: (i) a decreasing slope from the top surface of the inner gate spacer 216A to the position y1 in the inner gate spacer 216A, as shown in FIG. Figure 2H (ii) a decreasing slope from the bottom surface of the internal gate spacer 216A to the position y2 in the internal gate spacer 216A, as shown in FIG. Figure 2H (iii) a substantially constant distribution from the top surface of the internal gate spacer 216A to a position y3 in the internal gate spacer 216A and a decreasing slope from position y3 to position y4 in the internal gate spacer 216A, as shown in FIG. Figure 2I (iv) a substantially constant distribution from the bottom surface of the internal gate spacer 216A to a position y5 in the internal gate spacer 216A and a decreasing slope from the position y5 to the position y6 in the internal gate spacer 216A, as shown in FIG. Figure 2I (v) from the top surface of the internal gate spacer 216A to the internal gate spacer 216A position y7 decreases in the gradient distribution, as shown in FIG. Figure 2Jand (vi) a gradient distribution that decreases from the bottom surface of the internal gate spacer 216A to the position y8 in the internal gate spacer 216A, as shown in FIG. Figure 2J As shown in .

[0045] In some embodiments, the dopant in the internal gate spacer 216A can be the same as or different from the dopant in the internal gate spacer 216B. In some embodiments, the dopants in the internal gate spacers 216A and 216B can depend on the conductivity type of the FETs 102A and 102B. In some embodiments, the internal gate spacer 216A can include n-type dopants such as P, Cl, F, and Br for the n-type FET 102A, and the internal gate spacer 216B can include p-type dopants such as Al, B, and Ga for the p-type FET 102B. In some embodiments, the FETs 102A and 102B can both be n-type or p-type, and the dielectric material, dopants, and / or dopant concentrations in the internal gate spacers 216A and 216B can be different from each other so that the FETs 102A and 102B have different threshold voltages. In some embodiments, the internal gate spacer 216A may include n-type dopants such as P, Cl, F, and Br, and the internal gate spacer 216B may include p-type dopants such as Al, B, and Ga to change the threshold voltages of the FETs 102A and 102B relative to each other. The presence of the n-type dopant in the internal gate spacer 216A may provide a negative shift in the threshold voltage of the FET 102A compared to a FET without a dopant in the internal gate spacer. Furthermore, the presence of the p-type dopant in the internal gate spacer 216B may provide a positive shift in the threshold voltage of the FET 102B compared to a FET without a dopant in the internal gate spacer. Thus, by using different dopants in the internal gate spacers 216A and 216B, FETs 102A and 102B with the same conductivity but different threshold voltages may be achieved on the same substrate 104.

[0046] In some embodiments, the internal gate spacers 216A and 216B may have sidewalls with linear cross-sectional profiles, such as Figure 2A and Figure 2B In some embodiments, the internal gate spacers 216A and 216B may have sidewalls facing the S / D regions 110A and 110B, respectively, which may have: (i) a concave cross-sectional profile, such as Figure 28A and Figure 28B or (ii) a convex cross-sectional profile, such as Figure 29A and Figure 29B In some embodiments, the sidewalls of the internal gate spacers 216A and 216B may protrude into the S / D regions 110A and 110B, respectively, as shown in FIG. Figure 29Aand Figure 29B As shown in .

[0047] refer to Figure 2A and Figure 2B In some embodiments, the ESLs 118A and 118B may be disposed directly on the S / D regions 110A and 110B. In some embodiments, the ESLs 118A and 118B may have a dielectric constant of about 4 to about 7 and may include dielectric materials such as lanthanum oxide (LaO), aluminum oxide (Al2O3), yttrium oxide (Y2O3), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), SiOCN, SiOC, SiCN, zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), TiO2, Ta2O3, ZrO2, HfO2, SiN, hafnium silicide (HfSi), aluminum oxynitride (AlON), SiO2, SiC, SiN, and zinc oxide (ZnO). In some embodiments, the ILD layers 120A and 120B may be disposed directly on the ESLs 118A and 118B. In some embodiments, the ILD layer 118 may include an insulating material such as SiO 2 , SiN, SiON, SiCN, and SiOCN.

[0048] In some embodiments, each of the contact structures 222A and 222B may include: (i) a silicide layer 232; and (ii) a contact plug 234 disposed on the silicide layer 232. In some embodiments, the silicide layer 232 in the n-type FETs 102A and 102B may include titanium silicide (Ti x Si y ), tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y ), zirconium silicide (Zr x Si y ), Hafnium Silicide (Hf x Si y ), scandium silicide (Sc x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), Lutetium silicide (Lu x Si y ), Erbium Silicide (Er x Si y ), Ytterbium silicide (Yb x Si y ), europium silicide (Eu x Si y ), thorium silicide (Th x Siy ), other suitable metal silicide materials, or combinations thereof. In some embodiments, the silicide layer 232 in the p-type FETs 102A and 102B may include nickel silicide (Ni x Si y ), cobalt silicide (Co x Si y ), manganese silicide (Mn x Si y ), tungsten silicide (W x Si y ), iron silicide (Fe x Si y ), rhodium silicide (Rh x Si y ), palladium silicide (Pd x Si y ), ruthenium silicide (Ru x Si y ), platinum silicide (Pt x Si y ), iridium silicide (Ir x Si y ), osmium silicide (Os x Si y ), other suitable metal silicide materials, or combinations thereof. In some embodiments, the contact plug 234 may include a conductive material such as Co, W, Ru, Al, Mo, Ir, Ni, osmium (Os), rhodium (Rh), other suitable conductive materials, and combinations thereof.

[0049] refer to Figure 3A and Figure 3B In some embodiments, the FET 102A may have an internal gate spacer 316A instead of Figure 2A 1 and FET 102B may have internal gate spacers 316B instead of internal gate spacers 216A. Figure 2BThe internal gate spacer 216B is provided in the form of a spacer liner layer 316Ac. The discussion of the internal gate spacers 216A and 216B applies to the internal gate spacers 316A and 316B, respectively, unless otherwise noted. In some embodiments, the internal gate spacer 316A may include a spacer filling layer 316Af and a spacer liner layer 316Ac (also referred to as a "spacer capping layer 316Ac"). Similarly, the internal gate spacer 316B may include a spacer filling layer 316Bf and a spacer liner layer 316Bc (also referred to as a "spacer capping layer 316Bc"). In some embodiments, the spacer liner layers 316Ac and 316Bc may have a C-shaped cross-sectional profile. The spacer liner layers 316Ac and 316Bc may cover the top and bottom surfaces of the spacer filling layers 316Af and 316Bf, and may cover the sidewalls of the spacer filling layers 316Af and 316Bf facing the internal gate portions 215A and 215B. The top and bottom surfaces of the spacer liner layer 316Ac may be in physical contact with the extended channel region 208Ae, and the sidewalls of the spacer liner layer 316Ac may be in physical contact with the internal gate portion 215A. Similarly, the top and bottom surfaces of the spacer liner layer 316Bc may be in physical contact with the extended channel region 208Be, and the sidewalls of the spacer liner layer 316Bc may be in physical contact with the internal gate portion 215B.

[0050] In some embodiments, each of the spacer filling layers 316Af and 316Bf may include an undoped dielectric layer, and each of the spacer liner layers 316Ac and 316Bc may include a doped dielectric layer. The dielectric layers of the spacer filling layers 316Af and 316Bf and the spacer liner layers 316Ac and 316Bc may include SiO2, SiN, SiON, SiOC, SiOCN, or any other suitable dielectric material. In some embodiments, the dielectric materials of the spacer filling layers 316Af and 316Bf and the spacer liner layers 316Ac and 316Bc may be different from each other. In some embodiments, the spacer filling layers 316Af and 316Bf may have an undoped oxide layer (e.g., undoped SiO2 or SiOC), and the spacer liner layers 316Ac and 316Bc may have a doped nitride layer (e.g., doped SiN, SiON, or SiOCN). In some embodiments, each of the spacer filler layers 316Af and 316Bf may include a lightly doped dielectric layer, and each of the spacer liner layers 316Ac and 316Bc may include a doped dielectric layer having a dopant concentration greater than the dopant concentration of the lightly doped dielectric layer. In some embodiments, the lightly doped dielectric layer and the doped dielectric layer may include dopants such as Al, Sb, P, Cl, F, Br, B, Zn, Mg, Ge, Bi, In, Ga, and combinations thereof. In some embodiments, each of the spacer liner layers 316Ac and 316Bc may have a thickness of approximately 0.3 nm to approximately 2 nm. Within this thickness range, the spacer liner layers 316Ac and 316Bc may have a sufficient dopant concentration to induce a sufficient charge carrier concentration in the extended channel regions 208Ae and 208Be without compromising device size and manufacturing cost.

[0051] In some embodiments, the dopants in the spacer-fill layers 316Af and 316Bf can be the same or different from each other, and the dopants in the spacer liner layers 316Ac and 316Bc can be the same or different from each other. In some embodiments, similar to the internal gate spacers 216A and 216B, the dopants in the spacer liner layers 316Ac and 316Bc and / or in the spacer-fill layers 316Af and 316Bf can depend on the conductivity type of the FETs 102A and 102B. In some embodiments, the spacer-fill layer 316Af can be undoped, and the spacer liner layer 316Ac can include an n-type dopant, such as P, Cl, F, and Br for the n-type FET 102A, or both the spacer-fill layer 316Af and the spacer liner layer 316Ac can include an n-type dopant for the n-type FET 102A. In some embodiments, the spacer filler layer 316Bf may be undoped, and the spacer liner layer 316Bc may include a p-type dopant, such as Al, B, and Ga, for the p-type FET 102B, or both the spacer filler layer 316Bf and the spacer liner layer 316Bc may include a p-type dopant for the p-type FET 102B. In some embodiments, similar to the internal gate spacers 216A and 216B, the FETs 102A and 102B may be n-type or p-type, and the dielectric material, dopant, and / or dopant concentration in the internal gate spacers 316A and 316B may be different from each other so that the FETs 102A and 102B have different threshold voltages.

[0052] refer to Figure 4A and Figure 4B In some embodiments, the FET 102A may have an external gate spacer 414A instead of Figure 2A 114A, and FET 102B may have external gate spacer 414B instead of Figure 2B The discussion of the external gate spacers 114A and 114B applies to the external gate spacers 414A and 414B, respectively, unless otherwise mentioned. Figure 2A Unlike the outer gate spacer 114A of FIG, the outer gate spacer 414A may be disposed directly on the topmost inner gate spacer 216A, which is disposed directly on the topmost extended channel region 208Ae. Figure 2B Unlike the external gate spacer 114B, the external gate spacer 414B can be directly disposed on the topmost internal gate spacer 216B, which is directly disposed on the topmost extended channel region 208Be. Figure 2A and Figure 2BUnlike the structure of the topmost internal gate spacers 216A and 216B, the sidewalls of the topmost internal gate spacers 216A and 216B can be in physical contact with the sidewalls of the external gate portions 213A and 213B, respectively. When the topmost internal gate spacers 216A and 216B are placed on the topmost extended channel regions 208Ae and 208Be, the dopants in the internal gate spacers 216A and 216B can induce charges from the top and bottom surfaces of the topmost extended channel regions 208Ae and 208Be. Therefore, Figure 4A and Figure 4B The distribution of induced charges in the topmost extended channel regions 208Ae and 208Be is similar to Figure 2A and Figure 2B The distribution of induced charges in topmost-extended channel regions 208Ae and 208Be may be more uniform.

[0053] refer to Figure 5A and Figure 5B In some embodiments, the FET 102A may have an external gate spacer 514A instead of Figure 3A 114A, and FET 102B may have external gate spacer 514B instead of Figure 3B The discussion of the external gate spacers 114A and 114B applies to the external gate spacers 514A and 514B, respectively, unless otherwise mentioned. Figure 3A Unlike the outer gate spacer 114A of FIG, the outer gate spacer 514A may be disposed directly on the topmost inner gate spacer 316A, which is disposed directly on the topmost extended channel region 208Ae. Figure 3B Unlike the external gate spacer 114B, the external gate spacer 514B can be directly disposed on the topmost internal gate spacer 316B, which is directly disposed on the topmost extended channel region 208Be. Figure 3A and Figure 3B Unlike the structure of FIG. 3 , the sidewalls of the topmost inner gate spacers 316A and 316B may be in physical contact with the sidewalls of the outer gate portions 213A and 213B, respectively.

[0054] refer to Figure 6A and Figure 6B In some embodiments, the FET 102A may have an external gate spacer 614A instead of Figure 2A 114A, and FET 102B may have external gate spacer 614B instead of Figure 2BThe discussion of the external gate spacers 114A and 114B applies to the external gate spacers 614A and 614B, respectively, unless otherwise noted. In some embodiments, the external gate spacer 614A can have a doped dielectric layer similar to the doped dielectric layer of the inner gate spacer 216A, and the external gate spacer 614B can have a doped dielectric layer similar to the doped dielectric layer of the inner gate spacer 216B.

[0055] refer to Figure 7A and Figure 7B In some embodiments, the FET 102A may have an external gate spacer 714A instead of Figure 2A 114A, and FET 102B may have external gate spacer 714B instead of Figure 2B The discussion of the external gate spacers 114A and 114B applies to the external gate spacers 714A and 714B, respectively, unless otherwise noted. In some embodiments, the external gate spacer 714A may include a spacer filling layer 714Af and a spacer liner layer 714Ac (also referred to as a "spacer capping layer 714Ac"). Similarly, the external gate spacer 714B may include a spacer filling layer 714Bf and a spacer liner layer 714Bc (also referred to as a "spacer capping layer 714Bc"). The spacer liner layers 714Ac and 714Bc may cover the bottom surfaces of the spacer filling layers 714Af and 714Bf and may cover the sidewalls of the spacer filling layers 714Af and 714Bf facing the external gate portions 213A and 213B. The bottom surface of spacer liner layer 714Ac can be in physical contact with the topmost extended channel region 208Ae, and the bottom surface of spacer liner layer 714Bc can be in physical contact with the extended channel region 208Be. The sidewalls of spacer liner layer 714Ac can be in physical contact with the external gate portion 213A, and the sidewalls of spacer liner layer 714Bc can be in physical contact with the external gate portion 213B. Spacer filler layers 714Af and 714Bf can have doped dielectric layers similar to spacer filler layers 316Af and 316Bf, respectively. Spacer liner layers 714Ac and 714Bc can have undoped dielectric layers or lightly doped dielectric layers similar to spacer liner layers 316Ac and 316Bc.

[0056] refer to Figure 8A and Figure 8B In some embodiments, the FET 102A may have an external gate spacer 814A instead of Figure 3A 114A, and FET 102B may have external gate spacer 814B instead of Figure 3BThe discussion of the external gate spacers 114A and 114B applies to the external gate spacers 814A and 814B, respectively, unless otherwise noted. In some embodiments, the external gate spacer 814A can have a doped dielectric layer similar to the doped dielectric layer of the spacer liner layer 316Ac, and the external gate spacer 814B can have a doped dielectric layer similar to the doped dielectric layer of the spacer liner layer 316Bc.

[0057] refer to Figure 30A and Figure 30B In some embodiments, the FET 102A may have an internal gate spacer 3016A instead of Figure 2A 16A, and FET 102B may have internal gate spacer 3016B instead of Figure 2B The discussion of the internal gate spacers 216A and 216B applies to the internal gate spacers 3016A and 3016B, respectively, unless otherwise noted. In some embodiments, the internal gate spacer 3016A may include sub-spacers 3016A1 and 3016A2. Similarly, the internal gate spacer 3016B may include sub-spacers 3016B1 and 3016B2. In some embodiments, each of the sub-spacers 3016A1, 3016A2, 3016B1, and 3016B2 may include a doped dielectric layer, such as a doped SiO2 layer, a doped SiN layer, a doped SiON layer, a doped SiOC layer, a doped SiOCN layer, and any other suitable doped dielectric layer. In some embodiments, the doped dielectric layer may include dopants such as Al, Sb, P, Cl, F, Br, B, Zn, Mg, Ge, Bi, In, Ga, and combinations thereof, and may have a dielectric density of approximately 5×10 18 to about 5×10 20 atoms / cm 3 In some embodiments, the sub-spacers 3016A1 and 3016B1 may include a first dopant concentration, and the sub-spacers 3016A2 and 3016B2 may include a second dopant concentration different from the first dopant concentration. In some embodiments, the sub-spacers 3016A1 and 3016B1 may contact the internal gate portions 215A and 215B, respectively, and the sub-spacers 3016A2 and 3016B2 may contact the S / D regions 110A and 110B, respectively.

[0058] In some embodiments, the sub-spacers 3016A1, 3016A2, 3016B1, and 3016B2 may have sidewalls with linear cross-sectional profiles, such as Figure 30A and Figure 30BIn some embodiments, the subspacers 3016A1 and 3016B1 may have sidewalls facing the S / D regions 110A and 110B, respectively, which may have a concave cross-sectional profile, as shown in FIG. Figure 31A and Figure 31B In some embodiments, the subspacers 3016A2 and 3016B2 may have sidewalls with convex cross-sectional profiles, such as Figure 31A and Figure 31B In some embodiments, the sidewalls of the subspacers 3016A2 and 3016B2 may protrude into the S / D regions 110A and 110B, respectively, as shown in FIG. Figure 31A and Figure 31B As shown in .

[0059] In some embodiments, FET 102A may have Figure 2A structure, and FET 102B may have Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 28B 、 Figure 29B 、 Figure 30B or Figure 31B In some embodiments, FET 102A may have Figure 3A structure, and FET 102B may have Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 28B 、 Figure 29B 、 Figure 30B or Figure 31B In some embodiments, FET 102A may have Figure 4A structure, and FET 102B may have Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 28B 、 Figure 29B 、 Figure 30B or Figure 31B In some embodiments, FET 102A may have Figure 5A structure, and FET 102B may have Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 28B 、 Figure 29B 、 Figure 30B or Figure 31B In some embodiments, FET 102A may have Figure 6A structure, and FET 102B may have Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 28B 、 Figure 29B 、 Figure 30B or Figure 31B In some embodiments, FET 102A may have Figure 7A structure, and FET102B may have Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 28B 、 Figure 29B 、 Figure 30B or Figure 31B In some embodiments, FET 102A may have Figure 8A structure, and FET 102B may have Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 28B 、 Figure 29B 、 Figure 30B or Figure 31B In some embodiments, Figures 2A to 8A 、 Figures 28A to 31A 、 Figures 2B to 8B and Figures 28B to 31B The structure is not different from the two FETs 102A and 102B. Figures 2A to 8A 、 Figures 28A to 31A 、 Figures 2B to 8B and Figures 28A to 31B The structure may be a structure of 22 different FETs disposed on the same substrate 104 of the semiconductor device 100 .

[0060] Figure 9A An isometric view of a semiconductor device 900 is shown, in accordance with some embodiments. Figure 9B and Figure 9C The semiconductor device 100 according to some embodiments is shown along Figure 9A Different cross-sectional views of line EE. Figure 9B and Figure 9C Shown with no Figure 9A FIG. 1 is a view of the semiconductor device 100 showing additional structures. Figure 1 、 Figures 2A to 8A 、 Figures 28A to 31A 、 Figures 2B to 8B 、 Figures 28B to 31B and Figures 9A to 9C Discussions of elements with the same annotation apply to each other unless otherwise mentioned.

[0061] refer to Figure 9A and Figure 9B , the semiconductor device 100 may include: (i) a substrate 104; (ii) stacked FETs 902 disposed on the substrate 104; and (iii) an electrical isolation structure 903 disposed between the stacked FETs 902. In some embodiments, each stacked FET 902 may include: (i) a base structure 906 disposed on the substrate 104; (ii) an STI region 105 disposed on the substrate 104 and adjacent to the base structure 906; (iii) a GAA FET 902A disposed on the base structure 906 and the STI region 105; (iv) a GAA FET 902B disposed on the GAA FET 902A; (v) an ESL 918; (vi) an ILD layer 920; and (vii) a channel isolation layer 936 disposed between the GAA FETs 902A and 902B. In some embodiments, the fin structure 906 may include a material similar to that of the substrate 104 and extend along the X-axis. The discussion of the materials of ESL 118A and ILD layer 120A applies to the materials of ESL 918 and ILD layer 920. Electrical isolation structure 903 may include a dielectric oxide layer or a dielectric nitride layer.

[0062] When the GAA FET 902A has a different conductivity type than the GAA FET 902B, the stacked FET 902 may be referred to as a "complementary FET (CFET) 902." In some embodiments, the GAA FET 902A may be p-type and the GAA FET 902B may be n-type. In some embodiments, the GAA FET 902A may include: (i) a nanostructure channel region 908A disposed on the fin structure 906; (ii) an S / D region 910A disposed adjacent to the nanostructure channel region 908A; (iii) a gate structure 912A surrounding the nanostructure channel region 908A; and (iv) an internal gate spacer 916A. In some embodiments, the GAA FET 902B may include: (i) a nanostructure channel region 908B disposed on the GAA FET 902A; (ii) an S / D region 910B disposed adjacent to the nanostructure channel region 908V; (iii) a gate structure 912B surrounding the nanostructure channel region 908B; (iv) an external gate spacer 914; (v) an internal gate spacer 916B; (vi) a contact structure 922; and (vii) a gate cap layer 931.

[0063] The discussion of nanostructured channel regions 208A and 208B applies to nanostructured channel regions 908A and 908B, respectively, unless otherwise noted. In some embodiments, each nanostructured channel region 908A can have a core channel region 908Ac and an extended channel region 908Ae. Similarly, in some embodiments, each nanostructured channel region 908B can have a core channel region 908Bc and an extended channel region 908Be. In some embodiments, core channel regions 908Ac and 908Bc: (i) can be disposed below and in physical contact with gate structures 912A and 912B, respectively; (ii) can overlap gate structures 912A and 912B, respectively, along the Z-axis; and (iii) can not overlap internal gate spacers 916A and 916B along the Z-axis.

[0064] In some embodiments, the extended channel regions 908Ae and 908Be: (i) may be disposed on and in physical contact with the internal gate spacers 916A and 916B, respectively; (ii) may be located between adjacent internal gate spacers 916A and between adjacent internal gate spacers 916B, respectively; (iii) may overlap with the internal gate spacers 916A and 916B, respectively, along the Z-axis; and (iv) may not overlap with the gate structures 912A and 912B, respectively, along the Z-axis.

[0065] The S / D region 910A may include an epitaxially grown semiconductor material (such as Si and SiGe) and a p-type dopant (such as boron and other suitable p-type dopants for the p-type GAA FET 902A). The S / D region 910B may include an epitaxially grown semiconductor material (such as Si) and an n-type dopant (such as phosphorus and other suitable n-type dopants for the n-type GAA FET 902B).

[0066] In some embodiments, each gate structure 912B may have an outer gate portion 913B and an inner gate portion 915B. The outer gate portion 913B may be disposed on and in physical contact with the topmost nanostructure channel region 908B, and the inner gate portion 915B may be disposed between adjacent nanostructure channel regions 908B and between adjacent inner gate spacers 916B. Each of gate structures 912A and 912B may be a multilayer structure and may include: (i) an IL layer 226; (ii) an HK gate dielectric layer 228; and (iii) a conductive layer 230.

[0067] The discussion of the external gate spacer 114A applies to the external gate spacer 914 unless otherwise noted. The external gate spacer 914 can electrically isolate the external gate portion 913B from the adjacent S / D region 910B and from the adjacent contact structure 922. In some embodiments, the external gate spacer 914 can be disposed directly on the topmost nanostructure channel region 908B. In some embodiments, the GAA FET 902B can have Figure 6B The external gate spacer 614B, Figure 7B The external gate spacer 714B or Figure 8B The external gate spacer 814B is used instead of the external gate spacer 914.

[0068] The discussion of the internal gate spacers 216A and 216B applies to the internal gate spacers 916A and 916B, respectively, unless otherwise noted. The internal gate spacers 916A and 916B can electrically isolate the gate structure 912A and the internal gate portion 915B from the adjacent S / D regions 910A and 910B. Similar to the internal gate spacers 216A and 216B, the internal gate spacers 916A and 916B can include a doped dielectric layer, and the dopants in the internal gate spacers 916A and 916B can provide a doping effect in the extended channel regions 908Ae and 908Be, respectively, by inducing charge carriers (e.g., electrons or holes) in the extended channel regions 908Ae and 908Be. In some embodiments, the concentration profile of the dopant in the internal gate spacer 916A can have a decreasing slope from the interface between the internal gate spacer 916A and the gate structure 912A to the interface between the internal gate spacer 916A and the S / D region 910A. Similarly, in some embodiments, the concentration profile of the dopant in the internal gate spacer 916B can have a decreasing slope from the interface between the internal gate spacer 916B and the internal gate portion 915B to the interface between the internal gate spacer 916B and the S / D region 910B.

[0069] In some embodiments, the internal gate spacer 916A may include p-type dopants such as Al, B, and Ga for the p-type GAA FET 902A, and the internal gate spacer 916B may include n-type dopants such as P, Cl, F, and Br for the n-type GAA FET 102B. In some embodiments, both the GAA FETs 902A and 902B may be n-type or p-type, and the dielectric materials, dopants, and / or dopant concentrations in the internal gate spacers 916A and 916B may be different from each other so that the GAA FETs 902A and 902B have different threshold voltages. In some embodiments, the GAA FET 902A may have Figure 3A The internal gate spacer 316A or Figure 30A The internal gate spacer 3016A instead of the internal gate spacer 916A. Also, the GAA FET 902B may have Figure 3B The internal gate spacer 316B or Figure 30B The internal gate spacer 3016B is formed instead of the internal gate spacer 916B.

[0070] In some embodiments, each of the contact structures 922 may include: (i) a silicide layer 232; and (ii) a contact plug 234 disposed on the silicide layer 232. The gate cap layer 931 may protect the underlying external gate portion 913B from structural and / or compositional degradation during subsequent processing of the semiconductor device 100. In some embodiments, the gate cap layer 931 may include a dielectric oxide layer or a dielectric nitride layer. The channel isolation layer 936 may electrically isolate the channel region of the GAA FET 902A from the channel region of the upper GAA FET 902B. In some embodiments, the channel isolation layer 936 may include a dielectric material having a dielectric constant ranging from about 3 to about 25. In some embodiments, the dielectric material may include SiO2, SiN, SiON, SiOCN, HfO2, ZrO2, or a combination thereof.

[0071] refer to Figure 9C In some embodiments, the GAA FET 902B may have an external gate spacer 914* instead of Figure 9B The discussion of the external gate spacer 914 applies to the external gate spacer 914* unless otherwise mentioned. Figure 9B Unlike the external gate spacer 914, the external gate spacer 914* can be directly disposed on the topmost internal gate spacer 916B, which is directly disposed on the topmost extended channel region 908Be. Figure 9B Unlike the structure of the GAA FET 902A, the sidewalls of the topmost inner gate spacer 916B can be in physical contact with the sidewalls of the outer gate portion 913B. In some embodiments, the GAA FET 902A can have Figure 3A The internal gate spacer 316A or Figure 30A In some embodiments, the GAAFET 902A may have an inner gate spacer 3016A instead of an outer gate spacer 916A. Figure 5A The internal gate spacer 316A instead of the internal gate spacer 916A. Also, the GAA FET 902B may have Figure 5B The internal gate spacer 316B or Figure 30B The internal gate spacer 3016B is formed instead of the internal gate spacer 916B.

[0072] Figure 10 According to some embodiments, a method for manufacturing a Figure 2A 1 is a flow chart of an exemplary method 1000 of a cross-sectional view of a semiconductor device 100. For illustration purposes, Figure 10 The operations shown in the reference will be used to make Figures 11 to 16 1 and 2. The exemplary manufacturing process of the semiconductor device 100 shown in FIG.Figures 11 to 16 The semiconductor device 100 according to some embodiments is processed in various stages of manufacturing the semiconductor device 100. Figure 1 1. The method 1000 is a cross-sectional view of line AA. The operations may be performed in a different order or not performed at all, depending on the specific application. It should be noted that method 1000 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 1000, and some other processes may only be briefly described herein. Figure 1 、 Figure 2A 、 Figure 3A and Figures 11 to 16 Discussions of elements with the same annotation apply to each other unless otherwise mentioned.

[0073] refer to Figure 10 In operation 1005, a superlattice structure having a nanostructure layer and a nanostructure sacrificial layer is formed on a base structure on a substrate. Figure 11 As shown in FIG, a superlattice structure 1107 (also referred to as a "nanosheet stack 1107") is formed on a base structure 106A, which is formed on a substrate 104. The superlattice structure 1107 may include nanostructure layers 208A and nanostructure sacrificial layers 1108A arranged in an alternating configuration. In some embodiments, the nanostructure layers 208A may include Si, and the nanostructure sacrificial layers 1108A may include SiGe.

[0074] refer to Figure 10 In operation 1010, a polysilicon structure and an external gate spacer are formed on the topmost nanostructure layer of the superlattice structure. Figure 11 As shown in FIG, a polysilicon structure 1112 and an external gate spacer 114A are formed on the topmost nanostructure layer 208A of the superlattice structure 1107. In some embodiments, the formation of the polysilicon structure 1112 may include the following operations in sequence: (i) depositing a polysilicon layer (not shown) on the superlattice structure 1107; and (ii) performing a patterning process (e.g., a photolithography process) on the polysilicon layer to form the polysilicon structure 1112, as shown in FIG. Figure 11 In some embodiments, before forming the polysilicon structure 1112, a SiO2 layer 1138 may be formed on the superlattice structure 1107. During subsequent processing, the polysilicon structure 1112, the SiO2 layer 1138, and the nanostructure sacrificial layer 1108A may be replaced with the gate structure 112A in a gate replacement process.

[0075] In some embodiments, the formation of the external gate spacer 114A may include the following sequential operations: (i) depositing a dielectric material layer (not shown) on the polysilicon structure 1112 and on the exposed regions of the superlattice structure 1107; (ii) performing an annealing process to densify the dielectric material layer; and (iii) etching horizontal portions of the densified dielectric material layer on the superlattice structure 1107 to form the external gate spacer 114A. Figure 11 In some embodiments, a Figure 6A The external gate spacer 614A, Figure 7A The external gate spacer 714A or Figure 8A Instead of forming the external gate spacer 114A, the external gate spacer 814A is formed. The process of forming the external gate spacers 614A and 814A can be the same as the process of forming the external gate spacer 114A, except that the material of the dielectric material layer is different for the external gate spacers 114A, 614A, and 814A. The material of the dielectric material layer can be the same as that of the external gate spacers 114A, 614A, and 814A. Figure 2A 、 Figure 6A and Figure 8A The process for forming the external gate spacers 114A, 614A, and 814A described above can be the same as the process for forming the external gate spacers 114A, except that: (i) the doped liner layer can be deposited on the polysilicon structure 1112 and on the exposed areas of the superlattice structure 1107 before the dielectric material layer is deposited on the doped liner layer; and (ii) the horizontal portions of the liner layer and the dense dielectric material layer on the superlattice structure 1107 are etched to form the external gate spacers 714A. The materials used to form the doped liner layer and the dielectric material layer of the external gate spacers 714A can be the same as those described above with reference to FIG. Figure 7A Materials of the spacer liner layer 714Ac and the spacer filling layer 714Af are described.

[0076] refer to Figure 10 In operation 1015, S / D openings are formed in the superlattice structure. Figure 12As shown in FIG, S / D openings 1210 are formed in the superlattice structure 1107. The S / D openings 1210 can be formed by etching portions of the superlattice structure 1107 that are not covered by the polysilicon structure 1112. In some embodiments, the etching of the superlattice structure 1107 can include a plasma-based dry etching process using etching gases such as carbon tetrafluoride (CF4), sulfur dioxide (SO2), hexafluoroethane (C2F6), chlorine (Cl2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and hydrogen bromide (HBr) and mixed gases such as hydrogen (H2), oxygen (O2), nitrogen (N2), and argon (Ar). The etching can be performed at a temperature in the range of about 25° C. to about 200° C. at a pressure of about 5 mTorr to about 50 mTorr. The flow rate of the etching gas can be in the range of about 5 standard cubic centimeters per minute (sccm) to about 100 sccm. The plasma power may be in a range from about 50 W to about 200 W with a bias voltage from about 30 V to about 200 V.

[0077] refer to Figure 10 In operation 1020, an internal gate spacer opening is formed in the superlattice structure. Figure 13 As shown in FIG, an internal gate spacer opening 1316 is formed in the superlattice structure 1107. The formation of the internal gate spacer opening 1316 may include performing an etching process on the sidewalls of the nanostructured sacrificial layer 1108A facing the S / D opening 1210. The etching process may laterally etch the nanostructured sacrificial layer 1108A, such that the sidewalls of the nanostructured sacrificial layer 1108A are laterally recessed relative to the sidewalls of the nanostructured sacrificial layer 208A facing the S / D opening 1210. The etching process may include a dry etching process having a higher etch selectivity for SiGe in the nanostructured sacrificial layer 1108A than for Si in the nanostructured layer 208A. For example, a halogen-based chemistry may exhibit a higher etch selectivity for Ge than for Si. Thus, the halogen gas etches SiGe faster than Si. In some embodiments, the halogen-based chemistry may include a fluorine-based and / or chlorine-based gas. Alternatively, the etching of the nanostructured sacrificial layer 1108A may include a wet etching process having a higher selectivity for SiGe than for Si. For example, the wet etching process may include using a mixture of sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ) and / or a mixture of ammonium hydroxide (NH 4 OH) with H 2 O 2 and deionized water (DI).

[0078] refer to Figure 10 In operation 1025, an internal gate spacer is formed in the internal gate spacer opening. Figure 14As shown in FIG, an internal gate spacer 216A is formed in the internal gate spacer opening 1316. The formation of the internal gate spacer 216A may include the following operations in sequence: (i) Figure 13 (ii) performing an annealing process (e.g., a rapid thermal annealing process) on the doped dielectric layer in an argon, nitrogen, oxygen, and / or hydrogen environment at a temperature of about 500° C. to about 1000° C. for a period of about 1 second to about 30 minutes; and (iii) etching the doped dielectric layer to form Figure 14 In some embodiments, the etching of the doped dielectric material layer may be an anisotropic dry etching process and may have a higher etching rate along the Z axis than along the X axis or the Y axis. Therefore, the portion of the doped dielectric material layer located in the S / D opening 1210 may be etched without etching the portion of the doped dielectric material layer located in the internal gate spacer opening 1316. The material used to form the doped dielectric material layer of the internal gate spacer 216A may be the material described above with reference to Figure 3A The material of the inner gate spacer 216A is described.

[0079] In some embodiments, depositing the doped dielectric material layer may include depositing a doped SiO2 layer in an atomic layer deposition (ALD) process, which may include depositing monolayers of dopant-oxygen (DO) bonds and Si-O bonds in alternating ALD cycles at a temperature of about 150° C. to about 350° C. using a dopant precursor, a silicon precursor, and an oxygen precursor (e.g., water (H2O) or ozone (O3)). In some embodiments, the dopant D may include Al, B, Sb, P, Zn, Mg, Ge, Bi, In, or Ga. In some embodiments, depositing the doped dielectric material layer may include depositing a doped SiC layer in an ALD process, which may include depositing monolayers of D-O bonds and Si-O bonds in alternating ALD cycles at a temperature of about 150° C. to about 350° C. using a dopant precursor, a silicon precursor, an oxygen precursor, and a carbon precursor (e.g., methane gas (CH4)). In some embodiments, depositing the doped dielectric material layer may include depositing a doped SiN or SiON layer in an ALD process, which may include depositing a monolayer of D-O bonds and Si-O bonds in alternating ALD cycles using a dopant precursor, a silicon precursor, an oxygen precursor, and a nitrogen precursor (e.g., ammonia (NH3)) at a temperature of about 150° C. to about 350° C. In some embodiments, depositing the doped dielectric material layer may include depositing a doped SiOCN layer in an ALD process, which may include depositing a monolayer of D-O bonds and Si-O bonds in alternating ALD cycles using a dopant precursor, a silicon precursor, an oxygen precursor, a carbon precursor, and a nitrogen precursor at a temperature of about 150° C. to about 350° C.

[0080] In some embodiments, the silicon precursor may include tetra(ethoxy)silane (Si(OEt)4), ethyl orthosilicate, tri(3-tert-pentyloxy)silanol, hexachlorodisilane (HCDS). In some embodiments, the dopant precursor for (i) Al dopant may include trimethylaluminum (TMA), tri(ethoxy)aluminum (Al(OEt)3), aluminum methoxide, or dimethylaluminum isopropoxide; the dopant precursor for (ii) B dopant may include tri(methoxy)boron (B(OMe)3) or trimethyl borate; the dopant precursor for (iii) Sb dopant may include ethoxide (Sb(OEt)3), tris(dimethylamino)antimony (Sb(NMe2)3), or tris(trimethylsilyl)antimony ((SiMe3)3Sb); the dopant precursor for (iv) P dopant may include trimethyl phosphate (TMA). MP); the dopant precursor for the (v) Zn dopant may include diethylzinc (DEZ); the dopant precursor for the (vi) Mg dopant may include bis(cyclopentadienyl)magnesium (Mg(Cp)2); the dopant precursor for the (vii) Ge dopant may include GeCl2-dioxane; the dopant precursor for the (viii) Bi dopant may include Bi(N(SiMe3)2)3; the dopant precursor for the (ix) In dopant may include [3-(dimethylamino)propyl]dimethylindium (DADI); and the dopant precursor for the (x) Ga dopant may include trimethylgallium (TMG).

[0081] In some embodiments, a Figure 3A Instead of forming the internal gate spacer 216A, the internal gate spacer 316A is formed. The process of forming the internal gate spacer 316A may include the following operations in sequence: (i) Figure 13 (ii) depositing a doped liner layer (not shown) on the structure of ; (iii) depositing a doped or undoped dielectric material layer on the liner layer; (iv) performing an annealing process on the doped or undoped dielectric layer; and (iv) etching the doped liner layer and the doped or undoped dielectric material layer to form an internal gate spacer 316A. The materials used to form the doped liner layer and the doped or undoped dielectric material layer for forming the internal gate spacer 316A can be the materials described above. Figure 3A Materials of the spacer liner layer 314Ac and the spacer filling layer 314Af are described.

[0082] refer to Figure 10 In operation 1030, S / D regions are formed in the S / D openings. Figure 15 As shown in FIG, an S / D region 110A is formed in the S / D opening 1210. In some embodiments, the formation of the S / D region 110A may include epitaxially growing a semiconductor material (eg, Si or SiGe) having an n-type or p-type dopant in the S / D opening 1210, as shown in FIG. Figure 15 The formation of the S / D region 110A may be followed by the formation of the ESL 118A and the ILD layer 120A, as shown in FIG. Figure 15 As shown in .

[0083] refer to Figure 10 In operation 1035, the polysilicon structure and the nanostructure sacrificial layer are replaced with a gate structure. Figure 16 As shown in FIG, the polysilicon structure 1112 and the nanostructure sacrificial layer 1108A are replaced with a gate structure 112A. The formation of the gate structure 112A may include: (i) Figure 15 The polysilicon structure 1112, the SiO2 layer 1138 and the nanostructure sacrificial layer 1108A are removed to form a gate opening (not shown); and (ii) a gate structure 112A is formed in the gate opening, as shown in FIG. Figure 16 In some embodiments, the formation of the gate structure 112A may be followed by forming a contact structure 222A on the S / D region 110A, as shown in FIG. Figure 16 As shown in .

[0084] In some embodiments, Figure 10 The method 1000 can be used to form FETs 102A and 102B substantially parallel to each other on the same substrate 104. In some embodiments, elements of the FETs 102A and 102B can be formed simultaneously, except for their S / D regions and internal gate spacers, which can be formed sequentially. 17A to 20A and Figures 17B to 20B The sequential formation of the S / D regions 110A and internal gate spacers 216A of the FET 102A and the S / D regions 110B and internal gate spacers 216B of the FET 102B is shown. 17A to 20A FET 102A is shown along Figure 1 A cross-sectional view of line AA, and Figures 17B to 20B FET 102B is shown along Figure 1 Cross-sectional views of line BB at various stages of its fabrication. Figure 1 、 Figure 2A 、 Figure 2B 、 Figures 11 to 16 、 17A to 20A and Figures 17B to 20B Discussions of elements with the same annotation apply to each other unless otherwise mentioned.

[0085] Before forming the S / D regions 110A and 110B, Figure 17A and Figure 17B The structure can be implemented on the substrate 104 Figure 10In some embodiments, the formation of the S / D region 110A may be followed by the formation of the S / D region 110B. The formation of the internal gate spacer 216A and the S / D region 110A may include the following operations in sequence: (i) forming the S / D region 110B in the following order: Figure 17B A hard mask layer 1840 (e.g., aluminum oxide (AlO)) is deposited on the structure of the FET 102B in FIG. x ) layer) to form Figure 18B (ii) Figure 17A The structure of FET 102A is implemented in Figure 10 In operation 1025, internal gate spacers 216A are formed, as Figure 18A (iii) implementation Figure 10 Operation 1030 is performed to form the S / D region 110A, as shown in FIG. Figure 18A as shown in ; and (iv) from Figure 18B The hard mask layer 1840 can prevent the internal gate spacer 216A from being formed in the internal gate spacer opening 1316 of the FET 102B and prevent the S / D region 110A from being formed in the S / D opening 1210 of the FET 102B. In some embodiments, the hard mask layer 1840 can be formed. Figure 3A Instead of forming the inner gate spacers 216A, the inner gate spacers 316A are formed.

[0086] Similar to the formation of the internal gate spacer 216A and the S / D region 110A, the formation of the internal gate spacer 216B and the S / D region 110B may include the following sequential operations: (i) forming a plurality of gate spacers 216A and 110B at a plurality of gate spacers; Figure 18A A hard mask layer 1940 (e.g., AlO) is deposited on the structure of the FET 102A in FIG. x layer) to form Figure 19A (ii) after removing the hard mask layer 1840, the structure of the FET 102B is implemented Figure 10 In operation 1025, to form the inner gate spacer 216B, as Figure 19B (iii) implementation Figure 10 Operation 1030 is performed to form the S / D region 110B, as shown in FIG. Figure 19B as shown in ; and (iv) from Figure 19A The hard mask layer 1940 is removed from the structure. The hard mask layer 1940 can prevent the internal gate spacer 216B and the S / D region 110B from being formed on the Figure 18A In some embodiments, the FET 102A may be formed Figure 3BInstead of forming the internal gate spacer 316B, the internal gate spacer 216B is formed. In some embodiments, the removal of the hard mask layer 1940 may be followed by the formation of the ESL 118A and 118B and the ILD layers 120A and 120B, as shown in FIG. Figure 20A and Figure 20B The formation of ILD layers 120A and 120B may be followed by Figure 10 Operation 1035 is performed to form gate structures 112A and 112B in FETs 102A and 102B, as shown in FIG. Figure 20A and Figure 20B As shown in .

[0087] Figure 21 According to some embodiments, a method for manufacturing a Figure 4A 2100 is a flow chart of an exemplary method of a semiconductor device 100 with a cross-sectional view. For illustration purposes, Figure 21 The operations shown in the reference will be used to make Figures 22 to 27 1 and 2. The exemplary manufacturing process of the semiconductor device 100 shown in FIG. Figures 22 to 27 2100 are cross-sectional views of semiconductor device 100 at various stages of its fabrication, according to some embodiments. Operations may be performed in a different order, or not at all, depending on the specific application. It should be noted that method 2100 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 2100, and that some additional processes may only be briefly described herein. Figure 1 、 Figure 2A 、 Figure 4A 、 Figure 5A 、 Figures 11 to 16 and Figures 22 to 27 Discussions of elements with the same annotation apply to each other unless otherwise mentioned.

[0088] refer to Figure 21 In operation 2105, a superlattice structure having a nanostructure layer and a nanostructure sacrificial layer is formed on a base structure on a substrate. Figure 22 As shown in FIG, a superlattice structure 2207 (also referred to as a "nanosheet stack 2207") is formed on a base structure 106A, which is formed on a substrate 104. The superlattice structure 2207 may include nanostructure layers 208A and nanostructure sacrificial layers 1108A arranged in an alternating configuration. In some embodiments, the nanostructure layers 208A may include Si, and the nanostructure sacrificial layers 1108A may include SiGe.

[0089] refer to Figure 21 In operation 2110, a polysilicon structure and an external gate spacer are formed on the topmost nanostructure sacrificial layer of the superlattice structure. Figure 22 As shown in FIG, a polysilicon structure 1112 and an external gate spacer 114A are formed on the topmost nanostructure sacrificial layer 1108A of the superlattice structure 2207. In some embodiments, the formation of the polysilicon structure 1112 may include the following operations in sequence: (i) depositing a polysilicon layer (not shown) on the topmost nanostructure sacrificial layer 1108A of the superlattice structure 2207; and (ii) performing a patterning process (e.g., a photolithography process) on the polysilicon layer to form the polysilicon structure 1112, as shown in FIG. Figure 22 In some embodiments, SiGeO may be formed on the top nanostructure sacrificial layer 1108A before forming the polysilicon structure 1112. x Layer 2238. During subsequent processing, the polysilicon structure 1112, SiGeO x Layer 2238 and nanostructured sacrificial layer 1108A may be replaced with gate structure 112A in a gate replacement process.

[0090] In some embodiments, the formation of the external gate spacer 114A may include the following sequential operations: (i) depositing a dielectric material layer (not shown) on the polysilicon structure 1112 and on the exposed region of the topmost nanostructured sacrificial layer 1108A of the superlattice structure 2207; (ii) performing an annealing process to densify the dielectric material layer; and (iii) etching a horizontal portion of the densified dielectric material layer on the topmost nanostructured sacrificial layer 1108A to form the external gate spacer 114A, as shown in FIG. Figure 22 In some embodiments, a Figure 6A The external gate spacer 614A, Figure 7A The external gate spacer 714A or Figure 8A The external gate spacer 814A, instead of Figure 22 An outer gate spacer 114A is formed in the structure.

[0091] refer to Figure 21 , in operation 2115, S / D openings are formed in the superlattice structure. For example, Figure 23 As shown in FIG, S / D openings 1210 are formed in the superlattice structure 2207. The process of forming the S / D openings 1210 in the superlattice structure 2207 may be the same as the process of forming the S / D openings 1210 in the superlattice structure 1107 in operation 1015, as described in reference to FIG. Figure 12 described.

[0092] refer to Figure 21 , in operation 2120, an internal gate spacer opening is formed in the superlattice structure. For example, Figure 24As shown in FIG, an internal gate spacer opening 2416 is formed in the superlattice structure 2207. The process of forming the internal gate spacer opening 2416 in the superlattice structure 2207 may be the same as the process of forming the internal gate spacer opening 1316 in the superlattice structure 1107 in operation 1020, as described in reference to FIG. Figure 13 The topmost inner gate spacer opening 2416 may expose the bottom surface of the outer gate spacer 114A, as shown in FIG. Figure 24 , unlike the topmost inner gate spacer opening 1316 .

[0093] refer to Figure 21 In operation 2125, an internal gate spacer is formed in the internal gate spacer opening. Figure 25 As shown in FIG, an internal gate spacer 216A is formed in the internal gate spacer opening 2416. The process of forming the internal gate spacer 216A in the internal gate spacer opening 2416 may be the same as the process of forming the internal gate spacer 216A in the internal gate spacer opening 1316 in operation 1025, as described with reference to FIG. Figure 14 The topmost inner gate spacer 216A may be formed on the topmost nanostructure layer 208A using the method 2100, as described. Figure 25 As shown in the method 1000, Figure 14 In some embodiments, the topmost inner gate spacer 216A may be different. Figure 25 formed in the structure Figure 3A The internal gate spacer 316A, instead of Figure 25 An internal gate spacer 216A is formed in the structure.

[0094] refer to Figure 21 In operation 2130, S / D regions are formed in the S / D openings. Figure 26 As shown in FIG, an S / D region 110A is formed in the S / D opening 1210. In some embodiments, the formation of the S / D region 110A may include epitaxially growing a semiconductor material (eg, Si or SiGe) having an n-type or p-type dopant in the S / D opening 1210, as shown in FIG. Figure 26 The formation of the S / D region 110A may be followed by the formation of the ESL 118A and the ILD layer 120A, as shown in FIG. Figure 26 As shown in .

[0095] refer to Figure 21 In operation 2135, the polysilicon structure and the nanostructure sacrificial layer are replaced with a gate structure. Figure 26 and Figure 27As depicted, the polysilicon structure 1112 and the nanostructure sacrificial layer 1108A are replaced with a gate structure 112A. The formation of the gate structure 112A may include: (i) removing the polysilicon structure 1112, the SiGeO x layer 2238 and nanostructure sacrificial layer 1108A to form gate opening 2612, as shown Figure 26 and (ii) forming a gate structure 112A in the gate opening 2612, as shown in FIG. Figure 27 In some embodiments, the formation of the gate structure 112A may be followed by forming a contact structure 222A on the S / D region 110A, as shown in FIG. Figure 27 As shown in .

[0096] The disclosed embodiments provide exemplary GAA FETs (e.g., FETs 102A and 102B) with internal gate spacers (e.g., internal gate spacers 216A, 216B, 316A, 316B, 3016A, and 3016B) that can eliminate the complexity of doping nanostructure channel regions (e.g., nanostructure channel regions 208A and 208B) and minimize variations in dopant concentration between nanostructure channel regions. In some embodiments, each nanostructure channel region can have a core channel region (e.g., core channel regions 208Ac and 208Bc) and extended channel regions (e.g., extended channel regions 208Ae and 208Be) located on either side of core channel region 208Ac, and the nanostructure channel regions can be undoped. The top and bottom surfaces of the extended channel regions can be in contact with the internal gate spacers.

[0097] In some embodiments, each of the internal gate spacers may include a doped dielectric layer, such as a doped silicon oxide (SiO2) layer, a doped silicon nitride (SiN) layer, a doped silicon oxynitride (SiON) layer, a doped silicon oxycarbide (SiOC) layer, a doped silicon oxycarbonitride (SiOCN) layer, and any other suitable doped dielectric layer. In some embodiments, the doped dielectric layer may include a dopant, such as aluminum (Al), antimony (Sb), phosphorus (P), chlorine (Cl), fluorine (F), bromine (Br), boron (B), zinc (Zn), magnesium (Mg), germanium (Ge), bismuth (Bi), indium (In), gallium (Ga), and combinations thereof. The dopant in the internal gate spacer may provide a doping effect in the extended channel region by inducing charge carriers (e.g., electrons or holes) in the extended channel region. The induced charge carriers may reduce the resistance in the nanostructured channel region and improve the drive current through the nanostructured channel region. Thus, in the presence of a dopant in the internal gate spacer, the nanostructured channel region may have the same doping effect as in the absence of a dopant in the nanostructured channel region. Thus, the need to dope the nanostructure channel region by ion implantation, by in-situ doping epitaxy, by dopant diffusion, or by any other doping method may be eliminated, and the complexity of manufacturing the semiconductor device 100 may be reduced.

[0098] In some embodiments, a semiconductor device includes: a substrate; a first nanostructured channel region and a second nanostructured channel region disposed on the substrate; a first source / drain region and a second source / drain region disposed adjacent to the first nanostructured channel region and the second nanostructured channel region, respectively; and a first gate structure and a second gate structure surrounding the first nanostructured channel region and the second nanostructured channel region, respectively. Each of the first nanostructured channel region and the second nanostructured channel region includes a core channel region and an extended channel region, and each of the first gate structure and the second gate structure includes an outer gate portion and an inner gate portion. The semiconductor device also includes a first inner gate spacer disposed along a sidewall of the inner gate portion of the first gate structure and a second inner gate spacer disposed along a sidewall of the inner gate portion of the second gate structure. The first inner gate spacer includes a first doped dielectric layer, and the second inner gate spacer includes a second doped dielectric layer different from the first doped dielectric layer.

[0099] In some embodiments, a semiconductor device includes: a substrate; a first nanostructured channel region disposed on a first portion of the substrate; a second nanostructured channel region disposed on the first nanostructured channel region; a first dielectric layer disposed between the first nanostructured channel region and the second nanostructured channel region; a first gate structure and a second gate structure surrounding the first nanostructured channel region and the second nanostructured channel region, respectively; a first internal gate spacer disposed along a sidewall of the first gate structure and disposed on a top surface of the first nanostructured channel region; and a second internal gate spacer disposed along a sidewall of the second gate structure and disposed on a bottom surface of the second nanostructured channel region. The first internal gate spacer includes a first doped dielectric layer, and the second internal gate spacer includes a second doped dielectric layer different from the first doped dielectric layer.

[0100] In some embodiments, the method includes: forming a nanostructured layer on a substrate; forming a nanostructured sacrificial layer on the nanostructured layer; forming a polysilicon layer on the nanostructured sacrificial layer; forming an external gate spacer on the nanostructured sacrificial layer; etching the nanostructured sacrificial layer to form an internal gate spacer opening; depositing a doped liner layer in the internal gate spacer opening; depositing a fill layer on the doped liner layer; forming a source / drain region adjacent to the doped layer and the fill layer; and replacing the polysilicon layer and the nanostructured sacrificial layer with a gate structure.

[0101] Some embodiments of the present application provide a semiconductor device, comprising: a substrate; a first nanostructure channel region and a second nanostructure channel region, arranged on the substrate, wherein each of the first nanostructure channel region and the second nanostructure channel region includes a core channel region and an extended channel region; a first source / drain region and a second source / drain region, respectively arranged adjacent to the first nanostructure channel region and the second nanostructure channel region; a first gate structure and a second gate structure, respectively surrounding the first nanostructure channel region and the second nanostructure channel region, wherein each of the first gate structure and the second gate structure includes an external gate portion and an internal gate portion; a first internal gate spacer, arranged along a sidewall of the internal gate portion of the first gate structure, wherein the first internal gate spacer includes a first doped dielectric layer; and a second internal gate spacer, arranged along a sidewall of the internal gate portion of the second gate structure, wherein the second internal gate spacer includes a second doped dielectric layer different from the first doped dielectric layer.

[0102] In some embodiments, the first doped dielectric layer comprises an n-type dopant, and wherein the second doped dielectric layer comprises a p-type dopant. In some embodiments, the first doped dielectric layer comprises a dopant concentration profile having a decreasing slope. In some embodiments, the first doped dielectric layer and the second doped dielectric layer comprise different dopant concentrations from one another. In some embodiments, the first doped dielectric layer comprises a dopant concentration profile having a decreasing slope from an interface between the first internal gate spacer and the internal gate portion of the first gate structure to an interface between the first internal gate spacer and the first source / drain region. In some embodiments, the semiconductor device further comprises a third internal gate spacer disposed along a sidewall of the external gate portion of the first gate structure, wherein the third internal gate spacer comprises the first doped dielectric layer. In some embodiments, the semiconductor device further comprises: an external gate spacer disposed along a sidewall of the external gate portion of the first gate structure; and a third internal gate spacer disposed between the external gate spacer and the extended channel region of the first nanostructure channel region. In some embodiments, the semiconductor device further comprises: a first external gate spacer disposed along a sidewall of the external gate portion of the first gate structure, wherein the first external gate spacer comprises the first doped dielectric layer; and a second external gate spacer disposed along a sidewall of the external gate portion of the second gate structure, wherein the second internal gate spacer comprises the second doped dielectric layer. In some embodiments, the first doped dielectric layer comprises: a fill layer; and a liner layer having a C-shaped cross-sectional profile surrounding the fill layer. In some embodiments, the semiconductor device further comprises: an external gate spacer disposed along a sidewall of the external gate portion of the first gate structure, wherein the external gate spacer comprises: a fill layer comprising a first dopant concentration; and a liner layer comprising a second dopant concentration greater than the first dopant concentration.

[0103] Other embodiments of the present application provide a semiconductor device, comprising: a substrate; a first nanostructure channel region, arranged on a first portion of the substrate; a second nanostructure channel region, arranged on the first nanostructure channel region; a first dielectric layer, arranged between the first nanostructure channel region and the second nanostructure channel region; a first gate structure and a second gate structure, surrounding the first nanostructure channel region and the second nanostructure channel region, respectively; a first internal gate spacer, arranged along the sidewall of the first gate structure and on the top surface of the first nanostructure channel region, wherein the first internal gate spacer includes a first doped dielectric layer; and a second internal gate spacer, arranged along the sidewall of the second gate structure and on the bottom surface of the second nanostructure channel region, wherein the second internal gate spacer includes a second doped dielectric layer different from the first doped dielectric layer.

[0104] In some embodiments, the first doped dielectric layer and the second doped dielectric layer include different dopant concentrations from each other. In some embodiments, the first doped dielectric layer includes a p-type dopant, and wherein the second doped dielectric layer includes an n-type dopant. In some embodiments, the first doped dielectric layer includes: a fill layer including a first dopant concentration; and a liner layer including a second dopant concentration greater than the first dopant concentration. In some embodiments, the semiconductor device further includes a third internal gate spacer disposed on a top surface of the second nanostructure channel region, wherein the third internal gate spacer includes the second doped dielectric layer. In some embodiments, the semiconductor device further includes a source / drain region adjacent to the first nanostructure channel region, wherein the first doped dielectric layer includes a dopant concentration profile having a decreasing slope from an interface between the first internal gate spacer and the first gate structure to an interface between the first internal gate spacer and the source / drain region.

[0105] Some other embodiments of the present application provide a method, comprising: forming a nanostructure layer on a substrate; forming a nanostructure sacrificial layer on the nanostructure layer; forming a polysilicon layer on the nanostructure sacrificial layer; forming an external gate spacer on the nanostructure sacrificial layer; etching the nanostructure sacrificial layer to form an internal gate spacer opening; depositing a doped liner layer in the internal gate spacer opening; depositing a filling layer on the doped liner layer; forming a source / drain region adjacent to the doped layer and the filling layer; and replacing the polysilicon layer and the nanostructure sacrificial layer with a gate structure.

[0106] In some embodiments, the method further comprises annealing the fill layer. In some embodiments, depositing the fill layer comprises depositing a doped fill layer having a lower dopant concentration than the liner layer. In some embodiments, forming the external gate spacer comprises: depositing another doped liner layer on the polysilicon layer; and depositing another fill layer on the doped liner layer.

[0107] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device comprising: substrate; a first nanostructured channel region and a second nanostructured channel region disposed on the substrate, wherein each of the first nanostructured channel region and the second nanostructured channel region comprises a core channel region and an extended channel region; A first source / drain region and a second source / drain region are respectively disposed adjacent to the first nanostructure channel region and the second nanostructure channel region; a first gate structure and a second gate structure surrounding the first nanostructure channel region and the second nanostructure channel region, respectively, wherein each of the first gate structure and the second gate structure includes an outer gate portion and an inner gate portion; a first inner gate spacer disposed along a sidewall of the inner gate portion of the first gate structure, wherein the first inner gate spacer comprises a first doped dielectric layer; and A second inner gate spacer is disposed along a sidewall of the inner gate portion of the second gate structure, wherein the second inner gate spacer comprises a second doped dielectric layer different from the first doped dielectric layer.

2. The semiconductor device according to claim 1, wherein The first doped dielectric layer includes an n-type dopant, and Wherein, the second doped dielectric layer includes p-type dopant.

3. The semiconductor device according to claim 1, wherein The first doped dielectric layer includes a dopant concentration profile having a decreasing slope.

4. The semiconductor device according to claim 1, wherein The first doped dielectric layer and the second doped dielectric layer include dopant concentrations different from each other. The semiconductor device according to claim 1 , wherein The first doped dielectric layer includes a dopant concentration profile having a decreasing slope from an interface between the first inner gate spacer and the inner gate portion of the first gate structure to an interface between the first inner gate spacer and the first source / drain region.

6. The semiconductor device of claim 1 , further comprising a third inner gate spacer disposed along a sidewall of the outer gate portion of the first gate structure, wherein The third inner gate spacer includes the first doped dielectric layer.

7. The semiconductor device according to claim 1, further comprising: an outer gate spacer disposed along a sidewall of the outer gate portion of the first gate structure; as well as A third inner gate spacer is disposed between the outer gate spacer and the extended channel region of the first nanostructure channel region.

8. The semiconductor device according to claim 1, further comprising: a first external gate spacer disposed along a sidewall of the external gate portion of the first gate structure, wherein the first external gate spacer comprises the first doped dielectric layer; and A second outer gate spacer is disposed along a sidewall of the outer gate portion of the second gate structure, wherein the second inner gate spacer comprises the second doped dielectric layer.

9. A semiconductor device comprising: substrate; a first nanostructured channel region disposed on a first portion of the substrate; a second nanostructure channel region, disposed on the first nanostructure channel region; a first dielectric layer disposed between the first nanostructure channel region and the second nanostructure channel region; A first gate structure and a second gate structure surround the first nanostructure channel region and the second nanostructure channel region, respectively; a first internal gate spacer disposed along a sidewall of the first gate structure and on a top surface of the first nanostructure channel region, wherein the first internal gate spacer comprises a first doped dielectric layer; and A second internal gate spacer is disposed along a sidewall of the second gate structure and on a bottom surface of the second nanostructure channel region, wherein the second internal gate spacer comprises a second doped dielectric layer different from the first doped dielectric layer.

10. A method for manufacturing a semiconductor device, comprising: forming a nanostructure layer on a substrate; forming a nanostructured sacrificial layer on the nanostructured layer; forming a polysilicon layer on the nanostructured sacrificial layer; forming an external gate spacer on the nanostructured sacrificial layer; etching the nanostructured sacrificial layer to form inner gate spacer openings; depositing a doped liner layer in the inner gate spacer opening; depositing a filling layer on the doped liner layer; forming a source / drain region adjacent to the doped layer and the filling layer; as well as The polysilicon layer and the nanostructured sacrificial layer are replaced with a gate structure.

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